Boundary scan test structure of chip pins without BSDL model

Abstract

The present invention discloses a boundary scan test structure for a chip pin without a BSDL model, comprising: a constant current source, which provides a first stable current for the tested chip pin without a BSDL model; an ADC voltage acquisition unit, which inputs the constant current source current into the tested chip pin without a BSDL model, and presses the constant current source voltage to a first specified voltage to input the tested chip pin without a BSDL model, and feeds back the acquired voltage to an FPGA of a boundary scan test card; a boundary scan test card, wherein the FPGA of the boundary scan test card determines the electrical state of the tested chip pin without a BSDL model according to the acquired voltage and outputs it to a boundary scan test host computer. The test structure of the present invention can perform open and short circuit electrical tests on chip pins without a BSDL model, thereby improving the test coverage. Testers no longer need to use other equipment to test chip pins without a BSDL model, which saves test costs, test time, and improves test efficiency.

Description

Technical Field

[0001] The invention relates to the field of chip testing, and in particular to a BSDL model-free chip pin boundary scanning test structure. Background Art

[0002] Boundary Scan testing was developed in the 1990s. With the emergence of large-scale integrated circuits, the manufacturing process of printed circuit boards has developed towards small, micro and thin. Traditional ICT testing can no longer meet the testing requirements of such products. Due to the large number of pins on the chip, the small size of the components, and the extremely high density of the board, there is no way to perform probe testing. A new testing technology has emerged. The Joint Test Action Group (JTAG) defines this new testing method, namely boundary scan testing. Boundary scan is a collection of design rules applied to the integrated circuit level, allowing software to reduce the growing cost of designing, producing and testing digital systems.

[0003] Boundary scan testing can put the integrated circuit chips on the boundary scan chain into boundary scan mode through the built-in instructions required by the IEEE 1149.1 / 1149.6 protocol, and then test the open and short circuit faults of the interconnection network between chips by controlling the input / output status of the integrated circuit chip pins. Boundary scan testing can quickly and accurately test whether the connection between multiple chip pins is reliable, improving the test and inspection efficiency. Due to its short test time and high reliability, boundary scan testing is now well used in the consumer electronics and semiconductor fields.

[0004] Boundary scan testing implements pin continuity testing by controlling the BSDL model of the pins on the chip. For pins without BSDL models, testers cannot control the boundary scan registers to pass the test signals through the chip's input / output pins to the boundary scan device. Therefore, such pins cannot be tested for continuity, affecting the boundary scan test coverage.

[0005] When boundary scan testing cannot effectively test certain pins, the following two methods are usually used to supplement this deficiency:

[0006] 1. ICT testing uses a dedicated test fixture to connect multiple test probes to pins or test points on the PCB to perform electrical testing. This method requires a specific fixture design and has low test efficiency.

[0007] 2. FT testing, or functional testing, tests the actual function of the chip circuit by applying real working conditions and input signals. This method takes a long time to test and mainly focuses on the overall performance of the system, and cannot cover all pins. Summary of the invention

[0008] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0009] The technical problem to be solved by the present invention is to provide a boundary scan test structure capable of performing electrical tests on the pins of a chip without a BSDL model.

[0010] In order to solve the above technical problems, the present invention provides a BSDL-free model chip pin boundary scan test structure, comprising:

[0011] A constant current source, which provides a first stable current for the pin of the tested chip without BSDL model;

[0012] An ADC voltage acquisition unit, which inputs the constant current source current into the pin of the chip without BSDL model under test, presses the constant current source voltage to a first specified voltage and inputs it into the pin of the chip without BSDL model under test, and feeds back the acquired voltage to the FPGA of the boundary scan test card;

[0013] The FPGA of the boundary scan test card determines the electrical status of the pins of the chip without BSDL model under test according to the collected voltage and outputs it to the boundary scan test host computer.

[0014] Preferably, the BSDL-free model chip pin boundary scan test structure is further improved, the constant current source uses a voltage reference chip as a main chip, and a current-limiting resistor is connected in series to a reference pin REF of the voltage reference chip.

[0015] Voltage reference chips can provide an accurate and stable voltage output, and are usually used as reference voltages in measurement, control or power supply circuits. They can maintain the stability of the output voltage under different working conditions to ensure the normal operation of the electronic system. The present invention uses a voltage reference chip as the main chip of the constant current source circuit, and utilizes its characteristic that the voltage of the reference pin REF will be forcibly controlled at 2.5V when there is sufficient voltage margin (≥2.5V) and cathode current. A current limiting resistor of 1KΩ resistor is connected in series to the reference pin REF to obtain a stable current of 2.5mA.

[0016] Preferably, the BSDL-free model chip pin boundary scan test structure is further improved, the first stable current is 2.5mA, and the first specified voltage is 0.7V.

[0017] A 2.5mA current is input into the chip pin under test (i.e., the chip pin without a BSDL model). Due to the voltage drop characteristics of the protection diode inside the ADC voltage acquisition unit, a voltage of about 0.7V can be measured at the chip pin under test. The measured voltage is input into the ADC chip for voltage acquisition, and the electrical state of the chip pin under test is determined by the measured voltage.

[0018] Preferably, the BSDL-free model chip pin boundary scan test structure is further improved, and the ADC voltage acquisition unit communicates with the boundary scan test card I2C communication interface.

[0019] Preferably, the boundary scan test structure of the chip pin without BSDL model is further improved, and if the collected voltage is 0.7V, the electrical state of the chip pin without BSDL model is judged to be normal;

[0020] If the collected voltage is 2.5V, the electrical state of the chip pin without BSDL model is judged to be open circuit;

[0021] If the collected voltage is 0V, it is determined that the electrical state of the chip pin without the BSDL model is short-circuited to ground;

[0022] And output the judgment result to the host computer.

[0023] The present invention can at least achieve the following technical effects:

[0024] 1. The boundary scan test in the prior art can only cover the chip pins with BSDL models. The test structure of the present invention can perform open and short circuit electrical tests on chip pins without BSDL models, thereby improving the test coverage.

[0025] 2. Through the test structure of the present invention, testers no longer need to use other equipment (such as ICT fixtures) to test chip pins without BSDL models, which saves test costs, saves test time, and improves test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0027] Figure 1 Schematic diagram of the structure of the present invention. DETAILED DESCRIPTION

[0028] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. The difference is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all figures, the same reference numerals always represent the same element. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.

[0029] Example

[0030] refer to Figure 1 As shown, the present invention provides a BSDL model-free chip pin boundary scan test structure, comprising:

[0031] A constant current source provides a first stable current for the pin of the tested chip without BSDL model; the constant current source of this embodiment uses a voltage reference chip as a main chip, a reference pin REF of the voltage reference chip is connected in series with a current limiting resistor, the resistance of the current limiting resistor is 1KΩ, and the first stable current is 2.5mA;

[0032] An ADC voltage acquisition unit inputs a constant current source current into the pin of the chip without BSDL model being tested, and presses the constant current source voltage to a first specified voltage input into the pin of the chip without BSDL model being tested, wherein the first specified voltage is 0.7V, and the acquired voltage is fed back to the FPGA of the boundary scan test card through an I2C communication interface communication;

[0033] The boundary scan test card, whose FPGA determines the electrical status of the pins of the chip without BSDL model under test according to the collected voltage and outputs it to the boundary scan test host computer;

[0034] If the collected voltage is 0.7V, the electrical status of the chip pin without BSDL model is judged to be normal;

[0035] If the collected voltage is 2.5V, the electrical state of the chip pin without BSDL model is judged to be open circuit;

[0036] If the collected voltage is 0V, it is determined that the electrical state of the chip pin without the BSDL model is short-circuited to ground.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0038] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A chip pin boundary scan test structure without BSDL model, characterized in that: include: A constant current source, which provides a first stable current for the pin of the tested chip without BSDL model; An ADC voltage acquisition unit, which inputs the constant current source current into the pin of the chip without BSDL model under test, presses the constant current source voltage to a first specified voltage and inputs it into the pin of the chip without BSDL model under test, and feeds back the acquired voltage to the FPGA of the boundary scan test card; The FPGA of the boundary scan test card determines the electrical status of the pins of the chip without BSDL model under test according to the collected voltage and outputs it to the boundary scan test host computer.

2. The chip pin boundary scan test structure without BSDL model as claimed in claim 1, characterized in that: The constant current source uses a voltage reference chip as a main chip, and a current-limiting resistor is connected in series to a reference pin (REF) of the voltage reference chip.

3. The chip pin boundary scan test structure without BSDL model as claimed in claim 2, characterized in that: The current limiting resistor is 1KΩ.

4. The chip pin boundary scan test structure without BSDL model as claimed in claim 1, characterized in that: The first stable current is 2.5 mA, and the first specified voltage is 0.7V.

5. The chip pin boundary scan test structure without BSDL model as claimed in claim 1, characterized in that: The ADC voltage acquisition unit communicates with the boundary scan test card I2C communication interface.

6. The chip pin boundary scan test structure without BSDL model as claimed in claim 1, characterized in that: If the collected voltage is 0.7V, the electrical status of the chip pin without BSDL model is judged to be normal; If the collected voltage is 2.5V, the electrical state of the chip pin without BSDL model is judged to be open circuit; If the collected voltage is 0V, it is determined that the electrical state of the chip pin without the BSDL model is short-circuited to ground.

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