Chip debugging system

Abstract

The embodiment of the present application provides a chip debugging system, which comprises a debugging emulator, a host connected with the debugging emulator and a target chip; the host detects a debugging operation of a user to generate debugging data, encapsulates the debugging data into a first data packet in a preset protocol format, and receives a second data packet in the preset protocol format sent by the debugging emulator; the debugging emulator receives the first data packet sent by the host and parses the first data packet into the debugging data, sends a debugging signal to the target chip through a signal line according to the debugging data, receives a debugging signal fed back by the target chip to obtain a debugging result, encapsulates the debugging result into the second data packet in the preset protocol format, and sends the second data packet to the host; the target chip receives the debugging signal sent by the debugging emulator through the signal line, obtains the debugging data according to the debugging signal, performs debugging processing on the debugging data to obtain the debugging result, and sends a result signal to the debugging emulator through the signal line according to the result. The preset protocol of the present application designs a two-wire debugging protocol and a data frame structure, and simulation, debugging and firmware upgrading can be performed by using one signal line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal transmission, in particular to a chip debugging system. BACKGROUND

[0002] RISC-V(reduced instruction set computer-five, the fifth generation of reduced instruction set computer) is the fifth generation of free development instruction set architecture based on the principle of reduced instruction set. As an instruction set specification, RISC-V has the characteristics of complete open source, simple architecture and modular design, and has wide application prospects in consumer electronics, industrial control and Internet of Things fields. MCU(Microcontroller Unit, microcontroller) embedded software development field usually uses a debugging emulator as a necessary means for software development, debugging, code tracking and solving software bugs. With the rapid development of RSIC-V architecture in the semiconductor design field due to its advantages of simplicity, open source instruction set and modularity, a large number of chips based on RISC-V architecture design have appeared in the market. The existing debugger based on JTAG(Joint Test Action Group, Joint Test Action Group) is an important component in the software debugging process of RISC-V chips, which has problems such as the need for multiple IO(data transmission) pins, high deployment cost and great difficulty in secondary development. SUMMARY

[0003] In view of the above problems, the present application embodiment is proposed to provide a chip debugging system which overcomes the above problems or at least partially solves the above problems.

[0004] In order to solve the above problems, the present application embodiment discloses a chip debugging system, comprising: a host, a debugging emulator and a target chip; the debugging emulator is connected with the host and connected with the target chip through a signal line;

[0005] The host is used for detecting a user's debugging operation, generating debugging data according to the debugging operation, packaging the debugging data into a first data packet in a preset protocol format, and receiving a second data packet in a preset protocol format sent by the debugging emulator;

[0006] The debugging emulator is used for receiving the first data packet sent by the host, analyzing the first data packet to obtain the debugging data, and sending a debugging signal to the target chip through the signal line according to the debugging data; and receiving a result signal sent by the target chip through the signal line, obtaining a debugging result according to the result signal, packaging the debugging result into the second data packet in the preset protocol format and sending the second data packet to the host;

[0007] The target chip is configured to receive the debugging signal sent by the debugging emulator through the signal line, obtain the debugging data according to the debugging signal, perform a debugging process according to the debugging data to obtain the debugging result, and send the result signal to the debugging emulator through the signal line according to the debugging result.

[0008] Optionally, the data packet in the preset protocol format comprises a plurality of fields.

[0009] The debugging emulator is configured to parse the plurality of fields in the first data packet to obtain the debugging data, and send a debugging signal to the target chip through the signal line according to the debugging data.

[0010] The host is configured to parse the plurality of fields in the second data packet to obtain a debugging result.

[0011] Optionally, the data packet in the preset protocol format comprises a read data data packet and a write data data packet.

[0012] The read data data packet comprises a start field, a register selection field, a register read-write selection field, a first data signal direction inversion field, a data synchronization field, a read data field, a check field, and a second data signal direction inversion field.

[0013] The write data data packet comprises a start field, a register selection field, a register read-write selection field, a first data signal direction inversion field, a write data field, a check field, and a second data signal direction inversion field.

[0014] Optionally, the debugging emulator is configured to parse the start field and send a start signal to the target chip through the first signal line.

[0015] After sending the start signal, the register selection field is parsed, and a register selection signal is sent to the target chip through the signal line.

[0016] After sending the register selection signal, the register read-write selection field is parsed, and a register read-write selection signal is sent to the target chip through the signal line; the register read-write selection signal comprises a register read signal or a register write signal.

[0017] After sending the register read-write selection signal, the first data signal direction inversion field is parsed, and a first data signal direction inversion signal is sent to the target chip through the signal line.

[0018] After sending the first data signal direction reversal signal, if the register read-write selection signal is a register read signal, the data synchronization field is parsed, and a data synchronization signal is sent to the target chip through the signal line;

[0019] After sending the data synchronization signal, the read data field is parsed, and a target read data signal is sent to the target chip through the first signal line;

[0020] After sending the first data signal direction reversal signal, if the register read-write selection signal is a register write signal, the write data field is parsed, and a target write data signal is sent to the target chip through the first signal line;

[0021] After sending the target read data signal or the target write data signal, the check field is parsed, and a check signal is sent to the target chip through the signal line;

[0022] After sending the check signal, the second data signal direction reversal field is parsed, and a second data signal direction reversal signal is sent to the target chip through the signal line.

[0023] Optionally, the signal line includes a data signal line;

[0024] The debug emulator is configured to send a debug signal to the target chip through the data signal line according to the debug data, and receive a result signal sent by the target chip through the data signal line.

[0025] Optionally, the signal line further includes a clock signal line;

[0026] The debug emulator is further configured to send a clock signal to the target chip through the clock signal line.

[0027] Optionally, the target chip includes a debug transmission module, a debug module interface, a register, and a processor;

[0028] The debug transmission module is connected with the debug client through a signal line, and is configured to receive the debug signal sent by the debug emulator through the signal line, and send the result signal to the debug emulator through the signal line;

[0029] The debug module interface is connected with the debug transmission module, and is configured to obtain the debug data according to the debug signal, and obtain the debug result by performing a debug process according to the debug data, the register, and the processor.

[0030] Optionally, the register includes a debug module interface register;

[0031] The debugging transmission module is configured to store the debugging signal and the result signal into the debugging module interface register.

[0032] Optionally, the host comprises a debugging client and a debugging proxy server.

[0033] The debugging client is configured to detect a debugging operation of a user.

[0034] The debugging proxy server is connected with the debugging client and the debugging emulator, configured to generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and send the first data packet to the debugging emulator; and receive a second data packet in the preset protocol format sent by the debugging emulator.

[0035] Optionally, the host further comprises a configuration library.

[0036] The debugging proxy server is configured to obtain chip information of the target chip from the configuration library, and send the chip information of the target chip to the debugging client.

[0037] The debugging client is configured to show the chip information of the target chip to the user.

[0038] The embodiment of the application has the following advantages:

[0039] The application discloses a chip debugging system, which comprises a host, a debugging emulator and a target chip. The host detects a debugging operation of a user and generates debugging data, encapsulates the debugging data into a first data packet in a preset protocol format, and also receives a second data packet in the preset protocol format sent by the debugging emulator. The debugging emulator receives the first data packet sent by the host and parses the first data packet into debugging data, sends a debugging signal to the target chip according to the debugging data through a signal line, receives a debugging result obtained by the target chip by feeding back the debugging signal, encapsulates the debugging result into a second data packet in the preset protocol format, and sends the second data packet to the host. The target chip receives the debugging signal sent by the debugging emulator through the signal line, obtains debugging data according to the debugging signal, performs debugging processing on the debugging data to obtain a debugging result, and sends a result signal to the debugging emulator according to the result through the signal line. The preset protocol of the application only utilizes one signal line to transmit a data packet, so that the emulation, debugging and programming of the chip can be realized, the problem that the RISC-V CPU does not support the SWD protocol is solved, and the market competitiveness of the RISC-V MCU chip is increased. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a schematic structural diagram of a chip debugging system provided by the embodiment of the application.

[0041] Figure 2is an architecture schematic diagram of another chip debugging system provided by an embodiment of the application;

[0042] Figure 3 is a read data packet format schematic diagram of a chip debugging system provided by an embodiment of the application;

[0043] Figure 4 is a write data packet format schematic diagram of a chip debugging system provided by an embodiment of the application;

[0044] Figure 5 is a preset protocol communication state machine flowchart of a chip debugging system provided by an embodiment of the application;

[0045] Figure 6 is a preset protocol interface read register timing schematic diagram of a chip debugging system provided by an embodiment of the application;

[0046] Figure 7 is a preset protocol interface write register timing schematic diagram of a chip debugging system provided by an embodiment of the application. DETAILED DESCRIPTION

[0047] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the application will be further described in detail below with reference to the drawings and specific embodiments.

[0048] One of the core ideas of the embodiment of the application is to propose a two-wire debugging scheme and protocol for debugging a RISC-V processor, to realize high cohesion and low coupling, and to realize the debugging function by using a signal line to transmit a data packet by using STWI (Software Two wire Debugger), to realize the control of the RISC-V MCU, including pausing execution, single-step execution, accessing and modifying register / memory values, supporting setting breakpoints and monitoring watchpoints, and burning firmware.

[0049] Referring to Figure 1 , an architecture schematic diagram of a chip debugging system provided by an embodiment of the application is shown, and the system can specifically include: a host 10, a debugging emulator 11, and a target chip 12; the debugging emulator 11 is connected with the host 10, and is connected with the target chip 12 through a signal line;

[0050] CPU (Central Processing Unit) debugging is an indispensable part of software development and hardware design, which helps developers identify and fix errors in the code or problems in the hardware design. For a CPU based on the RISC-V architecture, the debugging process usually includes hardware support, debugging tools and related protocols.

[0051] Embodiments of the present application are mainly directed to a simulation and debugging system architecture for RISC-V MCU chips. This architecture typically includes multiple components that work together to provide a complete development and debugging environment. The debugging system architecture for RISC-V chips aims to provide an efficient and flexible way to diagnose and debug processors based on the RISC-V architecture. This architecture usually includes hardware support, software tools, and communication protocols to ensure that developers can effectively debug code, analyze performance, and troubleshoot.

[0052] The host 10 is configured to detect a user's debugging operation, generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and receive a second data packet in the preset protocol format sent by the debugging emulator 11.

[0053] The host 10 includes a host computer, and a computer PC (personal computer) end is connected to the debugging emulator 11 through USB (serial bus) and CAN (Controller Area Network) bus, etc. The host 10 generates data of the detected user's debugging operation, encapsulates the data according to an STWI protocol communication state machine process, obtains a first data packet in a preset protocol format, and transmits the first data packet to the debugging emulator 11 through USB and CAN bus encapsulated data. The host 10 can also receive a second data packet encapsulated by the debugging emulator 1 fed back by the target chip 12, and the second data packet is also encapsulated according to the STWI protocol communication state machine process, which is in the STWI protocol format.

[0054] The debugging emulator 11 is configured to receive the first data packet sent by the host, analyze the first data packet to obtain the debugging data, send a debugging signal to the target chip through the signal line according to the debugging data, receive a result signal sent by the target chip through the signal line, obtain a debugging result according to the result signal, encapsulate the debugging result into a second data packet in the preset protocol format, and send the second data packet to the host.

[0055] Debugging emulator generally refers to the process of testing and debugging programs using software tools that simulate the actual hardware environment during the software development process. Emulators can help developers check the behavior of the code without actual hardware and can provide additional debugging information such as memory state, register values, etc. The debugging emulator STWI-Link in the embodiment is connected to the host through a serial bus, and the STWI-Link receives data packets from the host end, parses the first data packet encapsulated according to the STWI protocol communication state machine process, and sends the debugging signal to the target chip 12 through the signal line. It also receives the result signal from the target chip 12, processes the signal according to the STWI protocol communication state machine process to obtain the debugging result data, and sends the second data packet to the host 10 according to the STWI protocol.

[0056] The target chip 12 is configured to receive the debugging signal sent by the debugging emulator through the signal line, obtain the debugging data according to the debugging signal, perform debugging processing according to the debugging data to obtain the debugging result, and send the result signal to the debugging emulator through the signal line according to the debugging result.

[0057] MCU (Microcontroller Unit) is a kind of small computer system that integrates processor, memory and various peripherals on a chip. MCU is usually used in embedded systems to perform specific control tasks. The main components of MCU include CPU (Central Processing Unit) responsible for executing program instructions, usually RISC architecture (such as ARM Cortex-M series) or CISC architecture (such as 8051 series); memory for storing program code and constant data; peripherals, GPIO (General Purpose Input Output Port) for connecting external devices such as LEDs, keys, etc., serial communication interfaces such as UART, SPI, I2C for communication with other devices; clock and reset circuit, etc.

[0058] In the embodiment of the application, after the target chip 12 receives the debugging signal sent by the STWI-Link, the debugging data is obtained according to the debugging signal, the target CPU responds to the debugging data, and the debugging result data or state is fed back to the host computer in the form of a debugging signal after the debugging result is obtained. The state refers to the success or failure of the debugging.

[0059] The chip debugging system provided in the embodiment of the application comprises a host, a debugging emulator and a target chip; the debugging emulator is connected with the host and the target chip; the host detects a debugging operation of a user and generates debugging data, encapsulates the debugging data into a first data packet in a preset protocol format, and also receives a second data packet in the preset protocol format sent by the debugging emulator; the debugging emulator receives the first data packet sent by the host and parses the first data packet into debugging data, sends a debugging signal to the target chip through a signal line according to the debugging data, receives a debugging signal fed back by the target chip to obtain a debugging result, encapsulates the debugging result into the second data packet in the preset protocol format, and sends the second data packet to the host; the target chip receives the debugging signal sent by the debugging emulator through the signal line, obtains debugging data according to the debugging signal, performs debugging processing to obtain a debugging result, and sends a result signal to the debugging emulator through the signal line according to the result. The preset protocol only uses one signal line of the RISC-V MCU chip to transmit the data packet, so that RISC-V MCU simulation, debugging and burning can be realized, the problem that the RISC-V CPU does not support the SWD protocol is solved, and the market competitiveness of the RISC-V MCU chip is increased.

[0060] Referring to Figure 2 , another architecture schematic diagram of a chip debugging system provided in the embodiment of the application is shown, and the system can specifically comprise a host 20, a debugging emulator 21 and a target chip 22; the debugging emulator 21 is connected with the host 20 and connected with the target chip 22 through a signal line;

[0061] In the embodiment, the RISC-V chip simulation debugging system architecture is composed of the host 21, the debugging emulator 21 and the target chip 22. The debugging emulator 21 can complete basic debugging operations such as single-step, breakpoint, full-speed running and access monitoring point on the target MCU in cooperation with the debugging software of the host 21 to achieve the purpose of the debugging software.

[0062] The host 20 is configured to detect a debugging operation of a user, generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and receive a second data packet in the preset protocol format sent by the debugging emulator;

[0063] The host 20 comprises a debugging client 200 and a debugging proxy server 201.

[0064] GDB client, GDB (GNU Debugger) is a powerful open-source debugging tool widely used for debugging in various programming languages and platforms. GDB client usually refers to the part that communicates with the GDB server or target device, allowing developers to control and observe program execution on remote targets through command-line or graphical interfaces on the host machine. The main functions of GDB client include: connecting to the target, or directly connecting to the target hardware that supports the GDB protocol; setting breakpoints, users can set breakpoints in the source code to pause program execution and check the state; single-step execution, executing code one instruction at a time to help understand program flow; viewing and modifying variables, you can view and modify variable values in memory when the program is paused; viewing call stacks, displaying the history of current function calls to help trace the root cause of problems; viewing registers and memory, directly viewing and modifying CPU registers and memory contents; conditional breakpoints, setting breakpoints that will only trigger when certain conditions are met.

[0065] STWI_OCD_Server, STWIOpen On-ChipDebugge, is an open-source debugging, memory access and flash programming tool widely used in embedded system development. It supports multiple processor architectures, including RISC-V. OpenOCD server (openocd) can be used with GDB debugger to provide powerful hardware debugging functions. The main functions of the debugging proxy server include: JTAG / SWD interface, providing JTAG and SWD interfaces for connecting target boards and debugging hosts, supporting multiple JTAG adapters; debugging interface, providing support for GDB remote debugging protocol, allowing GDB to connect to OpenOCD for remote debugging, supporting breakpoint setting, single-step execution, register and memory read / write debugging operations; flash programming, supporting various flash chips such as SPI Flash, QSPI Flash, eFlash, etc.; configuration file, using configuration files to define the hardware characteristics of the target board, JTAG adapter and debugging parameters, configuration files usually contain initialization scripts, target board definitions and debugging commands.

[0066] The debugging client 200 is used to detect the user's debugging operation.

[0067] The debugging proxy server 201 is connected with the debugging client 200 and the debugging emulator 21, and is used to generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and send the first data packet to the debugging emulator 21; and receive a second data packet in a preset protocol format sent by the debugging emulator 21.

[0068] In the embodiment of the application, the debugging agent server 201, that is, the debugging software IDE and the debugging agent service program, are called in a remote calling manner, wherein the STWI_OCD_Server implements logical implementation of operations such as burning, erasing, single-step execution, stopping, setting breakpoints, full-speed running, reading and writing peripheral registers, reading and writing storage spaces, setting breakpoints, and monitoring watchpoints, and encapsulates data according to an STWI read data packet format and an STWI write data packet format. The debugging agent server 201 can also receive a second data packet in an STWI protocol format sent by the debugging emulator 21.

[0069] The host 20 also includes a configuration library 202, the debugging agent server 201, configured to obtain chip information of the target chip 22 from the configuration library 202 and send the chip information of the target chip 22 to the debugging client 200, and the debugging client 200, configured to show the chip information of the target chip to a user.

[0070] In microcontroller (MCU) development, a library is a set of pre-written code that performs specific functions or manipulates hardware peripherals. These libraries are usually provided by MCU manufacturers or can come from third-party developers. Using libraries can greatly simplify the development process and improve code readability and maintainability.

[0071] In this embodiment, the configuration library 202, that is, the microcontroller debugging configuration library STWI MCU Library, can implement an address mapping table, an eflash (embedded Flash, a flash memory technology integrated on a chip) algorithm library, a configuration file, and a binary file of a RISC-V target chip executable driver library. The microcontroller debugging configuration library STWI MCU Library can implement compatibility with chips of different manufacturers and models in a high cohesion and low coupling manner, and supports chips of different manufacturers and models by only modifying PC host software without modifying the debugging emulator STWI-Link debugger firmware.

[0072] In another embodiment, the STWI_OCD_Server server is first started, MCU STWI Library configuration (including to-be-debugged chip information such as RAM, flash size, chipID, and the like) and flash algorithms are called, and then the IDE debugger (for example, GDB Client) is started, and a debugging (HALT CPU) command is sent to the STWI_OCD_Server to read the DMIDebug HALT bit through the STWI-Link and set it to 1, and the updated value is written to the DMIDebug register.

[0073] In an embodiment, the host 20 is configured to parse the second data packet to obtain a debugging result.

[0074] In addition to receiving the debugging signal from the debugging emulator 21, the host 20 can also parse the second data packet in the STWI protocol format encapsulated by the debugging emulator 21 to obtain the debugging result.

[0075] The debugging emulator 21 is configured to receive the first data packet sent by the host 20, parse the first data packet to obtain the debugging data, and send a debugging signal to the target chip 22 through the signal line according to the debugging data; receive a result signal sent by the target chip 22 through the signal line, obtain a debugging result according to the result signal, encapsulate the debugging result into a second data packet in the preset protocol format, and send the second data packet to the host.

[0076] In this embodiment, the debugging emulator 21, i.e., the STWI-Link, receives the data packaged according to the STWI protocol from the STWI_OCD_Server, parses the received data, and sends the data to the target CPU according to the STWI protocol. The target CPU responds and feeds back data or a state to the STWI-Link, which further encapsulates the data into a second data packet in the STWI protocol format and sends the second data packet to the host. When the target CPU is connected, the program to be debugged is loaded and the endpoint is set. The step command is used to perform single-step debugging. The value of the Single-step enable bit of the DMIDebug register can be set to 1 through the STWI-Link. After that, the CPU will automatically enter the halt state after executing each instruction.

[0077] In an embodiment, the data packet in the preset protocol format includes a plurality of fields.

[0078] The debugging emulator 21 is configured to parse the plurality of fields in the first data packet to obtain the debugging data, and send a debugging signal to the target chip 22 through the signal line according to the debugging data.

[0079] In an embodiment, the data packet in the preset protocol format includes a read data packet and a write data packet.

[0080] In the STWI communication protocol, data is always sampled or set at the rising edge of the clock. Data is transmitted in the form of data packets, which include a start bit (START), a register group selection bit (SR[1:0]), a read-write selection bit (R / W), a data signal direction reversal bit (Trun Around), a data synchronization bit (SYNC), a data segment (DATA), and a check bit (PARITY).

[0081] With reference to Figure 3 , a read data packet format diagram of a chip debugging system is shown, which includes a start field, a register selection field, a register read-write selection field, a first data signal direction reversal field, a data synchronization field, a read data field, a check field, and a second data signal direction reversal field.

[0082] The start field is a low level on the data signal line for one period; the register selection field indicates register group selection and occupies two clock periods. Selecting 00 indicates DMIDebug registers; 01 indicates selecting GPR general-purpose register groups; 10 indicates selecting CSR control and status registers; and 11 indicates selecting CPU floating-point operation unit registers (FPR). The register read-write selection field is high to indicate reading STWI registers and is low to indicate writing STWI registers. The first data signal direction reversal field is a period in which the data signal direction can be switched in read / write STWI register operations and is configured by the user. The data synchronization field is a low level for one period and exists only in STWI register read operations, and the user can determine when to start reading data returned by STWI according to this bit. The read data field is 8-bit wide or 32-bit wide according to different types. The check field is a data check field.

[0083] With reference to Figure 4 , a write data packet format diagram of a chip debugging system is shown, which includes a start field, a register selection field, a register read-write selection field, a first data signal direction reversal field, a write data field, a check field, and a second data signal direction reversal field.

[0084] The start field is a low level on the data signal line for one period; the register selection field indicates register group selection, occupying two clock periods. Selecting 00 indicates the DMIDebug register; 01 indicates selecting the GPR general-purpose register group register group; 10 indicates selecting the CSR control and status register; and 11 indicates selecting the CPU floating-point operation unit register (FPR). The register read-write selection field is high to indicate reading the STWI register operation, and is low to indicate writing the STWI register operation. The first data signal direction inversion field period is in the read / write STWI register operation, and the data signal direction can be switched by the user configuration. The write data field is 8-bit wide or 32-bit wide according to different types. The check field is the data check field.

[0085] To prevent the host and the debugged target chip from contending for the STWI IO, when the direction of driving the STWI IO needs to be changed, a turnaround period needs to be set to ensure that the IO direction switching is completed. During the turnaround period, neither the host nor the target chip drives the STWI IO, and the state of the STWI IO is undefined. The function of the two data signal direction inversion fields is to set the turnaround time period and wait for the IO state to be stable. The specific value is configured by the upper computer and can be set by the IDE debugger (GDB client) or the STWI_OCD Server or the MCU STWI Library.

[0086] Because there are only two GPIOs, one of which is a clock line and the other is a data line, the data line needs to be time-multiplexed when it is used as an input or an output, that is, when the direction changes, the data signal direction needs to be switched. The purpose of setting the data signal direction inversion period is to delay for a certain clock period when the GPIO multiplexes the data direction, so as to ensure that the GPIO direction switching is successful.

[0087] Referring to Figure 5 , a preset protocol communication state machine flowchart of a chip debugging system is shown, the debugging emulator 21 is used for parsing the start field and sending a start signal to the target chip 22 through the first signal line;

[0088] After sending the start signal, the register selection field is parsed, and a register selection signal is sent to the target chip 22 through the signal line;

[0089] After sending the register selection signal, the register read-write selection field is parsed, and a register read-write selection signal is sent to the target chip 22 through the signal line; the register read-write selection signal includes a register read signal or a register write signal;

[0090] After sending the register read-write selection signal, the first data signal direction reversal field is parsed, and a first data signal direction reversal signal is sent to the target chip through the signal line;

[0091] After sending the first data signal direction reversal signal, if the register read-write selection signal is a register read signal, the data synchronization field is parsed, and a data synchronization signal is sent to the target chip through the signal line;

[0092] After sending the data synchronization signal, the read data field is parsed, and a target read data signal is sent to the target chip through the first signal line;

[0093] After sending the first data signal direction reversal signal, if the register read-write selection signal is a register write signal, the write data field is parsed, and a target write data signal is sent to the target chip through the first signal line;

[0094] After sending the target read data signal or the target write data signal, the check field is parsed, and a check signal is sent to the target chip through the signal line;

[0095] After sending the check signal, the second data signal direction reversal field is parsed, and a second data signal direction reversal signal is sent to the target chip through the signal line.

[0096] In this embodiment, the debugging emulator STWI_Link supports a driver program (which can be a Windows OS driver or a Linux OS driver) conforming to the PC operating system specification, so that the PC can normally interact with the emulator. The host end communicates with the STWI_Link, and can select any one or more of USB, network, CAN, I2C, SPI, etc. bus for communication. In the debugging emulator STWI_Link, data reception and sending of one or more transmission media of USB, network, CAN, I2C, SPI, etc. bus are implemented, and control logic is implemented in the STWI_Link according to the STWI communication protocol through IO operation.

[0097] The target chip 22 is configured to receive the debugging signal sent by the debugging emulator through the signal line, obtain the debugging data according to the debugging signal, perform debugging processing according to the debugging data to obtain the debugging result, and send the result signal to the debugging emulator through the signal line according to the debugging result.

[0098] In one embodiment, the target chip 22 includes a debugging transmission module 220, a debugging module interface 221, a register and a processor 222.

[0099] The debugging transmission module 220 is connected with the debugging client through a signal line, for receiving the debugging signal sent by the debugging emulator 21 through the signal line, and sending the result signal to the debugging emulator 21 through the signal line;

[0100] The debugging module interface 221 is connected with the debugging transmission module 220, for obtaining the debugging data according to the debugging signal, and obtaining the debugging result by performing debugging processing according to the debugging data, the register and the processor 222.

[0101] The STWI debugging interface includes an STWI communication protocol and an STWI interface controller. The STWI debugging module interface controls the RISC-V processor, including pausing execution, single-step execution, and accessing and modifying register / memory values; supports setting breakpoints and watchpoints; and provides access to the entire system, including memory and peripherals. The STWI interface configures two debugging pins, and the defined interface signals are a clock CLOCK and an STWI IO, wherein the STWI IO is a bidirectional data signal used to transmit commands and data.

[0102] In an embodiment, the target chip further includes a system bus 223, a trigger module 224, an sram (static random access memory), an eflash (embedded flash memory), and peripherals, which are collectively a component 225. In the debugging process, a watchpoint is a very useful tool that allows you to monitor changes to specific memory addresses or variables while a program is running. When the contents of the monitored memory location change, the debugger will pause execution and notify you of the change. This is particularly useful for catching hard-to-trace bugs, such as unexpected data modifications. The trigger module is used to monitor a certain memory address and pause execution when a change occurs.

[0103] In an embodiment, the register includes a debugging module interface register;

[0104] The debugging transmission module 220 is configured to store the debugging signal and the result signal into the debugging module interface register.

[0105] The corresponding register of the debugging transmission module 220 is a DMIDebug register, which is usually directly related to the STWI module (located in the debugging transmission module, and the development board under debugging receives information and feeds back to the CPU). It can control the CPU to run in single-step and HALT states, set hardware breakpoints, and directly read and change PC pointers.

[0106] In the embodiment, the STWI related registers are divided into the following parts: DMIDebug registers, CPU general purpose registers (GPR), CPU control and status registers (CSR), and CPU floating point unit registers (FPR). In addition to the DMIDebug registers mentioned above, there are GPRs, which are the general purpose register set of the processor. The processor cannot directly access the memory, and the data to be processed needs to be moved from the memory to the GPR first and then processed, and after processing, the CPU writes back to the GPR, and then it can be saved to the memory. The CSR is the control status register of the CPU, which is used to store some states and control bits during the running of the CPU, including CPU state, exception enable, exception vector address, exception instruction, and exception type.

[0107] Referring to Figure 6 , a preset protocol interface read register timing diagram of a chip debugging system is shown, which represents the timing of reading the DMIDebug register through the STWI interface. To read the DMIDebug register, a write command needs to be sent first, and then the data is read. The steps are similar to the data packet flow in the previous text, and thus will not be described again.

[0108] Referring to Figure 7 , a preset protocol interface write register timing diagram of a chip debugging system is shown, which represents the timing of writing the DMIDebug register through the STWI interface. To write the DMIDebug register, a write command needs to be sent first, and then the data is written. The steps are similar to the data packet flow in the previous text, and thus will not be described again.

[0109] In an embodiment, the signal line includes a data signal line 23.

[0110] The debugging emulator 21 is configured to send a debugging signal to the target chip 22 through the data signal line 23 according to the debugging data, and receive a result signal sent by the target chip 22 through the data signal line.

[0111] In an embodiment, the signal line further includes a clock signal line 24.

[0112] The debugging emulator 21 is further configured to send a clock signal to the target chip 22 through the clock signal line 24.

[0113] The configuration of interface signals as clock (CLOCK) and data (IO) is usually used for some specific communication protocols or hardware interfaces, such as SPI (Serial Peripheral Interface), I 2The specific configuration and usage of these interface signals depend on the specific communication protocol and hardware design. The clock signal is a very important signal in synchronous communication protocols, which provides the timing reference for data transmission. The IO data signal is usually bidirectional and can be used for data transmission. In different communication protocols, the specific name and function of the IO data signal are different.

[0114] The chip debugging system of the embodiment of the application comprises a host, a debugging emulator and a target chip; the debugging emulator is connected with the host and the target chip; the host detects a debugging operation of a user and generates debugging data, encapsulates the debugging data into a first data packet in a preset protocol format, and also receives a second data packet in the preset protocol format sent by the debugging emulator; the debugging emulator receives the first data packet sent by the host and parses the first data packet into debugging data, sends a debugging signal to the target chip through a signal line according to the debugging data, receives a debugging signal fed back by the target chip to obtain a debugging result, encapsulates the debugging result into the second data packet in the preset protocol format, and sends the second data packet to the host; the target chip receives the debugging signal sent by the debugging emulator through the signal line, obtains debugging data according to the debugging signal, performs debugging processing to obtain a debugging result, and sends a result signal to the debugging emulator through the signal line according to the result. The preset protocol of the application can realize RISC-V MCU simulation, debugging and burning by using only one signal line of a RISC-V MCU chip to transmit a data packet, solves the problem that a RISC-V CPU does not support a SWD protocol, and increases the market competitiveness of the RISC-V MCU chip.

[0115] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0116] Those skilled in the art should understand that the embodiments of the application can be provided as a method, an apparatus or a computer program product. Therefore, the embodiments of the application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0117] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0118] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0119] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, such that a series of operational steps are performed on the computer or other programmable terminal devices to produce a computer implemented process so that the instructions which execute on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0120] Although preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to the embodiments without departing from the scope of the present application. Accordingly, the appended claims are intended to encompass all such modifications and variations as falling within the scope of the present application.

[0121] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other closure, are intended to cover the non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include those elements alone but can include other elements not expressly listed or even include elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0122] The above describes in detail the chip debugging system provided by the present application, and the principles and implementation modes of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A chip debugging system, characterized by, The application relates to a debugging system, which comprises a host, a debugging emulator and a target chip. The debugging emulator is connected with the host and the target chip through a signal line. The host is used for detecting a debugging operation of a user. According to the debugging operation, debugging data is generated, and the debugging data is packaged into a first data packet in a preset protocol format. The debugging emulator receives the first data packet sent by the host, analyzes the first data packet to obtain the debugging data, and sends a debugging signal to the target chip through the signal line according to the debugging data. The debugging emulator receives a result signal sent by the target chip through the signal line according to the result signal, obtains a debugging result, packages the debugging result into a second data packet in the preset protocol format, and sends the second data packet to the host. The target chip receives the debugging signal sent by the debugging emulator through the signal line, obtains the debugging data according to the debugging signal, carries out debugging processing according to the debugging data to obtain the debugging result, and sends the result signal to the debugging emulator through the signal line according to the debugging result. The data packet in the preset protocol format comprises a read data data packet and a write data data packet. The read data data packet comprises a start field, a register selection field, a register read-write selection field, a first data signal direction inversion field, a data synchronization field, a read data field, a check field and a second data signal direction inversion field. The write data data packet comprises a start field, a register selection field, a register read-write selection field, a first data signal direction inversion field, a write data field, a check field and a second data signal direction inversion field. The debugging emulator is further used for analyzing the start field, and sending a start signal to the target chip through the signal line. After the start signal is sent, the register selection field is analyzed, and a register selection signal is sent to the target chip through the signal line. After the register selection signal is sent, the register read-write selection field is analyzed, and a register read-write selection signal is sent to the target chip through the signal line; the register read-write selection signal comprises a register read signal or a register write signal. After the register read-write selection signal is sent, the first data signal direction inversion field is analyzed, and a first data signal direction inversion signal is sent to the target chip through the signal line. After the first data signal direction inversion signal is sent, if the register read-write selection signal is a register read signal, the data synchronization field is analyzed, and a data synchronization signal is sent to the target chip through the signal line. After the data synchronization signal is sent, the read data field is analyzed, and a target read data signal is sent to the target chip through the signal line. ​ ​ After sending the first data signal direction reversal signal, if the register read-write selection signal is a register write signal, the write data field is parsed, and a target write data signal is sent to the target chip through the signal line; After sending the target read data signal or the target write data signal, the check field is parsed, and a check signal is sent to the target chip through the signal line; After sending the check signal, the second data signal direction reversal field is parsed, and a second data signal direction reversal signal is sent to the target chip through the signal line.

2. The chip debugging system of claim 1, wherein, The data packet in the preset protocol format includes a plurality of fields: The debugging emulator is configured to parse the plurality of fields in the first data packet to obtain the debugging data, and send a debugging signal to the target chip through the signal line according to the debugging data; The host is configured to parse the plurality of fields in the second data packet to obtain a debugging result.

3. The chip debugging system of claim 1, wherein, The signal line includes a data signal line; The debugging emulator is configured to send a debugging signal to the target chip through the data signal line according to the debugging data, and receive a result signal sent by the target chip through the data signal line.

4. The chip debugging system according to claim 3, wherein The signal line further includes a clock signal line; The debugging emulator is further configured to send a clock signal to the target chip through the clock signal line.

5. The system of claim 1, wherein, The target chip includes a debugging transmission module, a debugging module interface, a register, and a processor; The debugging transmission module is connected with the debugging emulator through a signal line, and is configured to receive the debugging signal sent by the debugging emulator through the signal line, and send the result signal to the debugging emulator through the signal line; The debugging module interface is connected with the debugging transmission module, and is configured to obtain the debugging data according to the debugging signal, and obtain the debugging result by performing debugging processing according to the debugging data, the register, and the processor.

6. The chip debug system of claim 5, wherein, The register includes a debugging module interface register; The debugging transmission module is configured to store the debugging signal and the result signal into the debugging module interface register.

7. The system of claim 1, wherein, The host includes a debugging client and a debugging proxy server; The debugging client is configured to detect a debugging operation of a user; The debugging proxy server is connected with the debugging client and the debugging emulator, and is configured to generate debugging data according to the debugging operation, encapsulate the debugging data into a first data packet in a preset protocol format, and send the first data packet to the debugging emulator; And receive a second data packet in the preset protocol format sent by the debugging emulator.

8. The system of claim 7, wherein, The host further includes a configuration library, The debugging proxy server is configured to obtain chip information of the target chip from the configuration library, and send the chip information of the target chip to the debugging client; The debugging client is configured to show the chip information of the target chip to the user.

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