Chip signal verification method and device, verification equipment

Abstract

The present application relates to the field of chip technology, and discloses a chip signal verification method and device, and verification equipment, wherein the verification method is applied to a signal detection component, and the verification method includes: in a chip verification environment, instantiating the signal detection component according to the bit width parameter and configuration information of the signal to be detected; after the instantiation is completed, enabling the signal detection component in the test process, so that the signal detection component performs simulation verification on the signal to be detected according to the configuration information; and obtaining the simulation verification result output by the signal detection component. During the simulation verification process, the signal detection component can detect the abnormality of the signal in real time, and record and report the error in time, thereby improving the accuracy and timeliness of the chip signal verification.

Description

Technical Field

[0001] The present application relates to the field of chip technology, for example, to a chip signal verification method and device, and verification equipment. Background Art

[0002] In the chip system, some signals play a vital role, such as interrupt, alarm, enable and other indication and control signals. These signals notify the processor and other modules in the chip through level or edge that important events have occurred in the chip, such as input / output operation completion, abnormal situation occurrence, etc. The accuracy and timeliness of these important signals directly affect the performance and stability of the chip. Therefore, accurate and timely verification of important signals in the chip is a key issue in chip verification.

[0003] The chip signal verification method in the related art reads the signal status register value in the test case, and then detects whether the signal on the signal line is set when the signal status register value shows that the signal has been set. Or wait for the state of the signal line to be set, and then compare it with the value in the signal status register.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The signal detection logic only detects when the reset is released and when the status register jumps. It cannot detect changes in the signal at other time points, resulting in inaccurate and untimely signal detection.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a chip signal verification method and device, and a verification device to improve the accuracy and timeliness of chip signal verification.

[0009] In some embodiments, the verification device includes: a signal detection component.

[0010] Optionally, the signal detection component includes an interface module and a signal detection agent module. The signal detection agent module includes a monitor module and a configuration module. The interface module is connected to the monitor module, and the monitor module is connected to the configuration module. The interface module is configured to pass the signal to be detected, the clock signal and the reset signal to the monitor module. The monitor module is configured to verify the signal to be detected according to the clock signal and the reset signal. The configuration module is configured to configure the monitor module so that the monitor module verifies according to the configuration information in the configuration module.

[0011] In some embodiments, a chip signal verification method is applied to a signal detection component, and the verification method includes: in a chip verification environment, instantiating the signal detection component according to the bit width parameters and configuration information of the signal to be detected; after the instantiation is completed, enabling the signal detection component in the test process so that the signal detection component simulates and verifies the signal to be detected according to the configuration information; and obtaining the simulation verification result output by the signal detection component.

[0012] Optionally, the signal detection component is instantiated, including: instantiating an interface module in the top-level module of the chip verification environment according to the bit width parameter, and connecting the signal to be detected, the clock signal and the reset signal to the interface module; and, in the chip verification environment, instantiating a monitor module, and connecting the monitor module to the interface module; and, according to the configuration information, instantiating a configuration module in the configuration file of the chip verification environment, and connecting the configuration module to the monitor module.

[0013] Optionally, the signal detection component simulates and verifies the detection signal in one or more of the following ways: performing signal state detection on the detection signal; performing signal jump detection on the detection signal; counting the setting time of the detection signal; judging the detection data of the detection signal and printing the judgment result.

[0014] Optionally, a signal status detection is performed on the signal to be detected, including: after the chip verification environment reset is released, determining whether the configuration information allows the signal to be detected to jump on the line; when the configuration information does not allow the signal to be detected to jump on the line, performing a reset value detection on the signal to be detected to determine whether the reset value of the signal to be detected is consistent with the configuration value in the configuration information; when the reset value is consistent with the configuration value, returning to the process of determining whether the configuration information allows the signal to be detected to jump on the line; when the reset value is inconsistent with the configuration value, reporting a reset value error of the signal to be detected, recording and printing the error time, and returning to the process of determining whether the configuration information allows the signal to be detected to jump on the line.

[0015] Optionally, performing signal status detection on the signal to be detected also includes: when the configuration information allows line transitions on the signal to be detected, turning off reset value detection on the signal to be detected to determine whether the next reset signal is set; when the next reset signal is set, restarting the signal detection enable to perform reset value detection on the signal to be detected; when the next reset signal is not set, returning to wait for the next reset signal to be set.

[0016] Optionally, a signal jump detection is performed on the signal to be detected, including: after the chip verification environment is reset and released, detecting the online jump situation of the signal to be detected, and judging whether the configuration information allows the online jump of the signal to be detected; when the configuration information allows the online jump of the signal to be detected, each jump of the signal to be detected is defined as a legal jump, and the legal jump time information of the signal to be detected is recorded, and the correct signal to be detected jump counter is started to count the number of legal jumps, and after the counting is completed, the signal jump detection process is returned; when the configuration information does not allow the online jump of the signal to be detected, each jump of the signal to be detected is defined as an illegal jump, and the illegal jump time information of the signal to be detected is recorded, and the wrong signal to be detected jump counter is started to count the number of illegal jumps, and after the counting is completed, the signal jump detection process is returned.

[0017] Optionally, performing signal jump detection on the signal to be detected further includes: comparing the legal jump number and the illegal jump number of the signal to be detected with the expected jump number in the configuration information, and when the comparison results are inconsistent, reporting the jump number mismatch.

[0018] In some embodiments, a chip signal verification device includes a processor and a memory storing program instructions, and the processor is configured to execute the chip signal verification method as described above when running the program instructions.

[0019] Optionally, the verification device further comprises: a verification device for chip signals as described above, connected to the signal detection component.

[0020] The chip signal verification method, device, and verification equipment provided by the embodiments of the present disclosure can achieve the following technical effects:

[0021] In the disclosed embodiment, the bit width parameter can be determined according to the characteristics of the signal to be detected, and then in the chip verification environment, the bit width parameter is passed to the signal detection component, and the signal detection component is instantiated, which can ensure that the signal detection component can correctly identify and process the signal to be detected according to the configuration information. The signal detection component is enabled in the test process, so that the signal detection component starts to simulate and verify the signal to be detected according to the configuration information. During the simulation verification process, the signal detection component can detect the abnormality of the signal in real time, and record and report the error in time, thereby improving the accuracy and timeliness of the chip signal verification. In addition, the function for chip signal detection is integrated into a signal detection component, which reduces the complexity of the verification environment, makes the verification process more concise and efficient, and can effectively detect the problems of signal underreporting, false alarms and overreporting.

[0022] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0024] Figure 1 is a structural schematic diagram of a signal detection component provided by an embodiment of the present disclosure;

[0025] Figure 2 is a schematic diagram of a signal detection component provided by an embodiment of the present disclosure implemented in a chip verification environment;

[0026] Figure 3 is a schematic diagram of a chip signal verification method provided by an embodiment of the present disclosure;

[0027] Figure 4 is a schematic diagram of a simulation verification process of a signal detection component provided by an embodiment of the present disclosure;

[0028] Figure 5 is a schematic diagram of a reset value detection process of a signal detection component provided by an embodiment of the present disclosure;

[0029] Figure 6 is a schematic diagram of a signal transition detection process of another signal detection component provided in an embodiment of the present disclosure;

[0030] Figure 7 It is a schematic diagram of a chip signal verification device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0032] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0033] Unless otherwise stated, the term "plurality" means two or more.

[0034] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0035] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0036] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0037] The present disclosure provides a verification device, including a signal detection component. Figure 1 As shown, the signal detection component 10 includes an interface module 20 and a signal detection agent module 30. The signal detection agent module 30 includes a monitor module 31 and a configuration module 32. The interface module 20 is connected to the monitor module 31, and the monitor module 31 is connected to the configuration module 32.

[0038] The interface module 20 is configured to pass the signal to be detected, the clock signal and the reset signal to the monitor module 31. The monitor module 31 is configured to verify the signal to be detected according to the clock signal and the reset signal. The configuration module 32 is configured to configure the monitor module 31 so that the monitor module 31 performs verification according to the configuration information in the configuration module 32.

[0039] The signal detection component 10 provided in the embodiment of the present disclosure includes an interface module 20 and a signal detection agent module 30. The signal detection agent module 30 includes a monitor module 31 and a configuration module 32. Figure 2 As shown, when verifying the chip signal, in the chip verification environment, the interface module 20 receives the signal to be detected of the DUT (Design Under Test), as well as the clock signal and the reset signal, and passes these signals to the monitor module 31. The monitor module 31 monitors and verifies the signal to be detected in real time according to the received clock signal and reset signal. The configuration module 32 configures the monitor module 31, including setting detection rules, thresholds, expected signal behaviors, etc. After the configuration is completed, the monitor module 31 performs specific verification tasks according to the configuration information provided by the configuration module 32, such as the reset value, jump, and set duration of the detection signal. Once the monitor module 31 detects an abnormality or error, it will report the error according to the configured rules and record the error information.

[0040] The signal detection component provided by the embodiment of the present disclosure will continuously detect the signal to be detected from the beginning to the end of the test scenario. If an error is detected, the error will be reported in time, and the type of error and the time of the error occurring in the signal to be detected will be recorded. The signal detection component supports the detection functions of various signal anomalies, and can effectively detect the problems of underreporting, false alarm and overreporting of the signal to be detected. The signal detection component can be used in module-level, subsystem-level and system-level verification environments, and can also be used in verification scenarios such as various important signals of various chip modules, such as interrupt signals and alarm signals, to improve chip verification efficiency and reduce chip tape-out risks. In the verification environment, you only need to complete the instantiation and configuration of the signal detection component. The signal detection component will automatically detect the signal to be detected according to the configuration in all test cases, without adding additional cases.

[0041] Optionally, the signal detection component is based on UVM (Universal Verification Methodology) verification methodology and is written in SystemVerilog language.

[0042] In this embodiment, UVM provides a set of standardized verification methodology, which helps to ensure the consistency and systematicness of the verification process. UVM supports componentized and hierarchical verification environment construction, so that the signal detection component can be easily integrated into a larger verification environment. SystemVerilog is a language for electronic system-level modeling, architecture exploration and hardware design, which is suitable for the writing of verification components. SystemVerilog supports object-oriented programming, making the code more modular, easy to manage and maintain. Therefore, the signal detection component is written based on UVM verification methodology and SystemVerilog language, which provides powerful functions and flexibility for the signal detection component, can adapt to various complex verification scenarios, and improve the efficiency and accuracy of verification.

[0043] Optionally, the monitor module supports simultaneous detection of multi-bit signals.

[0044] In this embodiment, the monitor module can detect multiple bits of signals at the same time, reducing the time and resources required for detecting each bit separately, and improving the efficiency of the verification process. In addition, there is no need to write separate detection logic for each bit, reducing code redundancy and simplifying the complexity of the verification environment. The simultaneous detection of multi-bit signals can also ensure that all bits are monitored, improving the coverage of the detection and ensuring that there are no omissions.

[0045] Combination Figure 3 As shown, the present disclosure is applied to the above-mentioned signal detection component. An embodiment of the present disclosure provides a chip signal verification method. The execution subject of the verification method may be a processor. The verification method includes:

[0046] S301: In a chip verification environment, the processor instantiates a signal detection component according to a bit width parameter and configuration information of a signal to be detected.

[0047] S302, after instantiation is completed, the processor enables the signal detection component in the test process, so that the signal detection component performs simulation verification on the signal to be detected according to the configuration information.

[0048] S303: The processor obtains a simulation verification result output by the signal detection component.

[0049] In the disclosed embodiment, the bit width parameter can be determined according to the characteristics of the signal to be detected, and then in the chip verification environment, the bit width parameter is passed to the signal detection component, and the signal detection component is instantiated, which can ensure that the signal detection component can correctly identify and process the signal to be detected according to the configuration information. The signal detection component is enabled in the test process, so that the signal detection component starts to simulate and verify the signal to be detected according to the configuration information. During the simulation verification process, the signal detection component can detect the abnormality of the signal in real time, and record and report the error in time, thereby improving the accuracy and timeliness of the chip signal verification. In addition, the function for chip signal detection is integrated into a signal detection component, which reduces the complexity of the verification environment, makes the verification process more concise and efficient, and can effectively detect the problems of signal underreporting, false alarms and overreporting.

[0050] Optionally, the signal detection component is instantiated, including: instantiating an interface module in the top-level module of the chip verification environment according to the bit width parameter, and connecting the signal to be detected, the clock signal and the reset signal to the interface module; and, in the chip verification environment, instantiating a monitor module, and connecting the monitor module to the interface module; and, according to the configuration information, instantiating a configuration module in the configuration file of the chip verification environment, and connecting the configuration module to the monitor module.

[0051] In this embodiment, the instantiation of the signal detection component includes the instantiation of three modules: the interface module, the monitor module and the configuration module. Wherein, the instantiation of the interface module is realized by defining the instance of the interface module according to the bit width parameter of the signal to be detected in the top-level module of the chip verification environment testbench, and the signal to be detected, the clock signal and the reset signal are connected to the interface module to ensure that the signal detection component can correctly detect the signal to be detected according to the change of the clock and reset signal. The instantiation of the monitor module is realized by defining the instance of the monitor module in the appropriate position of the chip verification environment, such as a certain level of the testbench, and the monitor module is connected to the interface module so that the monitor can receive and process the signal from the interface module. The instantiation of the configuration module is realized by defining the instance of the configuration module according to the configuration information in the configuration file of the chip verification environment, such as the configuration database in the UVM environment, by setting the configuration parameters, including detection rules, threshold values, expected signal behaviors, etc., to ensure that the monitor module can perform correct signal verification according to these configuration information, and the configuration module is connected to the monitor module at the same time, so that the monitor module can perform signal detection according to the configuration information in the configuration module.

[0052] Combination Figure 4 As shown, the simulation verification process of the signal detection component provided by the embodiment of the present disclosure includes:

[0053] S401, the signal detection component enters a signal detection phase in response to an enable signal.

[0054] S402, the signal detection component enters a simulation test scenario to perform simulation verification on the signal to be detected.

[0055] S403, the signal detection component ends the simulation test scenario and outputs the simulation verification result.

[0056] S404, the signal detection component exits the signal detection phase and prints the simulation verification result.

[0057] Optionally, the signal detection component simulates and verifies the detection signal in one or more of the following ways: performing signal state detection on the detection signal; performing signal jump detection on the detection signal; counting the setting time of the detection signal; judging the detection data of the detection signal and printing the judgment result.

[0058] In this embodiment, the signal detection component can comprehensively simulate and verify the signal to be detected to ensure that the behavior of the signal meets the design expectations. Signal state detection refers to the monitor module checking whether the state of the signal to be detected at a specific time point meets expectations, including the high and low levels of the signal, valid / invalid states, etc. Signal state detection includes reset value detection. Signal jump detection refers to the monitor module detecting changes in the signal state, such as jumps from low to high or from high to low. Set-up duration statistics refers to the monitor module counting the total duration of the signal being set, by recording the duration of each signal being set, and finally adding up all the recorded set-up durations to obtain the total duration of the signal being set. The set-up duration includes the total duration of the signal maintaining a high level. Judging the detection data of the signal to be detected refers to the monitor module judging whether the detection data is correct after the simulation verification is completed, and outputting the judgment result to the log.

[0059] Optionally, a signal status detection is performed on the signal to be detected, including: after the chip verification environment reset is released, determining whether the configuration information allows the signal to be detected to jump on the line; when the configuration information does not allow the signal to be detected to jump on the line, performing a reset value detection on the signal to be detected to determine whether the reset value of the signal to be detected is consistent with the configuration value in the configuration information; when the reset value is consistent with the configuration value, returning to the process of determining whether the configuration information allows the signal to be detected to jump on the line; when the reset value is inconsistent with the configuration value, reporting a reset value error of the signal to be detected, recording and printing the error time, and returning to the process of determining whether the configuration information allows the signal to be detected to jump on the line.

[0060] Combination Figure 5 As shown, the embodiment of the present disclosure provides a process of a signal detection component performing reset value detection, including:

[0061] S501, the signal detection component completes the signal detection enabling configuration.

[0062] S502, the signal detection component determines whether the signal detection is enabled, if so, execute S503, if not, execute S502.

[0063] S503, the signal detection component determines whether the reset signal is released, if so, execute S504, if not, execute S503.

[0064] S504, the signal detection component determines whether the configuration information allows the jump on the signal line to be detected, if not, execute S505, if so, execute S508.

[0065] S505: The signal detection component performs reset value detection on the signal to be detected.

[0066] S506, the signal detection component determines whether the reset value of the signal to be detected is consistent with the configuration value, if so, execute S504, if not, execute S507.

[0067] S507, the signal detection component reports that the reset value of the signal to be detected is wrong, records and prints the error time, and executes S504.

[0068] S508: The signal detection component turns off reset value detection of the signal to be detected.

[0069] S509, the signal detection component determines whether the next reset signal is set, if so, execute S503, if not, execute S508.

[0070] In this embodiment, the signal state detection of the signal to be detected includes reset value detection. According to the configuration information in the signal detection component, after the signal detection component is enabled, the reset signal is released, so that the chip verification environment is reset and released. At this time, the detector module will first determine whether the configuration information allows the signal to be detected to jump online. In the case where the configuration information does not allow the signal to be detected to jump online, the monitor module can automatically detect the reset value of the signal to be detected, and report an error when it is found that the reset value does not match the configuration value, so that the error time can be recorded and printed, and the reset value detection of the next time point is performed. Reset value detection can be performed on the signal to be detected by implementing a task or function in the monitor module, and this task or function should be executed immediately after the reset is released. If the detected reset value is inconsistent with the configuration value, the error is reported using the error reporting mechanism of UVM.

[0071] Optionally, performing signal status detection on the signal to be detected also includes: when the configuration information allows line transitions on the signal to be detected, turning off reset value detection on the signal to be detected to determine whether the next reset signal is set; when the next reset signal is set, restarting the signal detection enable to perform reset value detection on the signal to be detected; when the next reset signal is not set, returning to wait for the next reset signal to be set.

[0072] In this embodiment, the monitor module will turn off the reset value detection of the signal to be detected when the configuration information allows the jump on the signal line to be detected, thereby avoiding the erroneous return of bit value errors during the expected signal jump period and improving the accuracy of the detection. When the next reset signal is received, it is re-determined whether the configuration information allows the jump on the signal line to be detected, and when the configuration information does not allow the jump on the signal line to be detected, the reset value detection of the signal to be detected is restarted to ensure that the signal state can be immediately verified to be as expected after the signal is reset. By dynamically controlling the reset value detection of the signal, specific detection can be flexibly turned on or off according to the needs of the test case, making the verification process more flexible and adaptable.

[0073] Optionally, a signal jump detection is performed on the signal to be detected, including: after the chip verification environment is reset and released, detecting the online jump situation of the signal to be detected, and judging whether the configuration information allows the online jump of the signal to be detected; when the configuration information allows the online jump of the signal to be detected, each jump of the signal to be detected is defined as a legal jump, and the legal jump time information of the signal to be detected is recorded, and the correct signal to be detected jump counter is started to count the number of legal jumps, and after the counting is completed, the signal jump detection process is returned; when the configuration information does not allow the online jump of the signal to be detected, each jump of the signal to be detected is defined as an illegal jump, and the illegal jump time information of the signal to be detected is recorded, and the wrong signal to be detected jump counter is started to count the number of illegal jumps, and after the counting is completed, the signal jump detection process is returned.

[0074] Combination Figure 6 As shown, the embodiment of the present disclosure provides a process of a signal detection component performing signal transition detection, including:

[0075] S601, the signal detection component completes the signal detection enabling configuration.

[0076] S602, the signal detection component determines whether the signal detection is enabled, if so, execute S603, if not, execute S602.

[0077] S603, the signal detection component determines whether the reset signal is released, if so, execute S604, if not, execute S603.

[0078] S604: The signal detection component detects the online transition of the signal to be detected.

[0079] S605, the signal detection component determines whether the configuration information allows the jump on the signal line to be detected. If so, execute S606, if not, execute S608.

[0080] S606, the signal detection component defines each jump of the signal to be detected as a legal jump, and records the legal jump time information of the signal to be detected.

[0081] S607, the signal detection component starts the correct signal transition counter to be detected to count the number of legal transitions, and executes S604 after the counting is completed.

[0082] S608, the signal detection component defines each jump of the signal to be detected as an illegal jump, and records the illegal jump time information of the signal to be detected.

[0083] S609, the signal detection component starts the error detection signal transition counter to count the number of illegal transitions, and executes S604 after the counting is completed.

[0084] In this embodiment, before performing signal transition detection on the signal to be detected, it is also necessary to define in the configuration information whether to allow the detection signal to perform online transition. In the signal monitor module, a task or function can be implemented to detect the online transition of the signal and record each transition information. According to whether the configuration information allows the online transition of the signal to be detected, the correct signal to be detected transition counter and the incorrect signal to be detected transition counter are used to record the legal transition times and illegal transition times of the signal to be detected.

[0085] Optionally, performing signal jump detection on the signal to be detected further includes: comparing the legal jump number and the illegal jump number of the signal to be detected with the expected jump number in the configuration information, and when the comparison results are inconsistent, reporting the jump number mismatch.

[0086] In this embodiment, in the reporting stage of the monitor module, the legal and illegal jump times of the signal to be detected are compared with the expected jump times in the configuration information. If the comparison results are inconsistent, the UVM error reporting mechanism is used to report the mismatch in the jump number.

[0087] Optionally, counting the set-up time of the signal to be detected includes: counting the set-up time of the signal to be detected according to each jump of the signal to be detected after the chip verification environment is reset and released.

[0088] In this embodiment, by detecting the signal jump of the signal to be detected, each jump of the signal to be detected can be recorded, and according to the jump of the signal to be detected, the rising edge and the falling edge of the signal can be analyzed, so that the setup time of the signal can be accurately captured and measured, so as to make statistics on the setup time of the signal to be detected. For example, the time interval between a rising edge and the next falling edge of the signal to be detected is taken as a setup time, so that the total setup time of the signal to be detected can be counted. By counting the signal setup time, the coverage of verification can be increased to ensure that all aspects of the signal behavior are checked.

[0089] Combination Figure 7 As shown, an embodiment of the present disclosure provides a chip signal verification device 600, including a processor (processor) 700 and a memory (memory) 701. Optionally, the device may also include a communication interface (Communication Interface) 702 and a bus 703. Among them, the processor 700, the communication interface 702, and the memory 701 can communicate with each other through the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call the logic instructions in the memory 701 to execute the chip signal verification method of the above embodiment.

[0090] In addition, the logic instructions in the memory 701 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0091] The memory 701 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 700 executes the functional application and data processing by running the program instructions / modules stored in the memory 701, that is, implements the chip signal verification method in the above embodiment.

[0092] The memory 701 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory and may also include a non-volatile memory.

[0093] The verification device provided by the embodiment of the present disclosure also includes: the above-mentioned chip signal verification device. The chip signal verification device is installed in the verification device body and connected to the signal detection component. The installation relationship described here is not limited to placement inside the verification device, but also includes installation connections with other components of the verification device, including but not limited to physical connections, electrical connections or signal transmission connections. It can be understood by those skilled in the art that the chip signal verification device can be adapted to a feasible verification device body, thereby realizing other feasible embodiments.

[0094] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned chip signal verification method.

[0095] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0096] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0097] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0098] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0099] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A chip signal verification method, characterized in that: Applied to signal detection components, the verification methods include: In a chip verification environment, a signal detection component is instantiated according to the bit width parameter and configuration information of the signal to be detected; After the instantiation is completed, the signal detection component is enabled in the test process so that the signal detection component performs simulation verification on the signal to be detected according to the configuration information; Get simulation verification results of the signal detection component output.

2. The verification method according to claim 1, characterized in that: The signal detection component includes: an interface module and a signal detection agent module; the signal detection agent module includes a monitor module and a configuration module; the instantiated signal detection component includes: Instantiating an interface module in a top-level module of a chip verification environment according to a bit width parameter, and connecting a signal to be detected, a clock signal, and a reset signal to the interface module; and, In a chip verification environment, instantiating a monitor module and connecting the monitor module to an interface module; and, According to the configuration information, in the configuration file of the chip verification environment, the configuration module is instantiated, and the configuration module is connected with the monitor module.

3. The verification method according to claim 1 or 2, characterized in that: The signal detection component performs simulation verification on the signal to be detected in one or more of the following ways: Perform signal status detection on the signal to be detected; Perform signal jump detection on the signal to be detected; Count the duration of the detection signal. The detection data of the detection signal is judged and the judgment result is printed.

4. The verification method according to claim 3, characterized in that: Perform signal status detection on the signal to be detected, including: After the chip verification environment reset is released, determine whether the configuration information allows the jump on the signal line to be detected; When the configuration information does not allow the line jump of the signal to be detected, the reset value detection is performed on the signal to be detected to determine whether the reset value of the signal to be detected is consistent with the configuration value in the configuration information; If the reset value is consistent with the configuration value, the process returns to determine whether the configuration information allows the jump process on the signal line to be detected; In the case where the reset value is inconsistent with the configuration value, the reset value error of the signal to be detected is reported, and after recording and printing the error time, it returns to determine whether the configuration information allows the online jump process of the signal to be detected.

5. The verification method according to claim 4, characterized in that: Performing signal status detection on the signal to be detected also includes: When the configuration information allows the jump on the signal line to be detected, the reset value detection of the signal to be detected will be turned off to determine whether the next reset signal is set; When the reset signal is set next time, the signal detection is enabled and the reset value detection of the signal to be detected is performed; If the next reset signal is not set, the process returns to wait for the next reset signal to be set.

6. The verification method according to claim 3, characterized in that: Perform signal transition detection on the signal to be detected, including: After the chip verification environment reset is released, the online jump of the signal to be detected is detected to determine whether the configuration information allows the online jump of the signal to be detected; When the configuration information allows the jump on the signal line to be detected, each jump of the signal to be detected is defined as a legal jump, and the legal jump time information of the signal to be detected is recorded, and the correct signal jump counter to be detected is started to count the number of legal jumps. After the counting is completed, the signal jump detection process is returned; When the configuration information does not allow jumps on the signal to be detected line, each jump of the signal to be detected is defined as an illegal jump, and the illegal jump time information of the signal to be detected is recorded, and the error signal to be detected jump counter is started to count the number of illegal jumps. After the counting is completed, the signal jump detection process is returned.

7. The verification method according to claim 3, characterized in that: Performing signal transition detection on the signal to be detected also includes: The legal hopping number and illegal hopping number of the signal to be detected are compared with the expected hopping number in the configuration information. If the comparison results are inconsistent, the reported hopping number does not match.

8. A chip signal verification device, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the chip signal verification method according to any one of claims 1 to 7 when running the program instructions.

9. A verification device, characterized in that: include: signal detection component; The chip signal verification device as described in claim 8 is connected to the signal detection component.

10. The verification device according to claim 9, characterized in that: The signal detection component includes: an interface module and a signal detection agent module; the signal detection agent module includes a monitor module and a configuration module; the interface module is connected to the monitor module, and the monitor module is connected to the configuration module; The interface module is configured to transmit the signal to be detected, the clock signal and the reset signal to the monitor module; The monitor module is configured to verify the signal to be detected based on the clock signal and the reset signal; The configuration module is configured to configure the monitor module so that the monitor module performs verification according to the configuration information in the configuration module.

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