Computer testing method and system based on machine learning

Abstract

The present invention provides a computer testing method and system based on machine learning. First, the original test sample set (including execution order identifier) ​​and the expected test result set of the target test task are obtained, and the original test sample set is sequentially preprocessed to generate an initial test path. Then, the pre-trained machine learning test model is called to analyze the execution dependency relationship of each test node in the initial test path, and the node arrangement order is adjusted accordingly to obtain an optimized test path. Subsequently, the test sample is executed according to the optimized path to obtain the actual execution result, and the difference is verified with the expected result to generate a test difference report. Finally, the optimized path is corrected according to the report to obtain the final test path, and it is associated with the actual execution result and stored in the test database. This method improves the accuracy, comprehensiveness and intelligence of computer testing, and can effectively optimize the test process.

Description

Technical Field

[0001] The present invention relates to the technical field of machine learning, and in particular to a computer testing method and system based on machine learning. Background Art

[0002] As computer technology continues to develop, the functions of computer systems and software are becoming increasingly complex and diverse, and comprehensive, accurate and efficient testing of them is becoming increasingly important. The purpose of computer testing is to discover potential defects and problems in the system or software and ensure that it can run stably and reliably.

[0003] There are many deficiencies in existing computer testing methods. Most traditional testing methods use pre-set fixed test paths and processes. In this way, the execution order of test samples is often determined based on experience or simple logical order, lacking in-depth consideration of the internal relationship between test samples and the complex dependencies in the actual operating environment. For example, many test processes are simply executed in the order in which the test cases are listed, ignoring the possible order constraints between different test cases during actual execution. This leads to misjudgment of some test cases in some cases due to unsatisfied preconditions, or failure to detect system problems caused by improper execution order.

[0004] At the same time, existing technologies are also limited in processing test results and adjusting test processes. When the actual execution results differ from the expected results, only simple error logging can be performed, and it is difficult to deeply analyze the root cause of the difference and how to effectively adjust the subsequent test process. This makes the test process lack flexibility and adaptability, and the test strategy cannot be optimized in real time according to the actual test situation, resulting in a lot of test time wasted on repeated and ineffective test links, and the test efficiency is low.

[0005] In addition, existing testing methods are difficult to fully consider the intricate dependencies between modules when facing increasingly complex computer systems. Different test samples may have different dependencies on system resources, the status of other modules, etc., and traditional methods cannot accurately capture these dependencies and adjust the test path accordingly, which greatly reduces the comprehensiveness and accuracy of the test and makes it difficult to discover deep-seated system defects. Summary of the invention

[0006] In view of the above-mentioned problems, in combination with the first aspect of the present invention, an embodiment of the present invention provides a computer testing method based on machine learning, the method comprising:

[0007] Acquire an original test sample set and an expected test result set corresponding to a target test task, wherein the original test sample set includes execution order identifiers of multiple test samples, and the expected test result set includes expected execution results corresponding to each test sample;

[0008] Sequentially preprocessing the original test sample set to generate an initial test path matching the target test task, wherein the initial test path is composed of a plurality of test nodes arranged according to the execution sequence identifier, and each test node corresponds to an execution entry of a test sample;

[0009] Calling a pre-trained machine learning test model, performing execution dependency analysis on each test node in the initial test path, determining the dependency relationship between each test node, and adjusting the node arrangement order of the initial test path based on the dependency relationship to generate an optimized test path;

[0010] According to the node arrangement order of the optimized test path, the test samples corresponding to each test node are executed in sequence to obtain an actual execution result set, and the actual execution result set is verified with the expected test result set to generate a test difference report;

[0011] The optimized test path is corrected according to the test difference report to generate a final test path, and the final test path is associated with the actual execution result set and stored in a test database.

[0012] On the other hand, an embodiment of the present invention also provides a computer testing system based on machine learning, including a processor and a machine-readable storage medium, wherein the machine-readable storage medium is connected to the processor, the machine-readable storage medium is used to store programs, instructions or codes, and the processor is used to execute the programs, instructions or codes in the machine-readable storage medium to implement the above method.

[0013] Based on the above aspects, the embodiment of the present application first obtains the original test sample set and the expected test result set corresponding to the target test task in the test sample processing stage, and sequentially preprocesses the original test sample set to generate an initial test path, breaking the simple preset mode of the test sample execution order in the traditional test method, and constructing the initial test path by using the execution order identifier of the test sample, so that the test process has the initial understanding and integration ability of the task's internal logic from the beginning. In the execution dependency analysis link, the pre-trained machine learning test model is called to conduct an in-depth analysis of each test node in the initial test path, determine the dependency relationship between each test node, and adjust the node arrangement order accordingly to generate an optimized test path. The test path is dynamically analyzed and optimized by introducing a machine learning model, which is different from the fixed and static test path setting in the traditional test method. The use of the machine learning model enables the test path to be adaptively adjusted according to the complex dependency relationship between the test nodes, greatly improving the rationality and effectiveness of the test path, and can more accurately simulate the interaction between each test sample in the actual operating environment, thereby significantly improving the accuracy and comprehensiveness of the test. In the test execution and verification stage, the test samples are executed in sequence according to the optimized test path and the difference degree verification is performed to generate a test difference report. Due to the high rationality of the optimized test path, the actual execution results can better reflect the real system status, and the difference verification is more reliable and targeted. The generated test difference report is no longer a simple result comparison, but contains detailed difference information based on the optimized path analysis, providing rich and accurate data support for subsequent path correction. Finally, the optimized test path is corrected according to the test difference report to generate the final test path, and it is associated with the actual execution result set and stored in the test database, breaking the limitation of the traditional test method that the test path is difficult to adjust once it is determined, so that the test process can be optimized in real time according to the actual execution situation, forming a self-improving closed-loop test system. At the same time, the final test path is associated with the actual execution results and stored, which provides data resources for subsequent test reuse, problem tracing and system performance evaluation, further improving the maintainability and sustainability of the entire test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the execution flow of the computer testing method based on machine learning provided in an embodiment of the present invention.

[0015] Figure 2 It is a schematic diagram of the hardware architecture of a computer testing system based on machine learning provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The present invention will be described in detail below with reference to the accompanying drawings. Figure 1It is a flowchart of a computer testing method based on machine learning provided by an embodiment of the present invention. The computer testing method based on machine learning is introduced in detail below.

[0017] Step S110 , obtaining an original test sample set and an expected test result set corresponding to the target test task, wherein the original test sample set includes execution order identifiers of multiple test samples, and the expected test result set includes expected execution results corresponding to each test sample.

[0018] In this embodiment, it is assumed that in a computer hardware testing scenario, the target test task is to conduct a comprehensive performance and compatibility test on a new type of computer motherboard. The original test sample set contains multiple test samples for different characteristics of the motherboard, and each test sample is marked with an execution order. For example, the first is the electrical performance test of the motherboard CPU slot, and its execution order is marked as 1, indicating that this is the first test sample to be executed. The expected execution result of the test is that within a specific voltage range, the CPU slot can stably provide power to the CPU without voltage fluctuations or short circuits.

[0019] Next is the compatibility test of the motherboard memory slots, with the execution order marked as 2. The expected execution result is that it can be compatible with various types and frequencies of mainstream memory sticks on the market, and there will be no data errors or system crashes during long-term data reading and writing.

[0020] There is also a test of the motherboard BIOS function, with the execution order marked as 3. The expected execution results include the ability to correctly identify various hardware devices, support different startup modes, and be able to perform normal BIOS settings and modifications. These test samples cover various key parts of the motherboard hardware, and the expected test result set clarifies the ideal results expected to be achieved by each test sample, providing a reference standard for subsequent tests.

[0021] Step S120, sequentially preprocessing the original test sample set to generate an initial test path matching the target test task, wherein the initial test path is composed of a plurality of test nodes arranged according to the execution sequence identifier, and each test node corresponds to an execution entry of a test sample.

[0022] For example, for the test scenario of the computer motherboard, the sample identifier and execution order identifier of each test sample in the original test sample set are first extracted, and the initial sequence queue is constructed based on the execution order identifier. For example, the test sample with the sample identifier "CPU slot electrical performance test" has an execution order identifier of 1, which is ranked first in the initial sequence queue.

[0023] Then, the test samples in the initial order queue are traversed, and the test type of each test sample is determined according to the sample identifier. For example, the CPU slot electrical performance test belongs to the hardware performance test type, the memory slot compatibility test belongs to the compatibility test type, and the BIOS function test belongs to the function test type.

[0024] The test samples in the initial sequential queue are classified according to the test type to generate multiple test type sub-queues. There will be hardware performance test type sub-queues, compatibility test type sub-queues, and functional test type sub-queues. And each test type sub-queue is assigned a priority weight. Since hardware performance is the basis of the motherboard, the hardware performance test type sub-queue may be assigned a higher priority weight, such as 0.8; the compatibility test type sub-queue weight is 0.6, and the functional test type sub-queue weight is 0.4.

[0025] Each test type subqueue is sorted according to the priority weight to generate an intermediate test path. In this intermediate test path, the hardware performance test type subqueue is at the front, followed by the compatibility test type subqueue, and finally the function test type subqueue.

[0026] Finally, the internal order of each test type subqueue in the intermediate test path is adjusted so that the test samples in each test type subqueue are rearranged according to the execution order identifier. For example, in the hardware performance test type subqueue, according to the previously determined execution order identifier, the CPU slot electrical performance test is ranked first, and other hardware performance-related test samples are arranged in sequence according to their respective execution order identifiers. In this way, the initial test path is generated. This initial test path determines the order of the tests, starting with the basic test of the motherboard hardware performance and gradually moving to compatibility and functional tests. Each test node corresponds to the execution entry of a test sample, which is convenient for subsequent testing in this order.

[0027] Step S130, calling a pre-trained machine learning test model, performing dependency analysis on each test node in the initial test path, determining the dependency relationship between each test node, and adjusting the node arrangement order of the initial test path based on the dependency relationship to generate an optimized test path.

[0028] Still in the computer motherboard test scenario, the initial test path is converted into a directed graph structure. For example, the test nodes in the initial test path, such as the CPU slot electrical performance test node, the memory slot compatibility test node, and the BIOS function test node, become vertices in the directed graph structure. The execution order between the test nodes corresponds to the edges in the directed graph structure. For example, there is an edge from the CPU slot electrical performance test node to the memory slot compatibility test node, which means that the CPU slot electrical performance test is performed first, and then the memory slot compatibility test is performed.

[0029] Then extract the node features of each test node. Take the CPU slot electrical performance test node as an example. The test type of the corresponding test sample is hardware performance test. The execution time may be short, assuming 10 minutes, and the historical execution success rate is 95%. For the memory slot compatibility test node, the test type is compatibility test. The execution time may be longer, assuming 30 minutes, and the historical execution success rate is 90%.

[0030] At the same time, the edge features of each edge are extracted. For example, the execution order difference value between the edge from the CPU socket electrical performance test node to the memory socket compatibility test node is 1 (because it is an adjacent order), and the number of historical dependency conflicts is 0 (indicating that there have been no problems caused by the order of these two tests in previous tests).

[0031] The directed graph structure, node features, and edge features are input into the machine learning test model. The dependency relationship inference of the directed graph structure is performed through the graph neural network layer in the machine learning test model. For example, in the graph neural network layer, each vertex in the directed graph structure is first initialized to a first feature vector, which is generated based on the node features of the corresponding test node. Each edge is initialized to a second feature vector, which is generated based on the edge features of the corresponding edge.

[0032] Then, multiple iterative calculations are performed through the vertex update unit and the edge update unit. For the vertex update unit, taking the CPU slot electrical performance test node as an example, the second eigenvectors corresponding to all its incoming edges and the first eigenvectors of the adjacent vertices are aggregated to generate vertex aggregation features. For example, if the incoming edge has only an initial source point (assuming it is the starting identification node), its corresponding second eigenvector and the first eigenvector of the adjacent vertex (here is the starting identification node) are aggregated. This vertex aggregation feature is concatenated with the first eigenvector of the current vertex to obtain a concatenated feature vector, which is then input into the fully connected layer for nonlinear transformation to obtain an updated vertex feature vector.

[0033] For the edge update unit, for the edge from the CPU slot electrical performance test node to the memory slot compatibility test node, obtain the updated vertex feature vectors of the two vertices connected by it, and splice the two vertex feature vectors with the second feature vector of the current edge to obtain the edge splicing feature vector, which is input into the fully connected layer for nonlinear transformation to obtain the updated edge feature vector.

[0034] Iterate the vertex update and edge update operations until the preset number of iterations is reached, input the edge feature vector obtained in the last iteration into the dependency strength prediction layer, and output the dependency strength value corresponding to each edge. Assume that after calculation, the dependency strength value from the CPU slot electrical performance test node to the memory slot compatibility test node is 0.8, indicating that there is a strong dependency relationship between the two test nodes.

[0035] The edges in the directed graph structure are screened according to the dependency strength value, and the edges whose dependency strength value exceeds the preset threshold (assuming it is 0.5) are retained, and a dependency graph is constructed based on the retained edges. In this dependency graph, for example, it is found that if the BIOS function test is performed first and then the memory slot compatibility test is performed, the dependency strength value is low and does not meet the requirements. Therefore, based on this dependency graph, the node arrangement order of the initial test path is adjusted, and the BIOS function test node is adjusted to after the memory slot compatibility test node to generate an optimized test path. In this way, the optimized test path is more in line with the actual dependency relationship between the test nodes, which improves the accuracy and efficiency of the test.

[0036] Step S140, according to the node arrangement order of the optimized test path, execute the test samples corresponding to each test node in turn, obtain an actual execution result set, and verify the difference between the actual execution result set and the expected test result set to generate a test difference report.

[0037] In detail, the computer motherboard can be tested according to the optimized test path. First, the CPU socket electrical performance test is performed. During the test, the voltage, current and other parameters of the CPU socket are measured by professional electrical testing equipment to obtain the actual execution results. For example, the voltage actually measured fluctuates within the normal range, without abnormal peaks or valleys, and the current is also stable near the rated value.

[0038] Then, perform the memory slot compatibility test in order, insert multiple memory sticks of different types and frequencies, run large data read and write programs, and observe the system operation. The actual execution result may be that when a high-frequency memory stick is inserted, occasional data read errors occur.

[0039] Then perform the BIOS function test, enter the BIOS setup interface, and check whether each function is working properly. The actual execution result found that some advanced setup options could not be saved.

[0040] These actual execution results are combined into an actual execution result set. Then, each actual execution result in the actual execution result set is parsed to extract key verification indicators. For the actual execution results of the CPU slot electrical performance test, the key verification indicators include the voltage response time (the time from the start of power supply to stability), the presence of error types (such as errors of too high or too low voltage), and the data consistency level (here refers to whether the stability of the power supply remains consistent).

[0041] These key verification indicators are compared item by item with the expected indicators of the corresponding test samples in the expected test result set to generate a list of indicator difference items. For example, in the memory slot compatibility test, it is expected that there will be no data read errors, but in fact there are occasional data read errors, which is an indicator difference item.

[0042] Assign a severity level to each indicator difference item. Since this is a computer motherboard test, it is assumed to be a high-precision task type. For the indicator difference item of data reading error in the memory slot compatibility test, its severity level is raised to the highest level because it involves data accuracy. For some advanced setting options in the BIOS function test, this indicator difference item cannot be saved. Although it also affects the function, its severity is slightly lower than data accuracy. Sort the indicator difference item list according to these severity levels, and generate a test difference report containing the sorted indicator difference item list and the corresponding severity levels. This test difference report records in detail the differences between the actual execution results and the expected results and the severity of each difference, providing a basis for subsequent path correction.

[0043] Step S150: perform path correction on the optimized test path according to the test difference report to generate a final test path, and associate the final test path with the actual execution result set and store them in a test database.

[0044] Specifically, the optimized test path is corrected based on the previously generated test difference report. The test difference report is parsed to determine the target test samples and their corresponding target test nodes in the actual execution result set that differ from the expected test result set. For example, it is determined that the target test sample of the memory slot compatibility test and its corresponding target test node have data read errors.

[0045] Obtain the node correction record of the target test node from the test database. Assume that in previous tests, for the memory slot compatibility test node, there was a correction operation of adjusting the memory bar insertion order or changing the memory bar type, and there was a record of the execution result after the correction.

[0046] Generate multiple candidate correction plans based on the node correction record. For example, one candidate correction plan is to adjust the insertion order of memory sticks, and the other is to replace memory sticks of different brands. Assign a correction priority score to each candidate correction plan. For the solution of adjusting the insertion order of memory sticks, the historical success rate of the correction operation is 60%, and the matching degree between the execution result after correction and the expected result is 80%. The correction priority score is obtained based on the calculation. For the solution of replacing memory sticks of different brands, the historical success rate is 70%, and the matching degree is 90%, and the corresponding correction priority score is obtained.

[0047] Select the candidate correction solution with the highest correction priority score, assuming that it is the solution of replacing memory sticks of different brands, and adjust the execution order or replace the test samples of the target test nodes in the optimized test path. Replace the memory stick in the original memory slot compatibility test with the memory stick of the new brand to generate the adjusted test path.

[0048] Perform secondary verification on the adjusted test path. Obtain the verification test sample set associated with the target test task from the test database. Assume that this verification test sample set contains some special memory bar test samples that are not included in the previous original test sample set. Insert these newly added test samples into the specified position of the adjusted test path. This specified position is determined based on the compatibility of the test type of the newly added test sample with the test type of the existing test nodes in the adjusted test path. For example, if the newly added test sample is a special compatibility test for high-frequency memory bars, insert it near the memory slot compatibility test node.

[0049] Execute all test nodes in the extended test path to obtain an extended execution result set. Perform extended difference verification on the extended execution result set and the expected test result set. If the result of the extended difference verification meets the preset compatibility condition, such as the difference is lower than the preset difference threshold, merge the extended test path into the adjusted test path to generate a merged test path.

[0050] Redundant node detection is performed on the merged test path. If a test node is found during the test process, such as the electrical performance test of a rarely used interface on the motherboard, and its execution result completely matches the expected result and the dependency strength value is lower than the redundancy threshold (assuming it is 0.3), then this test node is removed to generate a streamlined final test path. Finally, the final test path is associated with the actual execution result set and stored in the test database for future query and reference, which also provides experience and data support for subsequent similar computer motherboard tests.

[0051] Based on the above steps, the embodiment of the present application first obtains the original test sample set and the expected test result set corresponding to the target test task in the test sample processing stage, and sequentially preprocesses the original test sample set to generate an initial test path, breaking the simple preset mode of the test sample execution order in the traditional test method. By using the execution order identifier of the test sample to construct the initial test path, the test process has the initial understanding and integration ability of the task's internal logic from the beginning. In the execution dependency analysis link, the pre-trained machine learning test model is called to conduct an in-depth analysis of each test node in the initial test path, determine the dependency relationship between each test node, and adjust the node arrangement order accordingly to generate an optimized test path. The test path is dynamically analyzed and optimized by introducing a machine learning model, which is different from the fixed and static test path setting in the traditional test method. The use of the machine learning model enables the test path to be adaptively adjusted according to the complex dependency relationship between the test nodes, greatly improving the rationality and effectiveness of the test path, and can more accurately simulate the interaction between each test sample in the actual operating environment, thereby significantly improving the accuracy and comprehensiveness of the test. In the test execution and verification stage, the test samples are executed in sequence according to the optimized test path and the difference degree verification is performed to generate a test difference report. Due to the high rationality of the optimized test path, the actual execution results can better reflect the real system status, and the difference verification is more reliable and targeted. The generated test difference report is no longer a simple result comparison, but contains detailed difference information based on the optimized path analysis, providing rich and accurate data support for subsequent path correction. Finally, the optimized test path is corrected according to the test difference report to generate the final test path, and it is associated with the actual execution result set and stored in the test database, breaking the limitation of the traditional test method that the test path is difficult to adjust once it is determined, so that the test process can be optimized in real time according to the actual execution situation, forming a self-improving closed-loop test system. At the same time, the final test path is associated with the actual execution results and stored, which provides data resources for subsequent test reuse, problem tracing and system performance evaluation, further improving the maintainability and sustainability of the entire test process.

[0052] In a possible implementation, step S120 includes:

[0053] Step S121 , extracting the sample identifier and execution sequence identifier of each test sample in the original test sample set, and constructing an initial sequence queue based on the execution sequence identifier.

[0054] In this embodiment, for the computer motherboard test, the sample identifier clarifies the specific part or function of the motherboard targeted by each test sample. For example, the test sample with the sample identifier "Motherboard PCI-E interface bandwidth test" has an execution order identifier of 5, indicating that this test is in the fifth execution position in the overall test process. In this way, all test samples are arranged according to the execution order identifier to construct an initial sequence queue. This initial sequence queue can be understood as a step-by-step execution plan list that determines the preliminary execution order of each test sample.

[0055] Step S122, traverse each test sample in the initial sequence queue, and determine the test type of each test sample according to the sample identifier, wherein the test type includes a function test type, a performance test type, and a compatibility test type.

[0056] For example, the power supply stability test for the motherboard, according to its sample identification, is a performance test type, because it focuses on the motherboard's performance in power supply, such as voltage stability, current supply capacity, etc. As for the motherboard's compatibility test with different graphics cards, it is determined to be a compatibility test type according to the sample identification, and the focus is on whether the motherboard and different graphics cards can work together normally. For example, the basic function test of the motherboard BIOS, such as boot device identification, basic setting saving, etc., is determined to be a function test type according to the sample identification.

[0057] Step S123: classify the test samples in the initial sequential queue according to the test type, generate multiple test type sub-queues, and assign a priority weight to each test type sub-queue.

[0058] In the computer motherboard test scenario, the performance test type subqueue is assigned a higher priority weight, such as 0.8, because the performance of the motherboard is its basic attribute and directly affects the operating efficiency of the entire computer system. The weight of the compatibility test type subqueue is set to 0.6. Although compatibility is also important, it is slightly lower in the test order compared to performance. The weight of the functional test type subqueue is 0.4, because functional testing is more about checking the integrity of various functions of the motherboard based on performance and compatibility. Such different weight allocations reflect the differences in the importance of different test types in the overall test task.

[0059] Step S124 , sorting each test type sub-queue according to the priority weight to generate an intermediate test path, wherein the intermediate test path includes a plurality of test type sub-queues arranged in descending order of priority.

[0060] For example, in this intermediate test path, the performance test type subqueue is ranked first, followed by the compatibility test type subqueue, and finally the functional test type subqueue, which means that during the test, the motherboard's various performance indicators will be tested first, then its compatibility will be checked, and finally the functional integrity will be tested. This order helps to ensure the basic performance of the motherboard and its compatibility with other hardware first, and then comprehensively check whether all functions are normal on this basis.

[0061] Step S125 , adjusting the internal order of each test type subqueue in the intermediate test path so that the test samples in each test type subqueue are rearranged according to the execution order identifier to generate the initial test path.

[0062] Inside the performance test type subqueue, for example, there are mainboard CPU slot electrical performance tests, mainboard memory slot electrical performance tests, and so on. According to the execution order identifier, if the execution order identifier of the CPU slot electrical performance test is 1, and the execution order identifier of the memory slot electrical performance test is 2, then the order is followed within the performance test type subqueue. The same operation is performed for the compatibility test type subqueue and the functional test type subqueue, thereby generating an initial test path. This initial test path determines a more reasonable test order, starting with the basic test of the mainboard performance and gradually transitioning to compatibility and functional tests. Each test node corresponds to the execution entry of a test sample, laying a good foundation for subsequent test processes.

[0063] In a possible implementation, step S130 includes:

[0064] Step S131 : converting the initial test path into a directed graph structure, wherein the vertices in the directed graph structure correspond to the test nodes in the initial test path, and the edges in the directed graph structure correspond to the execution order between the test nodes.

[0065] For example, the mainboard CPU slot electrical performance test node, the mainboard memory slot compatibility test node, the mainboard BIOS function test node, etc. all become vertices in the directed graph. The edges in the directed graph structure correspond to the execution order between the test nodes. For example, there is an edge from the mainboard CPU slot electrical performance test node to the mainboard memory slot compatibility test node, which means that the CPU slot electrical performance test is performed first in the test process, followed by the memory slot compatibility test.

[0066] Step S132, extracting node features of each test node, wherein the node features include the test type, execution time and historical execution success rate of the corresponding test sample.

[0067] Taking the mainboard CPU slot electrical performance test node as an example, the test type of the corresponding test sample is the performance test type, and the execution time may be short, assuming 10 minutes, which is the average execution time based on the experience of multiple previous tests. The historical execution success rate is 95%, which is obtained by counting the results of multiple CPU slot electrical performance tests in the past. For the mainboard memory slot compatibility test node, the test type is the compatibility test, and the execution time may be longer, assuming 30 minutes, because it is necessary to insert multiple different types of memory sticks and perform a large amount of data read and write tests to check compatibility. Its historical execution success rate is 90%.

[0068] Step S133: extract edge features of each edge, where the edge features include an execution order identifier difference value and a historical dependency conflict count between two connected test nodes.

[0069] For example, the edge from the mainboard CPU slot electrical performance test node to the mainboard memory slot compatibility test node has an execution order identification difference value of 1 (because it is an adjacent order), and the number of historical dependency conflicts is 0 (indicating that there have been no problems caused by these two test orders in previous tests). For another example, the edge from the mainboard memory slot compatibility test node to the mainboard BIOS function test node has an execution order identification difference value of 1 and a number of historical dependency conflicts of 2, which means that in past tests, there have been two problems due to these two test orders, probably because when the BIOS function test was performed directly after the memory slot compatibility test, some changes in the memory state affected the results of the BIOS function test.

[0070] Step S134: input the directed graph structure, the node features, and the edge features into the machine learning test model, perform dependency reasoning on the directed graph structure through the graph neural network layer in the machine learning test model, and output the dependency strength value between each test node.

[0071] In the graph neural network layer, each vertex in the directed graph structure is first initialized to the first feature vector, which is generated based on the node features of the corresponding test node. For example, the first feature vector of the mainboard CPU slot electrical performance test node contains information such as its performance test type, 10 minutes of execution time, and 95% historical execution success rate. Each edge is initialized to a second feature vector, which is generated based on the edge features of the corresponding edge. For example, the second feature vector of the edge from the mainboard CPU slot electrical performance test node to the mainboard memory slot compatibility test node contains information such as an execution order identification difference value of 1 and a historical dependency conflict number of 0.

[0072] Step S135, screening the edges in the directed graph structure according to the dependency strength values, retaining the edges whose dependency strength values ​​exceed a preset threshold, and constructing a dependency graph based on the retained edges, wherein the dependency graph is used to describe the node execution order that must be followed in the initial test path.

[0073] For the vertex update unit, taking the motherboard CPU slot electrical performance test node as an example, aggregate the second feature vectors corresponding to all its incoming edges and the first feature vectors of adjacent vertices to generate vertex aggregation features. Assuming that the node has only one incoming edge (from the starting identification node), aggregate the second feature vector of this incoming edge and the first feature vector of the adjacent vertex (starting identification node). Splice this vertex aggregation feature with the first feature vector of the current vertex to obtain a spliced ​​feature vector, which is then input into the fully connected layer for nonlinear transformation to obtain an updated vertex feature vector. For the edge update unit, for the edge from the motherboard CPU slot electrical performance test node to the motherboard memory slot compatibility test node, obtain the updated vertex feature vectors of the two vertices connected to it, and splice the two vertex feature vectors with the second feature vector of the current edge to obtain an edge splicing feature vector, which is input into the fully connected layer for nonlinear transformation to obtain an updated edge feature vector. Iterate the vertex update and edge update operations until the preset number of iterations is reached. Assuming that the preset number of iterations is 10 times, after 10 iterations, the edge feature vector obtained in the last iteration is input into the dependency strength prediction layer, and the dependency strength value corresponding to each edge is output. For example, the dependency strength value from the motherboard CPU slot electrical performance test node to the motherboard memory slot compatibility test node is 0.8, indicating that there is a strong dependency between the two test nodes; while the dependency strength value from the motherboard memory slot compatibility test node to the motherboard BIOS function test node is 0.3, indicating that the dependency between the two test nodes is relatively weak.

[0074] Assuming that the preset threshold is 0.5, the edge from the motherboard CPU slot electrical performance test node to the motherboard memory slot compatibility test node with a dependency strength value of 0.8 is retained, while the edge from the motherboard memory slot compatibility test node to the motherboard BIOS function test node with a dependency strength value of 0.3 may be discarded. The constructed dependency graph describes the node execution order that must be followed in the initial test path. For example, this graph clearly states that the motherboard CPU slot electrical performance test must be completed before the motherboard memory slot compatibility test. This order is determined based on the dependencies between the test nodes, which helps to improve the accuracy and efficiency of the test and avoid erroneous results or additional testing costs caused by unreasonable test sequences.

[0075] In a possible implementation, the training process of the pre-trained machine learning test model includes:

[0076] Step S210, obtaining a historical test task set, wherein the historical test task set includes historical test paths, historical execution results, and historical difference reports corresponding to a plurality of historical test tasks.

[0077] In detail, the historical test path records the test sequence followed when testing the motherboard in the past. For example, in a historical test task, the motherboard CPU slot electrical performance test was performed first, followed by the motherboard memory slot compatibility test, and then the motherboard BIOS function test. This complete test sequence constitutes the historical test path. The historical execution results include the actual results obtained in each test step, such as the actual voltage fluctuation range and current supply stability in the motherboard CPU slot electrical performance test; the data reading and writing speed when different memory sticks are matched with the motherboard slot, whether errors occur, etc. in the motherboard memory slot compatibility test; and whether various functions are running normally and whether there are functional abnormalities in the motherboard BIOS function test. The historical difference report records in detail the differences between the historical execution results and the expected results. For example, in the motherboard memory slot compatibility test, if the expectation is that it can be perfectly compatible with a specific memory stick but a data reading error actually occurs, this difference will be recorded in the historical difference report.

[0078] Step S220 , extracting a historical test node sequence from the historical test path, and marking an actual dependency label for each historical test node, wherein the actual dependency label is used to indicate the dependency type between the historical test node and other historical test nodes.

[0079] Taking the motherboard CPU slot electrical performance test node in the historical test path as an example, its actual dependency label may indicate that it has a strong dependency with the motherboard memory slot compatibility test node, because the stability of the CPU slot electrical performance will affect the compatibility test results of the memory slot. If the CPU slot electrical performance is unstable, it may cause incorrect results in the compatibility test of the memory slot. For the motherboard BIOS function test node, its actual dependency label with the motherboard CPU slot electrical performance test node may be indicated as a weak dependency, because although the CPU slot electrical performance has a certain impact on the BIOS function, it is not a direct and decisive impact. These actual dependency labels accurately reflect the dependency types between various historical test nodes in the actual test process.

[0080] Step S230: convert the historical test node sequence into a historical directed graph structure, and extract the historical node features of each historical test node and the historical edge features of each historical edge.

[0081] In the constructed historical directed graph structure, the mainboard CPU slot electrical performance test node, the mainboard memory slot compatibility test node, the mainboard BIOS function test node, etc. all become vertices in the graph. The edges represent the execution order relationship between the test nodes. For the historical node features of each historical test node, taking the mainboard CPU slot electrical performance test node as an example, its historical node features include the test type is the performance test type, the execution time is an average of 10 minutes based on multiple previous tests, and the historical execution success rate is 95%. For the historical edge features, such as the edge from the mainboard CPU slot electrical performance test node to the mainboard memory slot compatibility test node, its historical edge features include the execution order identification difference value of 1 (because it is an adjacent order), and the number of historical dependency conflicts is 0 (indicating that no conflicts have occurred due to this order in previous tests).

[0082] Step S240, construct an initial machine learning test model, input the historical directed graph structure, the historical node features and the historical edge features into the initial machine learning test model, and obtain a predicted dependency label.

[0083] In detail, this initial machine learning test model can be built based on a graph neural network. After inputting the data, the initial machine learning test model analyzes the historical directed graph structure through an internal computing mechanism, and uses historical node features and historical edge features for reasoning to derive a predicted dependency label. For example, for the relationship between the motherboard CPU slot electrical performance test node and the motherboard memory slot compatibility test node, the model may predict a dependency label, indicating that there is a certain dependency between the two, and quantify the strength of this dependency.

[0084] Step S250, calculate the label difference loss value between the predicted dependency label and the actual dependency label, and iteratively adjust the parameters of the initial machine learning test model based on the label difference loss value until the label difference loss value converges to obtain the pre-trained machine learning test model.

[0085] Assuming that the actual dependency label indicates that the dependency strength between the motherboard CPU slot electrical performance test node and the motherboard memory slot compatibility test node is 0.8, and the predicted dependency label gives a strength of 0.6, then the label difference loss value between the two will be calculated. According to this label difference loss value, the model will adjust the internal parameters, such as adjusting the weight value in the graph neural network. After inputting different historical test task related data multiple times and continuously calculating the label difference loss value and adjusting the parameters, when the label difference loss value gradually decreases and finally converges to a very small value, the pre-trained machine learning test model is obtained. This pre-trained machine learning test model has learned the dependency pattern between each test node in the historical test task, and can perform dependency analysis on the test nodes in the new test path in the subsequent computer motherboard test task, thereby improving the accuracy and efficiency of the test. In the computer motherboard test scenario, this pre-trained model can accurately analyze the dependency between different test nodes, avoid erroneous results or unnecessary repeated tests caused by unreasonable test order, and help optimize the entire test process.

[0086] In a possible implementation, step S150 includes:

[0087] Step S151, parsing the test difference report, determining target test samples and their corresponding target test nodes in the actual execution result set that are different from the expected test result set.

[0088] In this embodiment, in the computer motherboard test, assuming that the test difference report is displayed on the test sample of the motherboard memory slot compatibility test, and there is a difference between the actual execution result and the expected result, then the motherboard memory slot compatibility test is the target test sample, and the corresponding motherboard memory slot compatibility test node is the target test node. For example, the expected result is that the motherboard should be compatible with a variety of mainstream memory sticks on the market and can run stably at different frequencies and capacities, while the actual execution result is that data read and write errors and system instability occur when a high-frequency and large-capacity memory stick is inserted.

[0089] Step S152: Acquire a node correction record of the target test node from the test database, wherein the node correction record includes a correction operation of the target test node in a historical test task and a corrected execution result.

[0090] For the motherboard memory slot compatibility test node, search for its node correction record in the test database. These records contain the correction operations of the node in the historical test tasks and the execution results after the correction. For example, historical correction operations may include adjusting the insertion order of memory sticks, updating the motherboard BIOS version to optimize memory compatibility, replacing memory sticks of different brands or models, and other operations. For the correction operation of adjusting the insertion order of memory sticks, historical execution results show that in some cases it can improve the compatibility of memory slots and reduce data read and write errors; the operation of updating the motherboard BIOS version has achieved good results on some motherboard models, enabling the motherboard to better identify and be compatible with high-frequency memory sticks; replacing memory sticks of different brands or models has also solved compatibility issues in some specific cases.

[0091] Step S153, generating multiple candidate correction schemes based on the node correction record, and assigning a correction priority score to each candidate correction scheme, wherein the correction priority score is calculated based on the historical success rate of the correction operation and the matching degree between the execution result after the correction and the expected result.

[0092] For the motherboard memory slot compatibility test node, the candidate correction schemes generated are: scheme 1 is to adjust the order of memory stick insertion, scheme 2 is to update the motherboard BIOS version, and scheme 3 is to replace the memory stick of a specific brand. When calculating the correction priority score, taking the adjustment of the memory stick insertion order as an example, the historical success rate of the correction operation is assumed to be 60%, that is, in similar compatibility issues in the past, 60% of the cases were improved by adjusting the memory stick insertion order. The matching rate between the corrected execution result and the expected result is assumed to be 80%, that is, after adjusting the memory stick insertion order, the motherboard's compatibility with the memory stick has improved, but it has not yet completely reached the expected perfect compatibility state. The correction priority score is calculated based on these two factors. For the scheme of updating the motherboard BIOS version, it is assumed that its historical success rate is 70%, and the matching degree between the corrected execution result and the expected result is 90%. The corresponding correction priority score is also calculated. For the scheme of replacing the memory stick of a specific brand, it is assumed that its historical success rate is 80%, and the matching degree between the corrected execution result and the expected result is 95%. The correction priority score of the scheme is calculated.

[0093] Step S154, selecting the candidate correction scheme with the highest correction priority score, adjusting the execution order or replacing the test samples of the target test nodes in the optimized test path, and generating an adjusted test path.

[0094] In the above example of the motherboard memory slot compatibility test, assuming that the solution of replacing the memory stick of a specific brand has the highest correction priority score. Then in the optimized test path, the memory stick originally used to test the motherboard memory slot compatibility is replaced with a memory stick of a specific brand, thereby generating an adjusted test path. This adjusted test path changes the part of the original test path related to the motherboard memory slot compatibility test, and it is expected that this correction will make the test results closer to the expected results.

[0095] Step S155 , performing secondary verification on the adjusted test path, and if the difference between the actual execution result set after the secondary verification and the expected test result set is lower than a preset difference threshold, determining the adjusted test path as the final test path.

[0096] In a possible implementation, step S155 includes:

[0097] Step S1551: Acquire a verification test sample set associated with the target test task from the test database, wherein the verification test sample set includes a plurality of newly added test samples that are not included in the original test sample set.

[0098] In the computer motherboard testing scenario, the newly added test samples may be compatibility test samples for the motherboard memory slots in extreme environments (such as high temperature and high humidity), or compatibility test samples for some new memory sticks (which were not yet on the market at the time of the original test), etc. The newly added test samples are inserted into the specified position of the adjusted test path, and this specified position is determined based on the compatibility of the test type of the newly added test samples with the test type of the existing test nodes in the adjusted test path. For example, the newly added motherboard memory slot compatibility test sample under high temperature environment is inserted near the motherboard memory slot compatibility test node because it is related to the motherboard memory slot compatibility test type. If the newly added test sample is about the compatibility test of the new memory stick, and there are nodes for compatibility tests of other memory sticks in the adjusted test path, then insert it to the appropriate position according to the logical order.

[0099] Step S1552: insert the newly added test sample into a designated position of the adjusted test path to generate an extended test path, wherein the designated position is determined based on the compatibility of the test type of the newly added test sample with the test type of the existing test nodes in the adjusted test path.

[0100] Step S1553, executing all test nodes in the extended test path, obtaining an extended execution result set, and performing an extended difference verification between the extended execution result set and the expected test result set.

[0101] When executing the extended test path, all test nodes including the newly added test samples are tested in the new test order. For example, when testing the motherboard memory slot compatibility test sample under a high temperature environment, by simulating a high temperature environment, inserting the memory stick and performing a large number of data read and write operations, observing the operation of the motherboard, and recording results such as whether data errors occur and whether the system is stable. These results constitute part of the extended execution result set. The extended execution result set and the expected test result set are verified for extended difference, and the degree of difference between the actual execution result of each test node and the expected result is compared. For example, for the motherboard memory slot compatibility test node under a high temperature environment, it is expected that the data read and write error rate under a high temperature environment does not exceed a certain proportion. If the actual test result meets this expectation, then the difference at this test node is low; if the actual data read and write error rate exceeds expectations, then the difference is high.

[0102] Step S1554: if the result of the extended difference verification satisfies a preset compatibility condition, the extended test path is merged into the adjusted test path to generate a merged test path.

[0103] The preset compatibility condition can be that the overall difference is lower than a certain threshold, or that the differences of key test nodes are within an acceptable range. Assume that after the extended difference verification, it is found that except for a test node of a rarely used interface on the motherboard, the differences of other key test nodes (such as the motherboard memory slot compatibility test node, etc.) meet the preset compatibility conditions. Then the extended test path is merged into the adjusted test path to generate a merged test path.

[0104] Step S1555 , performing redundant node detection on the merged test path, removing test nodes whose execution results completely match the expected results and whose dependency strength values ​​are lower than the redundant threshold, and generating a streamlined final test path.

[0105] In the merged test path, there may be some test nodes, such as the test node for a specific function on the motherboard (such as a functional test of a rarely used expansion interface), whose execution results completely match the expected results, and the previous dependency analysis found that its dependency strength value is lower than the redundancy threshold (for example, 0.3). This dependency strength value indicates that the dependency between this test node and other test nodes is weak, and the result of this test node is completely in line with expectations, with little impact on the overall test results. Therefore, this test node is removed to generate a streamlined final test path. This final test path has been corrected, verified, and optimized, and can test computer motherboards more efficiently and accurately, while reducing unnecessary test steps and improving test efficiency.

[0106] In a possible implementation, step S134 includes:

[0107] Step S1341 : Initialize each vertex in the directed graph structure as a first feature vector, where the first feature vector is generated based on the node feature of the corresponding test node.

[0108] In this embodiment, in the directed graph structure of the computer motherboard test, taking the mainboard CPU slot electrical performance test node as an example, its node features include the test type as a performance test type, execution time (assuming an average of 10 minutes) and historical execution success rate (assuming 95%), etc. Based on these node features, a first feature vector is generated for the vertex. This first feature vector can be a multidimensional vector, in which each dimension corresponds to the value of a node feature or a result after some encoding. For example, the performance test type may be encoded as a specific numerical value, the execution time of 10 minutes corresponds to a dimension value in the vector, and the historical execution success rate of 95% corresponds to another dimension value, etc. Similarly, for other nodes such as the mainboard memory slot compatibility test node and the mainboard BIOS function test node, corresponding first feature vectors are also generated according to their respective node features.

[0109] Step S1342: Initialize each edge in the directed graph structure as a second feature vector, where the second feature vector is generated based on the edge feature of the corresponding edge.

[0110] For example, the edge from the mainboard CPU slot electrical performance test node to the mainboard memory slot compatibility test node has edge features including the execution order identification difference value (assumed to be 1, because it is an adjacent order) and the number of historical dependency conflicts (assumed to be 0, indicating that no conflicts have occurred due to this order in previous tests). Based on these edge features, a second feature vector is generated for this edge. This second feature vector is also a multidimensional vector, in which each dimension corresponds to the value of an edge feature or a result after some encoding. For other edges, such as the edge from the mainboard memory slot compatibility test node to the mainboard BIOS function test node, corresponding second feature vectors are also generated according to their respective edge features.

[0111] Step S1343, through the vertex update unit in the graph neural network layer, calculate the updated vertex feature vector according to the first feature vector of each vertex and the second feature vector of its adjacent edge.

[0112] The calculation process of the vertex update unit is described in detail by taking the electrical performance test node of the motherboard CPU slot as the current vertex. First, the second feature vectors corresponding to all its incoming edges and the first feature vectors of the adjacent vertices are aggregated to generate vertex aggregate features. Assuming that the node has only one incoming edge (from the starting identification node), the second feature vector of this incoming edge and the first feature vector of the adjacent vertex (starting identification node) are aggregated. For example, the second feature vector of the incoming edge contains information about the difference value of the execution order identification and the number of historical dependency conflicts, and the first feature vector of the adjacent vertex (starting identification node) contains feature information related to the starting identification, which are aggregated according to certain rules. After that, the vertex aggregate feature is concatenated with the first feature vector of the current vertex to obtain a concatenated feature vector. For example, if the vertex aggregate feature is a three-dimensional vector and the first feature vector of the current vertex is a five-dimensional vector, then an eight-dimensional concatenated feature vector is obtained after concatenation. Finally, the concatenated feature vector is input into the fully connected layer for nonlinear transformation to obtain the updated vertex feature vector. The neurons in the fully connected layer perform weighted summation on the input concatenated feature vector and perform nonlinear transformation through an activation function (such as a ReLU function, etc.) to obtain the updated vertex feature vector. This updated vertex feature vector contains more information about the relationship between the vertex and its adjacent vertices and edges.

[0113] Step S1344, through the edge update unit in the graph neural network layer, calculate the updated edge feature vector based on the second feature vector of each edge and the updated vertex feature vectors of the two vertices connected to it.

[0114] Take the edge from the mainboard CPU slot electrical performance test node to the mainboard memory slot compatibility test node as the current edge for illustration. First, obtain the updated vertex feature vectors of the two vertices connected to it (the mainboard CPU slot electrical performance test node and the mainboard memory slot compatibility test node). Then, concatenate these two vertex feature vectors with the second feature vector of the current edge to obtain an edge concatenation feature vector. For example, if the two vertex feature vectors are eight-dimensional vectors and the second feature vector of the current edge is a three-dimensional vector, then a nineteen-dimensional edge concatenation feature vector is obtained after concatenation. Finally, the edge concatenation feature vector is input into the fully connected layer for nonlinear transformation to obtain an updated edge feature vector. This updated edge feature vector combines the characteristics of the edge itself and the updated information of the two connected vertices.

[0115] Step S1345, iteratively execute vertex update and edge update operations until a preset number of iterations is reached, input the edge feature vector obtained in the last iteration into the dependency strength prediction layer, and output the dependency strength value corresponding to each edge.

[0116] Assuming that the preset number of iterations is 10 times, in each iteration, all vertices and edges are updated according to the calculation process of the above vertex update unit and edge update unit. As the number of iterations increases, the feature vectors of vertices and edges are continuously updated and gradually contain more global information. When 10 iterations are reached, the edge feature vector obtained in the last iteration is input into the dependency strength prediction layer, and the dependency strength value corresponding to each edge is output. For example, the edge from the mainboard CPU slot electrical performance test node to the mainboard memory slot compatibility test node, after the above calculation and iteration, the dependency strength prediction layer outputs its dependency strength value as 0.8, indicating that there is a strong dependency relationship between the two test nodes; while the edge from the mainboard memory slot compatibility test node to the mainboard BIOS function test node, the output dependency strength value may be 0.3, indicating that the dependency relationship between the two test nodes is relatively weak. These dependency strength values ​​accurately reflect the dependency relationship between each test node in the computer mainboard test process, which helps to optimize and adjust the test path according to these relationships and improve the accuracy and efficiency of the test.

[0117] In a possible implementation, the calculation process of the vertex updating unit includes:

[0118] For the current vertex, the second eigenvectors corresponding to all its incoming edges and the first eigenvectors of adjacent vertices are aggregated to generate a vertex aggregation feature.

[0119] The vertex aggregation feature is concatenated with the first feature vector of the current vertex to obtain a concatenated feature vector.

[0120] The concatenated feature vector is input into a fully connected layer for nonlinear transformation to obtain an updated vertex feature vector.

[0121] The calculation process of the edge update unit includes:

[0122] For the current edge, the updated vertex feature vectors of the two vertices connected to it are obtained, and the two vertex feature vectors are concatenated with the second feature vector of the current edge to obtain an edge concatenation feature vector.

[0123] The edge-joined feature vector is input into a fully connected layer for nonlinear transformation to obtain an updated edge feature vector.

[0124] Based on the above steps, through the calculation and iterative operation of the vertex update unit and edge update unit in the graph neural network layer, the dependency strength value between each test node is finally obtained, which provides an important basis for the test path optimization of computer motherboard testing. This dependency relationship reasoning method based on graph neural network can effectively mine the intrinsic relationship between test nodes, avoiding the subjectivity and limitations that may exist in artificially setting dependency relationships, thereby improving the scientificity and reliability of the entire test process.

[0125] In a possible implementation, step S140 further includes:

[0126] Step S141 , performing result analysis on each actual execution result in the actual execution result set, and extracting key verification indicators, wherein the key verification indicators include response time, error type, and data consistency level.

[0127] In this embodiment, in the computer motherboard test, for the actual execution result of the electrical performance test of the motherboard CPU slot, the response time is a key verification indicator. For example, the time from the start of power supply to the CPU slot to the voltage stabilizing at the rated value is the response time. If this time exceeds the expected range, it may affect the normal startup and operation of the CPU. The error type is also a key verification indicator, such as whether there is an error of too high or too low voltage during the power supply process. If such an error occurs, the CPU may be damaged. The data consistency level is also a key verification indicator. Here it can be understood as the stability of the voltage and the stability of the current during the entire power supply process. If there is a large fluctuation, it means that the data consistency level is low. For the motherboard memory slot compatibility test, the response time can be the time for the system to recognize the memory stick after the memory stick is inserted and start working normally; the error type includes whether a data error occurs during the data reading and writing process, whether the memory stick is misidentified, etc.; the data consistency level is reflected in the accuracy and stability of the data reading and writing process, such as whether the same result is obtained by reading and writing the same block of data multiple times. For the motherboard BIOS function test, the response time can be the time to enter the BIOS setup interface or perform BIOS-related operations (such as saving settings); error types include failure to save BIOS settings, failure to enable certain functions normally, etc.; the data consistency level is reflected in the accuracy and reliability of the BIOS settings, such as whether the set startup sequence is executed as expected.

[0128] Step S142, comparing the key verification indicators with the expected indicators of the corresponding test samples in the expected test result set item by item, and generating a list of indicator difference items.

[0129] Taking the electrical performance test of the motherboard CPU slot as an example, if the expected response time is that the voltage is stable within 5 milliseconds, and the response time in the actual execution result is 8 milliseconds, this forms an indicator difference item. If it is expected that there should be no errors of over-voltage or over-low voltage during the entire power supply process, but the actual execution result shows that the voltage is too high, this is also an indicator difference item. If the expected data consistency level is above 99% (indicating that the voltage and current fluctuations are extremely small), and the data consistency level in the actual execution result is 95%, this is also an indicator difference item. For the motherboard memory slot compatibility test, if the system is expected to recognize the memory stick and start working normally within 2 seconds, and the actual execution result is 3 seconds, this is an indicator difference item; if it is expected that there should be no errors in the data reading and writing process, but data errors appear in the actual execution result, this is also an indicator difference item; if the expected data consistency level is 99.5%, and the actual execution result is 98%, this is also an indicator difference item. For the motherboard BIOS function test, if the expected time to enter the BIOS setup interface is 1 second, but the actual execution result is 1.5 seconds, this is an indicator difference item; if the expected BIOS setup saving should not fail, but the actual execution result shows a saving failure, this is also an indicator difference item; if the expected data consistency level is 100% (indicating that the BIOS setup is fully executed as expected), but the actual execution result shows that some settings are not executed as expected, this is also an indicator difference item. These indicator difference items together constitute the indicator difference item list.

[0130] Step S143, assigning a severity level to each indicator difference item, wherein the severity level is determined based on the overall impact of the indicator difference item on the target test task.

[0131] Step S144, sorting the indicator difference item list according to the severity level, and generating the test difference report including the sorted indicator difference item list and the corresponding severity level.

[0132] For example, in the test difference report, the indicator difference items with the highest severity level are listed first, such as the response time difference item in the electrical performance test of the motherboard CPU slot under the real-time task type, which will be listed first and its severity level will be noted as the highest. Then other indicator difference items are listed in order of severity level, such as the indicator difference items such as the voltage over-high error type in the electrical performance test of the motherboard CPU slot. This test difference report reflects in detail the difference between the actual execution results and the expected results and the severity of each difference, providing an important basis for subsequent test path correction, optimization and other operations, helping to accurately locate problems and take effective solutions, thereby improving the accuracy and efficiency of computer motherboard testing.

[0133] Wherein, step S143 includes:

[0134] Step S1431, obtaining the task type of the target test task, wherein the task type includes a real-time task type, a high-precision task type and a fault-tolerant task type.

[0135] Step S1432: if the task type is a real-time task type, the severity level of the indicator difference item including the response time difference is increased to the highest level.

[0136] Step S1433: if the task type is a high-precision task type, the severity level of the indicator difference item including the data consistency level difference is increased to the highest level.

[0137] Step S1434: if the task type is a fault-tolerant task type, the severity level of the indicator difference item including the error type difference and the error type belonging to the preset intolerable error set is increased to the highest level.

[0138] Step S1435: For the indicator difference items that do not match the task type specific rules, their severity levels are calculated based on the occurrence frequency and repair time of the same indicator difference items in historical tasks.

[0139] In the computer motherboard test scenario, first obtain the task type of the target test task. Assuming that this computer motherboard test task belongs to the real-time task type, this means that the response speed of each component of the motherboard is crucial to the real-time operation of the entire computer system. For indicator difference items that include response time differences, such as the response time in the motherboard CPU slot electrical performance test changes from the expected 5 milliseconds to 8 milliseconds, because the task type is a real-time task type, the severity level of this indicator difference item will be raised to the highest level. Because the extension of the CPU slot power supply response time may cause CPU startup delays, which in turn affects the real-time response of the entire computer system, such as extended boot time or jamming in certain application scenarios with high real-time requirements (such as real-time data processing, online games, etc.). For the response time of the system identifying the memory stick in the motherboard memory slot compatibility test changes from 2 seconds to 3 seconds, also because the task type is a real-time task type, the severity level of this indicator difference item will also be raised to the highest level, because this may cause delays in system startup or loading programs, affecting the real-time response of the entire computer system. For other indicator difference items that do not involve response time differences, such as the high voltage error type in the electrical performance test of the motherboard CPU socket, although they are also serious, their impact on real-time task types is slightly lower than that of response time differences.

[0140] If the target test task is a high-precision task type, such as motherboard testing in certain computer application scenarios that require extremely high data accuracy (such as scientific computing, financial data processing, etc.). Then the severity level of the indicator difference item containing the data consistency level difference will be raised to the highest level. Taking the motherboard memory slot compatibility test as an example, if the expected data consistency level is 99.5%, but the actual execution result is 98%, this means that the accuracy in the data reading and writing process is reduced. For high-precision task types, this may cause deviations in data processing results and affect the high-precision data processing capabilities of the entire system, so the severity level of this indicator difference item is raised to the highest level. For the situation where some settings in the motherboard BIOS function test are not executed as expected (which also affects the data consistency level), the severity level will also be raised to the highest level because the task type is a high-precision task type. For other indicator difference items such as response time difference, the severity level is lower than the impact of data consistency level difference on high-precision task types.

[0141] If the target test task is a fault-tolerant task type, such as motherboard testing of some computer systems with low error tolerance (such as server motherboards, which need to run stably for a long time and have low error tolerance). The severity level of the indicator difference items that contain error type differences and whose error types belong to the preset intolerant error set will be raised to the highest level. For example, in the electrical performance test of the motherboard CPU slot, an error such as overvoltage that may damage the CPU belongs to the preset intolerant error set. For the fault-tolerant task type, the severity level of this indicator difference item will be raised to the highest level because this error may cause the failure of the entire server system. For the error of BIOS setting saving failure in the motherboard BIOS function test, it is also an intolerant error, and its severity level will also be raised to the highest level. For other indicator difference items that do not belong to the preset intolerant error set, such as response time differences or data consistency levels that are slightly lower, the severity level is relatively low.

[0142] For the indicator difference items that do not match the task type specific rules, the severity level is calculated based on the frequency of occurrence and repair time of the same indicator difference items in historical tasks. For example, in the motherboard memory slot compatibility test, the memory stick is misidentified, but this error does not belong to any of the situations based on the task type specific rules mentioned above. Check the frequency of the indicator difference item "memory stick misidentification" in historical tasks. If it often appears in multiple tests in the past, it means that this problem is stubborn and the severity level will be increased accordingly. At the same time, consider the time it takes to repair this problem. If it takes a long time to repair this problem, such as replacing the memory stick, adjusting the motherboard BIOS settings, and other complex operations, then the severity level will also be increased. On the contrary, if this indicator difference item rarely appears in historical tasks and the repair time is short, such as only re-plugging the memory stick, then the severity level will be low.

[0143] Figure 2 The hardware structure of the computer testing system 100 based on machine learning for implementing the above-mentioned computer testing method based on machine learning provided by the embodiment of the present invention is shown as follows: Figure 2 As shown, the machine learning based computer testing system 100 may include a processor 110 , a machine readable storage medium 120 , a bus 130 , and a communication unit 140 .

[0144] The machine-readable storage medium 120 may store data and / or instructions. In some embodiments, the machine-readable storage medium 120 may store data acquired from an external terminal. In some embodiments, the machine-readable storage medium 120 may store data and / or instructions that the machine-learning-based computer test system 100 uses to execute or use to complete the exemplary methods described in the present invention.

[0145] During the specific implementation process, one or more processors 110 execute computer executable instructions stored in the machine-readable storage medium 120, so that the processor 110 can execute the computer testing method based on machine learning in the above method embodiment. The processor 110, the machine-readable storage medium 120 and the communication unit 140 are connected through the bus 130, and the processor 110 can be used to control the sending and receiving actions of the communication unit 140.

[0146] The specific implementation process of the processor 110 can refer to the various method embodiments executed by the above-mentioned computer testing system 100 based on machine learning. The implementation principles and technical effects are similar, and this embodiment will not be repeated here.

[0147] In addition, an embodiment of the present invention further provides a readable storage medium, in which computer executable instructions are preset. When a processor executes the computer executable instructions, the above-mentioned computer testing method based on machine learning is implemented.

[0148] It should be noted that in order to simplify the description of the present invention and thus help understand one or more embodiments of the invention, in the foregoing description of the embodiments of the present invention, various features are sometimes combined into one embodiment, drawing or description thereof.

Claims

1. A computer testing method based on machine learning, characterized in that: The method comprises: Acquire an original test sample set and an expected test result set corresponding to a target test task, wherein the original test sample set includes execution order identifiers of multiple test samples, and the expected test result set includes expected execution results corresponding to each test sample; Sequentially preprocessing the original test sample set to generate an initial test path matching the target test task, wherein the initial test path is composed of a plurality of test nodes arranged according to the execution sequence identifier, and each test node corresponds to an execution entry of a test sample; Calling a pre-trained machine learning test model, performing execution dependency analysis on each test node in the initial test path, determining the dependency relationship between each test node, and adjusting the node arrangement order of the initial test path based on the dependency relationship to generate an optimized test path; According to the node arrangement order of the optimized test path, the test samples corresponding to each test node are executed in sequence to obtain an actual execution result set, and the actual execution result set is verified with the expected test result set to generate a test difference report; Performing path correction on the optimized test path according to the test difference report to generate a final test path, and associating the final test path with the actual execution result set and storing it in a test database; The sequentially preprocessing the original test sample set to generate an initial test path matching the target test task includes: Extracting a sample identifier and an execution sequence identifier of each test sample in the original test sample set, and constructing an initial sequence queue based on the execution sequence identifier; Traversing each test sample in the initial sequential queue, and determining a test type of each test sample according to the sample identifier, wherein the test type includes a functional test type, a performance test type, and a compatibility test type; Classifying the test samples in the initial sequential queue according to the test type, generating a plurality of test type sub-queues, and assigning a priority weight to each test type sub-queue; Sorting each test type subqueue according to the priority weight to generate an intermediate test path, wherein the intermediate test path includes a plurality of test type subqueues arranged in descending order of priority; An internal order adjustment is performed on each test type subqueue in the intermediate test path so that the test samples in each test type subqueue are rearranged according to the execution order identifier to generate the initial test path.

2. The computer testing method based on machine learning according to claim 1, characterized in that: The calling of the pre-trained machine learning test model, performing execution dependency analysis on each test node in the initial test path, and determining the dependency relationship between each test node, includes: Converting the initial test path into a directed graph structure, wherein vertices in the directed graph structure correspond to test nodes in the initial test path, and edges in the directed graph structure correspond to an execution order between the test nodes; Extract node features of each test node, wherein the node features include the test type, execution time and historical execution success rate of the corresponding test sample; Extracting edge features of each edge, wherein the edge features include an execution order identification difference value and a number of historical dependency conflicts between two connected test nodes; Inputting the directed graph structure, the node features, and the edge features into the machine learning test model, performing dependency reasoning on the directed graph structure through the graph neural network layer in the machine learning test model, and outputting dependency strength values ​​between the test nodes; The edges in the directed graph structure are screened according to the dependency strength values, edges whose dependency strength values ​​exceed a preset threshold are retained, and a dependency graph is constructed based on the retained edges, wherein the dependency graph is used to describe the node execution order that must be followed in the initial test path.

3. The computer testing method based on machine learning according to claim 1, characterized in that: The training process of the pre-trained machine learning test model includes: Acquire a historical test task set, wherein the historical test task set includes historical test paths, historical execution results, and historical difference reports corresponding to multiple historical test tasks; Extracting a historical test node sequence from the historical test path, and marking an actual dependency label for each historical test node, wherein the actual dependency label is used to indicate a dependency type between the historical test node and other historical test nodes; Converting the historical test node sequence into a historical directed graph structure, and extracting historical node features of each historical test node and historical edge features of each historical edge; Constructing an initial machine learning test model, inputting the historical directed graph structure, the historical node features, and the historical edge features into the initial machine learning test model to obtain a predicted dependency relationship label; The label difference loss value between the predicted dependency label and the actual dependency label is calculated, and the parameters of the initial machine learning test model are iteratively adjusted based on the label difference loss value until the label difference loss value converges to obtain the pre-trained machine learning test model.

4. The computer testing method based on machine learning according to claim 1, characterized in that: The performing path correction on the optimized test path according to the test difference report to generate a final test path includes: Parsing the test difference report to determine target test samples and their corresponding target test nodes in the actual execution result set that are different from the expected test result set; Acquire a node correction record of the target test node from the test database, wherein the node correction record includes a correction operation of the target test node in a historical test task and a corrected execution result; Generate multiple candidate correction plans based on the node correction record, and assign a correction priority score to each candidate correction plan, wherein the correction priority score is calculated based on the historical success rate of the correction operation and the matching degree between the execution result after the correction and the expected result; Select the candidate correction scheme with the highest correction priority score, adjust the execution order or replace the test samples of the target test nodes in the optimized test path, and generate an adjusted test path; The adjusted test path is verified twice, and if the difference between the actual execution result set after the secondary verification and the expected test result set is lower than a preset difference threshold, the adjusted test path is determined as the final test path.

5. The computer testing method based on machine learning according to claim 4, characterized in that: The performing secondary verification on the adjusted test path includes: Acquire a verification test sample set associated with the target test task from the test database, wherein the verification test sample set includes a plurality of newly added test samples that are not included in the original test sample set; Inserting the newly added test sample into a designated position of the adjusted test path to generate an extended test path, wherein the designated position is determined based on the compatibility of the test type of the newly added test sample with the test type of the existing test node in the adjusted test path; Execute all test nodes in the extended test path, obtain an extended execution result set, and perform extended difference verification between the extended execution result set and the expected test result set; If the result of the extended difference verification meets the preset compatibility condition, merging the extended test path into the adjusted test path to generate a merged test path; Redundant nodes are detected on the merged test path, and test nodes whose execution results completely match the expected results and whose dependency strength values ​​are lower than the redundancy threshold are removed to generate a streamlined final test path.

6. The computer testing method based on machine learning according to claim 2, characterized in that: The method of performing dependency reasoning on the directed graph structure through the graph neural network layer in the machine learning test model and outputting dependency strength values ​​between the test nodes includes: Initializing each vertex in the directed graph structure as a first feature vector, where the first feature vector is generated based on a node feature of a corresponding test node; Initializing each edge in the directed graph structure as a second feature vector, where the second feature vector is generated based on an edge feature of the corresponding edge; Calculate an updated vertex feature vector according to the first feature vector of each vertex and the second feature vector of its adjacent edge through a vertex update unit in the graph neural network layer; Calculate an updated edge feature vector according to the second feature vector of each edge and the updated vertex feature vectors of two vertices connected to it by an edge update unit in the graph neural network layer; Iterate the vertex update and edge update operations until the preset number of iterations is reached, input the edge feature vector obtained in the last iteration into the dependency strength prediction layer, and output the dependency strength value corresponding to each edge.

7. The computer testing method based on machine learning according to claim 6, characterized in that: The calculation process of the vertex update unit includes: For the current vertex, aggregate the second eigenvectors corresponding to all its incoming edges and the first eigenvectors of adjacent vertices to generate vertex aggregate features; Concatenate the vertex aggregation feature with the first feature vector of the current vertex to obtain a concatenated feature vector; Input the concatenated feature vector into a fully connected layer for nonlinear transformation to obtain an updated vertex feature vector; The calculation process of the edge update unit includes: For the current edge, obtain the updated vertex feature vectors of the two vertices connected to it, and concatenate the two vertex feature vectors with the second feature vector of the current edge to obtain an edge concatenation feature vector; The edge-joined feature vector is input into a fully connected layer for nonlinear transformation to obtain an updated edge feature vector.

8. The computer testing method based on machine learning according to claim 1, characterized in that: The step of performing difference verification between the actual execution result set and the expected test result set to generate a test difference report includes: Performing result analysis on each actual execution result in the actual execution result set to extract key verification indicators, wherein the key verification indicators include response time, error type, and data consistency level; Compare the key verification indicators with the expected indicators of the corresponding test samples in the expected test result set item by item to generate a list of indicator difference items; Assigning a severity level to each indicator difference item, wherein the severity level is determined based on the overall impact of the indicator difference item on the target test task; Sorting the indicator difference item list according to the severity level, and generating the test difference report including the sorted indicator difference item list and the corresponding severity level; The step of assigning a severity level to each indicator difference item includes: Acquire the task type of the target test task, wherein the task type includes a real-time task type, a high-precision task type, and a fault-tolerant task type; If the task type is a real-time task type, the severity level of the indicator difference item including the response time difference is increased to the highest level; If the task type is a high-precision task type, the severity level of the indicator difference item including the data consistency level difference is increased to the highest level; If the task type is a fault-tolerant task type, the severity level of the indicator difference item including the error type difference and the error type belonging to the preset intolerable error set is increased to the highest level; For indicator difference items that do not match the specific rules of the task type, their severity level is calculated based on the frequency of occurrence and repair time of the same indicator difference items in historical tasks.

9. A computer testing system based on machine learning, characterized in that: The machine learning-based computer testing system includes a processor and a memory, the memory is connected to the processor, the memory is used to store programs, instructions or codes, and the processor is used to execute the programs, instructions or codes in the memory to implement the machine learning-based computer testing method described in any one of claims 1 to 8.

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