RISC-V-based security branch predictor and operation method

Abstract

The invention discloses a security branch predictor based on RI SC-V. The security branch predictor comprises an attack module and a defense module, and the attack module is used for carrying out simulation attack training on an initial condition branch instruction in the security branch predictor by adopting a side channel attack program to obtain a target condition branch instruction; the defense module is used for generating a target state update value according to the target condition branch instruction, and updating a current saturation counter state corresponding to the target condition branch instruction according to the target state update value so as to optimize the security branch predictor based on the updated current saturation counter state; a current saturation counter state is stored in a branch history table in a secure branch predictor. The method can effectively prevent an attacker from perceiving the state of the saturation counter, reduces the risk of hostile attack and data leakage, improves the security and reliability of the system, and can be widely applied to the technical field of data security.

Description

Technical Field

[0001] The present application relates to the field of data security technology, and in particular to a RISC-V-based secure branch predictor and operating method. Background Art

[0002] RISC-V is an open source instruction set architecture based on a reduced instruction set. The design goal of RISC-V is to provide a flexible, scalable, high-performance, and low-power processor architecture. However, microarchitectural side-channel attacks are a way of using the microarchitectural state of the processor to carry out side-channel attacks. Among them, branch predictor-based side-channel attacks are a type of microarchitectural side-channel attack. Branch predictor-based side-channel attacks are a variant of conditional branch misprediction. The main attack target is the branch predictor classification history table (Branch History Table, BHT), thereby stealing security-critical information. This attack poses a high threat to system security and faces security threats such as data leakage.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The embodiments of the present application aim to solve at least one of the technical problems in the related art to a certain extent. To this end, the main purpose of the embodiments of the present application is to propose a secure branch predictor and operation method based on RISC-V, which can effectively avoid the attacker's perception of the saturated counter state, reduce the risk of malicious attacks and data leakage, and improve the security and reliability of the system.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application proposes a RISC-V-based secure branch predictor, wherein the secure branch predictor is a prediction module on a RISC-V processor, and the secure branch predictor includes an attack module and a defense module, wherein:

[0006] The attack module is used to use a side channel attack program to perform simulated attack training on the initial conditional branch instruction in the security branch predictor to obtain a target conditional branch instruction;

[0007] The defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the security branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the security branch predictor.

[0008] In some embodiments, the defense module includes a storage unit, a state machine unit, and a random number generation unit, wherein:

[0009] The storage unit is used to store the first confidence data corresponding to the target conditional branch instruction; wherein the first confidence data includes a first confidence state and a first confidence level;

[0010] The state machine unit is used to update the first confidence data to obtain second confidence data corresponding to the target conditional branch instruction; wherein the second confidence data includes a second confidence state and a second confidence level;

[0011] The random number generation unit is used to generate the target state update value according to the second confidence data.

[0012] In some embodiments, the target state update value is used to update a current jump direction value of the target conditional branch instruction to update the current jump direction of the target conditional branch instruction.

[0013] In some embodiments, the RISC-V processor includes an instruction fetch unit, an instruction decoding unit, and a branch jump unit, wherein the instruction fetch unit includes the secure branch predictor, wherein:

[0014] The instruction extraction unit is used to pre-decode the target conditional branch instruction to obtain target conditional branch instruction information, and read the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, so as to predict the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmit the current predicted jump direction to the branch jump unit;

[0015] The instruction decoding unit is used to obtain the pre-decoded instruction information in the instruction fetching unit, and analyze the pre-decoded instruction information to obtain target instruction information, so as to transmit the target instruction information to the branch jump unit;

[0016] The branch jump unit is used to perform branch calculation according to the target instruction information to obtain a target jump direction, and compare the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

[0017] To achieve the above object, another aspect of the embodiment of the present application proposes an operation method of a secure branch predictor based on RI SC-V, which is applied to the secure branch predictor based on RI SC-V as described above, wherein the secure branch predictor is a prediction module on the RI SC-V processor, and the secure branch predictor includes an attack module and a defense module, and the method includes the following steps:

[0018] The attack module uses a side channel attack program to perform simulated attack training on the initial conditional branch instruction in the security branch predictor to obtain a target conditional branch instruction;

[0019] Generate a target state update value according to the target conditional branch instruction by the defense module;

[0020] The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, and optimizes the security branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the security branch predictor;

[0021] The optimized security branch predictor is used to predict the conditional branch instructions to be predicted on the RISC-V processor to obtain a target security branch prediction result.

[0022] In some embodiments, the RISC-V processor includes an instruction fetch unit, an instruction decoding unit, and a branch jump unit, the instruction fetch unit includes the secure branch predictor, and before the generating the target state update value according to the target conditional branch instruction by the defense module, the method further includes:

[0023] Inputting the target conditional branch instruction into the instruction extraction unit of the RISC-V processor, pre-decoding the target conditional branch instruction through the instruction extraction unit, and obtaining target conditional branch instruction information corresponding to the target conditional branch instruction;

[0024] The instruction extraction unit reads the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, predicts the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmits the current predicted jump direction to the branch jump unit;

[0025] Acquire pre-decoded instruction information in the instruction fetching unit through the instruction decoding unit, and analyze the pre-decoded instruction information to obtain target instruction information, so as to transmit the target instruction information to the branch jump unit;

[0026] The branch jump unit performs branch calculation according to the target instruction information to obtain a target jump direction, and compares the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

[0027] In some embodiments, the defense module includes a storage unit, a state machine unit, and a random number generation unit, the storage unit is used to store the first confidence data corresponding to the target conditional branch instruction; wherein the first confidence data includes a first confidence state and a first confidence level, and the generating of the target state update value according to the target conditional branch instruction by the defense module includes:

[0028] The first confidence data is updated by the state machine unit according to the first confidence state and the target jump direction output by the branch jump unit to obtain second confidence data corresponding to the target conditional branch instruction; wherein the second confidence data includes a second confidence state and a second confidence level;

[0029] The target state update value is generated according to the second confidence data by the random number generation unit.

[0030] In some embodiments, updating the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value by the defense module, and optimizing the security branch predictor based on the updated current saturation counter state, includes:

[0031] updating the current jump direction value of the target conditional branch instruction according to the target state update value through the defense module, and updating the current jump direction of the target conditional branch instruction according to the current jump direction value;

[0032] The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the updated current jump direction, and optimizes the security branch predictor based on the updated current saturation counter state.

[0033] To achieve the above-mentioned purpose, another aspect of an embodiment of the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above-mentioned method when executing the computer program.

[0034] To achieve the above objective, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0035] The embodiments of the present application include at least the following beneficial effects: The present application provides a secure branch predictor and an operating method based on RI SC-V, wherein the secure branch predictor is a prediction module on the RI SC-V processor, and the secure branch predictor includes an attack module and a defense module, wherein: the attack module is used to use a side channel attack program to simulate attack training on the initial conditional branch instruction in the secure branch predictor to obtain a target conditional branch instruction; the defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturated counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the secure branch predictor based on the updated current saturated counter state; wherein the current saturated counter state is stored in a branch history table in the secure branch predictor. The embodiment of the present application simulates side channel attacks through an attack module, so that the defense module can learn and adapt to the simulated attack mode, thereby improving the defense capability of the RI SC-V processor against actual side channel attacks based on the secure branch predictor; by performing targeted updates to the current saturation counter state in the branch history table, the attacker's perception of the saturation counter state can be effectively avoided, reducing the risk of malicious attacks and data leakage, improving the security and reliability of the system, and maintaining a high prediction accuracy even in the presence of side channel attacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the structure of a secure branch predictor based on RISC-V provided in an embodiment of the present application;

[0037] Figure 2 It is a schematic diagram of the overall architecture of the secure branch predictor provided in an embodiment of the present application;

[0038] Figure 3 is a schematic diagram of a signal transmission flow in a branch predictor provided by an embodiment of the present application;

[0039] Figure 4 It is a schematic diagram of the defense process of the secure branch predictor provided in an embodiment of the present application;

[0040] Figure 5 It is a schematic diagram of the state machine jump process provided in an embodiment of the present application;

[0041] Figure 6 is a flowchart of the steps of the operation method of the secure branch predictor based on RISC-V provided in an embodiment of the present application;

[0042] Figure 7 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0044] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0045] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0047] At present, in the field of chip instruction set architecture, with the promotion of open source code and the continuous development of the RISC-V ecosystem, RISC-V has received widespread attention. RISC-V is an open source instruction set architecture (ISA) based on the reduced instruction set (RISC). The design goal of RISC-V is to provide a flexible, scalable, high-performance, and low-power processor architecture that can be used in various fields, such as embedded systems, servers, and high-performance computing. However, RISC-V may be subject to microarchitectural side channel attacks (microarchitectural side channel attacks). Microarchitectural side channel attacks are a way of conducting side channel attacks using the microarchitectural state of the processor to steal security-critical information through the processor microarchitecture. Microarchitectural side channel attacks can not only steal sensitive information such as encryption keys, monitor device input, extract browser access history, and crack address randomization ALSR (Address space layout randomization), but also assist transient execution attacks such as Spectre and Meltdown to attack, and pass sensitive information obtained "transiently" to attackers through changes in the microarchitectural state. Many performance enhancements found in current processors have not been thoroughly analyzed for security vulnerabilities, leading to various attacks, such as predictors and multi-level memory structures, especially various predictors such as branch predictors have been found to be the source of security vulnerabilities. Among them, the Spectre attack induces the victim to perform speculative operations that would not occur during the strict serialized order processing of program instructions, and leaks the victim's confidential information to the attacker through a covert channel. The Spectre-V1 attack is a variant of the Spectre attack, which is a variant that exploits conditional branch mispredictions. The main attack target is the BHT (Branch History Table) of the branch predictor, thereby stealing security-critical information. This attack poses a high threat to system security and faces security threats such as data leakage.

[0048] In view of this, the embodiment of the present application provides a RISC-V-based secure branch predictor and an operation method, wherein the secure branch predictor is a prediction module on a RISC-V processor, and the secure branch predictor includes an attack module and a defense module, wherein: the attack module is used to simulate attack training on the initial conditional branch instruction in the secure branch predictor using a side channel attack program to obtain a target conditional branch instruction; the defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the secure branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the secure branch predictor. The embodiment of the present application simulates a side channel attack through an attack module, so that the defense module can learn and adapt to the simulated attack mode, thereby improving the defense capability of the RISC-V processor against actual side channel attacks based on the secure branch predictor; by updating the current saturation counter state in the branch history table in a targeted manner, the attacker's perception of the saturation counter state can be effectively avoided, the risk of malicious attacks and data leakage can be reduced, the security and reliability of the system can be improved, and a high prediction accuracy can be maintained even in the presence of a side channel attack.

[0049] The RISC-V-based secure branch predictor and operation method provided in the embodiment of the present application relate to the field of data security technology. The operation method of the RISC-V-based secure branch predictor provided in the embodiment of the present application can be applied to a terminal, can also be applied to a server, and can also be software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a car terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or a server cluster or distributed system composed of multiple physical servers, and can also be configured to provide cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network, content distribution network) and big data and artificial intelligence platforms and other basic cloud computing services. The server can also be a node server in a blockchain network; the software can be an application that implements the operation method of the RISC-V-based secure branch predictor, etc., but is not limited to the above forms.

[0050] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs (Personal Computers, personal computers), minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0051] See also Figure 1 , Figure 1 It is a schematic diagram of the structure of a RISC-V-based secure branch predictor provided in an embodiment of the present application; Figure 1 The secure branch predictor in is a prediction module on a RISC-V processor, and the secure branch predictor includes an attack module and a defense module, wherein:

[0052] The attack module is used to use a side channel attack program to perform simulated attack training on the initial conditional branch instruction in the security branch predictor to obtain a target conditional branch instruction;

[0053] The defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the security branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the security branch predictor.

[0054] In practical applications, the branch predictor is a prediction module on a RISC-V processor. Similarly, the secure branch predictor provided in the embodiment of the present application is also a prediction module on a RISC-V processor. However, the secure branch predictor in the embodiment of the present application is different from the traditional branch predictor. The secure branch predictor in the embodiment of the present application includes an attack module and a defense module. The attack module is used to use a side channel attack program to simulate attack training on the initial conditional branch instruction in the secure branch predictor to obtain a target conditional branch instruction; the defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturated counter state corresponding to the target conditional branch instruction according to the target state update value to optimize the secure branch predictor based on the updated current saturated counter state; wherein the current saturated counter state is stored in a branch history table in the secure branch predictor.

[0055] In the specific implementation, see Figure 2 , Figure 2 : is a schematic diagram of the overall architecture of the secure branch predictor provided in the embodiment of the present application; the overall architecture of the secure branch predictor designed in the embodiment of the present application to defend against Spectre-V1 attacks on a RISC-V processor is as follows Figure 2 As shown, Defend BHT refers to a BHT modified based on the defense method proposed in the embodiment of the present application, which is part of the RISC-V processor core; the RISC-V processor core is connected to the peripherals through the AXI bus, and the peripherals include a UART serial port and a memory. The side channel attack program mentioned in the embodiment of the present application is stored in the memory, and the UART serial port is used to output the program running results. The system has two parts: attack and defense. The attack part mainly uses the Spectre-V1 code adapted to the RISC-V instruction set and puts it into the memory of the SoC (System on Chip) of the RISC-V processor. After the SoC is started, the program will be read from the memory, and the attack program code will be executed after the RISC-V processor is initialized; the defense part mainly modifies the BHT (Branch History Table) part of the RISC-V processor branch predictor, records the confidence of each conditional branch instruction jump state, and then probabilistically adjusts the conditional branch instruction according to the confidence to update the state of the BHT, making the state of the BHT invisible to the attacker to a certain extent, so as to prevent the attacker from maliciously training the state of the conditional branch instruction, so that the RISC-V processor can be protected from Spectre-V1 attacks while ensuring that the original functions of the RISC-V processor are not affected.

[0056] It is worth mentioning that the design of the secure branch predictor in the embodiment of the present application is mainly aimed at defending against Spectre-V1 attacks, but the secure branch predictor in the embodiment of the present application can also effectively mitigate other attacks on speculative execution, thereby preventing security threats such as unauthorized access and data leakage. It has a certain adaptability and can be widely used in various fields, such as cloud computing, network security, etc., that is, it can be implemented in processors using the same type of branch predictor, providing reliability and security for various scenarios used by users.

[0057] For the side channel attack program, it is converted into an executable file through a compilation tool chain, and the executable file is then converted into a binary file through the tool chain and stored in the memory of the SoC of the RISC-V processor. After the SoC is started, the program will be read from the memory, and the attack program code will be executed after the RISC-V processor is initialized. The tool chain used in the embodiment of the present application is a standard tool chain of the RISC-V architecture. The compiled executable file also carries the processor initialization program, which is placed in the memory of the SoC and executed after power-on.

[0058] The embodiment of the present application mainly targets the Spectre-V1 attack. The conditional branch instruction targeted by the Spectre-V1 attack is presented in the following form:

[0059] if(x<16){

[0060] sec = array1[x];

[0061] temp = array2[sec*512];}.

[0062] Specifically, the process of simulation testing based on the Spectre-V1 attack simulation test code is as follows: Spectre-V1 uses the speculative execution of conditional branch instructions. When the conditional branch instruction is speculatively executed, the subsequent load instruction will be executed, and the secret data sec will be mapped to the address of the array array2 and the value will be put into the cache. When the conditional branch instruction is executed incorrectly, the state of the cache will not be restored, which should not happen according to normal procedures; the Spectre-V1 attack subsequently traverses all addresses of the cache, and restores the value of sec according to the different read and write times, so that the sec content that should not be read can be read.

[0063] In the embodiment of the present application, the Spectre-V1 attack requires malicious training of a conditional branch instruction, and trains its state to 11, representing the Taken state. Specifically, the branch predictor of the RICS-V processor uses a 2-bit saturated counter, with a total of four states, namely: 00, representing the Strong Not Taken state; 01, representing the Weak Not Taken state; 10, representing the Weak Taken state; 11, representing the Strong Taken state. In the attack code of Spectre-V1, in order to ensure that the conditional branch instruction will make an incorrect guess when the conditional branch instruction is executed with an incorrect condition, the conditional branch instruction is executed at least 4 times with the correct condition before using the incorrect condition to ensure that the saturated counter value in the BHT corresponding to the conditional branch instruction in the branch predictor is 11, that is, the Strong Taken state.

[0064] For the initial conditional branch instruction, it is the original conditional branch instruction without any processing. In the embodiment of the present application, it is necessary to use a side channel attack program to perform simulated attack training on the initial conditional branch instruction to obtain the target conditional branch instruction. The saturated counter value in the BHT (branch history table in the secure branch predictor) corresponding to the target conditional branch instruction obtained after the simulated attack training in the branch predictor is 11, that is, the Strong Taken state.

[0065] In some embodiments, the target state update value is used to update the current jump direction value of the target conditional branch instruction to update the current jump direction of the target conditional branch instruction.

[0066] Optionally, the RISC-V processor includes an instruction fetch unit, an instruction decoding unit and a branch jump unit, and the instruction fetch unit includes the secure branch predictor.

[0067] In some embodiments, the instruction extraction unit is used to pre-decode the target conditional branch instruction to obtain the target conditional branch instruction information, and read the current saturated counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, so as to predict the current predicted jump direction of the target conditional branch instruction according to the current saturated counter state, and transmit the current predicted jump direction to the branch jump unit; the instruction decoding unit is used to obtain the pre-decoded instruction information in the instruction extraction unit, and analyze the pre-decoded instruction information to obtain the target instruction information, so as to transmit the target instruction information to the branch jump unit; the branch jump unit is used to perform branch calculation according to the target instruction information to obtain the target jump direction, and compare the target jump direction with the current predicted jump direction to determine whether to update the current saturated counter state corresponding to the target conditional branch instruction.

[0068] In the secure branch predictor of the RISC-V processor, the components related to conditional branch instructions are the instruction fetch unit (IFU), instruction decode unit (IDU), and branch jump unit (BJU). Among them, the secure branch predictor is part of the instruction fetch unit; the instruction fetch unit, instruction decode unit, and branch jump unit are all part of the RISC-V processor and are all sub-units of the top-level module of the processor.

[0069] Among them, the pre-decoding operation in the instruction extraction unit is used to determine whether the instruction is a branch instruction, so as to decide whether to use the prediction result output by the branch predictor. When there is no branch instruction, the prediction result output by the branch predictor is not used. The instruction decoding unit will obtain the pre-decoded instruction information in the instruction extraction unit. The instruction decoding unit can decode the operation to be performed by the specific branch instruction and the register index or immediate number data used by the instruction according to the pre-decoded instruction information. The instruction decoding unit can also decode the execution unit corresponding to the instruction. Among them, the instruction extraction unit transmits the prediction information directly to the branch jump unit in order to check the prediction result to update the BHT, so the prediction information obtained by the instruction extraction unit does not need to be transmitted to the instruction decoding unit.

[0070] See also Figure 3 , Figure 3 is a schematic diagram of a signal transmission flow in a branch predictor provided by an embodiment of the present application; Figure 3 As shown, Figure 3 is the information flow when the conditional branch instruction is executed in the RISC-V processor, but does not include the modified BHT provided by the embodiment of the present application, that is, Figure 3 The BHT in the above refers to the unmodified BHT. Figure 3 The modules mentioned are all in Figure 2 In the RISC-V processor core, such as Figure 3As shown, the information flow transmission process for the execution of conditional branch instructions in the RISC-V processor is as follows: first, the PC (Program Counter) generation part generates a PC value, takes out the corresponding instruction from the I CACHE (instruction cache) and pre-decodes it. If it is a conditional branch instruction, the prediction information of the corresponding instruction will be obtained from the BHT according to the pre-decoding information, where the I CACHE and BHT are both in the I FU; the prediction information will be passed to the BJU, and the IDU will pass the decoded complete instruction information to the BJU. The BJU will perform branch calculations based on this information, including whether to jump and the calculation of the jump address, and will check the previous prediction. The BJU outputs the execution information to the corresponding execution unit. At the same time, if the BJU checks and finds that the previous prediction is wrong, it will trigger the instruction flow change, tell the PC generation part a new PC value, and update the saturation counter state of the corresponding conditional branch instruction in the BHT. If the prediction is correct, only the saturation counter state of the corresponding conditional branch instruction in the BHT will be updated.

[0071] In a specific implementation, when an instruction enters the RISC-V processor, it is first pre-decoded in the instruction fetch unit (IFU). At this time, if the instruction is a conditional branch instruction, the information of the conditional branch instruction (i.e., the target conditional branch instruction information) will be obtained in the instruction fetch unit. The information of the conditional branch instruction includes the source register, the specific conditional branch instruction type (such as the equal branch instruction (Branch if Equal, abbreviated as BEQ), the unequal branch instruction (Branch if NotEqual, abbreviated as BNE), the signed less than branch instruction (Branch if Less Than, referred to as BLT) etc.); then, in the instruction fetch unit, the saturated counter state of the corresponding conditional branch instruction in the branch history table (BHT) in the security branch predictor is read according to the information of these conditional branch instructions, and then the jump direction of the conditional branch instruction is predicted according to the saturated counter state, and the predicted jump direction information is passed to the instruction decoding unit (IDU), and the instruction information such as the value of the source register is obtained in the instruction decoding unit and passed to the branch jump unit (BJU), and the final jump direction of the conditional branch instruction is obtained in the branch jump unit, and compared with the prediction result (the jump direction of the conditional branch instruction) in the instruction fetch unit to determine whether pipeline redirection is required, and the result of the final jump direction is returned to the instruction fetch unit, so as to update the corresponding saturated counter state in the branch history table (BHT) according to the result and confidence of the final jump direction of the conditional branch instruction, so as to obtain a more accurate prediction result at the next prediction, thereby improving the processor performance.

[0072] Optionally, the defense module includes a storage unit, a state machine unit and a random number generation unit.

[0073] Specifically, as mentioned above, the attack code needs to first train a conditional branch instruction with a conditional value that satisfies the branch condition, and train its corresponding saturated counter state to 11, that is, the StrongTaken state, and then execute the conditional branch instruction with a conditional value that does not satisfy the branch condition, and read a value that should not be read according to the processor's speculative execution characteristics. The defense module will simulate interference with the training process based on this characteristic.

[0074] In some embodiments, a storage unit is used to store first confidence data corresponding to a target conditional branch instruction; wherein the first confidence data includes a first confidence state and a first confidence level; a state machine unit is used to update the first confidence data to obtain second confidence data corresponding to the target conditional branch instruction; wherein the second confidence data includes a second confidence state and a second confidence level; and a random number generation unit is used to generate a target state update value based on the second confidence data.

[0075] Specifically, in the architecture of the defense module, the storage unit is designed to store the confidence state and confidence level output by the state machine unit, wherein the confidence state and the confidence level correspond one to one, and the storage unit output value value[5:2] is the confidence state of the corresponding BHT table item, and value[1:0] is the confidence level of the corresponding BHT table item. Among them, the confidence level records the number of times a conditional branch instruction has undergone the aforementioned malicious training, and the confidence state records the intermediate behavior of the malicious training. The confidence state and the confidence level will be input together into the state machine unit for updating. Exemplarily, the start stage (or intermediate stage) of the target conditional branch instruction corresponds to a first confidence state and a first confidence level. First, the first confidence state and the first confidence level corresponding to the target conditional branch instruction are input into the state machine unit for updating, and the second confidence state and the second confidence level corresponding to the target conditional branch instruction can be obtained. The second confidence state and the second confidence level are the latest confidence state and confidence level.

[0076] In the architecture of the defense module, the state machine unit is designed to update the confidence state and confidence level of a conditional branch instruction. After receiving the confidence state and confidence level output by the storage unit, the state machine unit updates the confidence state and confidence level of the corresponding conditional branch instruction based on the current confidence state and the jump direction of the conditional branch instruction output by the branch jump unit (BJU).

[0077] Please participate Figure 4 , Figure 4 is a schematic diagram of the defense process of the secure branch predictor provided in the embodiment of the present application; Figure 4 As shown, Figure 4The value in refers to the output value of the storage unit. The value includes the current state (value[5:2]) and the current confidence (value[1:0]). Confidence refers to the confidence of the current conditional branch instruction. Figure 4 As shown, the security branch predictor will update the saturation counter of the conditional branch instruction in the BHT according to the execution result of the BJU, and the defense mentioned in the embodiment of the present application is carried out in this process. Specifically, according to the conditional branch instruction information, the state and confidence corresponding to the conditional branch instruction are read from the storage unit storing the state and confidence of the conditional branch instruction, and passed to the state machine unit. At the same time, the state machine unit obtains the branch jump result output from the BJU, and obtains a new state and confidence according to the branch jump result, which are used to update the value in the storage unit. At the same time, the confidence confidence is passed to the random number generation unit. The random number generation unit dynamically adjusts the negation probability according to the confidence, determines the update value of the BHT according to the branch jump result and the negation probability, and finally updates the saturation counter state of the corresponding conditional branch instruction in the BHT.

[0078] There are 9 states in the state machine unit, namely P1, P2, P3, P4, M1, M2, M3, M4, and IDLE. The initial state is IDLE, and the initial confidence is 0. Please refer to Figure 5 , Figure 5 is a schematic diagram of the state machine jump flow provided in the embodiment of the present application; it should be noted that, Figure 5 The content of "confidence change" in the content of "state transition" is an overall explanation of the confidence change in the content of "state transition". Specifically, Figure 5 As shown, the specific implementation process of updating the confidence state and confidence level of the corresponding conditional branch instruction by using the state machine jump is as follows:

[0079] When the jump direction of the conditional branch instruction is jump, the confidence state jumps from IDLE to P1, the state machine unit outputs the confidence state P1, and the confidence confidence is 0; if it is not jump, the confidence state jumps from IDLE to M1, the state machine unit outputs the confidence state M1, and the confidence confidence is 0. When the conditional branch instruction is executed again, if the jump direction of the conditional branch instruction is jump and the confidence state is P1, the confidence state jumps to P2, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction is jump and the confidence state is M1, the confidence state jumps to P1, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction is not jump and the confidence state is P1, the confidence state jumps to M1, and the confidence confidence remains unchanged; if the conditional branch instruction is not jump, the confidence state is P1, the confidence state jumps to M1, and the confidence confidence remains unchanged; If the jump direction of the conditional branch instruction executed this time is not to jump, and the input confidence state is M1, the confidence state jumps to M2, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction executed this time is to jump, and the input confidence state is P2, the confidence state jumps to P3, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction executed this time is to jump, and the input confidence state is M2, the confidence state jumps to P1, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction executed this time is not to jump, and the input confidence state is When the confidence state entered is P2, the confidence state jumps to M1, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction entered this time is not to jump, and the confidence state entered is M2, the confidence state jumps to M3, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction entered this time is to jump, and the confidence state entered is P3, the confidence state jumps to P4, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction entered this time is to jump, and the confidence state entered is M3, the confidence state jumps to P1 , the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction input this time is not to jump, and the input confidence state is P3, the confidence state jumps to M1, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction input this time is not to jump, and the input confidence state is M3, the confidence state jumps to M4, and the confidence confidence remains unchanged; if the jump direction of the conditional branch instruction input this time is to jump, and the input confidence state is P4, the confidence state remains P4 unchanged, and the confidence confidence remains unchanged;If the jump direction of the conditional branch instruction input this time is jump, and the input confidence state is M4, the confidence state jumps to P1, and the confidence confidence is added by 1 to the original confidence input to the state machine unit; if the jump direction of the conditional branch instruction input this time is not jump, and the input confidence state is P4, the confidence state jumps to M1, and the confidence confidence is added by 1 to the original confidence input to the state machine unit; if the jump direction of the conditional branch instruction input this time is not jump, and the input confidence state is M4, the confidence state remains unchanged at M4, and the confidence confidence remains unchanged. ;

[0080] In a specific implementation, the updated confidence state and confidence level output by the state machine unit will be returned to the storage unit for updating the value in the storage unit; at the same time, the confidence level will also be transmitted to the random number generation unit for adjusting the probability of the random number generation unit generating 0 or 1.

[0081] In the architecture of the defense module, the random number generation unit is designed to generate a random number that is approximately uniformly distributed. A reference value is set in the random number generation unit. When the generated random number is less than the reference value, the random number generation unit will invert the jump direction of the input conditional branch instruction for this execution and output it, and update the saturation counter state in the BHT table entry of the conditional branch instruction. When the confidence of the input random number generation unit changes, the reference value will also change accordingly, that is, the probability of inverting the value representing the jump direction will also change, and the probability of inversion is related to the confidence of the conditional branch instruction.

[0082] Specifically, the jump direction value output by the random number generation unit is output to the BHT table entry, replacing the original jump direction value, and updating the saturation counter state corresponding to the conditional branch instruction. Since the jump direction probability used for updating is reversed, the saturation counter state corresponding to the conditional branch instruction in the BHT is unpredictable to the attacker, that is, invisible, to reduce the risk of Spectre-V1 attacks.

[0083] In an embodiment of the present application, the security branch predictor is a prediction module on the RI SC-V processor, and the security branch predictor includes an attack module and a defense module, wherein: the attack module is used to simulate attack training on the initial conditional branch instruction in the security branch predictor using a side channel attack program to obtain a target conditional branch instruction; the defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the security branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the security branch predictor. In the embodiment of the present application, the attack module simulates the side channel attack, so that the defense module can learn and adapt to the simulated attack mode, thereby improving the defense capability of the RI SC-V processor against the actual side channel attack based on the security branch predictor; by updating the current saturation counter state in the branch history table in a targeted manner, the attacker's perception of the saturation counter state can be effectively avoided, the risk of malicious attacks and data leakage can be reduced, the security and reliability of the system can be improved, and a high prediction accuracy can be maintained even in the presence of a side channel attack.

[0084] It is easy to understand that the embodiment of the present application designs a scheme for the branch predictor BHT part of the RI SC-V processor by identifying and recording conditional branch instructions that may encounter malicious training. When malicious training is likely to occur, the value used to update the corresponding saturation counter in the BHT is reversed with probability, which can effectively avoid the attacker's perception of the saturation counter state, reduce the risk of malicious attacks and data leakage, and improve the security and reliability of the system. That is, the embodiment of the present application provides a secure branch predictor design for defending against Spectre-V1 attacks on the RI SC-V processor, which can protect the RI SC-V processor from Spectre-V1 attacks while ensuring that the original functions of the RI SC-V processor are not affected. At the same time, the secure branch predictor design provided by the embodiment of the present application can also effectively mitigate other attacks on speculative execution and prevent security threats such as unauthorized access and data leakage.

[0085] See also Figure 6 , Figure 6 is an optional step flow chart of the operation method of the secure branch predictor based on RISC-V provided in the embodiment of the present application, which is applied to Figure 1 A secure branch predictor based on RI SC-V, wherein the secure branch predictor is a prediction module on the RI SC-V processor, and the secure branch predictor includes an attack module and a defense module, Figure 6 The method may include but is not limited to steps S601 to S604.

[0086] Step S601, using the attack module to perform simulated attack training on the initial conditional branch instruction in the security branch predictor using a side channel attack program to obtain a target conditional branch instruction;

[0087] Step S602, generating a target state update value according to the target conditional branch instruction by the defense module;

[0088] Optionally, the RISC-V processor includes an instruction fetch unit, an instruction decoding unit and a branch jump unit, and the instruction fetch unit includes a secure branch predictor.

[0089] In some embodiments, before step S602, it may also include: inputting the target conditional branch instruction into the instruction extraction unit of the RISC-V processor, pre-decoding the target conditional branch instruction through the instruction extraction unit, and obtaining the target conditional branch instruction information corresponding to the target conditional branch instruction; reading the current saturated counter state corresponding to the target conditional branch instruction in the branch history table through the instruction extraction unit according to the target conditional branch instruction information, and predicting the current predicted jump direction of the target conditional branch instruction according to the current saturated counter state, and transmitting the current predicted jump direction to the branch jump unit; obtaining the pre-decoded instruction information in the instruction extraction unit through the instruction decoding unit, and analyzing the pre-decoded instruction information to obtain the target instruction information, so as to transmit the target instruction information to the branch jump unit; performing branch calculation according to the target instruction information through the branch jump unit to obtain the target jump direction, and comparing the target jump direction with the current predicted jump direction to determine whether to update the current saturated counter state corresponding to the target conditional branch instruction.

[0090] Optionally, the defense module includes a storage unit, a state machine unit and a random number generation unit, the storage unit is used to store first confidence data corresponding to the target conditional branch instruction; wherein the first confidence data includes a first confidence state and a first confidence level,

[0091] In some embodiments, step S602 may include: updating the first confidence data through the state machine unit according to the first confidence state and the target jump direction output by the branch jump unit to obtain the second confidence data corresponding to the target conditional branch instruction; wherein the second confidence data includes the second confidence state and the second confidence level; and generating the target state update value through the random number generation unit according to the second confidence data.

[0092] Step S603, updating the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value through the defense module, and optimizing the security branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the security branch predictor;

[0093] In some embodiments, step S603 may include: updating the current jump direction value of the target conditional branch instruction according to the target state update value through the defense module, and updating the current jump direction of the target conditional branch instruction according to the current jump direction value; updating the current saturation counter state corresponding to the target conditional branch instruction according to the updated current jump direction through the defense module, and optimizing the security branch predictor based on the updated current saturation counter state.

[0094] Step S604, predicting the conditional branch instruction to be predicted on the RISC-V processor through the optimized security branch predictor to obtain a target security branch prediction result.

[0095] In the specific implementation, the attack module uses a side channel attack program to simulate the attack training of the initial conditional branch instruction in the security branch predictor to obtain the target conditional branch instruction; the defense module generates a target state update value according to the target conditional branch instruction, and updates the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, and optimizes the security branch predictor based on the updated current saturation counter state; finally, the optimized security branch predictor predicts the conditional branch instruction to be predicted on the RISC-V processor to obtain the target security branch prediction result. The security branch predictor is trained by designing a scheme to identify and record the conditional branch instructions that may encounter malicious training to obtain an optimized security branch predictor. When malicious training is likely to be encountered, the probability is reversed when updating the value of the corresponding saturation counter in the BHT based on the optimized security branch predictor, which can effectively avoid the attacker's perception of the saturation counter state, reduce the risk of malicious attacks and data leakage, and improve the security and reliability of the system.

[0096] In steps S601 to S604 shown in the embodiment of the present application, an attack module uses a side channel attack program to simulate attack training on the initial conditional branch instruction in the security branch predictor to obtain a target conditional branch instruction; a defense module generates a target state update value according to the target conditional branch instruction; the defense module updates the current saturated counter state corresponding to the target conditional branch instruction according to the target state update value, and optimizes the security branch predictor based on the updated current saturated counter state; wherein the current saturated counter state is stored in a branch history table in the security branch predictor; the optimized security branch predictor predicts the conditional branch instruction to be predicted on the RISC-V processor to obtain a target security branch prediction result. The embodiment of the present application simulates side channel attacks through an attack module, so that the defense module can learn and adapt to the simulated attack mode, thereby improving the defense capability of the RISC-V processor against actual side channel attacks based on the secure branch predictor; by performing targeted updates to the current saturation counter state in the branch history table, the attacker's perception of the saturation counter state can be effectively avoided, reducing the risk of malicious attacks and data leakage, and improving the security and reliability of the system; finally, based on the optimized secure branch predictor, the predicted conditional branch instructions are predicted, which can reduce the risk of malicious attacks and data leakage, and maintain a high prediction accuracy even in the presence of side channel attacks.

[0097] It should be pointed out that this embodiment only briefly illustrates the general process of the operation method of the RISC-V-based secure branch predictor. The detailed description of each step can refer to the relevant content in the aforementioned RISC-V-based secure branch predictor embodiment, which will not be repeated here. It can be understood that the present invention is not limited to this.

[0098] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above-mentioned RISC-V-based secure branch predictor operation method when executing the computer program. The electronic device can be any intelligent terminal including a tablet computer, a car computer, etc.

[0099] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0100] See also Figure 7 , Figure 7 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0101] The processor 701 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0102] The memory 702 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 702 can store an operating system and other applications. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 702, and the processor 701 calls and executes the operation method of the RISC-V-based secure branch predictor in the embodiment of this application;

[0103] Input / output interface 703, used to implement information input and output;

[0104] Communication interface 704, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0105] A bus 705 that transmits information between the various components of the device (e.g., the processor 701, the memory 702, the input / output interface 703, and the communication interface 704);

[0106] The processor 701 , the memory 702 , the input / output interface 703 and the communication interface 704 are connected to each other in communication within the device via a bus 705 .

[0107] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, it implements the operating method of the above-mentioned RISC-V-based secure branch predictor.

[0108] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiments, the functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0109] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0110] The embodiment of the present application provides a secure branch predictor based on RI SC-V and an operation method thereof. The secure branch predictor is a prediction module on the RI SC-V processor. The secure branch predictor includes an attack module and a defense module, wherein: the attack module is used to simulate attack training on the initial conditional branch instruction in the secure branch predictor using a side channel attack program to obtain a target conditional branch instruction; the defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the secure branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the secure branch predictor. The embodiment of the present application simulates a side channel attack through the attack module, so that the defense module can learn and adapt to the simulated attack mode, thereby improving the defense capability of the RI SC-V processor against actual side channel attacks based on the secure branch predictor; by updating the current saturation counter state in the branch history table in a targeted manner, the attacker's perception of the saturation counter state can be effectively avoided, the risk of malicious attacks and data leakage can be reduced, the security and reliability of the system can be improved, and a high prediction accuracy can be maintained even in the presence of a side channel attack.

[0111] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0112] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0113] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0115] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0116] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0117] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0118] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0120] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0121] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A secure branch predictor based on RISC-V, wherein the secure branch predictor is a prediction module on a RISC-V processor, characterized in that: The secure branch predictor includes an attack module and a defense module, wherein: The attack module is used to use a side channel attack program to perform simulated attack training on the initial conditional branch instruction in the security branch predictor to obtain a target conditional branch instruction; The defense module is used to generate a target state update value according to the target conditional branch instruction, and update the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, so as to optimize the security branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the security branch predictor.

2. The RISC-V based secure branch predictor according to claim 1, characterized in that: The defense module includes a storage unit, a state machine unit and a random number generation unit, wherein: The storage unit is used to store the first confidence data corresponding to the target conditional branch instruction; wherein the first confidence data includes a first confidence state and a first confidence level; The state machine unit is used to update the first confidence data to obtain second confidence data corresponding to the target conditional branch instruction; wherein the second confidence data includes a second confidence state and a second confidence level; The random number generation unit is used to generate the target state update value according to the second confidence data.

3. The RISC-V based secure branch predictor according to claim 1, characterized in that: The target state update value is used to update the current jump direction value of the target conditional branch instruction to update the current jump direction of the target conditional branch instruction.

4. The RISC-V based secure branch predictor according to claim 1, characterized in that: The RISC-V processor includes an instruction fetch unit, an instruction decoding unit and a branch jump unit, and the instruction fetch unit includes the secure branch predictor, wherein: The instruction extraction unit is used to pre-decode the target conditional branch instruction to obtain target conditional branch instruction information, and read the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, so as to predict the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmit the current predicted jump direction to the branch jump unit; The instruction decoding unit is used to obtain the pre-decoded instruction information in the instruction fetching unit, and analyze the pre-decoded instruction information to obtain target instruction information, so as to transmit the target instruction information to the branch jump unit; The branch jump unit is used to perform branch calculation according to the target instruction information to obtain a target jump direction, and compare the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

5. A method for operating a RISC-V-based secure branch predictor, applied to a RISC-V-based secure branch predictor as claimed in any one of claims 1 to 4, wherein the secure branch predictor is a prediction module on a RISC-V processor, characterized in that: The security branch predictor comprises an attack module and a defense module, and the method comprises the following steps: The attack module uses a side channel attack program to perform simulated attack training on the initial conditional branch instruction in the security branch predictor to obtain a target conditional branch instruction; Generate a target state update value according to the target conditional branch instruction by the defense module; The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the target state update value, and optimizes the security branch predictor based on the updated current saturation counter state; wherein the current saturation counter state is stored in a branch history table in the security branch predictor; The optimized secure branch predictor is used to predict the conditional branch instructions to be predicted on the RISC-V processor to obtain a target secure branch prediction result.

6. The method according to claim 5, characterized in that The RISC-V processor includes an instruction fetch unit, an instruction decoding unit and a branch jump unit, the instruction fetch unit includes the secure branch predictor, and before the target state update value is generated according to the target conditional branch instruction by the defense module, the method further includes: Inputting the target conditional branch instruction into the instruction extraction unit of the RISC-V processor, pre-decoding the target conditional branch instruction through the instruction extraction unit, and obtaining target conditional branch instruction information corresponding to the target conditional branch instruction; The instruction extraction unit reads the current saturation counter state corresponding to the target conditional branch instruction in the branch history table according to the target conditional branch instruction information, predicts the current predicted jump direction of the target conditional branch instruction according to the current saturation counter state, and transmits the current predicted jump direction to the branch jump unit; Acquire pre-decoded instruction information in the instruction fetching unit through the instruction decoding unit, and analyze the pre-decoded instruction information to obtain target instruction information, so as to transmit the target instruction information to the branch jump unit; The branch jump unit performs branch calculation according to the target instruction information to obtain a target jump direction, and compares the target jump direction with the current predicted jump direction to determine whether to update the current saturation counter state corresponding to the target conditional branch instruction.

7. The method according to claim 6, characterized in that The defense module includes a storage unit, a state machine unit and a random number generation unit, wherein the storage unit is used to store first confidence data corresponding to the target conditional branch instruction; wherein the first confidence data includes a first confidence state and a first confidence level, and the generation of a target state update value according to the target conditional branch instruction by the defense module includes: The first confidence data is updated by the state machine unit according to the first confidence state and the target jump direction output by the branch jump unit to obtain second confidence data corresponding to the target conditional branch instruction; wherein the second confidence data includes a second confidence state and a second confidence level; The target state update value is generated according to the second confidence data by the random number generation unit.

8. The method according to claim 5, characterized in that The updating of the current saturation counter state corresponding to the target conditional branch instruction by the defense module according to the target state update value, and optimizing the security branch predictor based on the updated current saturation counter state, includes: updating the current jump direction value of the target conditional branch instruction according to the target state update value through the defense module, and updating the current jump direction of the target conditional branch instruction according to the current jump direction value; The defense module updates the current saturation counter state corresponding to the target conditional branch instruction according to the updated current jump direction, and optimizes the security branch predictor based on the updated current saturation counter state.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 5 to 8 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 5 to 8 is implemented.

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