WiFi signal sniffing and data transmission equipment with double transmission modes

Abstract

The invention discloses WiFi signal sniffing and data transmission equipment with double transmission modes. The WiFi signal sniffing and data transmission equipment comprises a first WiFi chip, a second WiFi chip, a third WiFi chip, a fourth WiFi chip, an Ethernet chip and a main control chip, when the transmission mode is a wired transmission mode, the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are used for sniffing WiFi data; the main control chip is used for classifying WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip; the Ethernet chip is used for sending the classified WiFi data to the server; when the transmission mode is a wireless transmission mode, the first WiFi chip, the second WiFi chip and the third WiFi chip are used for sniffing WiFi data; the main control chip is used for classifying WiFi data sniffed by the first WiFi chip, the second WiFi chip and the third WiFi chip; and the fourth WiFi chip is used for sending the classified WiFi data to the server. According to the invention, the deployment flexibility and adaptive capacity of equipment can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of WiFi signal sniffing, and more specifically to a WiFi signal sniffing and data transmission device with dual transmission modes. Background Art

[0002] With the rapid development of wireless communication technology, WiFi networks have become an important infrastructure in modern society and are widely used in various public and private places. WiFi signal sniffing technology has been widely used in network security, user behavior analysis, device management and other fields. Through WiFi sniffing devices, users can monitor the operating status of wireless networks, collect relevant information about connected devices, and help improve network security and optimize performance. However, the existing WiFi signal sniffing technology still has some problems and limitations in the application process.

[0003] In the prior art, WiFi signal sniffing devices mainly rely on a single transmission mode, namely the wired transmission mode. Although this method performs well in data transmission speed and stability, it limits the flexibility of the device. The deployment of the device usually requires complex wiring, which increases the installation cost and time. At the same time, in mobile scenarios or large areas, the wired transmission mode limits the mobility of the device, making it difficult to achieve flexible real-time monitoring and data transmission. In addition, existing devices are usually equipped with only one or two WiFi modules for sniffing signals, which may not be able to effectively cope with the needs of large-scale data processing in high-density wireless environments.

[0004] In order to deal with these problems, some existing technologies have begun to adopt wireless transmission mode, but its data transmission stability and speed are not as good as the wired mode, especially when processing large-scale data, the transmission efficiency is low. At the same time, most of the devices in the prior art have not realized the integration of dual transmission modes, that is, the mixed use of wired and wireless. Even if the wireless transmission mode is adopted, the real-time processing capability of the sniffer is also limited, and the device is usually unable to sniff and transmit data at the same time. This makes the flexibility and efficiency of existing WiFi sniffing devices still insufficient in actual application scenarios.

[0005] Therefore, how to provide a WiFi signal sniffing and data transmission device with dual transmission modes is a problem that technical personnel in this field need to solve urgently. Summary of the invention

[0006] In view of this, the present invention provides a WiFi signal sniffing and data transmission device with dual transmission modes.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A WiFi signal sniffing and data transmission device with dual transmission modes, comprising a first WiFi chip, a second WiFi chip, a third WiFi chip, a fourth WiFi chip, an Ethernet chip and a main control chip;

[0009] The first WiFi chip, the second WiFi chip, the third WiFi chip, the fourth WiFi chip, and the Ethernet chip are all communicatively connected to the main control chip;

[0010] When the transmission mode is wired transmission mode:

[0011] The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are used to sniff WiFi data;

[0012] The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip;

[0013] The Ethernet chip is used to send the classified WiFi data to the server;

[0014] When the transmission mode is wireless transmission mode:

[0015] The first WiFi chip, the second WiFi chip, and the third WiFi chip are used to sniff WiFi data;

[0016] The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip and the third WiFi chip;

[0017] The fourth WiFi chip is used to send the classified WiFi data to the server.

[0018] Preferably, the Ethernet chip is wired to the server via a standard RJ45 interface.

[0019] The first WiFi chip, the second WiFi chip, the third WiFi chip, and the fourth WiFi chip are all connected to the main control chip through a serial port.

[0020] Preferably, the main control chip classifies the sniffed WiFi data based on the following steps:

[0021] S1: Use mutual information and variance analysis to evaluate each feature in the sniffed WiFi data, and select target features from each feature; wherein each feature includes frequency, RSSI range, RSSI kurtosis, RSSI difference, RSSI median, RSSI mean, RSSI standardization, RSSI deviation, RSSI coefficient of variation; the target features are several features with the highest F value of variance analysis;

[0022] S2: Standardizing the target feature;

[0023] S3: input the standardized target features into the model selector, and select the corresponding classifier model based on the output result of the model selector;

[0024] in,

[0025] The model selector is a naive Bayes model;

[0026] The classifier model includes an optimized logistic regression model and an optimized decision tree model;

[0027] The optimized logistic regression model is a logistic regression model that introduces L1 regularization; the L1 regularization is used to remove the target feature with the lowest mutual information value;

[0028] The optimized decision tree model is a decision tree model that reduces model complexity by limiting the maximum depth and adopting cost complexity pruning technology;

[0029] S4: Input the standardized target features into the classifier model selected in S3 to obtain the classification results.

[0030] Preferably, the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are all ESP07S chips; that is, the first WiFi chip is a first ESP07S chip, the second WiFi chip is a second ESP07S chip, the third WiFi chip is a third ESP07S chip, and the fourth WiFi chip is a fourth ESP07S chip;

[0031] The main control chip is a STM32F103RCT6 chip;

[0032] The Ethernet chip is a W5500 chip.

[0033] Preferably, the PC6 pin of the STM32F103RCT6 chip is connected to the SCSn pin of the W5500 chip;

[0034] The PB15 pin of the STM32F103RCT6 chip is connected to the SCLK pin of the W5500 chip;

[0035] The PB14 pin of the STM32F103RCT6 chip is connected to the MISO pin of the W5500 chip;

[0036] The PB13 pin of the STM32F103RCT6 chip is connected to the MOSI pin of the W5500 chip;

[0037] The PB12 pin of the STM32F103RCT6 chip is connected to the INTn pin of the W5500 chip;

[0038] The PB1 pin of the STM32F103RCT6 chip is connected to the RSTn pin of the W5500 chip.

[0039] Preferably, the TXD0 pin of the first ESP07S chip is connected to the PA10 pin of the STM32F103RCT6 chip;

[0040] The RXD0 pin of the first ESP07S chip is connected to the PA9 pin of the STM32F103RCT6 chip;

[0041] The RST pin of the first ESP07S chip is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC;

[0042] The RST pin of the first ESP07S chip is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded;

[0043] The RST pin of the first ESP07S chip is connected to the PA11 pin of the STM32F103RCT6 chip;

[0044] The EN pin of the first ESP07S chip is connected to the power supply VCC through a resistor R2;

[0045] The GPIO0 pin of the first ESP07S chip is connected to the power supply VCC through a resistor R3;

[0046] The GPIO2 pin of the first ESP07S chip is connected to the power supply VCC through a resistor R4;

[0047] The GPIO15 pin of the first ESP07S chip is grounded via a resistor R5.

[0048] Preferably, the TXD0 pin of the second ESP07S chip is connected to the PA3 pin of the STM32F103RCT6 chip;

[0049] The RXD0 pin of the second ESP07S chip is connected to the PA2 pin of the STM32F103RCT6 chip;

[0050] The RST pin of the second ESP07S chip is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply VCC;

[0051] The RST pin of the second ESP07S chip is connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded;

[0052] The RST pin of the second ESP07S chip is connected to the PC9 pin of the STM32F103RCT6 chip;

[0053] The EN pin of the second ESP07S chip is connected to the power supply VCC through a resistor R7;

[0054] The GPIO0 pin of the second ESP07S chip is connected to the power supply VCC through a resistor R8;

[0055] The GPIO2 pin of the second ESP07S chip is connected to the power supply VCC through a resistor R9;

[0056] The GPIO15 pin of the second ESP07S chip is grounded via a resistor R10.

[0057] Preferably, the TXD0 pin of the third ESP07S chip is connected to the PB11 pin of the STM32F103RCT6 chip;

[0058] The RXD0 pin of the third ESP07S chip is connected to the PB10 pin of the STM32F103RCT6 chip;

[0059] The RST pin of the third ESP07S chip is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to the power supply VCC;

[0060] The RST pin of the third ESP07S chip is connected to one end of the capacitor C3, and the other end of the capacitor C3 is grounded;

[0061] The RST pin of the third ESP07S chip is connected to the PA8 pin of the STM32F103RCT6 chip;

[0062] The EN pin of the third ESP07S chip is connected to the power supply VCC through a resistor R12;

[0063] The GPIO0 pin of the third ESP07S chip is connected to the power supply VCC through a resistor R13;

[0064] The GPIO2 pin of the third ESP07S chip is connected to the power supply VCC through a resistor R14;

[0065] The GPIO15 pin of the third ESP07S chip is grounded via a resistor R15.

[0066] Preferably, the TXD0 pin of the fourth ESP07S chip is connected to the PC11 pin of the STM32F103RCT6 chip;

[0067] The RXD0 pin of the fourth ESP07S chip is connected to the PC10 pin of the STM32F103RCT6 chip;

[0068] The RST pin of the fourth ESP07S chip is connected to one end of a resistor R16, and the other end of the resistor R16 is connected to a power supply VCC;

[0069] The RST pin of the fourth ESP07S chip is connected to one end of the capacitor C4, and the other end of the capacitor C4 is grounded;

[0070] The RST pin of the fourth ESP07S chip is connected to the PA12 pin of the STM32F103RCT6 chip;

[0071] The EN pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R17;

[0072] The GPIO0 pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R18;

[0073] The GPIO2 pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R19;

[0074] The GPIO15 of the fourth ESP07S chip is grounded through a resistor R20.

[0075] Preferably, the INTn pin of the W5500 chip is connected to the power supply VCC via a resistor R22;

[0076] The SCSn pin of the W5500 chip is connected to the power supply VCC through a resistor R23;

[0077] The RSTn pin of the W5500 chip is connected to the power supply VCC through a resistor R21;

[0078] The EXRES1 pin of the W5500 chip is grounded via a resistor R24;

[0079] The TOCAP pin of the W5500 chip is grounded via capacitor C5;

[0080] The 1V2O pin of the W5500 chip is grounded via capacitor C6;

[0081] The RSVD pin of the W5500 chip is grounded.

[0082] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a WiFi signal sniffing and data transmission device with dual transmission modes, which can achieve the following beneficial technical effects:

[0083] 1) The present invention can flexibly perform data transmission in both wired and wireless modes, thereby improving the deployment flexibility and adaptability of the equipment;

[0084] 2) The device of the present invention integrates multiple WiFi modules and can process WiFi signals of multiple channels simultaneously, which significantly improves the signal capture capability and is suitable for high-density wireless environments.

[0085] 3) The present invention deploys a WiFi data classification algorithm on the main control chip, which effectively reduces unnecessary data transmission, significantly reduces the pressure of server-side storage and processing, and improves the accuracy and efficiency of data analysis and network monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0087] Figure 1 A schematic diagram of the structure of a WiFi signal sniffing and data transmission device in a dual transmission mode provided by the present invention;

[0088] Figure 2 A circuit schematic diagram of the first ESP07S chip provided by the present invention;

[0089] Figure 3 A circuit schematic diagram of a second ESP07S chip provided by the present invention;

[0090] Figure 4 A circuit schematic diagram of the third ESP07S chip provided by the present invention;

[0091] Figure 5 A circuit schematic diagram of the fourth ESP07S chip provided by the present invention;

[0092] Figure 6 The circuit schematic diagram of the STM32F103RCT6 chip provided by the present invention;

[0093] Figure 7 This is a circuit schematic diagram of the W5500 chip provided by the present invention. DETAILED DESCRIPTION

[0094] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0095] like Figure 1-Figure 7 As shown, an embodiment of the present invention discloses a WiFi signal sniffing and data transmission device with dual transmission modes, including a first WiFi chip, a second WiFi chip, a third WiFi chip, a fourth WiFi chip, an Ethernet chip and a main control chip;

[0096] The first WiFi chip, the second WiFi chip, the third WiFi chip, the fourth WiFi chip, and the Ethernet chip are all communicatively connected to the main control chip;

[0097] When the transmission mode is wired transmission mode:

[0098] The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are used to sniff WiFi data;

[0099] The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip;

[0100] The Ethernet chip is used to send the classified WiFi data to the server;

[0101] When the transmission mode is wireless transmission mode:

[0102] The first WiFi chip, the second WiFi chip, and the third WiFi chip are used to sniff WiFi data;

[0103] The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip and the third WiFi chip;

[0104] The fourth WiFi chip is used to send the classified WiFi data to the server.

[0105] In one embodiment, the Ethernet chip is connected to the server by wire through a standard RJ45 interface; the first WiFi chip, the second WiFi chip, the third WiFi chip, and the fourth WiFi chip are all connected to the main control chip through a serial port.

[0106] It can be understood that: the Ethernet chip sends the classified WiFi data to the server through the standard RJ45 interface; the server is used to store and display the classified WiFi data.

[0107] In a certain embodiment, the main control chip classifies the sniffed WiFi data based on the following steps:

[0108] S1: Use mutual information and variance analysis to evaluate each feature in the sniffed WiFi data, and select target features from each feature; wherein each feature includes frequency, RSSI range, RSSI kurtosis, RSSI difference, RSSI median, RSSI mean, RSSI standardization, RSSI deviation, RSSI coefficient of variation; the target features are the features with the highest mutual information value and F value of variance analysis;

[0109] Specifically, the present invention screens out the top five features of the F value of variance analysis, namely frequency, RSSI range, RSSI kurtosis, RSSI difference, and RSSI median. The specific values ​​are shown in the following table.

[0110] feature ANOVAF value Mutual Information Score frequency 155.659627 0.147381 RSSI Range 134.361794 0.071618 RSSI Kurtosis 13.122748 0.007954 RSSI Difference 6.135618 0.051190 Median RSSI 5.665123 0.030527 RSSI average value 4.488593 0.046209 RSSI Standard Deviation 2.454583 0.021785 RSSI Skewness 1.039151 0.000000 RSSI Coefficient of Variation 0.000005 0.011198

[0111] Specifically: The mutual information formula is:

[0112] Where I(X; Y) represents the mutual information value; X represents the feature, Y represents the classification label, p(x, y) is the joint probability distribution of X and Y, and p(x) and p(y) are the marginal probability distributions of X and Y, respectively.

[0113] Specifically: The F value formula for variance analysis is:

[0114] Among them, F represents the F value of variance analysis; Between-group variance: represents the variance between different groups, that is, the degree of variation between the mean values ​​of each group. It measures the difference between the means of each group. Within-group variance": represents the variance within each group, that is, the degree of variation between the observations in the same group. It reflects the degree of discreteness of the data within each group.

[0115] The mutual information formula is used to evaluate the correlation between each feature and the classification label, where the joint probability distribution and marginal probability distribution describe the dependency between the feature and the classification result. The F-value formula of variance analysis is used to measure the distribution difference of features between different classification labels, and to determine the importance of features by comparing the variance between groups and the variance within groups.

[0116] S2: Standardizing the target feature;

[0117] Specific: The standardized formula is:

[0118] Among them, x represents the feature before standardization; x norm represents the standardized feature; μ represents the feature mean, and σ represents the feature standard deviation.

[0119] S3: input the standardized target features into the model selector, and select the corresponding classifier model based on the output result of the model selector;

[0120] in,

[0121] The model selector is a naive Bayes model;

[0122] The classifier model includes an optimized logistic regression model and an optimized decision tree model;

[0123] The optimized logistic regression model is a logistic regression model that introduces L1 regularization;

[0124] The optimized decision tree model is a decision tree model that reduces model complexity by limiting the maximum depth and adopting cost complexity pruning technology;

[0125] 1) The logistic regression loss function with L1 regularization is:

[0126]

[0127]

[0128] Where n is the number of samples; y (i) is the true label of the i-th sample; h β (x (i) ) is the predicted probability of the model for the i-th sample; β is the weight vector;

[0129] It is understandable that L1 regularization compresses the coefficient of the RSSI kurtosis feature to zero, and ultimately only four features are retained: frequency, RSSI range, RSSI difference, and RSSI median (that is, the RSSI kurtosis with the lowest mutual information score is removed).

[0130] The introduction of regularization significantly reduces the number of model parameters and only retains features that have a significant impact on the classification results, thereby reducing the demand for computing resources and improving operating efficiency in embedded environments.

[0131] 2) The pruning loss function is:

[0132] R α (T) = R(T) + α × size(f);

[0133] Among them, R(T) represents the error of the decision tree, α is the complexity penalty parameter, which is used to balance the accuracy and simplicity of the model. By increasing α, the number of leaf nodes of the decision tree can be effectively reduced, overfitting can be avoided, and resource consumption can be reduced; size(T) is the number of leaf nodes.

[0134] The decision formula for classifier model selection is:

[0135]

[0136] Among them, s(x) represents the selected classifier model; PNB(LR|x) and PNB(DT|x) are the output results of the model selector, which respectively represent the probability that the standardized target feature x belongs to the logistic regression model and the decision tree model; LR represents the optimized logistic regression model; DT represents the optimized decision tree model; through this dynamic selection strategy, it is ensured that the classifier adapts to the current features, so that it can operate efficiently in different scenarios.

[0137] S4: Input the standardized target features into the classification model selected in S3 to obtain the classification results.

[0138] After the classification is completed, the classification results and characteristic statistical information (including frequency, RSSI range, RSSI kurtosis, RSSI difference, RSSI median) of each WIFI device are recorded and stored. The output results include the MAC address of the WIFI device, the classification label (fixed device or mobile device), the classification confidence and the characteristic information within the time window (including frequency, RSSI range, RSSI kurtosis, RSSI difference, RSSI median). Based on the classification results, only the mobile device data (specifically mobile phones, watches and other portable devices with WiFi functions, the WiFi signals of these devices are captured by the device and used for location analysis) are transmitted to the server, which greatly reduces useless data.

[0139] The present invention adopts a sliding window mechanism to aggregate and classify WiFi data once every minute, ensuring that the classification results are updated in a timely manner and adapt to dynamic environmental changes.

[0140] In one embodiment, the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are all ESP07S chips; that is, the first WiFi chip is a first ESP07S chip, the second WiFi chip is a second ESP07S chip, the third WiFi chip is a third ESP07S chip, and the fourth WiFi chip is a fourth ESP07S chip;

[0141] The main control chip is a STM32F103RCT6 chip;

[0142] The Ethernet chip is a W5500 chip.

[0143] In one embodiment, the PC6 pin of the STM32F103RCT6 chip is connected to the SCSn pin of the W5500 chip;

[0144] The PB15 pin of the STM32F103RCT6 chip is connected to the SCLK pin of the W5500 chip;

[0145] The PB14 pin of the STM32F103RCT6 chip is connected to the MISO pin of the W5500 chip;

[0146] The PB13 pin of the STM32F103RCT6 chip is connected to the MOSI pin of the W5500 chip;

[0147] The PB12 pin of the STM32F103RCT6 chip is connected to the INTn pin of the W5500 chip;

[0148] The PB1 pin of the STM32F103RCT6 chip is connected to the RSTn pin of the W5500 chip.

[0149] In one embodiment, the PA13 pin of the STM32F103RCT6 chip is connected to a data line of a debugging interface;

[0150] The PA14 pin of the STM32F103RCT6 chip is connected to the clock line of the debug interface;

[0151] It can be understood that: the debug interface is used to debug the program in the STM32F103RCT6 chip;

[0152] The NRST pin of the STM32F103RCT6 chip is connected to the reset circuit;

[0153] It can be understood that: the reset circuit is used to reset the STM32F103RCT6 chip;

[0154] In one embodiment, the TXD0 pin of the first ESP07S chip is connected to the PA10 pin of the STM32F103RCT6 chip;

[0155] The RXD0 pin of the first ESP07S chip is connected to the PA9 pin of the STM32F103RCT6 chip;

[0156] The RST pin of the first ESP07S chip is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC;

[0157] The RST pin of the first ESP07S chip is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded;

[0158] The RST pin of the first ESP07S chip is connected to the PA11 pin of the STM32F103RCT6 chip;

[0159] The EN pin of the first ESP07S chip is connected to the power supply VCC through a resistor R2;

[0160] The GPIO0 pin of the first ESP07S chip is connected to the power supply VCC through a resistor R3;

[0161] The GPIO2 pin of the first ESP07S chip is connected to the power supply VCC through a resistor R4;

[0162] The GPIO15 pin of the first ESP07S chip is grounded via a resistor R5.

[0163] It can be understood that: the GPIO0 pin of the first ESP07S chip is pulled up to VCC through the resistor R3, which is used for the startup mode selection of the first ESP07S chip;

[0164] The GPIO2 pin of the first ESP07S chip is pulled up to VCC through a resistor R4 to ensure that the first ESP07S chip starts normally;

[0165] The GPIO15 pin of the first ESP07S chip is grounded through a resistor R5 to ensure that the first ESP07S chip starts normally.

[0166] In one embodiment, the TXD0 pin of the second ESP07S chip is connected to the PA3 pin of the STM32F103RCT6 chip;

[0167] The RXD0 pin of the second ESP07S chip is connected to the PA2 pin of the STM32F103RCT6 chip;

[0168] The RST pin of the second ESP07S chip is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply VCC;

[0169] The RST pin of the second ESP07S chip is connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded;

[0170] The RST pin of the second ESP07S chip is connected to the PC9 pin of the STM32F103RCT6 chip;

[0171] The EN pin of the second ESP07S chip is connected to the power supply VCC through a resistor R7;

[0172] The GPIO0 pin of the second ESP07S chip is connected to the power supply VCC through a resistor R8;

[0173] The GPIO2 pin of the second ESP07S chip is connected to the power supply VCC through a resistor R9;

[0174] The GPIO15 pin of the second ESP07S chip is grounded via a resistor R10.

[0175] It can be understood that: the GPIO0 pin of the second ESP07S chip is pulled up to VCC through the resistor R8, which is used for the startup mode selection of the second ESP07S chip;

[0176] The GPIO2 pin of the second ESP07S chip is pulled up to VCC through a resistor R9 to ensure that the second EESP07S chip starts normally;

[0177] The GPIO15 pin of the second ESP07S chip is grounded through a resistor R10 to ensure that the second ESP07S chip starts normally.

[0178] In one embodiment, the TXD0 pin of the third ESP07S chip is connected to the PB11 pin of the STM32F103RCT6 chip;

[0179] The RXD0 pin of the third ESP07S chip is connected to the PB10 pin of the STM32F103RCT6 chip;

[0180] The RST pin of the third ESP07S chip is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to the power supply VCC;

[0181] The RST pin of the third ESP07S chip is connected to one end of the capacitor C3, and the other end of the capacitor C3 is grounded;

[0182] The RST pin of the third ESP07S chip is connected to the PA8 pin of the STM32F103RCT6 chip;

[0183] The EN pin of the third ESP07S chip is connected to the power supply VCC through a resistor R12;

[0184] The GPIO0 pin of the third ESP07S chip is connected to the power supply VCC through a resistor R13;

[0185] The GPIO2 pin of the third ESP07S chip is connected to the power supply VCC through a resistor R14;

[0186] The GPIO15 pin of the third ESP07S chip is grounded via a resistor R15.

[0187] It can be understood that: the GPIO0 pin of the third ESP07S chip is pulled up to VCC through the resistor R13, which is used for the startup mode selection of the third ESP07S chip;

[0188] The GPIO2 pin of the third ESP07S chip is pulled up to VCC through a resistor R14 to ensure that the third ESP07S chip starts normally;

[0189] The GPIO15 pin of the third ESP07S chip is grounded through a resistor R15 to ensure that the third ESP07S chip starts normally.

[0190] In one embodiment, the TXD0 pin of the fourth ESP07S chip is connected to the PC11 pin of the STM32F103RCT6 chip;

[0191] The RXD0 pin of the fourth ESP07S chip is connected to the PC10 pin of the STM32F103RCT6 chip;

[0192] The RST pin of the fourth ESP07S chip is connected to one end of a resistor R16, and the other end of the resistor R16 is connected to a power supply VCC;

[0193] The RST pin of the fourth ESP07S chip is connected to one end of the capacitor C4, and the other end of the capacitor C4 is grounded;

[0194] The RST pin of the fourth ESP07S chip is connected to the PA12 pin of the STM32F103RCT6 chip;

[0195] The EN pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R17;

[0196] The GPIO0 pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R18;

[0197] The GPIO2 pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R19;

[0198] The GPIO15 of the fourth ESP07S chip is grounded through a resistor R20.

[0199] It can be understood that: the GPIO0 pin of the fourth ESP07S chip is pulled up to VCC through the resistor R18, which is used for the startup mode selection of the fourth ESP07S chip;

[0200] The GPIO2 pin of the fourth ESP07S chip is pulled up to VCC through a resistor R19 to ensure that the fourth ESP07S chip starts normally;

[0201] The GPIO15 pin of the fourth ESP07S chip is grounded through a resistor R20 to ensure that the fourth ESP07S chip starts normally.

[0202] In one embodiment, the INTn pin of the W5500 chip is connected to the power supply VCC via a resistor R22;

[0203] The SCSn pin of the W5500 chip is connected to the power supply VCC through a resistor R23;

[0204] The RSTn pin of the W5500 chip is connected to the power supply VCC through a resistor R21;

[0205] The EXRES1 pin of the W5500 chip is grounded via a resistor R24;

[0206] The TOCAP pin of the W5500 chip is grounded via capacitor C5;

[0207] The 1V2O pin of the W5500 chip is grounded via capacitor C6;

[0208] The RSVD pin of the W5500 chip is grounded.

[0209] The TXN pin of the W5500 chip is connected to the TX- pin of the RJ45 interface through a 75Ω resistor R25;

[0210] The TXP pin of the W5500 chip is connected to the TX+ pin of the RJ45 interface through a 75Ω resistor R26;

[0211] The RXN pin of the W5500 chip is connected to the RX- pin of the RJ45 interface;

[0212] The RXP pin of the W5500 chip is connected to the RX+ pin of the RJ45 interface;

[0213] The LINKLED pin of the W5500 chip is connected to the LED0- pin and LED0+ pin of the RJ45 interface;

[0214] The DUPLED pin of the W5500 chip is left floating;

[0215] The ACTLED pin of the W5500 chip is connected to the LED1- pin and LED1+ pin of the RJ45 interface.

[0216] RJ45 is connected to the server using existing standard Ethernet technology and can be connected using a regular CAT5 / CAT6 network cable.

[0217] In one embodiment, the values ​​of the resistors and capacitors are as follows:

[0218] C1, C2, C3, C4: 0.1uF;

[0219] R1, R6, R11, R16: 10K ohms;

[0220] R2, R3, R4, R7, R8, R9, R12, R13, R14, R17, R18, R19: 10K ohms;

[0221] R5, R10, R15, R20: 46 EUR;

[0222] R21, R22, R23: 10K ohms;

[0223] R24: 12.4K ohms;

[0224] C5:4.7uF;

[0225] C6: 0.01uF;

[0226] The working principle of the present invention is as follows:

[0227] Based on the actual application scenario, select wired transmission mode and wireless transmission mode;

[0228] 1. In wired transmission mode, the four ESP07S chips on the device are responsible for sniffing WiFi data on four different channels, and transmitting the sniffed data to STM32F103RCT6. STM32F103RCT6 classifies the data, and then uses the W5500 chip to transmit the classified data to the server through the RJ45 network cable interface. Before the sniffer works, the sniffer's local IP, target IP, subnet mask, etc. need to be set. These settings ensure that the device can send data correctly via wired mode.

[0229] 2. In wireless transmission mode, set one ESP07S chip to transparent transmission mode. In transparent transmission mode setting, you need to first connect the transparent transmission chip to the WiFi network, then configure the IP address and port number of the server (destination), and finally adjust it to transparent transmission mode, so that there is no need to configure again after the device is powered off and reconnected. The other three ESP07S chips are responsible for sniffing WiFi data on three different channels, transmitting the sniffed data to the STM32F103RCT6 chip, which classifies the data and then uses the ESP07S set to transparent transmission mode to transmit the classified data to the server (the STM32F103RCT6 main control chip needs to be set so that after receiving the data sniffed by the three sniffers, it will directly send the data to the ESP07S set to transparent transmission mode). These settings ensure that the device can send data correctly via wireless.

[0230] It is understandable that:

[0231] The present invention uses AiThinkerIDE software to program the ESP07S chip. The present invention sets the function mode (transmitting mode or sniffing mode) for each ESP07S chip through AiThinkerIDE software.

[0232] The present invention uses flash_download_tool to program the ESP07S chip.

[0233] The present invention uses a serial port device to set the functional mode of the ESP07S chip. In the wired transmission mode, all ESP07S chips are set to the sniffing mode. In the wireless transmission mode, one of the ESP07S chips is set to the transparent transmission mode, and the other three remain in the sniffing mode.

[0234] The present invention uses IAR Embedded Workbench software to program STM32F103RCT6.

[0235] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0236] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein.

[0237] Rather, it is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A WiFi signal sniffing and data transmission device with dual transmission modes, characterized in that: It includes a first WiFi chip, a second WiFi chip, a third WiFi chip, a fourth WiFi chip, an Ethernet chip and a main control chip; The first WiFi chip, the second WiFi chip, the third WiFi chip, the fourth WiFi chip, and the Ethernet chip are all communicatively connected to the main control chip; When the transmission mode is wired transmission mode: The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are used to sniff WiFi data; The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip; The Ethernet chip is used to send the classified WiFi data to the server; When the transmission mode is wireless transmission mode: The first WiFi chip, the second WiFi chip, and the third WiFi chip are used to sniff WiFi data; The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip and the third WiFi chip; The fourth WiFi chip is used to send the classified WiFi data to the server.

2. A WiFi signal sniffing and data transmission device with dual transmission modes according to claim 1, characterized in that: The Ethernet chip is connected to the server via a standard RJ45 interface. The first WiFi chip, the second WiFi chip, the third WiFi chip, and the fourth WiFi chip are all connected to the main control chip through a serial port.

3. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 1, characterized in that: The main control chip classifies the sniffed WiFi data based on the following steps; S1: Use mutual information and variance analysis to evaluate each feature in the sniffed WiFi data, and select target features from each feature; wherein each feature includes frequency, RSSI range, RSSI kurtosis, RSSI difference, RSSI median, RSSI mean, RSSI standardization, RSSI deviation, RSSI coefficient of variation; the target features are several features with the highest F value of variance analysis; S2: Standardizing the target feature; S3: input the standardized target features into the model selector, and select the corresponding classifier model based on the output result of the model selector; in, The model selector is a naive Bayes model; The classifier model includes an optimized logistic regression model and an optimized decision tree model; The optimized logistic regression model is a logistic regression model that introduces L1 regularization; the L1 regularization is used to remove the target feature with the lowest mutual information value; The optimized decision tree model is a decision tree model that reduces model complexity by limiting the maximum depth and adopting cost complexity pruning technology; S4: Input the standardized target features into the classifier model selected in S3 to obtain the classification results.

4. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 2, characterized in that: The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip all use ESP07S chips; that is, the first WiFi chip is a first ESP07S chip, the second WiFi chip is a second ESP07S chip, the third WiFi chip is a third ESP07S chip, and the fourth WiFi chip is a fourth ESP07S chip; The main control chip is a STM32F103RCT6 chip; The Ethernet chip is a W5500 chip.

5. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 4, characterized in that: The PC6 pin of the STM32F103RCT6 chip is connected to the SCSn pin of the W5500 chip; The PB15 pin of the STM32F103RCT6 chip is connected to the SCLK pin of the W5500 chip; The PB14 pin of the STM32F103RCT6 chip is connected to the MISO pin of the W5500 chip; The PB13 pin of the STM32F103RCT6 chip is connected to the MOSI pin of the W5500 chip; The PB12 pin of the STM32F103RCT6 chip is connected to the INTn pin of the W5500 chip; The PB1 pin of the STM32F103RCT6 chip is connected to the RSTn pin of the W5500 chip.

6. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 4, characterized in that: The TXD0 pin of the first ESP07S chip is connected to the PA10 pin of the STM32F103RCT6 chip; The RXD0 pin of the first ESP07S chip is connected to the PA9 pin of the STM32F103RCT6 chip; The RST pin of the first ESP07S chip is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC; The RST pin of the first ESP07S chip is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; The RST pin of the first ESP07S chip is connected to the PA11 pin of the STM32F103RCT6 chip; The EN pin of the first ESP07S chip is connected to the power supply VCC through a resistor R2; The GPIO0 pin of the first ESP07S chip is connected to the power supply VCC through a resistor R3; The GPIO2 pin of the first ESP07S chip is connected to the power supply VCC through a resistor R4; The GPIO15 pin of the first ESP07S chip is grounded via a resistor R5.

7. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 4, characterized in that: The TXD0 pin of the second ESP07S chip is connected to the PA3 pin of the STM32F103RCT6 chip; The RXD0 pin of the second ESP07S chip is connected to the PA2 pin of the STM32F103RCT6 chip; The RST pin of the second ESP07S chip is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply VCC; The RST pin of the second ESP07S chip is connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded; The RST pin of the second ESP07S chip is connected to the PC9 pin of the STM32F103RCT6 chip; The EN pin of the second ESP07S chip is connected to the power supply VCC through a resistor R7; The GPIO0 pin of the second ESP07S chip is connected to the power supply VCC through a resistor R8; The GPIO2 pin of the second ESP07S chip is connected to the power supply VCC through a resistor R9; The GPIO15 pin of the second ESP07S chip is grounded via a resistor R10.

8. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 4, characterized in that: The TXD0 pin of the third ESP07S chip is connected to the PB11 pin of the STM32F103RCT6 chip; The RXD0 pin of the third ESP07S chip is connected to the PB10 pin of the STM32F103RCT6 chip; The RST pin of the third ESP07S chip is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to the power supply VCC; The RST pin of the third ESP07S chip is connected to one end of the capacitor C3, and the other end of the capacitor C3 is grounded; The RST pin of the third ESP07S chip is connected to the PA8 pin of the STM32F103RCT6 chip; The EN pin of the third ESP07S chip is connected to the power supply VCC through a resistor R12; The GPIO0 pin of the third ESP07S chip is connected to the power supply VCC through a resistor R13; The GPIO2 pin of the third ESP07S chip is connected to the power supply VCC through a resistor R14; The GPIO15 pin of the third ESP07S chip is grounded via a resistor R15.

9. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 4, characterized in that: The TXD0 pin of the fourth ESP07S chip is connected to the PC11 pin of the STM32F103RCT6 chip; The RXD0 pin of the fourth ESP07S chip is connected to the PC10 pin of the STM32F103RCT6 chip; The RST pin of the fourth ESP07S chip is connected to one end of a resistor R16, and the other end of the resistor R16 is connected to a power supply VCC; The RST pin of the fourth ESP07S chip is connected to one end of the capacitor C4, and the other end of the capacitor C4 is grounded; The RST pin of the fourth ESP07S chip is connected to the PA12 pin of the STM32F103RCT6 chip; The EN pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R17; The GPIO0 pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R18; The GPIO2 pin of the fourth ESP07S chip is connected to the power supply VCC through a resistor R19; The GPIO15 of the fourth ESP07S chip is grounded through a resistor R20.

10. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 4, characterized in that: The INTn pin of the W5500 chip is connected to the power supply VCC through a resistor R22; The SCSn pin of the W5500 chip is connected to the power supply VCC through a resistor R23; The RSTn pin of the W5500 chip is connected to the power supply VCC through a resistor R21; The EXRES1 pin of the W5500 chip is grounded via a resistor R24; The TOCAP pin of the W5500 chip is grounded via capacitor C5; The 1V2O pin of the W5500 chip is grounded via capacitor C6; The RSVD pin of the W5500 chip is grounded.

Images