WiFi signal sniffing and data transmission equipment with double transmission modes

Abstract

The utility model discloses WiFi signal sniffing and data transmission equipment with double transmission modes. When the transmission modes are wired transmission modes, a first WiFi chip, a second WiFi chip, a third WiFi chip and a fourth WiFi chip are used for sniffing WiFi data; the main control chip is used for classifying WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip; the Ethernet chip is used for sending the classified WiFi data to the server; when the transmission mode is a wireless transmission mode, the first WiFi chip, the second WiFi chip and the third WiFi chip are used for sniffing WiFi data; the main control chip is used for classifying WiFi data sniffed by the first WiFi chip, the second WiFi chip and the third WiFi chip; and the fourth WiFi chip is used for sending the classified WiFi data to the server. According to the utility model, the deployment flexibility and adaptive capacity of equipment can be improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of WiFi signal sniffing technology, more particularly to a WiFi signal sniffing and data transmission equipment with double transmission mode. BACKGROUND

[0002] With the rapid development of wireless communication technology, WiFi network has become an important infrastructure of modern society, and is widely used in various public and private places. WiFi signal sniffing technology has been widely used in network security, user behavior analysis, device management and other fields. Through WiFi sniffing equipment, users can monitor the running status of wireless network, collect relevant information of connected devices, and help improve the security and optimize the performance of the network. However, the existing WiFi signal sniffing technology still has some problems and limitations in the application process.

[0003] In the prior art, WiFi signal sniffing equipment mainly relies on a single transmission mode, namely wired transmission mode. Although this mode performs well in data transmission speed and stability, it limits the flexibility of the equipment. The deployment of the equipment usually requires complex wiring, which increases the installation cost and time. At the same time, in mobile scenarios or large area regions, wired transmission mode limits the mobility of the equipment, making it difficult to realize flexible real-time monitoring and data transmission. In addition, existing equipment usually only has one or two WiFi modules for sniffing signals, which may not be able to effectively cope with the demand for large-scale data processing in high-density wireless environments.

[0004] To address these problems, some existing technologies have begun to use wireless transmission mode, but its data transmission stability and speed are not as good as wired mode, especially when handling large-scale data, the transmission efficiency is low. At the same time, the devices in the existing technology mostly do not realize the integration of double transmission mode, that is, the mixed use of wired and wireless. Even if wireless transmission mode is used, the real-time processing capacity of the sniffer is limited, and the equipment usually cannot sniff and transmit data at the same time. This makes the flexibility and efficiency of existing WiFi sniffing equipment still insufficient in actual application scenarios.

[0005] Therefore, how to provide a WiFi signal sniffing and data transmission equipment with double transmission mode is a problem that technicians in the field need to solve urgently. UTILITY MODEL CONTENT

[0006] Therefore, the utility model provides a WiFi signal sniffing and data transmission equipment with double transmission mode.

[0007] In order to achieve the above purpose, the utility model adopts the following technical scheme:

[0008] A WiFi signal sniffing and data transmission device with dual transmission modes includes a first WiFi chip, a second WiFi chip, a third WiFi chip, a fourth WiFi chip, an Ethernet chip, and a main control chip.

[0009] The first WiFi chip, the second WiFi chip, the third WiFi chip, the fourth WiFi chip, and the Ethernet chip are all communicatively connected to the main control chip;

[0010] Specifically, when the transmission mode is wired transmission mode:

[0011] The first WiFi chip, the second WiFi chip, the third WiFi chip, and the fourth WiFi chip are used to sniff WiFi data;

[0012] The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip, and the fourth WiFi chip;

[0013] The Ethernet chip is used to send the classified WiFi data to the server.

[0014] When the transmission mode is wireless transmission mode:

[0015] The first WiFi chip, the second WiFi chip, and the third WiFi chip are used to sniff WiFi data;

[0016] The main control chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip, and the third WiFi chip;

[0017] The fourth WiFi chip is used to send the classified WiFi data to the server.

[0018] Preferably, the Ethernet chip is wired to the server via a standard RJ45 interface.

[0019] Preferably, the first WiFi chip, the second WiFi chip, the third WiFi chip, and the fourth WiFi chip are all connected to the main control chip via a serial port.

[0020] Preferably, the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip all adopt ESP07S chip; that is, the first WiFi chip is a first ESP07S chip, the second WiFi chip is a second ESP07S chip, the third WiFi chip is a third ESP07S chip, and the fourth WiFi chip is a fourth ESP07S chip.

[0021] The master control chip is an STM32F103RCT6 chip.

[0022] The Ethernet chip is a W5500 chip.

[0023] Preferably, the PC6 pin of the STM32F103RCT6 chip is connected with the SCSn pin of the W5500 chip.

[0024] The PB15 pin of the STM32F103RCT6 chip is connected with the SCLK pin of the W5500 chip.

[0025] The PB14 pin of the STM32F103RCT6 chip is connected with the MISO pin of the W5500 chip.

[0026] The PB13 pin of the STM32F103RCT6 chip is connected with the MOSI pin of the W5500 chip.

[0027] The PB12 pin of the STM32F103RCT6 chip is connected with the INTn pin of the W5500 chip.

[0028] The PB1 pin of the STM32F103RCT6 chip is connected with the RSTn pin of the W5500 chip.

[0029] Preferably, the TXD0 pin of the first ESP07S chip is connected with the PA10 pin of the STM32F103RCT6 chip.

[0030] The RXD0 pin of the first ESP07S chip is connected with the PA9 pin of the STM32F103RCT6 chip.

[0031] The RST pin of the first ESP07S chip is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with a power supply VCC.

[0032] The RST pin of the first ESP07S chip is connected with one end of a capacitor C1, and the other end of the capacitor C1 is grounded.

[0033] The RST pin of the first ESP07S chip is connected with the PA11 pin of the STM32F103RCT6 chip;

[0034] The EN pin of the first ESP07S chip is connected with the power supply VCC through the resistance R2;

[0035] The GPIO0 pin of the first ESP07S chip is connected with the power supply VCC through the resistance R3;

[0036] The GPIO2 pin of the first ESP07S chip is connected with the power supply VCC through the resistance R4;

[0037] The GPIO15 pin of the first ESP07S chip is grounded through the resistance R5.

[0038] Preferably, the TXD0 pin of the second ESP07S chip is connected with the PA3 pin of the STM32F103RCT6 chip;

[0039] The RXD0 pin of the second ESP07S chip is connected with the PA2 pin of the STM32F103RCT6 chip;

[0040] The RST pin of the second ESP07S chip is connected with one end of the resistance R6, and the other end of the resistance R6 is connected with the power supply VCC;

[0041] The RST pin of the second ESP07S chip is connected with one end of the capacitor C2, and the other end of the capacitor C2 is grounded;

[0042] The RST pin of the second ESP07S chip is connected with the PC9 pin of the STM32F103RCT6 chip;

[0043] The EN pin of the second ESP07S chip is connected with the power supply VCC through the resistance R7;

[0044] The GPIO0 pin of the second ESP07S chip is connected with the power supply VCC through the resistance R8;

[0045] The GPIO2 pin of the second ESP07S chip is connected with the power supply VCC through the resistance R9;

[0046] The GPIO15 pin of the second ESP07S chip is grounded through the resistance R10.

[0047] Preferably, the TXD0 pin of the third ESP07S chip is connected with the PB11 pin of the STM32F103RCT6 chip;

[0048] The RXD0 pin of the third ESP07S chip is connected with the PB10 pin of the STM32F103RCT6 chip;

[0049] The RST pin of the third ESP07S chip is connected with one end of the resistor R11, and the other end of the resistor R11 is connected with the power supply VCC;

[0050] The RST pin of the third ESP07S chip is connected with one end of the capacitor C3, and the other end of the capacitor C3 is grounded;

[0051] The RST pin of the third ESP07S chip is connected with the PA8 pin of the STM32F103RCT6 chip;

[0052] The EN pin of the third ESP07S chip is connected with the power supply VCC through the resistor R12;

[0053] The GPIO0 pin of the third ESP07S chip is connected with the power supply VCC through the resistor R13;

[0054] The GPIO2 pin of the third ESP07S chip is connected with the power supply VCC through the resistor R14;

[0055] The GPIO15 pin of the third ESP07S chip is grounded through the resistor R15.

[0056] Preferably, the TXD0 pin of the fourth ESP07S chip is connected with the PC11 pin of the STM32F103RCT6 chip;

[0057] The RXD0 pin of the fourth ESP07S chip is connected with the PC10 pin of the STM32F103RCT6 chip;

[0058] The RST pin of the fourth ESP07S chip is connected with one end of the resistor R16, and the other end of the resistor R16 is connected with the power supply VCC;

[0059] The RST pin of the fourth ESP07S chip is connected with one end of the capacitor C4, and the other end of the capacitor C4 is grounded;

[0060] The RST pin of the fourth ESP07S chip is connected with the PA12 pin of the STM32F103RCT6 chip;

[0061] The EN pin of the fourth ESP07S chip is connected with the power supply VCC through the resistor R17;

[0062] The GPIO0 pin of the fourth ESP07S chip is connected with the power supply VCC through the resistor R18;

[0063] The GPIO2 pin of the fourth ESP07S chip is connected with the power supply VCC through a resistor R19.

[0064] The GPIO15 of the fourth ESP07S chip is grounded through a resistor R20.

[0065] Preferably, the INTn pin of the W5500 chip is connected with the power supply VCC through a resistor R22.

[0066] The SCSn pin of the W5500 chip is connected with the power supply VCC through a resistor R23.

[0067] The RSTn pin of the W5500 chip is connected with the power supply VCC through a resistor R21.

[0068] The EXRES1 pin of the W5500 chip is grounded through a resistor R24.

[0069] The TOCAP pin of the W5500 chip is grounded through a capacitor C5.

[0070] The 1V2O pin of the W5500 chip is grounded through a capacitor C6.

[0071] The RSVD pin of the W5500 chip is grounded.

[0072] Compared with the prior art, the WiFi signal sniffing and data transmission device with double transmission modes provided by the utility model has the advantages that it can flexibly perform data transmission in wired and wireless modes, thereby improving the deployment flexibility and adaptability of the device; in the sniffing function, the device integrates multiple WiFi modules and can simultaneously process WiFi signals of multiple channels, thereby significantly improving the signal capturing capacity and being applicable to high-density wireless environments. BRIEF DESCRIPTION OF DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only embodiments of the utility model, and those skilled in the art can obtain other accompanying drawings according to the provided accompanying drawings without any creative effort.

[0074] Figure 1 The structural schematic diagram of the WiFi signal sniffing and data transmission device with double transmission modes provided by the utility model is shown in the figure.

[0075] Figure 2 The circuit principle diagram of the first ESP07S chip provided by the utility model is shown in the figure.

[0076] Figure 3 The utility model provides a second ESP07S chip's circuit principle drawing provided by the utility model,

[0077] Figure 4 The utility model provides a third ESP07S chip's circuit principle drawing provided by the utility model,

[0078] Figure 5 The utility model provides a fourth ESP07S chip's circuit principle drawing provided by the utility model,

[0079] Figure 6 The utility model provides a STM32F103RCT6 chip's circuit principle drawing provided by the utility model,

[0080] Figure 7 The utility model provides a W5500 chip's circuit principle drawing provided by the utility model. DETAILED DESCRIPTION

[0081] The technical scheme in the embodiments of the utility model will be described clearly and completely below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the utility model.

[0082] As Figures 1-7 The utility model discloses a kind of WiFi signal sniffing and data transmission equipment with double transmission mode, including first WiFi chip, second WiFi chip, third WiFi chip, fourth WiFi chip, Ethernet chip and master control chip;

[0083] The first WiFi chip, the second WiFi chip, the third WiFi chip, the fourth WiFi chip, the Ethernet chip are all connected with the master control chip in communication;

[0084] When transmission mode is wired transmission mode, the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are used to sniff WiFi data;

[0085] The master control chip is used to classify WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip,

[0086] The master control chip is used to classify WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip,

[0087] It can be understood that the master chip uses a naive Bayesian classification algorithm to classify the sniffed WiFi data, specifically classifies the sniffed WiFi data according to fixed devices and mobile devices (for reference: Flach P A, Lachiche N. Naive Bayesian classification of structured data [J]. Machine learning, 2004, 57: 233-269.).

[0088] The Ethernet chip is used to send the classified WiFi data to the server.

[0089] It can be understood that the Ethernet chip only sends mobile device data to the server (fixed device data is irrelevant to crowd analysis).

[0090] When the transmission mode is a wireless transmission mode:

[0091] The first WiFi chip, the second WiFi chip, and the third WiFi chip are used to sniff WiFi data.

[0092] The master chip is used to classify the WiFi data sniffed by the first WiFi chip, the second WiFi chip, and the third WiFi chip.

[0093] The fourth WiFi chip is used to send the classified WiFi data to the server.

[0094] In an embodiment, the Ethernet chip is connected to the server by a standard RJ45 interface.

[0095] In an embodiment, the first WiFi chip, the second WiFi chip, the third WiFi chip, and the fourth WiFi chip are connected to the master chip by a serial port.

[0096] It can be understood that the classification specifically refers to identifying the type of device providing WiFi data (fixed device or mobile device), and the classification method is a prior art (such as the classification method described in the reference: Flach P A, Lachiche N. Naive Bayesian classification of structured data [J]. Machine learning, 2004, 57: 233-269.), which will not be repeated here.

[0097] It can be understood that the Ethernet chip sends the classified WiFi data to the server through a standard RJ45 interface; and the server is used for storing and displaying the classified WiFi data.

[0098] In an embodiment, the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip all adopt ESP07S chips; that is, the first WiFi chip is a first ESP07S chip, the second WiFi chip is a second ESP07S chip, the third WiFi chip is a third ESP07S chip, and the fourth WiFi chip is a fourth ESP07S chip.

[0099] The master chip is an STM32F103RCT6 chip.

[0100] The Ethernet chip is a W5500 chip.

[0101] In an embodiment, a PC6 pin of the STM32F103RCT6 chip is connected with a SCSn pin of the W5500 chip.

[0102] A PB15 pin of the STM32F103RCT6 chip is connected with a SCLK pin of the W5500 chip.

[0103] A PB14 pin of the STM32F103RCT6 chip is connected with a MISO pin of the W5500 chip.

[0104] A PB13 pin of the STM32F103RCT6 chip is connected with a MOSI pin of the W5500 chip.

[0105] A PB12 pin of the STM32F103RCT6 chip is connected with an INTn pin of the W5500 chip.

[0106] A PB1 pin of the STM32F103RCT6 chip is connected with a RSTn pin of the W5500 chip.

[0107] In an embodiment, a PA13 pin of the STM32F103RCT6 chip is connected with a data line of a debugging interface.

[0108] A PA14 pin of the STM32F103RCT6 chip is connected with a clock line of the debugging interface.

[0109] It can be understood that the debugging interface is used for debugging the program in the STM32F103RCT6 chip.

[0110] The NRST pin of the STM32F103RCT6 chip is connected with the reset circuit;

[0111] It can be understood that the reset circuit is used for resetting the STM32F103RCT6 chip.

[0112] In an embodiment, the TXD0 pin of the first ESP07S chip is connected with the PA10 pin of the STM32F103RCT6 chip.

[0113] The RXD0 pin of the first ESP07S chip is connected with the PA9 pin of the STM32F103RCT6 chip.

[0114] The RST pin of the first ESP07S chip is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with the power supply VCC.

[0115] The RST pin of the first ESP07S chip is connected with one end of the capacitor C1, and the other end of the capacitor C1 is grounded.

[0116] The RST pin of the first ESP07S chip is connected with the PA11 pin of the STM32F103RCT6 chip.

[0117] The EN pin of the first ESP07S chip is connected with the power supply VCC through the resistor R2.

[0118] The GPIO0 pin of the first ESP07S chip is connected with the power supply VCC through the resistor R3.

[0119] The GPIO2 pin of the first ESP07S chip is connected with the power supply VCC through the resistor R4.

[0120] The GPIO15 pin of the first ESP07S chip is grounded through the resistor R5.

[0121] It can be understood that the GPIO0 pin of the first ESP07S chip is pulled up to VCC through the resistor R3, which is used for the start mode selection of the first ESP07S chip.

[0122] The GPIO2 pin of the first ESP07S chip is pulled up to VCC through the resistor R4, which is used to ensure the normal start of the first ESP07S chip.

[0123] The GPIO15 pin of the first ESP07S chip is grounded through the resistor R5, which ensures the normal start of the first ESP07S chip.

[0124] In an embodiment, the TXD0 pin of the second ESP07S chip is connected to the PA3 pin of the STM32F103RCT6 chip;

[0125] The RXD0 pin of the second ESP07S chip is connected to the PA2 pin of the STM32F103RCT6 chip;

[0126] The RST pin of the second ESP07S chip is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply VCC;

[0127] The RST pin of the second ESP07S chip is connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded;

[0128] The RST pin of the second ESP07S chip is connected to the PC9 pin of the STM32F103RCT6 chip;

[0129] The EN pin of the second ESP07S chip is connected to the power supply VCC through the resistor R7;

[0130] The GPIO0 pin of the second ESP07S chip is connected to the power supply VCC through the resistor R8;

[0131] The GPIO2 pin of the second ESP07S chip is connected to the power supply VCC through the resistor R9;

[0132] The GPIO15 pin of the second ESP07S chip is grounded through the resistor R10.

[0133] It can be understood that the GPIO0 pin of the second ESP07S chip is pulled up to VCC through the resistor R8, which is used for the start mode selection of the second ESP07S chip;

[0134] The GPIO2 pin of the second ESP07S chip is pulled up to VCC through the resistor R9, which is used to ensure the normal start of the second ESP07S chip;

[0135] The GPIO15 pin of the second ESP07S chip is grounded through the resistor R10, which ensures the normal start of the second ESP07S chip.

[0136] In an embodiment, the TXD0 pin of the third ESP07S chip is connected to the PB11 pin of the STM32F103RCT6 chip;

[0137] The RXD0 pin of the third ESP07S chip is connected to the PB10 pin of the STM32F103RCT6 chip;

[0138] The RST pin of the third ESP07S chip is connected with one end of the resistor R11, and the other end of the resistor R11 is connected with the power supply VCC;

[0139] The RST pin of the third ESP07S chip is connected with one end of the capacitor C3, and the other end of the capacitor C3 is grounded;

[0140] The RST pin of the third ESP07S chip is connected with the PA8 pin of the STM32F103RCT6 chip;

[0141] The EN pin of the third ESP07S chip is connected with the power supply VCC through the resistor R12;

[0142] The GPIO0 pin of the third ESP07S chip is connected with the power supply VCC through the resistor R13;

[0143] The GPIO2 pin of the third ESP07S chip is connected with the power supply VCC through the resistor R14;

[0144] The GPIO15 pin of the third ESP07S chip is grounded through the resistor R15.

[0145] It can be understood that the GPIO0 pin of the third ESP07S chip is pulled up to VCC through the resistor R13, which is used for the start mode selection of the third ESP07S chip;

[0146] The GPIO2 pin of the third ESP07S chip is pulled up to VCC through the resistor R14, which is used to ensure the normal start of the third ESP07S chip;

[0147] The GPIO15 pin of the third ESP07S chip is grounded through the resistor R15, which ensures the normal start of the third ESP07S chip.

[0148] In an embodiment, the TXD0 pin of the fourth ESP07S chip is connected with the PC11 pin of the STM32F103RCT6 chip;

[0149] The RXD0 pin of the fourth ESP07S chip is connected with the PC10 pin of the STM32F103RCT6 chip;

[0150] The RST pin of the fourth ESP07S chip is connected with one end of the resistor R16, and the other end of the resistor R16 is connected with the power supply VCC;

[0151] The RST pin of the fourth ESP07S chip is connected with one end of the capacitor C4, and the other end of the capacitor C4 is grounded;

[0152] The RST pin of the fourth ESP07S chip is connected with the PA12 pin of the STM32F103RCT6 chip;

[0153] The EN pin of the fourth ESP07S chip is connected with the power supply VCC through the resistance R17;

[0154] The GPIO0 pin of the fourth ESP07S chip is connected with the power supply VCC through the resistance R18;

[0155] The GPIO2 pin of the fourth ESP07S chip is connected with the power supply VCC through the resistance R19;

[0156] The GPIO15 of the fourth ESP07S chip is grounded through the resistance R20.

[0157] It can be understood that: the GPIO0 pin of the fourth ESP07S chip is pulled up to VCC through the resistance R18, which is used for the start mode selection of the fourth ESP07S chip;

[0158] The GPIO2 pin of the fourth ESP07S chip is pulled up to VCC through the resistance R19, which is used to ensure the normal start of the fourth ESP07S chip;

[0159] The GPIO15 pin of the fourth ESP07S chip is grounded through the resistance R20, which ensures the normal start of the fourth ESP07S chip.

[0160] In an embodiment, the INTn pin of the W5500 chip is connected with the power supply VCC through the resistance R22;

[0161] The SCSn pin of the W5500 chip is connected with the power supply VCC through the resistance R23;

[0162] The RSTn pin of the W5500 chip is connected with the power supply VCC through the resistance R21;

[0163] The EXRES1 pin of the W5500 chip is grounded through the resistance R24;

[0164] The TOCAP pin of the W5500 chip is grounded through the capacitor C5;

[0165] The 1V2O pin of the W5500 chip is grounded through the capacitor C6;

[0166] The RSVD pin of the W5500 chip is grounded.

[0167] The TXN pin of the W5500 chip is connected with the TX- pin of the RJ45 interface through the 75Ω resistance R25;

[0168] The TXP pin of the W5500 chip is connected with the TX+ pin of the RJ45 interface through a 75Ω resistor R26.

[0169] The RXN pin of the W5500 chip is connected with the RX- pin of the RJ45 interface.

[0170] The RXP pin of the W5500 chip is connected with the RX+ pin of the RJ45 interface.

[0171] The LINKLED pin of the W5500 chip is connected with the LED0- pin and the LED0+ pin of the RJ45 interface.

[0172] The DUPLED pin of the W5500 chip is left hanging.

[0173] The ACTLED pin of the W5500 chip is connected with the LED1- pin and the LED1+ pin of the RJ45 interface.

[0174] The RJ45 is connected with the server, adopts the existing standard Ethernet technology, and can be connected by using a conventional CAT5 / CAT6 network cable.

[0175] In an embodiment, the values of the resistors and capacitors are as follows:

[0176] C1, C2, C3, C4: 0.1uF;

[0177] R1, R6, R11, R16: 10K ohms;

[0178] R2, R3, R4, R7, R8, R9, R12, R13, R14, R17, R18, R19: 10K ohms;

[0179] R5, R10, R15, R20: 46 ohms;

[0180] R21, R22, R23: 10K ohms;

[0181] R24: 12.4K ohms;

[0182] C5: 4.7uF;

[0183] C6: 0.01uF;

[0184] The working principle of the utility model is as follows:

[0185] Based on the actual application scene, the wired transmission mode and the wireless transmission mode are selected.

[0186] 1) If the wired transmission mode is selected, the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are all set to the sniffing mode (the mode of the WiFi chip can be set to the sniffing mode or the transparent mode by using the AiThinker IDE software);

[0187] The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip sniff the WiFi data of different channels, and transmit the WiFi data to the master control chip; the master control chip sends the classified WiFi data to the Ethernet chip; and the Ethernet chip sends the classified WiFi data to the server through the standard RJ45 interface.

[0188] 2) If the wireless transmission mode is selected, the first WiFi chip, the second WiFi chip and the third WiFi chip are all set to the sniffing mode; and the fourth WiFi chip is set to the transparent mode (the mode of the WiFi chip can be set to the sniffing mode or the transparent mode by using the AiThinker IDE software);

[0189] The first WiFi chip, the second WiFi chip and the third WiFi chip sniff the WiFi data of different channels, and transmit the WiFi data to the master control chip; the master control chip sends the classified WiFi data to the Ethernet chip; and the Ethernet chip sends the classified WiFi data to the server through the standard RJ45 interface.

[0190] The various embodiments are described in a progressive manner in the specification, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the device disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0191] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A WiFi signal sniffing and data transmission device with dual transmission mode, characterized in that, The first WiFi chip, the second WiFi chip, the third WiFi chip, the fourth WiFi chip, the Ethernet chip and the master control chip are connected in communication; The first WiFi chip, the second WiFi chip, the third WiFi chip, the fourth WiFi chip and the Ethernet chip are connected in communication with the master control chip; When the transmission mode is a wired transmission mode: The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are used for sniffing WiFi data; The master control chip is used for classifying the WiFi data sniffed by the first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip; The Ethernet chip is used for sending the classified WiFi data to a server; When the transmission mode is a wireless transmission mode: The first WiFi chip, the second WiFi chip and the third WiFi chip are used for sniffing WiFi data; The master control chip is used for classifying the WiFi data sniffed by the first WiFi chip, the second WiFi chip and the third WiFi chip; The fourth WiFi chip is used for sending the classified WiFi data to a server.

2. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 1, characterized in that, The Ethernet chip is connected in wired connection with the server through a standard RJ45 interface.

3. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 1, characterized in that, The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are connected in communication with the master control chip through serial ports.

4. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 2, wherein: The first WiFi chip, the second WiFi chip, the third WiFi chip and the fourth WiFi chip are all ESP07S chips; that is, the first WiFi chip is a first ESP07S chip, the second WiFi chip is a second ESP07S chip, the third WiFi chip is a third ESP07S chip, and the fourth WiFi chip is a fourth ESP07S chip; The master control chip is an STM32F103RCT6 chip; The Ethernet chip is a W5500 chip.

5. The WiFi signal sniffing and data transmission device with dual transmission modes according to claim 4, wherein: The PC6 pin of the STM32F103RCT6 chip is connected with the SCSn pin of the W5500 chip; The PB15 pin of the STM32F103RCT6 chip is connected with the SCLK pin of the W5500 chip; The PB14 pin of the STM32F103RCT6 chip is connected with the MISO pin of the W5500 chip; The PB13 pin of the STM32F103RCT6 chip is connected with the MOSI pin of the W5500 chip; The PB12 pin of the STM32F103RCT6 chip is connected with the INTn pin of the W5500 chip; The PB1 pin of the STM32F103RCT6 chip is connected with the RSTn pin of the W5500 chip.

6. The WiFi signal sniffing and data transmission device with double transmission modes according to claim 4, characterized in that: The TXD0 pin of the first ESP07S chip is connected with the PA10 pin of the STM32F103RCT6 chip; The RXD0 pin of the first ESP07S chip is connected with the PA9 pin of the STM32F103RCT6 chip; The RST pin of the first ESP07S chip is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with the power supply VCC; The RST pin of the first ESP07S chip is connected with one end of the capacitor C1, and the other end of the capacitor C1 is grounded; The RST pin of the first ESP07S chip is connected with the PA11 pin of the STM32F103RCT6 chip; The EN pin of the first ESP07S chip is connected with the power supply VCC through the resistor R2; The GPIO0 pin of the first ESP07S chip is connected with the power supply VCC through the resistor R3; The GPIO2 pin of the first ESP07S chip is connected with the power supply VCC through the resistor R4; The GPIO15 pin of the first ESP07S chip is grounded through the resistor R5.

7. The WiFi signal sniffing and data transmission device with double transmission modes according to claim 4, characterized in that: The TXD0 pin of the second ESP07S chip is connected with the PA3 pin of the STM32F103RCT6 chip; The RXD0 pin of the second ESP07S chip is connected with the PA2 pin of the STM32F103RCT6 chip; The RST pin of the second ESP07S chip is connected with one end of the resistor R6, and the other end of the resistor R6 is connected with the power supply VCC; The RST pin of the second ESP07S chip is connected with one end of the capacitor C2, and the other end of the capacitor C2 is grounded; The RST pin of the second ESP07S chip is connected with the PC9 pin of the STM32F103RCT6 chip; The EN pin of the second ESP07S chip is connected with the power supply VCC through the resistor R7; The GPIO0 pin of the second ESP07S chip is connected with the power supply VCC through the resistor R8; The GPIO2 pin of the second ESP07S chip is connected with the power supply VCC through the resistor R9; The GPIO15 pin of the second ESP07S chip is grounded through the resistor R10.

8. The WiFi signal sniffing and data transmission device with double transmission modes according to claim 4, characterized in that: The TXD0 pin of the third ESP07S chip is connected with the PB11 pin of the STM32F103RCT6 chip; The RXD0 pin of the third ESP07S chip is connected with the PB10 pin of the STM32F103RCT6 chip; The RST pin of the third ESP07S chip is connected with one end of the resistor R11, and the other end of the resistor R11 is connected with the power supply VCC; The RST pin of the third ESP07S chip is connected with one end of the capacitor C3, and the other end of the capacitor C3 is grounded; The RST pin of the third ESP07S chip is connected with the PA8 pin of the STM32F103RCT6 chip; The EN pin of the third ESP07S chip is connected with the power supply VCC through the resistor R12; The GPIO0 pin of the third ESP07S chip is connected with the power supply VCC through the resistor R13; The GPIO2 pin of the third ESP07S chip is connected with the power supply VCC through the resistor R14; The GPIO15 pin of the third ESP07S chip is grounded through the resistor R15.

9. The WiFi signal sniffing and data transmission device with dual transmission mode according to claim 4, characterized in that: The TXD0 pin of the fourth ESP07S chip is connected with the PC11 pin of the STM32F103RCT6 chip; The RXD0 pin of the fourth ESP07S chip is connected with the PC10 pin of the STM32F103RCT6 chip; The RST pin of the fourth ESP07S chip is connected with one end of the resistor R16, and the other end of the resistor R16 is connected with the power supply VCC; The RST pin of the fourth ESP07S chip is connected with one end of the capacitor C4, and the other end of the capacitor C4 is grounded; The RST pin of the fourth ESP07S chip is connected with the PA12 pin of the STM32F103RCT6 chip; The EN pin of the fourth ESP07S chip is connected with the power supply VCC through the resistor R17; The GPIO0 pin of the fourth ESP07S chip is connected with the power supply VCC through the resistor R18; The GPIO2 pin of the fourth ESP07S chip is connected with the power supply VCC through the resistor R19; The GPIO15 of the fourth ESP07S chip is grounded through the resistor R20.

10. The WiFi signal sniffing and data transmission device with dual transmission mode according to claim 4, characterized in that: The INTn pin of the W5500 chip is connected with the power supply VCC through the resistor R22; The SCSn pin of the W5500 chip is connected with the power supply VCC through the resistor R23; The RSTn pin of the W5500 chip is connected with the power supply VCC through the resistor R21; The EXRES1 pin of the W5500 chip is grounded through the resistor R24; The TOCAP pin of the W5500 chip is grounded through the capacitor C5; The 1V2O pin of the W5500 chip is grounded through the capacitor C6; The RSVD pin of the W5500 chip is grounded.

Images