Testing device and method for gateway equipment

Abstract

The invention discloses a testing device and method for gateway equipment, the gateway equipment comprises a main board, an AP and a CP are arranged on the main board, and the testing device comprises an open communication module; the password state signal transmission test channel is used for testing the on-off of a password module working state transmission channel, the state indication interface is grounded through the first test key and is connected with the working state indication unit, and the working state indication unit is used for indicating the on-off of the password module working state transmission channel when the first test key is pressed down; the key-destroying signal transmission test path is used for testing the on-off of the key-destroying path, and the key-destroying interface is connected with the power supply through a second indication unit and is connected with the key-destroying switch; and the key injection signal transmission test channel is used for testing the on-off of a key injection interface of the mainboard externally connected with the cipher module. According to the invention, the whole machine of the gateway equipment, the working state indicating lamp and the external dense interface can be tested without the help of an external tool, so that time, manpower and cost are greatly saved.

Description

Technical Field

[0001] The invention belongs to the technical field of gateway device testing, and in particular relates to a testing device and method for a gateway device with a military encryption module. Background Art

[0002] Most existing gateway devices are equipped with an encryption module for encrypting signals transmitted between the AP (Application Processor) and CP (Communication Processor) of the gateway device.

[0003] With the growing demand for military encrypted gateway projects, data cannot be transmitted between AP and CP under the condition of encryption processing by the password module. It can only be transmitted after encryption and decryption processing by the password module. In order to prevent leakage, the password module can only be used by special personnel and special equipment after application. For manufacturers, the password module cannot be obtained, and the whole machine function test cannot be completed during the production process of the gateway device. Therefore, in the face of this situation, it is necessary to use test tools to test the motherboard, the whole machine, the Mingtong communication module, the external encryption interface, etc. separately. It is not only time-consuming and laborious, but also the current encryption gateway projects are of various types and different forms. The tooling that needs to be tested needs to change with the changes in the project form. The tooling is generally large and difficult to carry. A single test tooling costs about 1,300 yuan, and the number of tooling will be increased according to the number of orders. It saves time cost but increases the production cost of the project. In addition, the test tooling cannot complete the bare metal function and external interface test of the gateway device. Summary of the invention

[0004] In response to the problems pointed out in the background technology, one of the purposes of the present application is to provide a testing device for a gateway device, which can test the entire gateway device, the status indication interface for connecting to the external password module to output a working status indication, the working status indication unit, the key destruction interface and the key injection interface by setting a clear communication module, a password status signal transmission test path, a key destruction signal transmission test path and a key injection signal transmission test path on the main board of the gateway device, without the need for external tooling, thereby greatly saving time, manpower and cost.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions to achieve the above problems: The present application relates to a test device for a gateway device, wherein the gateway device comprises a mainboard, an AP and a CP are arranged on the mainboard, and the test device comprises: Mingtong communication module, which is used to communicate between AP and CP during testing; a password status signal transmission test path, which is used to test the continuity of the password module working status transmission path to be connected between the AP and the CP; a status indication interface is grounded through a first test button and connected to a working status indication unit; when the first test button is pressed, the working status indication unit is used to indicate the continuity of the password module working status transmission path; the first test button and the working status indication unit are both arranged on the main board; the status indication interface is an external interface on the main board for connecting to an output end of the password module outputting a signal indicating its working status; a key-destroying signal transmission test path, which is used to test the continuity of the key-destroying path; a key-destroying interface is connected to a power source and a key-destroying switch through a second indication unit; the second indication unit is used to issue an indication when the key-destroying switch is lightly touched or the password module destroys the key; the key-destroying switch and the second indication unit are arranged on the mainboard; the key-destroying interface is an external interface on the mainboard used to connect to the key-destroying interface of the password module; The key injection signal transmission test path is used to test the continuity of the key injection interface of the mainboard connected to the cryptographic module.

[0006] In some embodiments of the present application, the key injection signal transmission test path includes: The first key injection signal transmission test channel is used to test the continuity of the debugging channel where the RS232 level serial port is located; The second key injection signal transmission test channel is used to test the continuity of the authentication channel where the I2C interface is located; The third key injection signal transmission test path is used to test the continuity of the injection path where the USB interface is located.

[0007] In some embodiments of the present application, the first key injection signal transmission test path includes: A second test button is arranged on the main board, and the second test button is connected between the serial port sending end and the serial port receiving end. During the test, the second test button is pressed, and the continuity between the serial port sending end and the serial port receiving end is judged according to the window display on the serial port debugging host computer, and the serial port debugging host computer is connected to the serial port sending end and the serial port receiving end; the second key injection signal transmission test path includes: A third indication unit is arranged on the main board, and one end of the third indication unit is connected to the serial data line interface in the I2C bus and the other end is connected to a DC power supply; A fourth indicating unit is arranged on the main board, and one end of the fourth indicating unit is connected to the serial clock line interface in the I2C bus and the other end is connected to a DC power supply; When both the third indication unit and the fourth indication unit issue indications, the I2C bus interface is normal; the third key injection signal transmission test path includes: A fifth indicating unit is arranged on the main board, and one end of the fifth indicating unit is connected to the positive data terminal of the USB bus and the other end is connected to a DC power supply; A sixth indicating unit is arranged on the main board, and one end of the sixth indicating unit is connected to the negative data terminal of the USB bus and the other end is connected to a DC power supply; When both the fifth indication unit and the sixth indication unit send out indications, the USB bus interface is normal.

[0008] In some embodiments of the present application, the testing device comprises: A connector having a plurality of connection pins; One end of the first connecting pin is connected to the state indication interface, and the other end is connected to the output end of the password module outputting a signal indicating its working state; One end of the second connecting pin is connected to the key-destroying interface, and the other end is connected to the key-destroying interface of the password module; One end of the third connecting pin is connected to the serial port sending end on the mainboard and the other end is connected to the serial port sending end of the password module; One end of the fourth connecting pin is connected to the serial port receiving end on the mainboard and the other end is connected to the serial port receiving end of the password module; One end of the fifth connecting pin is connected to the serial data line interface on the mainboard, and the other end is connected to the serial data line interface of the password module; One end of the sixth connecting pin is connected to the serial clock line interface on the mainboard, and the other end is connected to the serial clock line interface of the password module; One end of the seventh connecting pin is connected to the positive data terminal of the USB bus on the mainboard, and the other end is connected to the positive data terminal of the USB bus of the password module; One end of the eighth connecting pin is connected to the negative terminal of the data in the USB bus on the mainboard, and the other end is connected to the negative terminal of the data in the USB bus of the password module.

[0009] Compared with the prior art, the testing device involved in some embodiments of the present application has the following advantages and beneficial effects: A Mingtong communication module, a password status signal transmission test path, a key destruction signal transmission test path and a key injection signal transmission test path are added to the main board. That is, it is only necessary to arrange the components of the corresponding test paths on the main board to realize the testing of the entire gateway device, the status indication interface for connecting to the external password module to output the working status indication, the working status indication unit, the key destruction interface and the key injection interface. This is simple and easy to operate, and does not require external tooling, which greatly saves time, manpower and cost.

[0010] The present application also relates to a test method for a gateway device, which uses the test device as described above to test the gateway device, and the test method includes: S1: Test whether the communication between AP and CP is normal. If so, proceed to S2. If not, check the main board and the communication module between AP and CP, and return to S1. S2: Perform signal test on external dense interface; The test is completed when the working status indication unit issues an indication when the first test button is pressed, the second indication unit issues an indication when the key-destroying switch is lightly pressed, and the key injection signal transmission test path is connected; When the working status indication unit does not issue an indication when the first test button is pressed, and / or when the second indication unit does not issue an indication when the key-destroying switch is lightly pressed, proceed to S3; When the key injection signal transmission test path is not connected, proceed to S4; S3: Determine whether the communication module between the AP and the CP is faulty. If so, replace the communication module. If not, proceed to S4. S4: Determine if the mainboard is faulty, replace it, and then return to S1.

[0011] In some embodiments of the present application, the key injection signal transmission test path includes: The first key injection signal transmission test channel is used to test the continuity of the debugging channel where the RS232 level serial port is located; The second key injection signal transmission test channel is used to test the continuity of the authentication channel where the I2C interface is located; A third key injection signal transmission test path, which is used to test the continuity of the injection path where the USB interface is located; The gateway device test method also includes testing a key injection signal transmission test path, specifically: When at least one of the first key injection signal transmission test path, the second key injection signal transmission test path and the third key injection signal transmission test path is tested to be not connected, it indicates that the key injection signal transmission test path is not connected; otherwise, it indicates that the key injection signal transmission test path is connected.

[0012] In some embodiments of the present application, the gateway device testing method further includes testing a first key injection signal transmission test path, specifically: Press the second test button, and determine the continuity between the serial port sending end and the serial port receiving end according to the data displayed in the window of the serial port debugging host computer, and the serial port debugging host computer is connected to the serial port sending end and the serial port receiving end; Wherein, the first key injection signal transmission test path includes a second test button, which is arranged on the main board, and the second test button is connected between the serial port sending end and the serial port receiving end.

[0013] In some embodiments of the present application, the gateway device testing method further includes testing the continuity of the authentication path where the I2C interface is located by observing whether the third indication unit and the fourth indication unit both issue indications; Among them, the second key injection signal transmission test path includes a third indication unit and a fourth indication unit, both of which are arranged on the main board, one end of the third indication unit is connected to the serial data line interface in the I2C bus and the other end is connected to a DC power supply, and one end of the fourth indication unit is connected to the serial clock line interface in the I2C bus and the other end is connected to a DC power supply.

[0014] In some embodiments of the present application, the gateway device testing method further includes testing the continuity of the injection path where the USB interface is located by observing whether the fifth indication unit and the sixth indication unit both issue indications; Wherein, the third key injection signal transmission test path includes a fifth indication unit and a sixth indication unit, both of which are arranged on the main board, one end of the fifth indication unit is connected to the positive data terminal in the USB bus and the other end is connected to a DC power supply, and one end of the sixth indication unit is connected to the negative data terminal in the USB bus and the other end is connected to a DC power supply.

[0015] Other features and advantages of the present invention will become more apparent after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1It is the principle block diagram of the gateway device for existing AP and CP to communicate through the Mingtong communication module; Figure 2 It is a schematic diagram of the connection between an embodiment of the test device proposed by the present invention and a password module; Figure 3 It is a circuit implementation diagram of an encryption signal transmission test path, a key destruction signal transmission test path and a key injection signal transmission test path in one embodiment of the test device proposed by the present invention; Figure 4 It is a schematic diagram of an embodiment of the test device proposed by the present invention being connected to the password module through a connector; Figure 5 is a flow chart of the testing method proposed by the present invention; Reference numerals: 100, main board; 110, AP; 120, CP; 130, Mingtong communication module; 140, password status signal transmission test path; 150, key destruction signal transmission test path; 151, key destruction switch; 160, key injection signal transmission test path; 200, password module; 300, connector. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0021] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0023] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0024] In order to implement testing of the entire gateway device and the external secure interface with the external cryptographic module 200 when the cryptographic module cannot be obtained, the present application relates to a testing device applied to this type of gateway device, and this testing device is used to test the entire device and the external secure interface, avoiding the high cost, time and labor-intensive problems caused by using external tooling for the gateway device.

[0025] See also Figure 1 The AP 110 and the CP 120 and the Mingtong communication module 130 for communication connection between the AP 110 and the CP 120 are arranged on the mainboard 100 of the gateway device. The Mingtong communication module 130 here is a commonly used communication module that is only responsible for the non-confidential data interaction between the AP 110 and the CP 120. The Mingtong communication module 130 can be used to test whether the communication of the whole machine is normal.

[0026] In some embodiments of the present application, the Mingtong communication module 130 can use the internal network port or the USB port to realize data interaction between the AP 110 and the CP 120 .

[0027] For example, the Mingtong communication module 130 can be arranged on the mainboard 100 in a plug-in manner.

[0028] When the whole machine communication is abnormal, check the mainboard 100 and the Mingtong communication module 130, and replace the mainboard 100 and / or the Mingtong communication module 130 if necessary.

[0029] See also Figure 2 The main board 100 of the gateway device is connected to the password module 200 through the external encryption interface, so as to realize the encrypted data interaction between the AP 110 and the CP 120 through the password module 200.

[0030] When the cryptographic module 200 is not available, it is a challenging problem to test the external cryptographic interface at low cost and high efficiency.

[0031] In some embodiments of the present application, in order to test the external secret interface, the test device involved in the present application includes, in addition to the clear communication module 130, a cryptographic status signal transmission test path 140, a key destruction signal transmission test path 150 and a key injection signal transmission test path 160.

[0032] The password status signal transmission test path 140 is used to test the continuity of the working status transmission path of the password module 200 to be connected between the AP 110 and the CP 120 .

[0033] The key-destroying signal transmission test path 150 is used to test the on-off of the key-destroying path, wherein the key-destroying path is a path for destroying the key of the password module 200 through the key-destroying switch 151 .

[0034] The key injection signal transmission test path 160 is used to test the continuity of the password signal communication interface of the mainboard 100 connected to the password module 200.

[0035] In some embodiments of the present application, see Figure 2 The password status signal transmission test path 140 involves a status indication interface for the working status of the external password module 200. When the status indication interface is abnormal, the password status signal transmission test path 140 is not connected and when the password module 200 is connected to the mainboard 100 through the status indication interface, the working status of the password module 200 cannot be prompted.

[0036] In some embodiments of the present application, the status indication interface is an external interface on the mainboard 100 for connecting to an output terminal A of the password module 200 to output a signal indicating its working status.

[0037] Before testing the status indication interface, it is necessary to ensure that the AP 110 and the CP 120 can communicate normally through the clear communication module 130, otherwise the test cannot be performed.

[0038] In the present application, the main concern is whether the password status signal transmission test path 140 can be connected when tested to be turned on, and whether the working status indication unit LED1 can give an indication.

[0039] When the password status signal transmission test path 140 is open and the working status indication unit LED1 also issues an indication, it indicates that the status indication interface is normal.

[0040] Therefore, in order to test the working status indicator unit LED1 and the password status signal transmission test path 140, see Figure 3 , a first test button S1 and a working status indicating unit LED1 are arranged on the main board 100 .

[0041] The status indication interface is respectively connected to one end of the working status indication unit LED1 and the first test button S1, the other end of the first test button S1 is grounded, and the end of the working status indication unit LED1 that is not connected to the status indication interface can be connected to a DC power supply +5.5V, that is, the password status signal transmission test path 140 is a path formed in series by the DC power supply, the working status indication unit LED1, the status indication interface, the first test button S1 and the ground.

[0042] During the test phase, when the first test button S1 is pressed, the DC power supply supplies power to the working status indication unit LED1, so that the working status indication unit LED1 gives an indication, which means that the password status signal transmission test path 140 is a path and the status indication interface and the working status indication unit LED1 are normal. Otherwise, it is necessary to check whether the status indication interface is faulty, whether the first test button S1 is faulty, whether the working status indication unit LED1 is faulty, and / or whether the communication between AP 110 and CP 120 is normal.

[0043] If the working status indication unit LED1 does not give an indication, and if the communication between AP 110 and CP 120 is normal (that is, the Mingtong communication module 130 is normal), the status indication interface may be faulty, the first test button S1 may be faulty, or the working status indication unit LED1 may be faulty. In this case, replace the mainboard 100 and return it to the factory for repair.

[0044] In some embodiments of the present application, the working state indicating unit LED1 is an LED lamp, which can be a single-color lamp or a red-green dual-color lamp. Figure 3 shown.

[0045] When the test password status signal transmission test path 140 is normal and the working status indication unit LED1 is normal, when the mainboard 100 is actually connected to the password module 200, the working status indication unit LED1 can be controlled to give different indications according to the working status of the password module 200 during the actual key injection signal communication.

[0046] For example, when the working status indication unit LED1 is selected as a red and green dual-color light, the working status indication unit LED1 can be controlled not to indicate when the password module 200 is not turned on or the authentication stick is not inserted; when the authentication stick is authenticated and in the authentication state, the green light in the working status indication unit LED1 is controlled to flash quickly; when a fault occurs, the red light in the working status indication unit LED1 is controlled to be on, and so on.

[0047] In some embodiments of the present application, refer back to Figure 2 The external interface involved in the key destruction signal transmission test path 150 is the key destruction interface. When the key destruction interface is abnormal, the key destruction signal transmission test path 150 is not connected and when the password module 200 is connected to the key destruction switch 151 on the mainboard 100 through the key destruction interface on the mainboard 100, the key destruction function cannot be completed.

[0048] In some embodiments of the present application, the key destruction interface is an external interface on the mainboard 100 for connecting to the key destruction interface of the cryptographic module 200. When the cryptographic module 200 is used to complete the encrypted data interaction between the AP 110 and the CP 120, if the key destruction interface receives a key destruction signal from the key destruction switch 151, the real key of the cryptographic module 200 is destroyed to avoid information leakage.

[0049] To test the key destruction interface, see Figure 3 A key-destroying switch 151 and a second indicating unit LED6 are arranged on the main board 100, and a key-destroying interface is respectively connected to the second indicating unit LED6 and the key-destroying switch 151. The key-destroying switch 151 is grounded when lightly pressed, and the end of the second indicating unit LED6 that is not connected to the key-destroying interface can be connected to a DC power supply +5.5V, that is, the key-destroying signal transmission test path 150 is a path formed by connecting the DC power supply, the second indicating unit LED6, the key-destroying interface and the key-destroying switch 151 in series.

[0050] During the test phase, when the key-destroying switch 151 is pressed, the DC power supply supplies power to the second indication unit LED6, so that the second indication unit LED6 gives an indication, indicating that the key-destroying interface and the key-destroying switch 151 are normal. Otherwise, it is necessary to check whether the key-destroying interface is faulty, whether the key-destroying switch 151 is faulty, whether the second indication unit LED6 is faulty, and / or whether the communication between AP110 and CP 120 is normal.

[0051] If the second indication unit LED6 does not give an indication, and if the communication between AP 110 and CP 120 is normal (that is, the Mingtong communication module 130 is normal), the key-destroying interface may be faulty, the key-destroying switch 151 may be faulty, or the second indication unit LED6 may be faulty. In this case, replace the mainboard 100 and return it to the factory for repair.

[0052] In some embodiments of the present application, see Figure 3 The second indicating unit LED6 is an LED lamp, which can be a single-color lamp or a dual-color lamp.

[0053] When the motherboard 100 is tested and shipped out of the factory, the key destruction interface of the password module 200 is connected to the key destruction interface on the motherboard 100, and the key destruction switch 151 is pressed, and the key destruction interface is at a low level, so that the password module 200 realizes key destruction.

[0054] In some embodiments of the present application, see Figure 2 The test device also includes a key injection signal transmission test path 160, which is used to test the key injection interface (including the I2C interface for providing authentication of the gateway device, the USB interface for providing injection, and the serial port for providing debugging).

[0055] The key injection interface is an external interface on the mainboard 100 for transmitting key injection signal data with the cryptographic module 200 .

[0056] When the key injection signal transmission test path 160 is connected, it indicates that the key injection interface is normal. Thus, when the mainboard 100 is connected to the cryptographic module 200 , it can ensure that the cryptographic module 200 can normally interact with encrypted data between the AP 110 and the CP 120 .

[0057] In some embodiments of the present application, in order to enable the cryptographic module 200 to provide authentication, injection and debugging functions for the gateway, see Figure 3 The key injection interface may include a serial port, a USB interface and an I2C interface, and these interfaces are all external confidentiality interfaces of the mainboard 100.

[0058] In some embodiments of the present application, the key injection signal transmission test path 160 includes a first key injection signal transmission test path, which is used to test the continuity of the debugging path where the RS232 level serial port is located.

[0059] In some embodiments of the present application, the key injection signal transmission test path 160 includes a second key injection signal transmission test path for testing the continuity of the authentication path where the I2C interface is located. In some embodiments of the present application, the key injection signal transmission test path 160 includes a third key injection signal transmission test path, which is used to test the continuity of the injection path where the USB interface is located.

[0060] During the test, AP 110 and CP 120 communicate with each other through the communication module 130. The interface used for the communication connection is an Internet port or a USB port, etc., and is an internal interface. Therefore, even if the communication module 130 is used for normal communication, there is no communication signal at the external confidential interface.

[0061] In some embodiments of the present application, see Figure 3 The first key injection signal transmission test path includes a second test button S2, which is arranged on the main board 100 and connected between the serial port transmitting end Tx of the AP 110 and the serial port receiving end Rx of the CP 120.

[0062] During the test, press the second test button S2, and use the serial port debugging host computer to check whether the number 1 is spit out in its window as the second test button S2 is pressed. If so, it means that the debugging path where the serial port and the RS232 level serial port are located are normal. Otherwise, the debugging path where the serial port and / or the RS232 level serial port are located is abnormal.

[0063] The serial port debugging host computer is connected to the serial port transmitting end Tx and the serial port receiving end Rx.

[0064] In some embodiments of the present application, the second key injection signal transmission test path includes a third indication unit LED2 and a fourth indication unit LED3.

[0065] The third indicating unit LED2 and the fourth indicating unit LED3 are both arranged on the main board 100 , wherein the third indicating unit LED3 indicates the serial data line SDA in the I2C bus, and the fourth indicating unit LED3 indicates the serial clock line SCL in the I2C bus.

[0066] In some embodiments of the present application, one end of the third indication unit LED3 is connected to the serial data line interface SDA in the I2C bus and the other end is connected to a DC power source (eg, 5.5V DC arranged on the mainboard 100).

[0067] When testing, a high level of 5.5V DC is provided to the third indication unit LED2, so the path where the serial data line interface SDA in the I2C bus is located is connected, and the third indication unit LED2 gives an indication, that is, the serial data line interface SDA in the I2C bus is normal, otherwise, the third indication unit LED2 may fail, or the serial data line interface SDA in the I2C bus may fail.

[0068] In some embodiments of the present application, one end of the fourth indication unit LED3 is connected to the serial clock line interface SCL in the I2C bus and the other end is connected to a DC power source (eg, 5.5V DC arranged on the mainboard 100).

[0069] When testing, a high level of 5.5V DC is provided to the fourth indication unit LED3, so the path where the serial clock line interface SCL in the I2C bus is located is connected, and the fourth indication unit LED3 gives an indication, that is, the serial clock line interface SCL in the I2C bus is normal, otherwise, the fourth indication unit LED3 may fail, or the serial clock line interface SCL in the I2C bus may fail.

[0070] Only when the third indication unit LED2 and the fourth indication unit LED3 both give indications, it can be indicated that the I2C bus interface and the authentication path where the I2C interface is located are normal. Otherwise, the I2C bus interface and / or the authentication path where the I2C interface is located is abnormal.

[0071] In some embodiments of the present application, the third key injection signal transmission test path includes a fifth indication unit LED4 and a sixth indication unit LED5.

[0072] The fifth indicating unit LED4 and the sixth indicating unit LED5 are both arranged on the mainboard 100 , wherein the fifth indicating unit LED4 indicates the data positive terminal DP in the USB bus, and the sixth indicating unit LED5 indicates the data negative terminal DM in the USB bus.

[0073] In some embodiments of the present application, one end of the fifth indicating unit LED4 is connected to the data positive terminal DP in the USB bus and the other end is connected to a DC power source (eg, 5.5V DC arranged on the mainboard 100).

[0074] When testing, a high level of 5.5V DC is provided to the fifth indication unit LED4, so the path where the data positive terminal DP in the USB bus is located is connected, and the fifth indication unit LED4 gives an indication, that is, the data positive terminal DP in the USB bus is normal, otherwise, the fifth indication unit LED4 may fail, or the data positive terminal DP in the USB bus may fail.

[0075] In some embodiments of the present application, one end of the sixth indicator unit LED5 is connected to the data negative terminal DM in the USB bus and the other end is connected to a DC power source (eg, 5.5V DC arranged on the mainboard 100).

[0076] When testing, a high level of 5.5V DC is provided to the sixth indication unit LED5, so the path where the data negative terminal DM in the USB bus is located is connected, and the sixth indication unit LED5 gives an indication, that is, the data negative terminal DM in the USB bus is normal, otherwise, the sixth indication unit LED5 may fail, or the data negative terminal DM in the USB bus may fail.

[0077] Only when the fifth indicating unit LED4 and the sixth indicating unit LED5 both give indications, it can be indicated that the USB bus interface and the injection path where the USB interface is located are normal, otherwise the USB bus interface and / or the injection path where the USB interface is located are abnormal.

[0078] It should be noted that during testing, the serial data line interface in the I2C bus, the serial clock line interface in the I2C bus, the data positive terminal DP in the USB interface, and the data negative terminal DM in the USB interface are all connected to the ground on, for example, the motherboard 100 through a test aviation plug.

[0079] In some embodiments of the present application, in order to facilitate testing and installation of the password module 200, see Figure 4 The testing device further includes a connector 300 having a plurality of connecting pins.

[0080] As described above, the status indication interface, the key destruction interface, the serial port transmitting end Tx, the serial port receiving end Rx, the serial data line interface SDA, the serial clock line interface SCL, the data positive terminal DP and the data positive terminal DM can correspond to the first connection pin, the second connection pin, the third connection pin, the fourth connection pin, the fifth connection pin, the sixth connection pin, the seventh connection pin and the eighth connection pin respectively.

[0081] One end of the first connecting pin is connected to the status indication interface on the mainboard 100 , and the other end can be used to connect to the output terminal A of the password module 200 after the mainboard 100 leaves the factory.

[0082] One end of the second connection pin is connected to the key-destruction interface on the mainboard 100 , and the other end can be used to connect the mainboard 100 to the key-destruction interface of the password module 200 after leaving the factory.

[0083] One end of the third connection pin is connected to the serial port transmitting terminal Tx on the mainboard 100 , and the other end can be used to connect the mainboard 100 with the serial port transmitting terminal Tx of the password module 200 after leaving the factory.

[0084] One end of the fourth connection pin is connected to the serial port receiving terminal Rx on the mainboard 100 , and the other end can be used to connect the mainboard 100 with the serial port receiving terminal Rx of the password module 200 after leaving the factory.

[0085] One end of the fifth connection pin is connected to the serial data line interface SDA on the mainboard 100 , and the other end can be used to connect the mainboard 100 with the serial data line interface SDA of the password module 200 after leaving the factory.

[0086] One end of the sixth connection pin is connected to the serial clock line interface SCL on the mainboard 100 , and the other end can be used to connect the mainboard 100 to the serial clock line interface SCL of the password module 200 after leaving the factory.

[0087] One end of the seventh connection pin is connected to the data positive terminal DP on the mainboard 100 , and the other end can be used to connect the mainboard 100 to the data positive terminal DP of the password module 200 after leaving the factory.

[0088] One end of the eighth connection pin is connected to the negative data terminal DM on the mainboard 100 , and the other end can be used to connect the negative data terminal DM of the password module 200 after the mainboard 100 leaves the factory.

[0089] In this way, after the test is completed, the connector 300 can be used to conveniently connect the mainboard 100 and the password module 200 .

[0090] It should be noted that when the test is completed and the product is shipped out of the factory, the Mingtong communication module 130 and the aviation plug on the mainboard 100 need to be removed.

[0091] The removed Mingtong communication module 130 and aviation plug can be reused when testing other mainboards.

[0092] In some embodiments of the present application, only low-cost devices such as test buttons and LED indicator lights are added to the mainboard 100, and with the help of the existing serial port debugging host computer, Mingtong communication module 130 and aviation plug, the mainboard 100 and external confidential interface testing can be completed, and the operation is simple and easy to implement; since the cost of the devices added to the mainboard 100 is only increased by 3.5 yuan, and no separate tooling is required, compared with the original test that requires off-factory test tooling, 1296.5 yuan is saved, which greatly saves costs, and the mainboard 100 can be mass-produced, saving time and improving test efficiency.

[0093] See also Figure 5 , which shows the flow chart of the test device testing the gateway device as a whole and the external confidential interface.

[0094] S1: Test whether the communication between AP 110 and CP 120 is normal. If so, proceed to S2. If not, check the main board 100 and the Mingtong communication module 130, and return to S1.

[0095] The test method involved in the present application requires that the AP 110 and the CP 120 communicate normally. As described above, the AP 110 and the CP 120 perform clear communication via the clear communication module 130 .

[0096] S2: Perform signal test on external dense interface.

[0097] In S2, it is necessary to test the status indication interface, key destruction interface, serial port transmitting end Tx, serial port receiving end Rx, serial data line interface SDA, serial clock line interface SCL, data positive terminal DP and data positive terminal DM as described above.

[0098] In some embodiments of the present application, when the first test button S1 is pressed, the working status indication unit LED1 sends an indication, indicating that the status indication interface is normal.

[0099] When the key-destroying switch 151 is lightly pressed, the second indication unit LED6 sends out an indication, indicating that the key-destroying interface is normal.

[0100] When the second test button S2 is pressed, the serial port debugging host computer window will spit out the number 1 along with the button, indicating that the serial port transmitter Tx and the serial port receiver Rx are normal.

[0101] The third indication unit LED2 issues an indication, indicating that the serial data line interface SDA is normal.

[0102] The fourth indication unit LED3 sends out an indication, indicating that the serial clock line interface SCL is normal.

[0103] The fifth indication unit LED4 issues an indication, indicating that the data positive terminal DP is normal.

[0104] The sixth indication unit LED5 issues an indication, indicating that the data positive terminal DM is normal.

[0105] During the test, the working status indication unit LED1, the second indication unit LED6, the third indication unit LED2, the fourth indication unit LED3, the fifth indication unit LED4 and the sixth indication unit LED5 all give indications, and the serial port debugging host computer window spit out the number 1 as the key is pressed, indicating that the gateway device data and password signal path function normally, the Mingtong communication module 130 and the main board 100, and the external password interface function normally. At this time, the test is completed and the main board 100 can be shipped.

[0106] In some embodiments of the present application, when the first test button S1 is pressed, the working status indication unit LED1 does not give an indication. This may be due to a fault in the first test button S1, a fault in the status indication interface, a fault in the Mingtong communication module 130, and / or a fault in the working status indication unit LED1.

[0107] Since the first test button S1, the status indication interface and the working status indication unit LED1 are all located on the mainboard 100, it is necessary to confirm whether the mainboard 100 and the Mingtong communication module 130 are normal.

[0108] In some embodiments of the present application, when the key-destroying switch 151 is pressed, the second indication unit LED6 does not give an indication. This may be due to a failure of the key-destroying switch 151, a failure of the key-destroying interface, a failure of the Mingtong communication module 130, and / or a failure of the second indication unit LED6.

[0109] Since the key-destroying switch 151 , the key-destroying interface and the second indicating unit LED 6 are all located on the mainboard 100 , it is necessary to confirm whether the mainboard 100 and the Mingtong communication module 130 are normal.

[0110] In some embodiments of the present application, when the second test button S2 is pressed, the serial port debugging host computer does not spit out the number 1 along with the button. It is possible that the second test button S2 is faulty, and / or the serial port transmitter Tx is faulty, and / or the serial port receiver Rx is faulty.

[0111] Since the second test button S2, the serial port transmitting terminal Tx and the serial port receiving terminal Rx are all located on the mainboard 100, it is necessary to confirm whether the mainboard 100 is normal.

[0112] In some embodiments of the present application, if the third indication unit LED2 does not issue an indication, it is possible that the serial data line interface SDA fails and / or the third indication unit LED2 fails.

[0113] Since the serial data line interface SDA and the third indication unit LED2 are both located on the main board 100 , at this time, it is necessary to confirm whether the main board 100 is normal.

[0114] In some embodiments of the present application, if the fourth indication unit LED3 does not issue an indication, it is possible that the serial clock line interface SCL fails and / or the fourth indication unit LED3 fails.

[0115] Since the serial clock line interface SCL and the fourth indication unit LED3 are both located on the main board 100 , at this time, it is necessary to confirm whether the main board 100 is normal.

[0116] In some embodiments of the present application, if the fifth indication unit LED4 does not issue an indication, it is possible that the data positive terminal DP fails and / or the fifth indication unit LED4 fails.

[0117] Since the data positive terminal DP and the fifth indicating unit LED4 are both located on the mainboard 100 , at this time, it is necessary to confirm whether the mainboard 100 is normal.

[0118] In some embodiments of the present application, if the sixth indication unit LED5 does not issue an indication, it is possible that the data negative terminal DM fails and / or the sixth indication unit LED5 fails.

[0119] Since the negative data terminal DM and the sixth indication unit LED5 are both located on the main board 100 , at this time, it is necessary to confirm whether the main board 100 is normal.

[0120] Therefore, in S2, if the working status indicating unit LED1 does not issue an indication, the process proceeds to S3; if the second indicating unit LED6 does not issue an indication, the process proceeds to S3.

[0121] If the host computer does not spit out the number 1 in response to the key press during serial port debugging, and / or the third indication unit LED2 does not issue an indication, and / or the fourth indication unit LED3 does not issue an indication, and / or the fifth indication unit LED4 does not issue an indication, and / or the sixth indication unit LED5 does not issue an indication, then proceed to S4.

[0122] S3: Determine whether the communication module 130 between the AP 110 and the CP 120 is faulty. If so, replace the communication module 130. If not, proceed to S4.

[0123] As described in S2, the working status indication unit LED1 does not issue an indication, and / or the second indication unit LED6 does not issue an indication, and it is necessary to confirm whether the mainboard 100 and the Mingtong communication module 130 are normal.

[0124] S4: Determine that the mainboard 100 is faulty, replace the mainboard 100 and return to S1.

[0125] In some embodiments of the present application, when the working status indication unit LED1 does not issue an indication and / or the second indication unit LED6 does not issue an indication, if the Mingtong communication module 130 is not faulty, then the mainboard 100 is faulty.

[0126] When the working status indication unit LED1 does not issue an indication, the mainboard 100 may have a fault, including but not limited to the following faults: the first test button S1, the working status indication unit LED1, and the status indication interface.

[0127] In some embodiments of the present application, when the second indication unit LED6 does not issue an indication, the failure of the mainboard 100 includes but is not limited to the following failures: the key-destroying switch 151, the second indication unit LED6, and the key-destroying interface.

[0128] Specifically, which part of the main board 100 is faulty and needs to be returned to the factory for inspection.

[0129] In some embodiments of the present application, if the serial port debugging host computer does not spit out the number 1 in response to a key press, and / or the third indication unit LED2 does not issue an indication, and / or the fourth indication unit LED3 does not issue an indication, and / or the fifth indication unit LED4 does not issue an indication, and / or the sixth indication unit LED5 does not issue an indication, then the mainboard 100 has a fault.

[0130] When the serial port debugging host computer does not spit out the number 1 in response to the key press, the main board 100 has a fault including but not limited to the following faults: the second test button S2, the serial port sending end Tx, and the serial port receiving end Rx.

[0131] When the third indication unit LED2 does not issue an indication, the failure of the mainboard 100 includes but is not limited to the following failures: the serial data line interface SDA, the third indication unit LED2.

[0132] When the fourth indication unit LED3 does not issue an indication, the mainboard 100 has a fault including but not limited to the following faults: the serial clock line interface SCL, the fourth indication unit LED3.

[0133] When the fifth indication unit LED4 does not issue an indication, the failure of the mainboard 100 includes but is not limited to the following failures: the data positive terminal DP, the fifth indication unit LED4.

[0134] When the sixth indication unit LED5 does not issue an indication, the failure of the mainboard 100 includes but is not limited to the following failures: the negative data terminal DM, the sixth indication unit LED5.

[0135] Specifically, which part of the main board 100 is faulty and needs to be returned to the factory for inspection.

[0136] After replacing the main board 100, return to S1.

[0137] The test device involved in this application can be applied to all physically encrypted gateway devices. It is small and easy to operate, low in cost, and has strong operability.

[0138] Of course, the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test device for a gateway device, the gateway device comprising a mainboard, an AP and a CP are arranged on the mainboard, characterized in that: The testing device comprises: Mingtong communication module, which is used to communicate between AP and CP during testing; a password status signal transmission test path, which is used to test the continuity of the password module working status transmission path to be connected between the AP and the CP; a status indication interface is grounded through a first test button and connected to a working status indication unit; when the first test button is pressed, the working status indication unit is used to indicate the continuity of the password module working status transmission path; the first test button and the working status indication unit are both arranged on the main board; the status indication interface is an external interface on the main board for connecting to an output end of the password module outputting a signal indicating its working status; a key-destroying signal transmission test path, which is used to test the continuity of the key-destroying path; a key-destroying interface is connected to a power source and a key-destroying switch through a second indication unit; the second indication unit is used to issue an indication when the key-destroying switch is lightly touched or the password module destroys the key; the key-destroying switch and the second indication unit are arranged on the mainboard; the key-destroying interface is an external interface on the mainboard used to connect to the key-destroying interface of the password module; The key injection signal transmission test path is used to test the continuity of the key injection interface of the mainboard connected to the cryptographic module.

2. The testing device according to claim 1, characterized in that: The key injection signal transmission test path includes: The first key injection signal transmission test channel is used to test the continuity of the debugging channel where the RS232 level serial port is located; The second key injection signal transmission test channel is used to test the continuity of the authentication channel where the I2C interface is located; The third key injection signal transmission test path is used to test the continuity of the injection path where the USB interface is located.

3. The testing device according to claim 2, characterized in that: The first key injection signal transmission test path includes: A second test button is arranged on the main board, and the second test button is connected between the serial port sending end and the serial port receiving end. When testing, the second test button is pressed, and the connection between the serial port sending end and the serial port receiving end is judged according to the window display on the serial port debugging host computer, and the serial port debugging host computer is connected to the serial port sending end and the serial port receiving end; The second key injection signal transmission test path includes: A third indication unit is arranged on the main board, and one end of the third indication unit is connected to the serial data line interface in the I2C bus and the other end is connected to a DC power supply; A fourth indicating unit is arranged on the main board, and one end of the fourth indicating unit is connected to the serial clock line interface in the I2C bus and the other end is connected to a DC power supply; When both the third indication unit and the fourth indication unit send out indications, the I2C bus interface is normal; The third key injection signal transmission test path includes: A fifth indicating unit is arranged on the main board, and one end of the fifth indicating unit is connected to the positive data terminal of the USB bus and the other end is connected to a DC power supply; A sixth indicating unit is arranged on the main board, and one end of the sixth indicating unit is connected to the negative data terminal of the USB bus and the other end is connected to a DC power supply; When both the fifth indication unit and the sixth indication unit send out indications, the USB bus interface is normal.

4. The testing device according to claim 3, characterized in that: The testing device comprises: A connector having a plurality of connection pins; One end of the first connecting pin is connected to the state indication interface, and the other end is connected to the output end of the password module outputting a signal indicating its working state; One end of the second connecting pin is connected to the key-destroying interface, and the other end is connected to the key-destroying interface of the password module; One end of the third connecting pin is connected to the serial port sending end on the mainboard and the other end is connected to the serial port sending end of the password module; One end of the fourth connecting pin is connected to the serial port receiving end on the mainboard and the other end is connected to the serial port receiving end of the password module; One end of the fifth connecting pin is connected to the serial data line interface on the mainboard, and the other end is connected to the serial data line interface of the password module; One end of the sixth connecting pin is connected to the serial clock line interface on the mainboard, and the other end is connected to the serial clock line interface of the password module; One end of the seventh connecting pin is connected to the positive data terminal of the USB bus on the mainboard, and the other end is connected to the positive data terminal of the USB bus of the password module; One end of the eighth connecting pin is connected to the negative terminal of the data in the USB bus on the mainboard, and the other end is connected to the negative terminal of the data in the USB bus of the password module.

5. A test method for a gateway device, which uses the test device described in any one of claims 1 to 4 to test the gateway device, and the test method comprises: S1: Test whether the communication between AP and CP is normal. If so, proceed to S2. If not, check the main board and the communication module between AP and CP, and return to S1. S2: Perform signal test on external dense interface; The test is completed when the working status indication unit issues an indication when the first test button is pressed, the second indication unit issues an indication when the key-destroying switch is lightly pressed, and the key injection signal transmission test path is connected; When the working status indication unit does not issue an indication when the first test button is pressed, and / or when the second indication unit does not issue an indication when the key-destroying switch is lightly pressed, proceed to S3; When the key injection signal transmission test path is not connected, proceed to S4; S3: Determine whether the communication module between the AP and the CP is faulty. If so, replace the communication module. If not, proceed to S4. S4: Determine if the mainboard is faulty, replace it, and then return to S1.

6. The gateway device testing method according to claim 5, characterized in that: The key injection signal transmission test path includes: The first key injection signal transmission test channel is used to test the continuity of the debugging channel where the RS232 level serial port is located; The second key injection signal transmission test channel is used to test the continuity of the authentication channel where the I2C interface is located; A third key injection signal transmission test path, which is used to test the continuity of the injection path where the USB interface is located; The gateway device test method also includes testing a key injection signal transmission test path, specifically: When at least one of the first key injection signal transmission test path, the second key injection signal transmission test path and the third key injection signal transmission test path is tested to be not connected, it indicates that the key injection signal transmission test path is not connected.

7. The gateway device testing method according to claim 6, characterized in that: The gateway device test method further includes testing a first key injection signal transmission test path, specifically: Press the second test button, and determine the continuity between the serial port sending end and the serial port receiving end according to the data displayed in the window of the serial port debugging host computer, and the serial port debugging host computer is connected to the serial port sending end and the serial port receiving end; Wherein, the first key injection signal transmission test path includes a second test button, which is arranged on the main board, and the second test button is connected between the serial port sending end and the serial port receiving end.

8. The gateway device testing method according to claim 6, characterized in that: The gateway device testing method further includes testing the continuity of the authentication path where the I2C interface is located by observing whether the third indication unit and the fourth indication unit both issue indications; Among them, the second key injection signal transmission test path includes a third indication unit and a fourth indication unit, both of which are arranged on the main board, one end of the third indication unit is connected to the serial data line interface in the I2C bus and the other end is connected to a DC power supply, and one end of the fourth indication unit is connected to the serial clock line interface in the I2C bus and the other end is connected to a DC power supply.

9. The gateway device testing method according to claim 6, characterized in that: The gateway device testing method further includes testing the continuity of the injection path where the USB interface is located by observing whether the fifth indication unit and the sixth indication unit both issue indications; Wherein, the third key injection signal transmission test path includes a fifth indication unit and a sixth indication unit, both of which are arranged on the main board, one end of the fifth indication unit is connected to the positive data terminal in the USB bus and the other end is connected to a DC power supply, and one end of the sixth indication unit is connected to the negative data terminal in the USB bus and the other end is connected to a DC power supply.

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