Preconditionable dual mode trim circuit

Abstract

The application relates to a pre-adjustable dual-mode trimming circuit. The current trimming main unit comprises a current trimming main unit and a trimming reset control signal generation unit connected with the current trimming main unit; when current trimming is carried out based on the current trimming unit, pre-trimming is first carried out by using the current trimming main unit, and post-trimming is carried out after the pre-trimming; when the post-trimming is carried out, target trimming data is loaded into the current trimming main unit based on a current trimming target state signal, and a corresponding current trimming target state signal is output through the current trimming unit; after the current trimming unit is powered on again, the trimming reset control signal generation unit generates a trimming reset control signal, so that the current trimming main unit configures the generated trimming state signal as the corresponding current trimming target state signal under the trimming reset control signal. The application can effectively improve the output precision of the trimmed object after trimming and the flexibility of the trimming operation.

Description

Technical Field

[0001] This invention relates to a trimming circuit, and more particularly to a pre-trimmable dual-mode trimming circuit. Background Technology

[0002] Adjustment circuits are widely used in analog circuits such as reference circuits and power supply circuits. Due to manufacturing errors, it is difficult for unadjusted analog circuits to achieve very accurate values. Therefore, reference circuits and power supply circuits generally need to undergo adjustment processing.

[0003] Currently, when adjusting analog circuits such as reference circuits and power supply circuits, laser adjustment is often used. By controlling the melting or non-melting state of the polysilicon, one or more non-volatile values ​​are provided to achieve the adjustment purpose. Of course, current adjustment is also used. This involves adding control circuits to the circuit to control the current path and melt the top aluminum layer to provide one or more non-volatile values.

[0004] For the two conventional adjustment methods mentioned above, the fuse that should be adjusted is generally calculated theoretically based on the first test value, so that the output value of the object being adjusted is closer to the ideal value. However, since the state of the fuse cannot be adjusted a second time after adjustment, there may still be a certain error between the output value of the object being adjusted and the ideal value. Therefore, how to effectively improve the adjustment accuracy and reduce the adjustment cost is a technical problem that continues to be solved. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a pre-adjustable dual-mode adjustment circuit, which can effectively improve the output accuracy of the object after adjustment and the flexibility of the adjustment operation.

[0006] According to the technical solution provided by the present invention, a pre-adjustable dual-mode adjustment circuit is provided. The dual-mode adjustment circuit includes a plurality of dual-mode adjustment units, wherein each dual-mode adjustment unit generates a corresponding dual-mode adjustment state signal.

[0007] The dual-mode trimming unit includes at least a current trimming unit based on current trimming, wherein the current trimming main unit includes a current trimming main unit and a trimming reset control signal generation unit adapted and connected to the current trimming main unit.

[0008] When performing current adjustment based on the current adjustment unit, pre-adjustment is first performed using the main current adjustment unit, followed by post-adjustment.

[0009] During pre-adjustment, the pre-adjustment data is loaded into the current adjustment master unit so that the current adjustment master unit generates a pre-adjustment status signal corresponding to the pre-adjustment data.

[0010] Based on the pre-adjustment state signal generated by the pre-adjustment, the current adjustment target state signal of the current adjustment master unit during the post-adjustment is determined, wherein the state of the current adjustment target state signal is an adjustment effective state or an adjustment ineffective state.

[0011] During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the corresponding current adjustment target state signal is output through the current adjustment unit. Furthermore, a dual-mode adjustment state signal is formed based on the current adjustment target state signal.

[0012] When the current adjustment target status signal is in the adjustment active state, the polycrystalline fuse in the current adjustment main unit is blown by current blowing based on the current adjustment target status signal and the adjustment enable signal in the active state, so as to lock the current adjustment target status signal output by the current adjustment main unit after the polycrystalline fuse blows.

[0013] After the current trimming unit is powered on again, the trimming reset control signal generation unit generates a trimming reset control signal so that the current trimming master unit configures the generated trimming status signal as the corresponding current trimming target status signal under the trimming reset control signal.

[0014] The current adjustment main unit includes a DFF trigger, a polysilicon fuse unit, and an adjustment reset unit, wherein...

[0015] The data input of the DFF flip-flop receives pre-adjustment data or target adjustment data, and the CLK input receives a clock signal CLK. Based on the clock signal CLK, the pre-adjustment data or target adjustment data is loaded into the DFF flip-flop.

[0016] When the pre-adjustment data is loaded into the data terminal of the DFF flip-flop, a pre-adjustment status signal is generated through the Q terminal of the DFF flip-flop.

[0017] When the target adjustment data is loaded into the data terminal of the DFF flip-flop, a current adjustment target state signal is generated through the Q terminal of the DFF flip-flop.

[0018] The polycrystalline fuse is located within a polycrystalline fuse unit, which also includes a fuse current path unit adapted and connected to the polycrystalline fuse.

[0019] The fuse current path unit receives the trimming enable signal and is connected to the Q terminal of the DFF flip-flop.

[0020] When the DFF flip-flop outputs the current adjustment target state signal of the adjustment effective state, and the adjustment enable signal is also in the effective state, it drives the fuse current path unit to form an effective current path. Thereafter, the polycrystalline fuse is current-fuse-broken based on the fuse breaking voltage and the formed effective current path.

[0021] The trimming and reset unit is adapted and connected to the polysilicon fuse unit and the DFF flip-flop, and generates a trimming and reset control signal based on the trimming and reset control signal generation unit. Based on the received trimming and reset control signal, the DFF flip-flop Q terminal is configured to output the corresponding current trimming target state signal.

[0022] When the current adjustment target state signal in the effective adjustment state is high, the current adjustment target state signal in the ineffective adjustment state is low.

[0023] When the adjustment enable signal is active low, the fuse current path unit includes a NOR gate NOR0 and an NMOS transistor N0 connected to the output of the NOR gate NOR0, wherein...

[0024] The Q input of the DFF flip-flop is connected to one end of the inverter INV0 and the NOR gate NOR0, and the adjustment enable signal is connected to the other end of the NOR gate NOR0.

[0025] The source terminal of NMOS transistor N0 is grounded, the drain terminal of NMOS transistor N0 is connected to the first end of the polysilicon fuse, and the second end of the polysilicon fuse is connected to the fuse breaking voltage.

[0026] When the current adjustment target state signal based on the adjustment effective state and the low-level adjustment enable signal cause the NMOS transistor N0 to be in the conducting state, an effective current path is formed based on the NMOS transistor N0.

[0027] The adjustment and reset unit includes a level state detection unit and a reset position signal generation unit adapted and connected to the level state detection unit, wherein,

[0028] The adjustment and reset control signal is applied to the level state detection unit, and the level state detection unit obtains the fuse level state signal that characterizes the melting state of the polycrystalline fuse based on the adjustment and reset control signal;

[0029] Based on the adjustment and reset control signal and the fuse level status signal, the reset signal generation unit generates a reset signal that is applied to the DFF flip-flop.

[0030] When the fuse level status signal indicates that the polycrystalline fuse is in the blown state, the current adjustment target status signal of the effective state is output by the Q terminal of the DFF flip-flop based on the reset position signal.

[0031] When the fuse level status signal indicates that the polycrystalline fuse is in an unfuse state, the Q terminal of the DFF flip-flop is configured to output a current adjustment target status signal to adjust the invalid state based on the reset position signal.

[0032] The adjustment and reset control signals include the preload control signal RE-LOAD, the low-level detection control signal CFG-N, and the high-level detection control signal CFG-P, among which,

[0033] After the current adjustment unit is powered on again, the high level detection control signal CFG-P and the low level detection control signal CFG-N are immediately in an effective level state, and the preload control signal RE-LOAD enters the effective level state with a delay. Based on the preload control signal RE-LOAD entering the effective level state with a delay, the reset position signal generation unit outputs an invalid reset position signal.

[0034] When the preload control signal RE-LOAD enters the valid level state, the level state detection unit generates the fuse level state signal based on the preload control signal RE-LOAD, the low level detection control signal CFG-N, and the high level detection control signal CFG-P.

[0035] When the preload control signal RE-LOAD, the low-level detection control signal CFG-N are active high, and the high-level detection control signal CFG-P is active low, the level state detection unit includes NMOS transistors N1, NMOS transistor N2, and PMOS transistor P0. The source terminal of NMOS transistor N2 is grounded, the drain terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N1, the drain terminal of NMOS transistor N1 is connected to the drain terminal of PMOS transistor P0 and the reset bit signal generation unit, and the source terminal of PMOS transistor P0 is connected to the first end of the polysilicon fuse.

[0036] The gate of NMOS transistor N1 is connected to the low-level detection control signal CFG-N, the gate of NMOS transistor N2 is connected to the preload control signal RE-LOAD, and the gate of PMOS transistor P0 is connected to the high-level detection control signal CFG-P.

[0037] The reset bit signal generation unit includes a PMOS transistor P1 and a Schmitt trigger, wherein,

[0038] The source terminal of PMOS transistor P1 is connected to the power supply VDD. The gate terminal of PMOS transistor P1 is connected to the preload control signal RE-LOAD and connected to one end of NAND gate NAND0 and one end of NAND gate NAND1. The drain terminal of PMOS transistor P1 is connected to the drain terminal of PMOS transistor P0, the drain terminal of NMOS transistor N1, and the input terminal of Schmitt trigger.

[0039] The output of the Schmitt trigger is connected to the other end of the NAND gate NAND0 and the input of the inverter INV1. The output of the inverter INV1 is connected to the other end of the NAND gate NAND1.

[0040] The output of NAND gate NAND0 is connected to the set terminal of DFF flip-flop, and the output of NAND gate NAND1 is connected to the reset terminal of DFF flip-flop.

[0041] The adjustment and reset control signal generation unit includes at least an adjustment and reset control signal generation main circuit, wherein...

[0042] After the current adjustment unit is powered on again, a high-level active power-on reset control pulse PRO is applied to the main circuit for generating the adjustment reset control signal;

[0043] Based on the power-on reset control pulse PRO, the main circuit for generating the reset control signal simultaneously generates a preload control signal RE-LOAD, a low-level detection control signal CFG-N, and a high-level detection control signal CFG-P.

[0044] The main circuit for generating adjustment and reset control signals includes a high-level detection control signal generation unit, a low-level detection control signal generation unit, and a preload control signal generation unit.

[0045] Based on the power-on reset control pulse PRO, the high-level detection control signal generation unit synchronously generates the high-level detection control signal CFG-P in the low-level state.

[0046] Based on the high-level detection control signal CFG-P, the low-level detection control signal generation unit synchronously generates a high-level low-level detection control signal CFG-N;

[0047] Based on the low-level detection control signal CFG-N, the preload control signal generation unit delays the generation of a high-level preload control signal RE-LOAD. The rising edge of the high-level state of the preload control signal RE-LOAD is located after the corresponding rising edge of the low-level detection control signal CFG-N, and the falling edge of the preload control signal RE-LOAD is located before the corresponding falling edge of the low-level detection control signal CFG-N.

[0048] The dual-mode trimming unit also includes a laser trimming-based laser trimming unit, wherein...

[0049] The output terminals of the laser trimming unit and the current trimming unit are connected to the corresponding input terminals of the trimming unit OR gate.

[0050] The laser trimming target status signal is output through the output terminal of the laser trimming unit;

[0051] Based on the laser-adjusted target state signal and / or the current-adjusted target state signal, a dual-mode adjustment state signal is output through the output terminal of the adjustment unit or gate.

[0052] The laser trimming unit includes a laser fuse, wherein...

[0053] The first end of the laser fuse is grounded, and the second end of the laser fuse is connected to the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N2.

[0054] The drain terminal of PMOS transistor P3 is connected to the gate terminal of PMOS transistor P4, the drain terminal of NMOS transistor N2, and the gate terminal of NMOS transistor N3.

[0055] The source terminals of PMOS transistors P2, P3, and P4 are all grounded to the power supply VDD.

[0056] The source terminals of NMOS transistors N2 and NMOS transistor N3 are both grounded;

[0057] The drain terminals of PMOS transistor P4 and NMOS transistor N4 are connected to form the output terminal of the laser trimming unit.

[0058] Advantages of the present invention: The dual-mode image editing circuit may include several dual-mode adjustment units, each of which may include at least a current adjustment unit. The current adjustment unit can be used to perform pre-adjustment and post-adjustment. The pre-adjustment can be used to determine the current adjustment target state signal that each current adjustment unit should output. The current adjustment target state signal can be used as the dual-mode adjustment state signal, thereby effectively improving the output accuracy of the object after the adjustment operation and the flexibility of the adjustment operation. Attached Figure Description

[0059] Figure 1 This is a circuit diagram of one embodiment of the dual-mode adjustment circuit of the present invention.

[0060] Figure 2 This is a circuit diagram of one embodiment of the current adjustment unit of the present invention.

[0061] Figure 3 This is a circuit diagram of one embodiment of the laser trimming unit of the present invention.

[0062] Figure 4 This is a circuit diagram of one embodiment of the main circuit for generating the adjustment and reset control signal of the present invention.

[0063] Figure 5 This is a timing diagram of one embodiment of the dual-mode trimming circuit of the present invention.

[0064] Explanation of reference numerals in the attached diagram: 1-Power-on reset circuit, 2-Main circuit for generating adjustment reset control signal, 3-Current adjustment unit, 4-Laser adjustment unit. Detailed Implementation

[0065] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0066] To effectively improve the output accuracy and flexibility of the adjusted object after adjustment operation, this invention provides a pre-adjustable dual-mode adjustment circuit. Specifically, the dual-mode adjustment circuit includes several dual-mode adjustment units, each of which generates a corresponding dual-mode adjustment status signal.

[0067] The dual-mode trimming unit includes at least a current trimming unit 3 based on current trimming, wherein the current trimming unit 3 includes a current trimming main unit and a trimming reset control signal generation unit adapted and connected to the current trimming main unit.

[0068] When performing current adjustment based on the current adjustment unit, pre-adjustment is first performed using the main current adjustment unit, followed by post-adjustment.

[0069] During pre-adjustment, the pre-adjustment data is loaded into the current adjustment master unit so that the current adjustment master unit generates a pre-adjustment status signal corresponding to the pre-adjustment data.

[0070] Based on the pre-adjustment state signal generated by the pre-adjustment, the current adjustment target state signal of the current adjustment master unit during the post-adjustment is determined, wherein the state of the current adjustment target state signal is an adjustment effective state or an adjustment ineffective state.

[0071] During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the corresponding current adjustment target state signal is output through the current adjustment unit. Furthermore, a dual-mode adjustment state signal is formed based on the current adjustment target state signal.

[0072] When the current adjustment target status signal is in the adjustment active state, the polycrystalline fuse in the current adjustment main unit is blown by current blowing based on the current adjustment target status signal and the adjustment enable signal in the active state, so as to lock the current adjustment target status signal output by the current adjustment main unit after the polycrystalline fuse blows.

[0073] After the current trimming unit is powered on again, the trimming reset control signal generation unit generates a trimming reset control signal so that the current trimming master unit configures the generated trimming status signal as the corresponding current trimming target status signal under the trimming reset control signal.

[0074] Specifically, the dual-mode adjustment circuit should include one or more dual-mode adjustment units. In this case, a corresponding dual-mode adjustment status signal can be generated by one dual-mode adjustment unit, and the corresponding adjustment operation can be performed using the corresponding dual-mode adjustment status signal. Figure 1The diagram illustrates one embodiment of a dual-mode trimming circuit comprising X+1 dual-mode trimming units. Figure 1 In this context, FUSE[0]~FUSE[X] are the X+1 dual-mode trimming state signals generated by the dual-mode trimming circuit.

[0075] It is understandable that a corresponding adjustment operation can be performed using a dual-mode adjustment status signal. The dual-mode adjustment status signals generated by the dual-mode adjustment circuit are independent of each other. That is, the adjustment operation performed by one dual-mode adjustment status signal is unrelated to the adjustment operation performed by other dual-mode adjustment status signals. Specifically, it is based on the ability to meet the required adjustment of the object to be adjusted. The object to be adjusted can be the aforementioned reference circuit or power supply circuit, or other analog circuits.

[0076] Figure 1 The image shows an embodiment of trimming operation using a dual-mode trimming status signal. Figure 1 In this process, the dual-mode adjustment state signal FUSE[0] is applied to the gate terminal of NMOS transistor NM0. The source and drain terminals of NMOS transistor N0 are connected to the two ends of resistor R0. At this time, when the dual-mode adjustment state signal FUSE[0] is high, NMOS transistor NM0 is in the conducting state. Resistor R0 can be short-circuited using NMOS transistor NM0. It can be understood that when resistor R0 is short-circuited, the resistance of the resistor network containing resistor R0 can be adjusted, thus realizing the adjustment operation. Similarly, Figure 1 In this context, the dual-mode adjustment state signal FUSE[1] is applied to the gate of NMOS transistor NM1, and the dual-mode adjustment state signal FUSE[X] is applied to the gate of NMOS transistor NMX. The method and process of using the dual-mode adjustment state signals FUSE[1] and FUSE[X] for adjustment operation can be referred to the above description of the dual-mode adjustment state signal FUSE[0]. As can be seen from the above description, the corresponding level states of the dual-mode adjustment state signals FUSE[0], FUSE[1], and FUSE[X] can be different, thereby achieving the purpose of different adjustment operations.

[0077] As explained above, the dual-mode adjustment status signal can be a digital signal, and it can be either a high-level or low-level state. To obtain the dual-mode adjustment status signal, the dual-mode adjustment unit can include at least a current adjustment unit 3. As described in the background section, the current adjustment unit 3 is a current-based adjustment method for polycrystalline fuse melting.

[0078] In one embodiment of the present invention, the current adjustment unit 3 may include a current adjustment main unit and an adjustment reset control signal generation unit. The current adjustment main unit can realize the current adjustment function, and the adjustment reset control signal generation unit can reset the output state of the current adjustment main unit after power-on. The specific working mode and process of the current adjustment main unit and the adjustment reset control signal generation unit are described in detail below.

[0079] In practice, current adjustment using the current adjustment master unit can include a pre-adjustment stage and a post-adjustment stage. During current adjustment, pre-adjustment can be performed first, followed by post-adjustment. Specifically, post-adjustment is the actual adjustment operation performed using the current adjustment master unit after pre-adjustment. It can be seen that during pre-adjustment, the polycrystalline fuse in the current adjustment master unit is not used for current breaking, so it will not affect the functional state of the current adjustment master unit. However, the current adjustment target state of the current adjustment master unit can be determined through pre-adjustment.

[0080] During pre-adjustment, pre-adjustment data can be loaded into the current adjustment master unit. At this time, the current adjustment master unit can generate a pre-adjustment status signal corresponding to the pre-adjustment data. It should be noted that the pre-adjustment data can generally be "0" or "1", and the pre-adjustment status signal should be consistent with the dual-mode adjustment status signal mentioned above. That is, the pre-adjustment status signal can be a low level or a high level. For example, when the pre-adjustment data is "0", the pre-adjustment status signal can be low level, and when the pre-adjustment data is "1", the pre-adjustment status signal can be high level.

[0081] Since the pre-adjustment state signal is consistent with the dual-mode adjustment state signal, the pre-adjustment state signal can be used to drive the aforementioned NMOS transistor. For example, if the dual-mode adjustment state signal FUSE[0] is high, then when the pre-adjustment state signal generated by the corresponding current adjustment main circuit is high, the dual-mode adjustment state signal can be simulated to perform the corresponding adjustment operation. It can be understood that when pre-adjusting the object to be adjusted, the pre-adjustment state signals output by different current adjustment units will be adjusted until the output value of the object to be adjusted is consistent with or close to the ideal output value. It can be seen that compared with the theoretical calculation method used in the existing adjustment of the object to be adjusted, the method of determining the output value of the object to be adjusted through pre-adjustment can make the output value of the object to be adjusted closer to the ideal output value, which can improve the adjustment accuracy of the object to be adjusted. The method of determining the output value of the object to be adjusted can adopt the commonly used method in the existing technology, which will not be elaborated here.

[0082] As explained above, during pre-adjustment, the pre-adjustment status signals generated by different current adjustment master units can be adjusted and combined until the output value of the object being adjusted approaches the ideal output value. At this point, the pre-adjustment status signal output by each current adjustment master unit is used as the current adjustment target status signal. It can be understood that when all current adjustment master units generate the corresponding current adjustment target status signal, and the object being adjusted is adjusted using the current adjustment target status signal, the output value of the object being adjusted will approach the ideal output value.

[0083] It is understandable that a defined current adjustment target state signal can be considered a dual-mode adjustment state signal output by a current adjustment unit. Therefore, for the current adjustment target state signal, the state can be either an effective adjustment state or an ineffective adjustment state. An effective adjustment state means that an actual adjustment operation can occur, while an ineffective adjustment state means that no actual adjustment operation will occur. The adjustment state of the current adjustment target state signal is generally related to the object controlled by it. For example, when using the current adjustment target state signal to control the on / off state of an NMOS transistor to perform an adjustment operation, a high-level current adjustment target state signal can control the NMOS transistor to be in the on state. In this case, for the current adjustment target state signal, when it is high, it is an effective adjustment state; otherwise, it is an ineffective adjustment state. Other cases can be referred to here for explanation, and will not be illustrated further.

[0084] When determining the target current adjustment status signal to be output by each current adjustment unit 3 through the above pre-adjustment, the target adjustment data corresponding to the target current adjustment status signal can be determined simultaneously. As can be seen from the above pre-adjustment, when the target current adjustment status signal is high, the target adjustment data can be "1". The correspondence between the current adjustment status signal and the target adjustment data can be selected and determined according to actual needs, and will not be listed and explained one by one here. After determining the target adjustment data, the target adjustment data can be loaded into the current adjustment main unit. At this time, the current adjustment main unit can output the corresponding target current adjustment status signal.

[0085] In specific implementation, when the current adjustment target state signal is in an effective adjustment state, the polycrystalline fuse in the current adjustment main unit is blown using a current-induced blowing method based on the current adjustment target state signal and the effective adjustment enable signal. This locks the current adjustment target state signal output by the current adjustment main unit after the polycrystalline fuse blows. It can be understood that locking the current adjustment target state signal output by the current adjustment main unit ensures that the current adjustment unit 3 output remains in an effective adjustment state. Figure 1 In some embodiments, the conduction drive of the corresponding NMOS transistor can be maintained.

[0086] It is understandable that when the current adjustment target status signal is in the adjustment invalid state, it is not necessary to lock the current adjustment target status signal output by the current adjustment master unit. At this time, the polysilicon fuse in the current adjustment master unit is still in the unfuse state.

[0087] Since both the object to be adjusted and the adjustment circuit of this invention may experience power loss, when power is restored after a power loss, the output of each current adjustment unit 3 should be kept at the corresponding current adjustment target state so as not to affect the working state of the object to be adjusted after adjustment.

[0088] To control the output state of each current trimming unit 3 after power-on, in one embodiment of the present invention, a trimming reset control signal generation unit cooperates with the current trimming master unit. Specifically, the trimming reset control signal generation unit generates a trimming reset control signal, which configures the output of the current trimming master unit to the corresponding current trimming target state signal. The corresponding current trimming target state signal specifically refers to the trimming state signal determined by the current current trimming master unit after pre-trimming and post-trimming. It can be understood that configuring the output of the current trimming master unit to the corresponding current trimming target state signal maintains the current trimming state of the trimming object based on the current trimming target state signal of the current current trimming unit. Figure 1 In this embodiment, the NMOS transistor NM0 is kept in a conducting drive state.

[0089] In one embodiment of the present invention, the current adjustment main unit includes a DFF trigger, a polysilicon fuse unit, and an adjustment reset unit, wherein,

[0090] The data input of the DFF flip-flop receives pre-adjustment data or target adjustment data, and the CLK input receives a clock signal CLK. Based on the clock signal CLK, the pre-adjustment data or target adjustment data is loaded into the DFF flip-flop.

[0091] When the pre-adjustment data is loaded into the data terminal of the DFF flip-flop, a pre-adjustment status signal is generated through the Q terminal of the DFF flip-flop.

[0092] When the target adjustment data is loaded into the data terminal of the DFF flip-flop, a current adjustment target state signal is generated through the Q terminal of the DFF flip-flop.

[0093] The polycrystalline fuse is located within a polycrystalline fuse unit, which also includes a fuse current path unit adapted and connected to the polycrystalline fuse.

[0094] The fuse current path unit receives the trimming enable signal and is connected to the Q terminal of the DFF flip-flop.

[0095] When the DFF flip-flop outputs the current adjustment target state signal of the adjustment effective state, and the adjustment enable signal is also in the effective state, it drives the fuse current path unit to form an effective current path. Thereafter, the polycrystalline fuse is current-fuse-broken based on the fuse breaking voltage and the formed effective current path.

[0096] The trimming and reset unit is adapted and connected to the polysilicon fuse unit and the DFF flip-flop, and generates a trimming and reset control signal based on the trimming and reset control signal generation unit. Based on the received trimming and reset control signal, the DFF flip-flop Q terminal is configured to output the corresponding current trimming target state signal.

[0097] To receive pre-adjustment data or target adjustment data, the current adjustment master unit may include a DFF flip-flop. Figure 2 The figure illustrates one embodiment of the current trimming master unit. In the figure, DFF0 is a DFF flip-flop. The DFF flip-flop can adopt commonly used forms. Generally, a DFF flip-flop has a CLK terminal and a data terminal. The data terminal of the DFF flip-flop can receive pre-trimmed data or target trimming data, and the CLK terminal receives the clock signal CLK. Figure 5 In the illustrated embodiment, pre-adjustment data or target adjustment data can be loaded into the DFF flip-flop via the rising edge of the clock signal CLK. Subsequently, the pre-adjustment status signal or the current adjustment target status signal can be obtained at the Q terminal of the DFF flip-flop.

[0098] The polycrystalline fuse should be located within a polycrystalline fuse unit. When the polycrystalline fuse blows, a current adjustment target state signal, indicating an effective adjustment state, can be locked at the Q terminal of the DFF flip-flop. To ensure the polycrystalline fuse blows, it is located within the polycrystalline fuse unit and adapted to the fuse current path unit. The fuse current path unit receives an adjustment enable signal and is connected to the Q terminal of the DFF flip-flop. In specific implementation, when the DFF flip-flop outputs a current adjustment target state signal indicating an effective adjustment state, and the adjustment enable signal is also active, the fuse current path unit is configured to form an effective current path based on the current adjustment target state signal and the adjustment enable signal. Subsequently, the polycrystalline fuse is current-blown based on the fuse breaking voltage and the formed effective current path.

[0099] To enable power-on reset, the current trimming main unit should also include a trimming reset unit. This trimming reset unit is connected to the polysilicon fuse unit and the DFF flip-flop, and generates a trimming reset control signal based on the trimming reset control signal generation unit. Based on the received trimming reset control signal, it configures the Q terminal of the DFF flip-flop to output the corresponding current trimming target state signal. Specifically, the Q terminal of the DFF flip-flop outputs the corresponding current trimming target state signal. For details, please refer to the above description, which will not be repeated here.

[0100] In one embodiment of the present invention, when the current adjustment target state signal of the effective adjustment state is high, the current adjustment target state signal of the ineffective adjustment state is low.

[0101] When the adjustment enable signal is active low, the fuse current path unit includes a NOR gate NOR0 and an NMOS transistor N0 connected to the output of the NOR gate NOR0, wherein...

[0102] The Q input of the DFF flip-flop is connected to one end of the inverter INV0 and the NOR gate NOR0, and the adjustment enable signal is connected to the other end of the NOR gate NOR0.

[0103] The source terminal of NMOS transistor N0 is grounded, the drain terminal of NMOS transistor N0 is connected to the first end of the polysilicon fuse, and the second end of the polysilicon fuse is connected to the fuse breaking voltage.

[0104] When the current adjustment target state signal based on the adjustment effective state and the low-level adjustment enable signal cause the NMOS transistor N0 to be in the conducting state, an effective current path is formed based on the NMOS transistor N0.

[0105] When the current adjustment target status signal of the effective adjustment state is high, the current adjustment master unit can use... Figure 2 The illustrated embodiment, Figure 2 In this context, a low level is used as the effective state of the adjustment enable signal. Specifically, when the adjustment enable signal is low and the effective state of the current adjustment target state signal is high, the output of the NOR gate NOR0 can output a high level. At this time, the NMOS transistor N0 can be turned on, and the polyfuse forms a path to ground through the NMOS transistor N0, that is, an effective current path is formed based on the NMOS transistor N0.

[0106] Figure 2 In the diagram, Rfuse-poly is the polycrystalline fuse, and ENB-PGM is the tuning enable signal. When using the effective current path to fuse the polycrystalline fuse via current fusing, a fuse breaking voltage should also be applied to the second terminal of the polycrystalline fuse. Figure 2 In this circuit, Vf represents the fuse breaking voltage. After an effective current path is formed, the fuse breaking voltage forms a loop through the polycrystalline fuse and the NMOS transistor N0. Current flows through the polycrystalline fuse, which is used to melt it. In practice, the NMOS transistor N0 should be designed to be relatively large to ensure that it can carry a sufficiently large current when melting the polycrystalline fuse. The size of the NMOS transistor N0 can be selected and determined according to actual needs, based on meeting the current breaking requirements of the polycrystalline fuse.

[0107] Depend on Figure 2As described above, when the current adjustment target state signal output from the Q terminal of the DFF flip-flop is in an inactive state, it becomes high level after passing through the inverter INV0. At this time, even if the adjustment enable signal is in an active low level state, the output of the NOR gate NOR0 remains low level. At this time, the NMOS transistor N0 remains in the off state and cannot form an effective current path.

[0108] In one embodiment of the present invention, the adjustment and reset unit includes a level state detection unit and a reset position signal generation unit adapted and connected to the level state detection unit, wherein,

[0109] The adjustment and reset control signal is applied to the level state detection unit, and the level state detection unit obtains the fuse level state signal that characterizes the melting state of the polycrystalline fuse based on the adjustment and reset control signal;

[0110] Based on the adjustment and reset control signal and the fuse level status signal, the reset signal generation unit generates a reset signal that is applied to the DFF flip-flop.

[0111] When the fuse level status signal indicates that the polycrystalline fuse is in the blown state, the current adjustment target status signal of the effective state is output by the Q terminal of the DFF flip-flop based on the reset position signal.

[0112] When the fuse level status signal indicates that the polycrystalline fuse is in an unfuse state, the Q terminal of the DFF flip-flop is configured to output a current adjustment target status signal to adjust the invalid state based on the reset position signal.

[0113] Figure 2 The DFF flip-flop shown includes a set terminal and a reset terminal. In the figure, SEB is the set terminal of the DFF flip-flop, and RSB is the reset terminal. In specific implementation, the fuse level status signal can be obtained by detecting the level status. The fuse level status signal can be used to characterize whether the polycrystalline fuse has blown. Subsequently, based on the adjusted reset control signal and the fuse level status signal, the reset position signal generation unit can generate a reset position signal. In specific implementation, the reset position signal may include a reset drive signal and a set drive signal. At this time, the reset drive signal is applied to the reset terminal of the DFF flip-flop, and the set drive signal is applied to the set terminal of the DFF flip-flop.

[0114] right Figure 2In the embodiment of the DFF flip-flop shown, both the set and reset terminals of the DFF flip-flop are active low. That is, a reset or set operation will only be performed when a low level is received. For example, if the set drive signal applied to the set terminal is low, the DFF flip-flop will be set. At this time, the Q terminal of the DFF flip-flop can output a high level, which means that the Q terminal of the DFF flip-flop is set to the current adjustment target state signal in the adjustment active state. If the reset drive signal applied to the reset terminal is low, the DFF flip-flop will be reset. At this time, the Q terminal of the DFF flip-flop can output a low level, which means that the Q terminal of the DFF flip-flop is configured to the current adjustment target state signal in the adjustment inactive state.

[0115] In one embodiment of the present invention, the adjustment reset control signal includes a preload control signal RE-LOAD, a low-level detection control signal CFG-N, and a high-level detection control signal CFG-P, wherein,

[0116] After the current adjustment unit is powered on again, the high level detection control signal CFG-P and the low level detection control signal CFG-N are immediately in an effective level state, and the preload control signal RE-LOAD enters the effective level state with a delay. Based on the preload control signal RE-LOAD entering the effective level state with a delay, the reset position signal generation unit outputs an invalid reset position signal.

[0117] When the preload control signal RE-LOAD enters the valid level state, the level state detection unit generates the fuse level state signal based on the preload control signal RE-LOAD, the low level detection control signal CFG-N, and the high level detection control signal CFG-P.

[0118] Specifically, the adjustment and reset control signals include the preload control signal RE-LOAD, the low-level detection control signal CFG-N, and the high-level detection control signal CFG-P. It can be understood that when the current adjustment main unit is pre-adjusted and post-adjusted, the preload control signal RE-LOAD, the low-level detection control signal CFG-N, and the high-level detection control signal CFG-P should all be in an invalid level state. When the current adjustment unit is powered on again, the high-level detection control signal CFG-P and the low-level detection control signal CFG-N immediately become valid, and the preload control signal RE-LOAD becomes valid after a delay.

[0119] In practical implementation, the RE-LOAD preload control signal, which delays entry into the valid level state, causes the reset position signal generation unit to output an invalid reset position signal. That is, both the reset drive signal and the set drive signal are invalid. As explained above, when the invalid reset drive signal and set drive signal are high, the DFF flip-flop will neither be set nor reset. Using the invalid reset position signal, the system can wait for the level state detection unit to acquire the fuse level state signal.

[0120] When the preload control signal RE-LOAD enters the valid level state, the level state detection unit generates a fuse level state signal based on the preload control signal RE-LOAD, the low level detection control signal CFG-N, and the high level detection control signal CFG-P. Subsequently, the corresponding reset drive signal and set drive signal can be generated based on the fuse level state signal to improve the reliability of resetting or setting the DFF flip-flop.

[0121] In one embodiment of the present invention, when the preload control signal RE-LOAD, the low-level detection control signal CFG-N are active high, and the high-level detection control signal CFG-P is active low, the level state detection unit includes NMOS transistors N1, NMOS transistors N2, and PMOS transistor P0. The source terminal of NMOS transistor N2 is grounded, the drain terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N1, the drain terminal of NMOS transistor N1 is connected to the drain terminal of PMOS transistor P0 and the reset bit signal generation unit, and the source terminal of PMOS transistor P0 is connected to the first end of the polyfusible fuse.

[0122] The gate of NMOS transistor N1 is connected to the low-level detection control signal CFG-N, the gate of NMOS transistor N2 is connected to the preload control signal RE-LOAD, and the gate of PMOS transistor P0 is connected to the high-level detection control signal CFG-P.

[0123] Figure 5 The diagram illustrates a timing sequence of the preload control signal RE-LOAD, the low-level detection control signal CFG-N, and the high-level detection control signal CFG-P during the operation of a dual-mode trimming circuit. In the diagram, during pre-trimming and post-trimming of the current trimming main unit, the high-level detection control signal CFG-P is at a high level, while the preload control signal RE-LOAD and the low-level detection control signal CFG-N are at a low level. After the dual-mode trimming circuit is powered off, all three signals are at a low level.

[0124] After power is restored, the high-level detection control signal CFG-P remains at a low level, while the low-level detection control signal CFG-N immediately becomes high. The preload control signal RE-LOAD becomes high and then enters a high level state, that is, the preload control signal RE-LOAD enters the high level state with a longer duration than the low-level detection control signal CFG-N.

[0125] Figure 2 The diagram illustrates one embodiment of the level state detection unit. When the high-level detection control signal CFG-P is low, the PMOS transistor P0 is turned on; when the low-level detection control signal CFG-N is high, the NMOS transistor N2 is turned on. When the preload control signal RE-LOAD is low, the NMOS transistor N1 is turned off; when the preload control signal RE-LOAD is high, the NMOS transistor N1 is turned on.

[0126] Furthermore, by Figure 5 It is known that when power is restored, the fuse breaking voltage should also be applied to the second terminal of the polycrystalline fuse. During normal operation, the fuse breaking voltage needs to be removed. During the power-on phase, the melting point voltage can be lower than the voltage value during the polycrystalline fuse breaking phase. Furthermore, during the pre-adjustment phase, the fuse breaking voltage does not need to be applied to the second terminal of the polycrystalline fuse; during the post-adjustment phase, the fuse breaking voltage should be applied to the second terminal of the polycrystalline fuse.

[0127] It is understandable that when NMOS transistors N1, N2, and PMOS transistor P0 are all turned on and the fuse level status signal is obtained, then: when the polysilicon fuse is not blown, the drain terminal of PMOS transistor P0 forms a path to ground through NMOS transistors N1 and N2, and the voltage at the drain terminal of PMOS transistor P0 is 0 level; when the polysilicon fuse is blown, the drain terminal of PMOS transistor P0 is pulled up to the fuse blowing voltage by the fuse blowing voltage, and at this time, the voltage at the drain terminal of PMOS transistor P0 is high level.

[0128] In one embodiment of the present invention, the repositioning bit signal generation unit includes a PMOS transistor P1 and a Schmitt trigger, wherein,

[0129] The source terminal of PMOS transistor P1 is connected to the power supply VDD. The gate terminal of PMOS transistor P1 is connected to the preload control signal RE-LOAD and connected to one end of NAND gate NAND0 and one end of NAND gate NAND1. The drain terminal of PMOS transistor P1 is connected to the drain terminal of PMOS transistor P0, the drain terminal of NMOS transistor N1, and the input terminal of Schmitt trigger.

[0130] The output of the Schmitt trigger is connected to the other end of the NAND gate NAND0 and the input of the inverter INV1. The output of the inverter INV1 is connected to the other end of the NAND gate NAND1.

[0131] The output of NAND gate NAND0 is connected to the set terminal of DFF flip-flop, and the output of NAND gate NAND1 is connected to the reset terminal of DFF flip-flop.

[0132] Figure 2 The figure shows an embodiment of a complex position signal generation unit. In the figure, SMIT-TRIGO is a Schmitt trigger. The Schmitt trigger can be in the form of a commonly used one. The Schmitt trigger can be used to achieve level degluing.

[0133] Depend on Figure 2 As can be seen from the reset signal generation unit in the middle, when the preload control signal RE-LOAD is in an invalid state of low level, the NAND gate NAND0 and NAND gate NAND1 output a high level. At this time, the set drive signal of the DFF flip-flop set terminal is high level, and the reset drive signal of the DFF flip-flop reset terminal is also high level. As can be seen from the above description, the DFF flip-flop does not perform a set operation or a reset operation at this time.

[0134] When the preload control signal RE-LOAD is high, PMOS transistor P1 is off. The input voltage of the Schmitt trigger is only related to the voltage at the drain terminal of PMOS transistor P0. If the voltage at the drain terminal of PMOS transistor P0 is high, the set drive signal output through NAND gate NAND0 is low, while the reset drive signal output through NAND gate NAND1 is high. At this time, the DFF trigger is set, and the Q terminal of the DFF trigger is the current adjustment target state signal for the active state. If the voltage at the drain terminal of PMOS transistor P0 is low, the set drive signal output through NAND gate NAND0 is high, while the reset drive signal output through NAND gate NAND1 is low. At this time, the DFF trigger is reset, and the Q terminal of the DFF trigger is the current adjustment target state signal for the inactive state.

[0135] The above illustrates one way to configure the output of the Q terminal of the DFF flip-flop as the target current adjustment state signal after power-on. Of course, other methods can also be used to reset or set the output of the Q terminal of the DFF flip-flop, depending on whether they can configure the output of the Q terminal of the DFF flip-flop as the corresponding target current adjustment state signal. These methods will not be listed here.

[0136] In one embodiment of the present invention, the adjustment and reset control signal generation unit includes at least an adjustment and reset control signal generation main circuit, wherein,

[0137] After the current adjustment unit is powered on again, a high-level active power-on reset control pulse PRO is applied to the main circuit for generating the adjustment reset control signal;

[0138] Based on the power-on reset control pulse PRO, the main circuit for generating the reset control signal simultaneously generates a preload control signal RE-LOAD, a low-level detection control signal CFG-N, and a high-level detection control signal CFG-P.

[0139] The main circuit for generating adjustment and reset control signals includes a high-level detection control signal generation unit, a low-level detection control signal generation unit, and a preload control signal generation unit.

[0140] Based on the power-on reset control pulse PRO, the high-level detection control signal generation unit synchronously generates the high-level detection control signal CFG-P in the low-level state.

[0141] Based on the high-level detection control signal CFG-P, the low-level detection control signal generation unit synchronously generates a high-level low-level detection control signal CFG-N;

[0142] Based on the low-level detection control signal CFG-N, the preload control signal generation unit delays the generation of a high-level preload control signal RE-LOAD. The rising edge of the high-level state of the preload control signal RE-LOAD is located after the corresponding rising edge of the low-level detection control signal CFG-N, and the falling edge of the preload control signal RE-LOAD is located before the corresponding falling edge of the low-level detection control signal CFG-N.

[0143] Specifically, the adjustment and reset control signal is used to generate the main circuit at least once. Figure 1 The diagram also shows an embodiment in which the adjustment reset control signal generation unit includes a power-on reset circuit 1. That is, the adjustment reset control signal generation unit may include a power-on reset circuit 1 and an adjustment reset control signal generation main circuit. In this case, the power-on reset circuit 1 can generate a power-on reset control pulse PRO. At this time, based on the power-on reset control pulse PRO, the adjustment reset control signal generation main circuit simultaneously generates a preload control signal RE-LOAD, a low-level detection control signal CFG-N, and a high-level detection control signal CFG-P.

[0144] Figure 5 In the embodiment shown, the power-on reset control pulse PRO is high only after power-on, and low in all other stages. Figure 5In the above, for the power supply VDD, it is 0 only when the power supply is off; otherwise, it provides the corresponding voltage. Furthermore, the clock signal CLK and the DATA input of the DFF flip-flop are valid only during the pre-adjustment and post-adjustment phases; otherwise, they are low.

[0145] Figure 4 The diagram illustrates one embodiment of the main circuit for generating the adjustment and reset control signal. Figure 4 The high-level detection and control signal generation unit includes inverters INV2, INV3, and INV4, a NOR gate NOR1, capacitors C1, C2, and C3.

[0146] The input of inverter INV2 receives the power-on reset control pulse PRO, and the power-on reset control pulse PRO is also applied to the first input of NOR1.

[0147] The output of inverter INV2 is connected to one end of capacitor C1 and the input of inverter INV3. The output of inverter INV3 is connected to one end of capacitor C2 and the input of inverter INV4. The output of inverter INV4 is connected to one end of capacitor C3 and the second input of NOR gate NOR1.

[0148] The other ends of capacitors C1, C2, and C3 are all grounded.

[0149] The output of the NOR1 gate outputs a high-level detection control signal CFG-P.

[0150] Figure 4 In the middle, the low-level detection control signal generation unit includes an inverter INV5. The input terminal of the inverter INV5 is connected to the output terminal of the NOR gate NOR1. That is, the inverter INV5 can invert the high-level detection control signal CFG-P. Thus, the level state of the low-level detection control signal CFG-N is opposite to the level state of the high-level detection control signal CFG-P.

[0151] Figure 5 During power-on, the effective duration of the low-level detection control signal CFG-N and the high-level detection control signal CFG-P is less than the effective high-level duration of the power-on reset control pulse PRO.

[0152] Figure 4 The preload control signal generation unit includes inverters INV6, INV7, INV8, and INV9, a NOR gate NOR2, an inverter INV10, capacitor C4, and capacitor C5.

[0153] The output of inverter INV5 is connected to the input of inverter INV6. The input of inverter INV6 is connected to one end of capacitor C3, the input of inverter INV7, and the input of inverter INV8. The output of inverter INV7 is connected to the first input of NOR gate NOR2.

[0154] The output of inverter INV8 is connected to one end of capacitor C5 and one end of inverter INV9. The output of inverter INV9 is connected to the second input of NOR2, and the output of NOR2 is connected to the input of inverter INV10. The preload control signal RE-LOAD is generated through the output of inverter INV10.

[0155] When the preload control signal generation unit adopts the above form, the effective time of the preload control signal RE-LOAD is less than the effective time of the low-level detection control signal CFG-N.

[0156] In one embodiment of the present invention, the dual-mode trimming unit further includes a laser trimming unit 4 based on laser trimming, wherein,

[0157] The output terminals of laser trimming unit 4 and current trimming unit 3 are connected to the corresponding input terminals of the trimming unit OR gate.

[0158] The laser trimming target status signal is output through the output terminal of the laser trimming unit 4;

[0159] Based on the laser-adjusted target state signal and / or the current-adjusted target state signal, a dual-mode adjustment state signal is output through the output terminal of the adjustment unit or gate.

[0160] Figure 1 The illustration shows an embodiment where each dual-mode trimming unit also includes a laser trimming unit 4. It is understood that the laser trimming unit 4 can employ laser trimming. In this case, each dual-mode trimming unit can use either current trimming or laser trimming. The dual-mode trimming in this case is both current trimming and laser trimming. The trimming method used by the dual-mode trimming unit can be selected as needed to meet actual application requirements. Alternatively, current trimming unit 3 can be used for pre-trimming, while laser trimming unit 4 performs post-trimming. If the current trimming target state signal is in a trimming effective state, laser trimming unit 4 can be modified using laser without using current to blow the polycrystalline fuse within current trimming unit 3.

[0161] When the dual-mode trimming unit includes a laser trimming unit 4 and a current trimming unit 3, it should be connected to the laser trimming unit 4 and the current trimming unit 3 through a trimming unit OR gate. Figure 1 In this context, OR0, OR1, and ORX are all corresponding trimming units or NOT gates.

[0162] It should be noted that, depending on the adjustment state of the laser adjustment unit 4, the output terminal of the laser adjustment unit 4 can output a laser adjustment target state signal. The only difference between the two is the adjustment method. For the laser adjustment target state signal, please refer to the above description of the current adjustment target state signal, which will not be repeated here.

[0163] When the dual-mode trimming unit contains only the current trimming unit 3, a dual-mode trimming state signal can be generated based on the current trimming target state signal. However, when the dual-mode trimming unit contains both the current trimming unit 3 and the laser trimming unit 4, the dual-mode trimming state signal is output through the output of the trimming unit's OR gate based on the laser trimming target state signal and / or the current trimming target state signal. Generally, for a single dual-mode trimming unit, the object being trimmed is trimmed through either the current trimming unit 3 or the laser trimming unit.

[0164] Figure 1 In the illustrated embodiment, when there are multiple dual-mode trimming units in the dual-mode trimming circuit, in order to load data, the current trimming unit 3 is configured in a cascaded state, such as the output terminal of one current trimming unit 3 being connected to the data terminal of the DFF flip-flop in the next current trimming unit 3. At this time, serial loading of data can be achieved.

[0165] In one embodiment of the present invention, the laser trimming unit 4 includes a laser fuse, wherein,

[0166] The first end of the laser fuse is grounded, and the second end of the laser fuse is connected to the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N2.

[0167] The drain terminal of PMOS transistor P3 is connected to the gate terminal of PMOS transistor P4, the drain terminal of NMOS transistor N2, and the gate terminal of NMOS transistor N3.

[0168] The source terminals of PMOS transistors P2, P3, and P4 are all grounded to the power supply VDD.

[0169] The source terminals of NMOS transistors N2 and NMOS transistor N3 are both grounded;

[0170] The drain terminals of PMOS transistor P4 and NMOS transistor N4 are connected to form the output terminal of the laser trimming unit.

[0171] Figure 3The image shows one embodiment of the laser trimming unit 4. The fuse Rfuse-tm is the laser fuse, which is generally made of top-layer aluminum and can be trimmed by laser. In practical applications, the laser fuse is located around the chip and has precise coordinate positions. Therefore, by using the coordinate positions of the laser fuse, an automatic laser programming program is written to melt the laser fuse that needs to be melted by laser irradiation.

[0172] After the laser fuse melts, Figure 3 Point A in the circuit is pulled up to a higher potential, and D-F2 is the output terminal of the laser trimming unit. When node A is pulled up, D-F2 outputs a high level; when the laser fuse is not blown, node A is pulled down to a lower potential, and D-F2 outputs a low level. The gate and drain terminals of PMOS transistor P3 are shorted together, and PMOS transistor P3 is used as a pull-up resistor to reduce static current. The size of PMOS transistor P3 is designed to be relatively small, specifically to meet the requirements of being used as a pull-up resistor.

Claims

1. A pre-adjustable dual-mode adjustment circuit, characterized in that, The dual-mode tuning circuit includes several dual-mode tuning units, each of which generates a corresponding dual-mode tuning status signal. The dual-mode trimming unit includes at least a current trimming unit based on current trimming, wherein the current trimming unit includes a current trimming main unit and a trimming reset control signal generation unit adapted and connected to the current trimming main unit. When performing current adjustment based on the current adjustment unit, pre-adjustment is first performed using the main current adjustment unit, followed by post-adjustment. During pre-adjustment, the pre-adjustment data is loaded into the current adjustment master unit so that the current adjustment master unit generates a pre-adjustment status signal corresponding to the pre-adjustment data. Based on the pre-adjustment state signal generated by the pre-adjustment, the current adjustment target state signal of the current adjustment master unit during the post-adjustment is determined, wherein the state of the current adjustment target state signal is an adjustment effective state or an adjustment ineffective state. During post-adjustment, based on the current adjustment target state signal, the target adjustment data is loaded into the current adjustment main unit, and the corresponding current adjustment target state signal is output through the current adjustment unit. Furthermore, a dual-mode adjustment state signal is formed based on the current adjustment target state signal. When the current adjustment target status signal is in the adjustment active state, the polycrystalline fuse in the current adjustment main unit is blown by current blowing based on the current adjustment target status signal and the adjustment enable signal in the active state, so as to lock the current adjustment target status signal output by the current adjustment main unit after the polycrystalline fuse blows. After the current trimming unit is powered on again, the trimming reset control signal generation unit generates a trimming reset control signal so that the current trimming master unit configures the generated trimming status signal as the corresponding current trimming target status signal under the trimming reset control signal. The current adjustment main unit includes a DFF trigger, a polysilicon fuse unit, and an adjustment reset unit, wherein... The data input of the DFF flip-flop receives pre-adjustment data or target adjustment data, and the CLK input receives a clock signal CLK. Based on the clock signal CLK, the pre-adjustment data or target adjustment data is loaded into the DFF flip-flop. When the pre-adjustment data is loaded into the data terminal of the DFF flip-flop, a pre-adjustment status signal is generated through the Q terminal of the DFF flip-flop. When the target adjustment data is loaded into the data terminal of the DFF flip-flop, a current adjustment target state signal is generated through the Q terminal of the DFF flip-flop. The polycrystalline fuse is located within a polycrystalline fuse unit, which also includes a fuse current path unit adapted and connected to the polycrystalline fuse. The fuse current path unit receives the adjustment enable signal and is connected to the Q terminal of the DFF flip-flop. When the DFF flip-flop outputs the current adjustment target state signal of the adjustment effective state, and the adjustment enable signal is also in the effective state, it drives the fuse current path unit to form an effective current path. Thereafter, the polycrystalline fuse is current-fuse-broken based on the fuse breaking voltage and the formed effective current path. The trimming and reset unit is adapted and connected to the polysilicon fuse unit and the DFF flip-flop, and generates a trimming and reset control signal based on the trimming and reset control signal generation unit. Based on the received trimming and reset control signal, the DFF flip-flop Q terminal is configured to output the corresponding current trimming target state signal. The adjustment and reset unit includes a level state detection unit and a reset position signal generation unit adapted and connected to the level state detection unit, wherein, The adjustment and reset control signal is applied to the level state detection unit, and the level state detection unit obtains the fuse level state signal that characterizes the melting state of the polycrystalline fuse based on the adjustment and reset control signal; Based on the adjustment and reset control signal and the fuse level status signal, the reset signal generation unit generates a reset signal that is applied to the DFF flip-flop. When the fuse level status signal indicates that the polycrystalline fuse is in the blown state, the current adjustment target status signal of the effective state is output by the Q terminal of the DFF flip-flop based on the reset position signal. When the fuse level status signal indicates that the polycrystalline fuse is in an unfuse state, the Q terminal of the DFF flip-flop is configured to output a current adjustment target status signal to adjust the invalid state based on the reset position signal.

2. The pre-adjustable dual-mode adjustment circuit according to claim 1, characterized in that: adjustment When the target current adjustment signal for the active state is high, the target current adjustment signal for the inactive state is low. When the adjustment enable signal is active low, the fuse current path unit includes a NOR gate NOR0 and an NMOS transistor N0 connected to the output of the NOR gate NOR0, wherein... The Q input of the DFF flip-flop is connected to one end of the inverter INV0 and the NOR gate NOR0, and the adjustment enable signal is connected to the other end of the NOR gate NOR0. The source terminal of NMOS transistor N0 is grounded, the drain terminal of NMOS transistor N0 is connected to the first end of the polysilicon fuse, and the second end of the polysilicon fuse is connected to the fuse breaking voltage. When the current adjustment target state signal based on the adjustment effective state and the low-level adjustment enable signal cause the NMOS transistor N0 to be in the conducting state, an effective current path is formed based on the NMOS transistor N0.

3. The pre-adjustable dual-mode adjustment circuit according to claim 1, characterized in that: The adjustment and reset control signals include the preload control signal RE-LOAD, the low-level detection control signal CFG-N, and the high-level detection control signal CFG-P, among which, After the current adjustment unit is powered on again, the high level detection control signal CFG-P and the low level detection control signal CFG-N are immediately in an effective level state, and the preload control signal RE-LOAD enters the effective level state with a delay. Based on the preload control signal RE-LOAD entering the effective level state with a delay, the reset position signal generation unit outputs an invalid reset position signal. When the preload control signal RE-LOAD enters the valid level state, the level state detection unit generates the fuse level state signal based on the preload control signal RE-LOAD, the low level detection control signal CFG-N, and the high level detection control signal CFG-P.

4. The pre-adjustable dual-mode adjustment circuit according to claim 3, characterized in that: When the preload control signal RE-LOAD, the low-level detection control signal CFG-N are active high, and the high-level detection control signal CFG-P is active low, the level state detection unit includes NMOS transistors N1, NMOS transistor N2, and PMOS transistor P0. The source terminal of NMOS transistor N2 is grounded, the drain terminal of NMOS transistor N2 is connected to the source terminal of NMOS transistor N1, the drain terminal of NMOS transistor N1 is connected to the drain terminal of PMOS transistor P0 and the reset bit signal generation unit, and the source terminal of PMOS transistor P0 is connected to the first end of the polysilicon fuse. The gate of NMOS transistor N2 is connected to the low-level detection control signal CFG-N, the gate of NMOS transistor N1 is connected to the preload control signal RE-LOAD, and the gate of PMOS transistor P0 is connected to the high-level detection control signal CFG-P.

5. The pre-adjustable dual-mode adjustment circuit according to claim 4, characterized in that: The reset bit signal generation unit includes a PMOS transistor P1 and a Schmitt trigger, wherein, The source terminal of PMOS transistor P1 is connected to the power supply VDD. The gate terminal of PMOS transistor P1 is connected to the preload control signal RE-LOAD and connected to one end of NAND gate NAND0 and one end of NAND gate NAND1. The drain terminal of PMOS transistor P1 is connected to the drain terminal of PMOS transistor P0, the drain terminal of NMOS transistor N1, and the input terminal of Schmitt trigger. The output of the Schmitt trigger is connected to the other end of the NAND gate NAND0 and the input of the inverter INV1. The output of the inverter INV1 is connected to the other end of the NAND gate NAND1. The output of NAND gate NAND0 is connected to the set terminal of DFF flip-flop, and the output of NAND gate NAND1 is connected to the reset terminal of DFF flip-flop.

6. The pre-adjustable dual-mode adjustment circuit according to claim 4, characterized in that: The adjustment and reset control signal generation unit includes at least an adjustment and reset control signal generation main circuit, wherein... After the current adjustment unit is powered on again, a high-level active power-on reset control pulse PRO is applied to the main circuit for generating the adjustment reset control signal; Based on the power-on reset control pulse PRO, the main circuit for generating the reset control signal simultaneously generates a preload control signal RE-LOAD, a low-level detection control signal CFG-N, and a high-level detection control signal CFG-P. The main circuit for generating adjustment and reset control signals includes a high-level detection control signal generation unit, a low-level detection control signal generation unit, and a preload control signal generation unit. Based on the power-on reset control pulse PRO, the high-level detection control signal generation unit synchronously generates the high-level detection control signal CFG-P in the low-level state. Based on the high-level detection control signal CFG-P, the low-level detection control signal generation unit synchronously generates a high-level low-level detection control signal CFG-N; Based on the low-level detection control signal CFG-N, the preload control signal generation unit delays the generation of a high-level preload control signal RE-LOAD. The rising edge of the high-level state of the preload control signal RE-LOAD is located after the corresponding rising edge of the low-level detection control signal CFG-N, and the falling edge of the preload control signal RE-LOAD is located before the corresponding falling edge of the low-level detection control signal CFG-N.

7. The pre-adjustable dual-mode adjustment circuit according to any one of claims 1 to 6, characterized in that: The dual-mode trimming unit also includes a laser trimming-based laser trimming unit, wherein... The output terminals of the laser trimming unit and the current trimming unit are connected to the corresponding input terminals of the trimming unit OR gate. The laser trimming target status signal is output through the output terminal of the laser trimming unit; Based on the laser-adjusted target state signal and / or the current-adjusted target state signal, a dual-mode adjustment state signal is output through the output terminal of the adjustment unit or gate.

8. The pre-adjustable dual-mode adjustment circuit according to claim 7, characterized in that: The laser trimming unit includes a laser fuse, wherein... The first end of the laser fuse is grounded, and the second end of the laser fuse is connected to the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N2. The drain terminal of PMOS transistor P3 is connected to the gate terminal of PMOS transistor P4, the drain terminal of NMOS transistor N2, and the gate terminal of NMOS transistor N3. The source terminals of PMOS transistors P2, P3, and P4 are all grounded to the power supply VDD. The source terminals of NMOS transistors N2 and NMOS transistor N3 are both grounded; The drain terminals of PMOS transistor P4 and NMOS transistor N4 are connected to form the output terminal of the laser trimming unit.

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