Processor providing physical machine and virtual machine operation, and processor acceleration method
By preserving the target trigger instruction content of the virtual machine in the virtual machine control data structure, the processor cycle consumption problems caused by repeated address conversion and data copying in the virtual machine operation are solved, and the operation of the virtual machine is accelerated.
Patent Information
- Application Number
- CN202411814231.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-04-04
AI Technical Summary
In the prior art, the instruction finger fetching operations repeatedly executed during the operation of a virtual machine involve multiple address conversion and data copying from user state to kernel state, resulting in excessive consumption of processor cycles and affecting the operation efficiency of the virtual machine.
A processor is designed to include a virtualized hardware accelerator, which accelerates the instruction simulation process by preserving the instruction content of the target trigger instruction in the virtual machine control data structure, avoiding repeated multiple address conversion and data copying.
By pre-stored instruction content, the number of multiple address conversion and data copying is reduced, which significantly accelerates the operation process of the virtual machine and improves the efficiency of the processor.
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Figure CN119759494A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a processor that provides operation of a physical machine and a virtual machine. Background Art
[0002] A virtual machine (VM) is another computer simulated by software on a physical computer.
[0003] Figure 1 The diagram illustrates the operation of a traditional virtual machine (VM). In addition to a physical machine 102, a computer system 100 also includes a virtual machine 104 simulated by a processor using software. The virtual machine 104 is shown executing a trigger instruction 106, triggering a switch back to the physical machine 102 to perform a virtual machine exit (VM exit) event 108. The software determines in step 110 whether it is necessary to simulate the trigger instruction 106. If not, the physical machine 102 performs other processing procedures for the virtual machine exit event in step 112. On the contrary, if there is a need for instruction simulation, the physical machine 102 performs the instruction simulation process 114.
[0004] The instruction simulation process 114 includes three steps: instruction fetch 116; instruction decoding 118; and instruction simulation 120. Instruction fetch 116 reads the instruction content from the virtual machine memory 122. Instruction decoding 118 parses the instruction content and determines whether a complete instruction has been obtained. If it is not a complete instruction, instruction fetch 116 needs to be performed again. Otherwise, the program enters instruction simulation 120. Instruction fetch 116 is implemented step by step and may be executed repeatedly.
[0005] However, each instruction fetch 116 performed by the physical machine 102 on the virtual machine memory 122 involves time-consuming multiple address translations. The guest virtual address (GVA) on the virtual machine side must be converted to the guest physical address (GPA) on the virtual machine side, and the virtual machine side physical address (GPA) must be converted to the host virtual address (HVA) on the physical machine side. In addition, the instruction fetch 116 performed by the physical machine 102 on the virtual machine memory 122 also involves data copying from user mode to kernel mode; for example, executing an instruction copy_from_user copies the instruction content from user space to kernel space. Such data copying will also consume a considerable number of processor cycles. Therefore, the repeatedly executed instruction fetch 116 will repeatedly consume a large number of processor cycles on multiple address translations (GVA→GPA→HVA) and instruction content copying (from user mode to kernel mode).
[0006] How to speed up the operation of virtual machines is an important issue in the technical field. Summary of the invention
[0007] The present application proposes a processor acceleration technology.
[0008] According to one embodiment of the present application, a processor includes a virtualization hardware accelerator. When the virtual machine executes a target trigger instruction, the virtualization hardware accelerator completely pre-stores the instruction content of the target trigger instruction from the virtual machine memory to the virtual machine control data structure; wherein the target trigger instruction triggers a virtual machine exit event and waits for the physical machine simulation to provide it. The virtual machine monitor running in software on the physical machine obtains the instruction content of the target trigger instruction from the virtual machine control data structure, performs instruction decoding and instruction simulation of the target trigger instruction.
[0009] In one implementation, the virtual machine monitor reads the virtual machine control data structure with the physical machine-side virtual address without performing address conversion between the physical machine and the virtual machine to obtain the instruction content of the target trigger instruction.
[0010] In one implementation, the virtual machine monitor obtains the instruction content of the target trigger instruction from the virtual machine control data structure without copying data from the user state to the kernel state.
[0011] In one implementation, the virtual machine monitor obtains the instruction content of the target trigger instruction from the virtual machine control data structure at one time.
[0012] The simulation of the target trigger instruction avoids repeatedly consuming a large number of processor cycles on multiple address translations (GVA→GPA→HVA) and instruction content copying (from user state to kernel state), which significantly speeds up the processor.
[0013] The above concept is also implemented as a processor acceleration method.
[0014] The following is a detailed description of the present invention with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 Illustrate the traditional virtual machine (VM) operation;
[0016] Figure 2 A virtual machine control data structure (VMCS) 200 is illustrated according to one embodiment of the present application;
[0017] Figure 3 Illustrate the operation of a virtual machine (VM) according to one embodiment of the present application; and
[0018] Figure 4 A computer system 400 is illustrated according to one embodiment of the present application.
[0019]
Explanation of symbols
[0020] 100, 300, 400: Computer systems
[0021] 102, 302: physical machine
[0022] 104, 304: Virtual Machine
[0023] 106, 306: trigger instruction
[0024] 108, 308: Virtual machine exit event
[0025] 110, 112, 116 ... 120, 314, 316, 320, 322, 326 ... 334: Steps 114, 318: Instruction simulation process
[0026] 122, 324: virtual machine memory
[0027] 200: Virtual machine control data structure
[0028] 202: Virtual instruction control table
[0029] 204: Virtual instruction content
[0030] 310: Virtualization Hardware Accelerator
[0031] 312: Virtual Machine Monitor
[0032] 402:Processor
[0033] 404: Memory
[0034] 406: Software
[0035] 408: Control interface
[0036] 410: Hardware DETAILED DESCRIPTION
[0037] The following description lists various embodiments of the present application, but is not intended to limit the content of the present application. The actual scope of the invention should be defined in accordance with the claims. The various units, modules, or functional blocks mentioned below can be implemented by hardware, software, firmware combination, and can also include special circuits. These units, modules, or functional blocks are not limited to being implemented separately, but can also be combined together to share certain functional units.
[0038] The present invention proposes an instruction pre-caching method in a virtualization scenario to accelerate the instruction fetching speed in a virtual instruction simulation process.
[0039] Certain instructions executed in the virtual machine will trigger a virtual machine exit event, and a software-implemented virtual machine monitor (hypervisor) is required to simulate the triggering instruction. The instruction simulation process is as described above, including three steps: instruction fetch, instruction decoding, and instruction simulation. In software design, the instruction length is uncertain (but does not exceed a specific number of bytes; for example, x86 instructions do not exceed 15 bytes). Traditional software fetches instructions in segments, confirming whether the complete instruction is obtained segment by segment. Such repeated instruction fetching involves time-consuming multiple address conversions (GVA→GPA→HVA), and instruction content copying (from user state to kernel state). One implementation method of the present application makes special design in hardware to accelerate the instruction fetching speed during virtual instruction simulation.
[0040] In accordance with the hardware adjustments, the present application has a special design for the virtual-machine control data structure (VMCS). The virtual-machine control data structure (VMCS) is used as a communication bridge between the virtual machine and the physical machine. The virtual-machine control data structure (VMCS) generally stores the following information: the running status of the physical machine (i.e., the central processing unit CPU); the running status of the virtual machine (vCPU); and the running logic of the virtual machine (vCPU). Figure 2 According to one embodiment of the present application, a virtual machine control data structure (VMCS) 200 is illustrated. The virtual machine control data structure 200 is specially designed with two special fields.
[0041] The first field records a guest instruction control bitmap 202. Each bit of the guest instruction control bitmap 202 corresponds to a trigger instruction that triggers a VM exit event. For trigger instructions that the physical machine will use as the simulation target, the relevant bit in the guest instruction control bitmap 202 will be set to 1, indicating that the instruction content of the trigger instruction needs to be pre-stored. The virtual instruction control bitmap 202 in the accompanying figure manages multiple trigger instructions, including: input / output instructions (I / O instruction VM Exit) that trigger a VM exit event; application program interface connection access (APIC access VM Exit) that triggers a VM exit event; register GDTR / IDTR access that triggers a VM exit event (access to GDTR / IDTR VM Exit); register LDTR / TR access that triggers a VM exit event (access to LDTR / TR VMExit); page table EPT exception that triggers a VM exit event (EPT violation VM Exit); page table EPT configuration exception that triggers a VM exit event (EPT misconfiguration VM Exit); ... etc. In one implementation, when accessing memory, a page table EPT configuration exception (EPT misconfiguration VM Exit) caused by a page table format error requires instruction simulation and occurs frequently, and the flag position is set to 1.
[0042] If the executed trigger instruction is at the relevant position 1 of the virtual instruction control table 202 (i.e., it will be the simulation target), the hardware of the present application will record the complete instruction content of the trigger instruction in the second field of the virtual machine control data structure 200 for direct access by the subsequent instruction simulation. The second field stores the guest instruction contents 204. Bit [0] is used as a valid bit; bits [7:1] are reserved bits; and bits [127:8] provide a full 15 bytes (maximum instruction size) as instruction bytes to fully pre-fetch the instruction content of the trigger instruction.
[0043] Figure 3 The diagram illustrates the operation of a virtual machine (VM) implemented according to an embodiment of the present application. In addition to a physical machine 302, a computer system 300 also includes a virtual machine 304 simulated by a processor in software. When the virtual machine 304 executes a trigger instruction 306 to switch back to the physical machine 302 to perform a virtual machine exit event 308, the virtualization hardware accelerator 310 implemented in hardware by the processor of the present application acts accordingly.
[0044] The virtualization hardware accelerator 310 includes a reference to the virtual instruction control table 202 on the virtual machine control data structure (VMCS) 200. If the trigger instruction 306 is at position 1 on the virtual instruction control table 202, it means that the trigger instruction 306 is a simulation target. The virtualization hardware accelerator 310 writes the instruction content of the trigger instruction from the virtual machine memory 324 into the virtual machine control data structure 200 to form the bit [127:8] of the virtual instruction content 204, and sets the valid bit [0] of the virtual instruction content 204 to 1. In one embodiment, the virtualization hardware accelerator 310 writes the instruction content completely into the instruction bytes [127:8] of the virtual instruction content 204 at one time (no need to fill up 15 bytes) depending on the instruction length. Therefore, multiple address translations (GVA→GPA→HVA) only occur once, and the instruction content copy (from user mode to kernel mode) also occurs in one go, which is quite fast.
[0045] In response to the virtual machine exit event 308, a virtual machine monitor (hypervisor) 312 is run on the physical machine 302, which is a software design. The virtual machine monitor 312 determines whether it is necessary to simulate the trigger instruction 306 in step 314. If not, the physical machine 302 performs other processing procedures for the virtual machine exit event in step 316. On the contrary, if there is a need for instruction simulation, the physical machine 302 performs the instruction simulation process 318.
[0046] The instruction simulation process 318 first determines the valid bit [0] of the virtual instruction content 204 of the virtual machine control data structure (VMSC) 200 in step 320. If it is not set to 1, the process performs instruction fetching in step 322 and reads the instruction content from the virtual machine memory 324. Then, step 326 performs instruction decoding, parses the instruction content, and determines whether a complete instruction has been obtained. If it is not a complete instruction, the process repeats step 322 and continues to fetch instructions from the virtual machine memory 324 until the complete instruction content is obtained, and then performs step 328 to perform instruction simulation.
[0047] If step 320 determines that the valid bit [0] of the virtual instruction content 204 is set to 1, the process proceeds to step 330 to perform instruction fetching, and reads out the complete 15 bytes (the maximum size allowed for the instruction) at one time from the instruction bytes [127:8] of the virtual instruction content 204. Next, step 332 performs instruction decoding, and parses out the complete instruction content from the complete 15 bytes of data read at one time, and hands it over to step 334 for instruction simulation.
[0048] In particular, step 330 is to fetch instructions from the virtual machine control data structure 200, using the physical machine virtual address (HVA), which can be fetched once, unlike step 322 which repeatedly reads the virtual machine memory 324. Compared with the multiple address translations (GVA→GPA→HVA) and instruction content copying (from user state to kernel state) involved in each instruction fetch in step 322, the instruction fetch in step 330 does not require multiple address translations (GVA→GPA→HVA) and instruction content copying (from user state to kernel state). The computer system 300 is significantly accelerated.
[0049] After sorting out, compared with the traditional technology, one implementation of the present application makes a special design in the hardware; during the process of the hardware exiting the virtual machine, the instruction content can be cached in the virtual machine control data structure (VMCS) 200, thereby accelerating the speed of the virtual machine monitor 312 to perform instruction simulation. In particular, the present application also provides a control interface for the software to flexibly arrange the virtual instruction control table 202 and determine which types of trigger instruction content to cache in the virtual machine control data structure 200 (stored in the virtual instruction content 204).
[0050] Figure 4 According to one embodiment of the present application, a computer system 400 is illustrated, including a processor 402 and a memory 404 coupled to the processor 402. The memory 404 is configured with the aforementioned virtual machine memory 324 and the aforementioned virtual machine control data structure (VMCS) 200. In addition to running the virtual machine 304 in addition to the physical machine 302, the processor 402 software 406 also implements the aforementioned virtual machine monitor 312 and a control interface for writing the virtual instruction control table 202. The processor 402 hardware 408 is designed with the aforementioned virtualization hardware accelerator 310. The virtualization hardware accelerator 310 determines whether to pre-store instruction content in writing the virtual machine control data structure (VMCS) 200 based on the virtual instruction control table 202. The virtual machine monitor 312 is used to determine whether to obtain instruction content from the virtual machine memory 324 or the virtual machine control data structure (VMCS) 200.
[0051] The technology can be further used to implement a processor acceleration method. The processor acceleration method operates a physical machine 302 and a virtual machine 304, and includes: when the virtual machine 304 executes a target trigger instruction, the instruction content of the target trigger instruction is completely pre-stored from the virtual machine memory 324 to the virtual machine control data structure (VMCS) 200, wherein the target trigger instruction triggers a virtual machine exit event and waits for the physical machine 302 to simulate; and the virtual machine monitor 312 running in software on the physical machine 302 obtains the instruction content of the target trigger instruction from the virtual machine control data structure 200, performs instruction decoding (332) and instruction simulation (334) of the target trigger instruction.
[0052] Any technology that pre-stores instruction content in a virtual machine control data structure (VMCS) so that instruction simulation is to fetch instructions from the virtual machine control data structure (VMCS) instead of from the virtual machine memory is related to the spirit of this application.
[0053] Although the preferred embodiments of the present invention are disclosed above, they are not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.
Claims
1. A processor that operates a physical machine and a virtual machine, comprising: The virtualized hardware accelerator, when the virtual machine executes the target trigger instruction, completely pre-stores the instruction content of the target trigger instruction from the virtual machine memory to the virtual machine control data structure, wherein the target trigger instruction triggers the virtual machine exit event and waits for the physical machine simulation; The virtual machine monitor running on the physical machine in software obtains the instruction content of the target trigger instruction from the virtual machine control data structure, and performs instruction decoding and instruction simulation of the target trigger instruction.
2. The processor of claim 1, wherein: The virtual machine monitor reads the virtual machine control data structure with the physical machine end virtual address without address conversion between the physical machine and the virtual machine, and obtains the instruction content of the target trigger instruction.
3. The processor of claim 2, wherein: The virtual machine monitor obtains the instruction content of the target trigger instruction from the virtual machine control data structure without copying the data from the user state to the kernel state.
4. The processor of claim 3, wherein: The virtual machine monitor obtains the instruction content of the target trigger instruction from the virtual machine control data structure at one time.
5. The processor as claimed in claim 1 further provides a control interface by software, edits a virtual instruction control table in the virtual machine control data structure, and marks whether multiple trigger instructions that cause the virtual machine exit event belong to the target trigger instruction.
6. The processor of claim 5, wherein: In response to the virtual machine executing the trigger instruction, the virtualized hardware accelerator queries the virtual instruction control table on the virtual machine control data structure to determine whether the trigger instruction belongs to the target trigger instruction.
7. The processor of claim 6, wherein: In response to the target trigger instruction, the virtualized hardware accelerator completely pre-stores the instruction content of the target trigger instruction in the instruction bytes of the virtual instruction content of the virtual machine control data structure, and sets a valid position of the virtual instruction content to 1; and In response to the valid bit being set to 1, the virtual machine monitor obtains the instruction content of the target trigger instruction from the instruction byte of the virtual instruction content, and performs instruction decoding and instruction simulation of the target trigger instruction.
8. The processor of claim 7, wherein: In the virtual machine control data structure, the virtual instruction content provides instruction bytes of a maximum instruction size.
9. The processor of claim 7, wherein: The trigger instruction does not belong to the target trigger instruction, but when the physical machine is simulated, the corresponding valid bit is not set to 1, and the virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory, performs instruction decoding and instruction simulation of the trigger instruction.
10. The processor of claim 9, wherein: The virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory using the physical machine end virtual address after performing address conversion between the physical machine and the virtual machine; and The virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory by copying data from the user state to the kernel state; and The virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory in segments according to preset units.
11. A processor acceleration method, operating a physical machine and a virtual machine, comprising: When the virtual machine executes the target trigger instruction, the instruction content of the target trigger instruction is completely pre-stored in the virtual machine control data structure from the virtual machine memory, wherein the target trigger instruction triggers the virtual machine exit event and waits for the physical machine simulation; and The virtual machine monitor running in software on the physical machine obtains the instruction content of the target trigger instruction from the virtual machine control data structure, and performs instruction decoding and instruction simulation of the target trigger instruction.
12. The processor acceleration method according to claim 11, wherein: The virtual machine monitor reads the virtual machine control data structure with the physical machine end virtual address without address conversion between the physical machine and the virtual machine, and obtains the instruction content of the target trigger instruction.
13. The processor acceleration method according to claim 12, wherein: The virtual machine monitor obtains the instruction content of the target trigger instruction from the virtual machine control data structure without copying the data from the user state to the kernel state.
14. The processor acceleration method according to claim 13, wherein: The virtual machine monitor obtains the instruction content of the target trigger instruction from the virtual machine control data structure at one time.
15. The processor acceleration method according to claim 11, further comprising: A control interface is provided by software, and a virtual instruction control table is edited in the virtual machine control data structure to mark whether the multiple trigger instructions that cause the virtual machine exit event belong to the target trigger instruction.
16. The processor acceleration method according to claim 15, further comprising: In response to the virtual machine executing the trigger instruction, the virtual instruction control table on the virtual machine control data structure is queried to determine whether the trigger instruction belongs to the target trigger instruction.
17. The processor acceleration method according to claim 16, wherein: The instruction content of the target trigger instruction is the instruction byte of the virtual instruction content completely pre-stored in the virtual machine control data structure, and a valid position of the virtual instruction content is 1; and In response to the valid bit being set to 1, the virtual machine monitor obtains the instruction content of the target trigger instruction from the instruction byte of the virtual instruction content, and performs instruction decoding and instruction simulation of the target trigger instruction.
18. The processor acceleration method according to claim 17, wherein: In the virtual machine control data structure, the virtual instruction content provides instruction bytes of a maximum instruction size.
19. The processor acceleration method according to claim 17, wherein: The trigger instruction does not belong to the target trigger instruction, but when the physical machine is simulated, the corresponding valid bit is not set to 1, and the virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory, performs instruction decoding and instruction simulation of the trigger instruction.
20. The processor acceleration method according to claim 19, wherein: The virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory using the physical machine end virtual address after performing address conversion between the physical machine and the virtual machine; and The virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory by copying data from the user state to the kernel state; and The virtual machine monitor obtains the instruction content of the trigger instruction from the virtual machine memory in segments according to preset units.