Instruction prefix encoding for cryptographically capable computation data types

Abstract

The present application discloses instruction prefix encoding for cryptographic capability computing data types. Techniques for instruction prefix encoding for cryptographic capability computing data types are described. In an embodiment, an apparatus includes: an instruction decoder for decoding a first instruction including a first prefix; and cryptographic circuitry for performing a cryptographic operation on data, the cryptographic operation being based at least in part on the first prefix and a relative enumeration in a pointer to the data.

Description

[0001] Statement Regarding Federal Funding of Research and Development

[0002] This invention was made with government support under Agreement No. N66001-23-9-4004 awarded by the Naval Information Warfare Center Pacific and funded by the Defense Advanced Research Projects Agency. The government has certain rights in this invention. Technical Field

[0003] The present disclosure relates to instruction prefix encoding for cryptographically capable computational data types. Background Art

[0004] Computers and other information processing systems may store confidential, private, and secret information in their memory. Software may have vulnerabilities that can be exploited to steal this information. Hardware may also have vulnerabilities that can be exploited and / or an adversary may physically modify the system to steal information. Therefore, memory safety and security are important issues in computer system architecture and design. Summary of the invention

[0005] According to a first aspect of the present disclosure, a processor device for instruction prefix encoding is provided, comprising: an instruction decoder for decoding a first instruction including a first prefix; and a cryptographic circuit system for performing a cryptographic operation on data, the cryptographic operation being based at least in part on a relative enumeration in the first prefix and a pointer to the data.

[0006] According to a second aspect of the present disclosure, a method for instruction prefix encoding is provided, comprising: decoding a first instruction including a first prefix by an instruction decoder of a processing device; and performing a cryptographic operation on data by a cryptographic circuit system of the processing device, the cryptographic operation being based at least in part on a relative enumeration in the first prefix and a pointer to the data.

[0007] According to a third aspect of the present disclosure, a non-temporary machine-readable medium is provided, storing at least a single instruction, which, when executed by a machine, causes the machine to perform a method for instruction prefix encoding, the method comprising: decoding a first instruction including a first prefix by an instruction decoder of a processing device; and performing a cryptographic operation on data by a cryptographic circuit system of the processing device, the cryptographic operation being based at least in part on a relative enumeration in a pointer to the data and the first prefix. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various examples according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0009] Figure 1A computing system for instruction prefix encoding according to an embodiment is illustrated.

[0010] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F A method for instruction prefix encoding according to an embodiment is illustrated.

[0011] Figure 3 An encryption / decryption example that may include location-dependent pointers according to an embodiment is illustrated.

[0012] Figure 4 An example computing system is illustrated.

[0013] Figure 5 Illustrated is a block diagram of an example processor and / or system on a chip (SoC) that may have one or more cores and an integrated memory controller.

[0014] Fig. 6A is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example.

[0015] Figure 6B is a block diagram illustrating an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0016] Figure 7 Examples of execution unit(s) circuitry are illustrated.

[0017] Figure 8 is a block diagram illustrating converting binary instructions in a source instruction set architecture to binary instructions in a target instruction set architecture using a software instruction converter according to an example. DETAILED DESCRIPTION

[0018] The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for instruction prefix encoding of cryptographic capability computing data types. According to some examples, an apparatus includes: an instruction decoder to decode a first instruction including a first prefix; and cryptographic circuitry to perform a cryptographic operation on data, the cryptographic operation being based at least in part on a relative enumeration in a pointer to data accessed by the first instruction.

[0019] As mentioned in the Background section, memory safety and security are important issues in computer system architecture and design.

[0020] Examples of computer memory security violations include overflowing a buffer to cause adjacent memory locations to be overwritten, reading past the end of a buffer, and creating a dangling pointer that does not resolve to a valid destination (e.g., a use after free). Some methods of protecting memory from attacks such as these include marking data with metadata to encode information about ownership, memory size, location, type, version, etc. However, particularly for implementations with fine-grained marking, these methods may require additional storage and / or instructions and may have a negative impact on performance. Embodiments according to the present specification may provide methods that use less storage (e.g., no or less metadata) and / or have less impact on performance, even for protecting data at a fine granularity. Additionally, the use of cryptography protects against physical and hardware adversaries, such as the use of interposers on the memory bus or hardware Trojan horses.

[0021] For example, embodiments may use fine-grained cryptography to isolate objects and their individual member variables. In embodiments, the encryption of variables may be associated with an instruction prefix enumeration of the object instance and the members of the object (e.g., each member). By uniquely encrypting an object and its member variables, protection may be maintained even in the presence of vulnerabilities (such as access overflowing from one variable to another variable).

[0022] As may be described and / or illustrated by the examples below and / or in the accompanying drawings, embodiments may use instruction prefix enumeration and cryptographic addressing for individual members of an object. For example, based on the instruction prefix and memory address, cryptographic tweaks for each object instance and each object member variable may be used to provide cryptographic distinction between objects and members within the objects without requiring additional instructions, tags, or isolated memory for metadata.

[0023] Descriptions of embodiments based on instruction prefix enumeration, relative enumeration in pointers, cryptographic capability calculation (C3), etc. are provided as examples. Embodiments may include and / or relate to other memory security techniques.

[0024] Figure 1 An apparatus (eg, a computing system) 100 for instruction prefix encoding according to an embodiment is illustrated. The apparatus 100 may correspond to a computer system such as Figure 4 A multiprocessor system 400 in FIG.

[0025] The device 100 Figure 1 1 is shown as including a processor 110 and a memory 150, each of which may represent any number of corresponding components (eg, multiple processors and / or processor cores, multiple dynamic random access memories (DRAMs), etc.).

[0026] For example, processor 110 may represent all or part of one or more hardware components, including one or more processors, processor cores, or execution cores integrated on a single substrate or packaged in a single package, each of which may include multiple execution threads and / or multiple execution cores in any combination. Each processor represented as or in processor 110 may be any type of processor, including a general-purpose microprocessor such as a processor such as a processor 110 or processor 110. Processor series or from The processor 110 may be a processor from another processor family of Intel or another company, a special purpose processor or a microcontroller, or any other device or component in an information processing system in which an embodiment may be implemented. The processor 110 may be architected and designed to operate according to any instruction set architecture (ISA), whether or not controlled by microcode. For convenience and / or example, some features (e.g., instructions, etc.) may be referred to by names associated with a specific processor architecture (e.g., 64 and / or IA32), but the embodiments are not limited to these features, names, architectures, etc.

[0027] Processor 110 may be implemented in circuitry, gates, logic, structures, hardware, etc., all or part of which may be included in discrete components and / or integrated into the circuitry of a processing device or any other apparatus in a computer or other information processing system. For example, Figure 1 The processor 110 in may correspond to and / or be implemented / included in any of the following: Figure 4 The processor 470, 480 or 415, Figure 5 processor 500 or one of cores 502A to 502N in the embodiment of the present invention, and / or Figure 6B The core 690 in, each of which is described below.

[0028] Memory 150 may represent one or more DRAMs and / or other memory components that provide system memory or other memory or storage in or for device 100. Memory 150 may include one or more memory objects 152. Any such memory object may represent an object, region, structure, segment, stack frame, etc. in memory in addition to associated program code or instructions, and the use of instruction prefix encodings according to embodiments may be associated with such memory objects, and such memory objects may be referred to as objects for convenience.

[0029] As shown, processor 110 includes instruction unit 120, execution unit 140, and secure memory access unit 130 (which may be included in execution unit 140). Processor 110 may include any number of each of these elements (e.g., multiple execution units) and / or Figure 1 Any other elements not shown.

[0030] The instruction unit 120 may correspond to Figure 6B The front end unit 630 in and / or is implemented / included in the front end unit 630, as described below, and / or may include any circuit system, gate, logic, structure, hardware, etc., such as an instruction decoder, to extract, receive, decode, interpret, schedule and / or process instructions to be executed by the processor 110, such as data movement instructions (e.g., mov, add, sub, etc.) 122, address calculation instructions (e.g., load effective address or lea) 124, etc. Figure 1 , instructions that may be decoded or otherwise processed by instruction unit 120 are represented as blocks with dashed boundaries because the instructions themselves are not hardware, but instruction unit 120 may include hardware or logic capable of decoding or otherwise processing these instructions.

[0031] Any instruction format may be used in embodiments; for example, an instruction may include an opcode and one or more operands, where the opcode may be decoded into one or more microinstructions or micro-operations for execution by the execution unit 140. The operands or other parameters may be associated with the instruction implicitly, directly, indirectly, or according to any other method. Prefixes may be added to instructions to modify instruction behavior, and the prefix may also include additional prefix data. Prefixes have the additional benefit that some prefix values ​​may be ignored by existing processors, so that binaries compiled using instructions of a new prefix function constructed for a new processor will also be compatible with existing processors, thereby being effectively ignored by existing processors.

[0032] The execution unit 140 may correspond to and / or be implemented / included in any of the following: Figure 6B The execution engine 650 and / or Figure 6B and Figure 7 , each of which is described below, and / or execution unit 140 includes any circuitry, gates, logic, structures, hardware, etc., such as an arithmetic unit, a logic unit, a floating point unit, a shifter, a load / store unit, etc., to process data and execute instructions (including Figure 1 Execution unit 140 may represent any one or more physically or logically distinct execution units.

[0033] The secure memory access unit 130 may represent and / or include any circuit system, gate, logic, structure, hardware, etc., such as a cryptographic unit, an arithmetic unit, a logic unit, a load / store unit, etc., to control, execute, participate in the encryption, decryption, encoding, decoding, etc. of the objects and their members described in this specification. The secure memory access unit 130 may include a cryptographic unit 132, which may represent and / or include any circuit system, gate, logic, structure, hardware, etc., such as to control, execute, participate in the encryption, decryption, encoding, decoding, etc. of the objects and their members described in this specification.

[0034] The secure memory access unit may decrypt the partially encrypted pointer in conjunction with the processor's address generation unit before converting the generated linear / virtual address to a physical address. The secure memory access unit may use the encrypted pointer as a fine-tuning or keystream generator to be used in combination with a secret key to encrypt data stored to memory / cache or decrypt data loaded from memory / cache. The secure memory access unit may also create an integrity check value associated with the encrypted data on storage and verify the integrity check value against the encrypted data when loaded from memory / cache.

[0035] Despite Figure 1 Although shown as separate units, in various embodiments, the secure memory access unit 130 and / or the cryptographic unit 132 may be partially or wholly integrated or included into another unit of the processor 110, such as the instruction unit 120 and / or the execution unit 140.

[0036] For example, embodiments may provide cryptographic protection of individual member variables, data elements, etc. (any of which may be referred to as members) of objects, data structures, etc. (any of which may be referred to as objects) using a combination of instruction prefix enumerations and relative enumeration fields in pointers to provide fine-tuning of encryption of members. In embodiments, relative enumeration fields in pointers may be combined with version fields, location fields, etc. in pointers to provide fine-tuning encryption for individual instances of encrypted objects. In embodiments, encryption of members may be separated from encryption of object instances to allow operation of unstructured memory copies (e.g., memcpy) and other general-purpose functions that are unaware of the internal composition of individual memory allocations / objects.

[0037] The embodiments may be described by way of example using the following sample of C source code and its corresponding x86 assembly code:

[0038] C code:

[0039]

[0040]

[0041]

[0042] Embodiments may include and / or be implemented according to two concepts. The first concept is to flatten structures and enumeration variables, such as Figure 2A The second concept is to provide a relative enumeration field in a pointer (e.g., linear / virtual address), such as Figure 2B As shown in the example.

[0043] The prefix enumeration of the individual instructions can then be added to the relative enumeration in the pointer to generate values ​​to fine-tune the encryption of the member, e.g. Figure 2C As shown in the example.

[0044] refer to Figure 2C , the compiler adds an enumeration prefix to the named SStrings structure so that there is a direct association between the instruction and the data members of the composite structure. The prefix is ​​then added as a tweak for data encryption of the storage device or decryption of the load instruction associated with the respective memory data access. In this case, the instruction operates on the first byte of each string in the string, where the first mov sets the first byte of the first string to the value 0 using the first prefix value as the tweak, and the second mov sets the first byte value of the second string to the value 0 using the second prefix value as the tweak. Since the prefix value of each mov instruction is different, the resulting 0 is encrypted using a different tweak, resulting in different ciphertext. Since the tweaks between the two string members are different, an overflow from one member to another will result in different ciphertext, thereby preventing leakage and preventing a write adversary from having deterministic control over adjacent members and / or non-adjacent members of the same data structure / object and / or across different instance data structures / objects.

[0045] Reference now Figure 2DThe pointer relative enumeration manipulation example shown, in order to allow manipulation of substructures across functions and specialized libraries that operate on more primitive data types, the pointer's relative enumeration field allows the compiler to specify a relative offset using a prefix on the LEA instruction. Thus, the LEA operation provides an address to the associated substructure with the correct relative enumeration. For example, LEA can add the prefix value to the input memory address relative enumeration field in the input register to produce a correctly formatted / encoded / encrypted address with the updated enumeration in the output register. The first LEA instruction with a prefix value of 0 operates on the address of the first nested SString structure in the SStrings structure, while the second LEA instruction with a prefix value of 2 operates on the address of the second nested SString structure in the SStrings structure. The first LEA instruction with a prefix value of 0 does not increment the relative enumeration field of the address because the first SString is at the beginning of the nested SStrings structure. The second LEA instruction with a prefix value of 2 adds 2 to the relative enumeration field of the address because the second SString structure is two move enumerations away from the first SString structure in the nested SStrings structure.

[0046] Then, refer to Figure 2E In the example shown, an access function can use a relative enumeration pointer field with an instruction prefix that is designed for a function that only understands substructures of primitive data types of nested structures or objects by adding the relative enumeration to the enumeration specified by the compiler in the instruction prefix. For example, the SStringCompare function understands the more primitive SString data type, not the composite SStrings data type. However, the source address and destination address passed into the function have the correct relative enumeration for each SString substructure nested within the SStrings data structure. The prefix value added to the mov instruction is then used to correctly access the byte array members of the SString structure. The prefix of the first mov instruction is added to the relative enumeration field of the address to produce the correct enumeration of the first SString byte array member with a value of 1, so the processor will decrypt the value of the first byte array with the correct fine tuning. The second move of the destination byte array of the destination SString structure will add a prefix value of 1 to the relative enumeration field of the destination address, thereby producing the correct enumeration value of 3 for the second byte array member of the SStrings data structure. The processor will use this value 3 as the fine tuning for data encryption of the destination byte array.

[0047] Some embodiments may isolate individual array elements. For example, a different relative enumeration value or prefix value may be used to address each array element. This may also be applied in a nested manner. For example, in an array of structures where each structure contains three fields, a relative enumeration or prefix value of 3 may be added each time a pointer needs to advance to the next structure entry in the array. For example, if one or more fields in a structure are themselves arrays or nested structures, additional enumeration or prefix value offsets may be added for those fields.

[0048] Figure 2F A method 200 for instruction prefix encoding according to an embodiment is illustrated. The method 200 may be implemented by, for example, Figure 1 The method 200 may be performed in accordance with and / or in relation to the operation of a device such as device 100, and / or in relation to the compilation of code to be executed by a device such as device 100; therefore, all or any part of the foregoing description of device 100 may apply to method 200.

[0049] At 210, one or more structures are flattened structures, and one or more variables of the structure(s) are enumerated, such as by a compiler, such as Figure 2A In 220, a relative enumeration field is provided in a pointer (eg, a linear address), such as Figure 2B As shown in the example.

[0050] At 230, the prefix enumeration of the respective instructions is added to the relative enumeration in the pointer, for example by a compiler, such as Figure 2C As shown in the example in , to generate an encryption fine-tuning value. In 232, the generated value is used to fine-tune the encryption of the member.

[0051] At 240, a relative offset may be specified using a relative enumeration field of a pointer, such as by a compiler using a prefix on a LEA instruction, such as Figure 2D As shown in the example of . At 242, (one or more) LEA operations calculate and / or provide addresses to associated substructures with correct relative enumeration.

[0052] In 250, the access function uses a relative enumeration pointer field with an instruction prefix, such as Figure 2E As shown in the example.

[0053] In a processor pipeline, a data object can be encrypted based on a version field (or position) to provide instance-specific cryptographic distinction, and then the enumeration is used again to provide cryptographic distinction of individual member variables of the data. Thus, a function (such as memcpy) can use the version field as a fine-tuning to decrypt the source instance, and re-encrypt the same object using a different version in the destination instance without knowing the enumeration of the individual members of the data object.

[0054] Pointers may also be partially encrypted or authenticated first using relative enumeration and then again using version / position to prevent pointer forgery and deterministic manipulation of fields by an adversary. Encrypting the fields will prevent an adversary from deterministically predicting the value. In an embodiment, fields may be combined with pointer authentication to provide further protection.

[0055] The detailed encoding of the prefix can take various forms. For example, existing prefix bytes (such as prefix bytes used to override fragment selection or repeat data access) can be redefined to number fields and array elements. However, few existing prefix bytes can be used to redefine in this way. Larger field or array element numbers can be specified using larger prefix encodings, such as REX, REX2, VEX, EVEX, and extended EVEX. Fields within such prefix encodings can be redefined, although this may interfere with previous uses of these fields, such as addressing extended register files. To avoid interfering with previous uses of these fields, (one or more) additional bytes can be appended to these extended prefixes to accommodate the numbering of fields and array elements.

[0056] Figure 3 An example of encryption / decryption that may include location-dependent pointers is shown. Figure 3 In the embodiment, the encoding pointer 310 is provided to the address cryptographic unit 302, which generates a data / code trim 317 and a decoded linear address 312 based on the encoding pointer 310. The data / code key 316 and the data / code trim 317 are provided to the block cipher 372 in the cryptographic computing engine 370 to generate a key stream 376 for a logic function 374 in the cryptographic computing engine 370, thereby generating a decrypted data / code 322 by decrypting the encrypted data / code 324.

[0057] In an embodiment, the cryptographic computation engine may also provide diffusion data using a block cipher directly on the data, or a combination of a block cipher that uses an enumerated value as a fine-tuning value to diffuse the data and a stream cipher that uses a version / position and a secret key stored in a processor register to encrypt the data.

[0058] In an embodiment, a cryptographic computation engine such as Advanced Encryption Standard (AES) Galois Counter Mode (GCM) or Ascon may provide authenticated encryption, allowing integrity values ​​to be stored with data particles (e.g., a message authentication code or MAC). Using the integrity data, corruption may be detected, as well as fine-tuning the use of an incorrect key when attempting to access the data. Pointer encryption may use a k-cipher or a fine-tunable bipbip cipher or similar, or a pointer authentication code may be used to encrypt or authenticate data using a secret key stored in a processor register.

[0059] In an embodiment, data (and / or pointer) encryption keys may be configured in registers accessible to privileged software and may be switched when a process, virtual machine, kernel, or the like is switched.

[0060] Techniques according to embodiments may also be used for memory tagging, for example a pointer tag may provide a relative enumeration, and an instruction prefix may be added to the relative enumeration, and the resulting value may be compared to a memory tag stored for a memory granule (e.g., 8 or 16 bytes).

[0061] Example Apparatus, Methods, etc.

[0062] According to some examples, an apparatus (e.g., a processing device) includes: an instruction decoder for decoding a first instruction including a first prefix; and a cryptographic circuit system for performing a cryptographic operation on data, the cryptographic operation being based at least in part on the first prefix and a relative enumeration in a pointer to the data.

[0063] According to some examples, a method includes: decoding, by an instruction decoder of a processing device, a first instruction including a first prefix; and performing, by a cryptographic circuit system of the processing device, a cryptographic operation on data, the cryptographic operation being based at least in part on a relative enumeration in a pointer to the data and the first prefix.

[0064] Any such example may include any one or any combination of the following aspects. The instruction decoder may also be used to decode a second instruction, the second instruction including a second prefix based on the relative enumeration in the pointer. The method may also include: decoding the second instruction by the instruction decoder, the second instruction including a second prefix based on the relative enumeration in the pointer. The data may correspond to a member of the object. The first prefix may be associated with the member. The second prefix may be associated with the object. The cryptographic operation may be based at least on a fine-tuning derived from the first prefix and the relative enumeration. The fine-tuning may be derived from the sum of the first prefix and the relative enumeration. The processor device may also include an execution circuit system for performing one or more operations corresponding to the first instruction, the one or more operations including moving data. The method may also include: performing, by the execution circuit system of the processing device, one or more operations corresponding to the first instruction, the one or more operations including moving data. The processor device may also include an execution circuit system for performing one or more operations corresponding to the second instruction, the one or more operations including calculating an effective address of the data based at least in part on the pointer. The method may also include: performing, by the execution circuit system of the processing device, one or more operations corresponding to the second instruction, the one or more operations including calculating an effective address of the data based at least in part on the pointer.

[0065] According to some examples, an apparatus may include a module for performing any function disclosed herein; an apparatus may include a data storage device storing code that, when executed by a hardware processor or controller, causes the hardware processor or controller to perform any method or part of a method disclosed herein; the apparatus, method, system, etc. may be as described in the detailed description; a non-transitory machine-readable medium may store instructions that, when executed by a machine, causes the machine to perform any method or part of a method disclosed herein. Embodiments may include any details, features, etc., or combinations of details, features, etc., described in this specification.

[0066] Example Computer Architecture

[0067] The description of the example computer architecture is described in detail below. Other system designs and configurations known in the art for the following are also suitable: laptop computers, desktop computers and handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, decomposition servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable media players, handheld devices and various other electronic devices. Generally, various systems or electronic devices that can incorporate processors and / or other execution logic disclosed herein are generally suitable.

[0068] Figure 4 An example computing system is illustrated. Multiprocessor system 400 is an interface system and includes multiple processors or cores including a first processor 470 and a second processor 480 coupled via an interface 450 (such as a point-to-point (PP) interconnect, structure and / or bus). In some examples, first processor 470 and second processor 480 are homogeneous. In some examples, first processor 470 and second processor 480 are heterogeneous. Although example system 400 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is a system on chip (SoC).

[0069] Processors 470 and 480 are shown as including integrated memory controller (IMC) circuitry 472 and 482, respectively. Processor 470 also includes interface circuits 476 and 478; similarly, second processor 480 includes interface circuits 486 and 488. Processors 470, 480 may exchange information via interface 450 using interface circuits 478, 488. IMCs 472 and 482 couple processors 470, 480 to respective memories, namely memory 432 and memory 434, which may be portions of main memory locally attached to the respective processors.

[0070] Processors 470, 480 may each exchange information with a network interface (NW I / F) 490 via respective interfaces 452, 454 using interface circuits 476, 494, 486, 498. Network interface 490 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples a chipset) may optionally exchange information with a coprocessor 438 via interface circuit 492. In some examples, coprocessor 438 is a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural network processing unit (NPU), an embedded processor, and the like.

[0071] A shared cache (not shown) may be included in either of processors 470, 480, or may be included external to both processors but connected to the processors via an interface such as a PP interconnect, such that if the processors are in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0072] The network interface 490 may be coupled to the first interface 416 via the interface circuit 496. In some examples, the first interface 416 may be an interface such as a peripheral component interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, the first interface 416 is coupled to a power control unit (PCU) 417, which may include circuitry, software, and / or firmware for performing power management operations for the processors 470, 480, and / or the coprocessor 438. The PCU 417 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 417 also provides control information to control the generated operating voltage. In various examples, the PCU 417 may include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be completely controlled by the processor (e.g., controlled by various processor hardware and may be triggered by workload and / or power, thermal, or other processor constraints) and / or may be performed in response to an external source (such as a platform or power management source or system software).

[0073] PCU 417 is illustrated as existing as logic separate from processor 470 and / or processor 480. In other cases, PCU 417 may execute on a given core or cores (not shown) of processor 470 or 480. In some cases, PCU 417 may be implemented as a microcontroller (dedicated or general purpose) or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other examples, the power management operations to be performed by PCU 417 may be implemented external to the processor, such as by a separate power management integrated circuit (PMIC) or another component external to the processor. In still other examples, the power management operations to be performed by PCU 417 may be implemented within BIOS or other system software.

[0074] Various I / O devices 414 may be coupled to the first interface 416 along with a bus bridge 418 that couples the first interface 416 to the second interface 420. In some examples, one or more additional processors 415 (e.g., a coprocessor, a high throughput multi-integrated core (MIC) processor, a GPGPU, an accelerator (e.g., a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interface 416. In some examples, the second interface 420 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 420, including, for example, a keyboard and / or mouse 422, a communication device 427, and a storage circuit system 428. The storage circuit system 428 may be one or more non-transitory machine-readable storage media described below, such as a disk drive or other mass storage device that may include instructions / code and data 430. In addition, an audio I / O 424 may be coupled to the second interface 420. Note that other architectures besides the point-to-point architecture described above are also possible. For example, instead of a point-to-point architecture, a system such as multiprocessor system 400 may implement a multi-point interface or other such architecture.

[0075] Example core architectures, processors, and computer architectures

[0076] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU, on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or as a dedicated core); and 4) a system on a chip, which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality on the same die. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0077] Figure 5 A block diagram of an example processor and / or SoC 500 that may have one or more cores and an integrated memory controller is illustrated. The solid lined box illustrates the processor 500 having a single core 502(A), a system agent unit circuitry 510, and a set of one or more interface controller unit circuitry 516, while the optional addition of the dashed lined box illustrates an alternative processor 500 having multiple cores 502(A) through 502(N), a set of one or more integrated memory controller unit circuitry 514 and dedicated logic 508 in the system agent unit circuitry 510, and a set of one or more interface controller unit circuitry 516. Note that the processor 500 may be Figure 4 One of the processors 470 or 480 or the coprocessors 438 or 415.

[0078] Thus, different implementations of processor 500 may include: 1) dedicated logic 508 is a CPU with integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown) and cores 502(A) to 502(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of both); 2) cores 502(A) to 502(N) are coprocessors of a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) cores 502(A) to 502(N) are coprocessors of a large number of general purpose in-order cores. Thus, processor 500 may be a general purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput multi-integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 500 may be part of and / or may be implemented on one or more substrates using any of a variety of process technologies, such as, for example, complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0079] The memory hierarchy includes one or more levels of cache unit circuitry 504(A) to 504(N) within the cores 502(A) to 502(N), a set of one or more shared cache unit circuitry 506, and external memory (not shown) coupled to a set of (one or more) integrated memory controller unit circuitry 514. The set of one or more shared cache unit circuitry 506 may include one or more mid-level caches (such as level 2 (L2), level 3 (L3), level 4 (L4)) or other levels of cache (such as last level cache (LLC)) and / or combinations thereof. While in some examples, an interface network circuitry 512 (e.g., a ring interconnect) interfaces with dedicated logic 508 (e.g., integrated graphics logic), a set of (one or more) shared cache unit circuitry 506, and a system agent unit circuitry 510, alternative examples use any number of well-known techniques to interface with such units. In some examples, coherency is maintained between one or more of the (one or more) shared cache unit circuitry 506 and the cores 502(A) to 502(N). In some examples, interface controller unit circuitry 516 couples core 502 to one or more other devices 518 , such as one or more I / O devices, storage, one or more communication devices (eg, wireless network, wired network, etc.), and the like.

[0080] In some examples, one or more of the cores 502(A)-502(N) are capable of multithreading. System agent unit circuitry 510 includes those components that coordinate and operate cores 502(A)-502(N). System agent unit circuitry 510 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be or may include logic and components required to regulate the power state of cores 502(A)-502(N) and / or dedicated logic 508 (e.g., integrated graphics logic). Display unit circuitry is used to drive one or more externally connected displays.

[0081] The cores 502(A) to 502(N) may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 502(A) to 502(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 502(A) to 502(N) may be able to execute an ISA, while other cores may only be able to execute a subset of that ISA or another ISA.

[0082] Example core architecture - in-order and out-of-order core block diagram

[0083] Fig. 6A is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example. Figure 6B is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example. Figures 6A to 6B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optional addition of dashed line boxes illustrates the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0084] exist Fig. 6A, the processor pipeline 600 includes a fetch stage 602, an optional length decode stage 604, a decode stage 606, an optional allocation (Alloc) stage 608, an optional rename stage 610, a schedule (also called dispatch or issue) stage 612, an optional register read / memory read stage 614, an execute stage 616, a write back / memory write stage 618, an optional exception handling stage 622, and an optional commit stage 624. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 602, one or more instructions are fetched from the instruction memory, and during the decode stage 606, the fetched one or more instructions may be decoded, an address using a forwarding register port (e.g., a load storage unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In one example, the decode stage 606 and the register read / memory read stage 614 may be combined into one pipeline stage. In one example, during the execute stage 616, decoded instructions may be executed, the LSU address / data pipeline to the advanced microcontroller bus (AMB) interface may be executed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, etc.

[0085] By example, Figure 6B An example register renaming, out-of-order issue / execution architecture core may implement pipeline 600 as follows: 1) instruction fetch circuitry 638 performs fetch stage 602 and length decode stage 604; 2) decode circuitry 640 performs decode stage 606; 3) rename / allocator unit circuitry 652 performs allocate stage 608 and rename stage 610; 4) (one or more) scheduler circuitry 656 performs schedule stage 612; 5) (one or more) physical register file circuitry 658 and memory unit circuitry 670 perform register read / memory read stage 614; (one or more) execution clusters 660 perform execute stage 616; 6) memory unit circuitry 670 and (one or more) physical register file circuitry 658 perform write back / memory write stage 618; 7) various circuitry may be involved in exception handling stage 622; and 8) retirement unit circuitry 654 and (one or more) physical register file circuitry 658 perform commit stage 624.

[0086] Figure 6BThe processor core 690 is shown to include a front end unit circuit system 630 coupled to an execution engine unit circuit system 650, and both the execution engine unit circuit system 650 and the front end unit circuit system 630 are coupled to a memory unit circuit system 670. The core 690 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As a further option, the core 690 can be a special purpose core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0087] The front end unit circuit system 630 may include a branch prediction circuit system 632, which is coupled to an instruction cache circuit system 634, which is coupled to an instruction translation lookaside buffer (TLB) 636, which is coupled to an instruction fetch circuit system 638, which is coupled to a decoding circuit system 640. In one example, the instruction cache circuit system 634 is included in the memory unit circuit system 670 instead of the front end circuit system 630. The decoding circuit system 640 (or decoder) can decode the instruction and generate one or more micro-operations, micro-code entry points, micro-instructions, other instructions or other control signals as outputs, which are decoded from the original instruction, or otherwise reflect the original instruction, or are derived from the original instruction. The decoding circuit system 640 may also include an address generation unit (AGU, not shown) circuit system. In one example, the AGU generates an LSU address using the forwarded register port and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decoding circuit system 640 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one example, the core 690 includes a microcode ROM (not shown) or other medium storing microcode for certain macroinstructions (e.g., in the decoding circuit system 640 or within the front-end circuit system 630). In one example, the decoding circuit system 640 includes a micro-op or operation cache (not shown) to hold / cache decode operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 600. The decoding circuit system 640 may be coupled to the rename / allocator unit circuit system 652 in the execution engine circuit system 650.

[0088] Execution engine circuitry 650 includes rename / allocator unit circuitry 652 coupled to retirement unit circuitry 654 and a set of one or more scheduler circuitry 656. Scheduler circuitry(s) 656 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. In some examples, scheduler circuitry(s) 656 may include arithmetic logic unit (ALU) scheduler / scheduling circuitry, ALU queues, address generation unit (AGU) scheduler / scheduling circuitry, AGU queues, and the like. Scheduler circuitry(s) 656 are coupled to physical register file(s) circuitry 658. Each of the physical register file(s) circuitry 658 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one example, the physical register file(s) circuitry 658 includes a vector register unit circuitry, a write mask register unit circuitry, and a scalar register unit circuitry. These register units may provide architected vector registers, vector mask registers, and general purpose registers, among others. The physical register file(s) circuitry 658 is coupled to a retirement unit circuitry 654 (also referred to as a retirement queue or retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register map and a register pool; etc.). The retirement unit circuitry 654 and the physical register file(s) circuitry 658 are coupled to an execution cluster(s) 660. The execution cluster(s) 660 includes a set of one or more execution unit circuitry 662 and a set of one or more memory access circuitry 664. Execution unit circuitry 662 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some examples may include several execution units or execution unit circuitry dedicated to a specific function or set of functions, other examples may include only one execution unit circuitry or multiple execution units / execution unit circuitry that all perform all functions.Scheduler circuitry(s) 656, physical register file circuitry(s) 658, and execution cluster(s) 660 are shown as potentially multiple because certain examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / compressed integer / compressed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each with its own scheduler circuitry, physical register file circuitry(s), and / or execution clusters—and in the case of separate memory access pipelines, certain embodiments are implemented where only the execution cluster for that pipeline has memory access unit circuitry(s) 664). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest are in-order.

[0089] In some examples, the execution engine unit circuitry 650 may perform a load store unit (LSU) address / data pipeline as well as address level and write back, data level loads, stores, and branches to an advanced microcontroller bus (AMB) interface (not shown).

[0090] A set of memory access circuitry 664 is coupled to memory cell circuitry 670, which includes data TLB circuitry 672, which is coupled to data cache circuitry 674, which is coupled to level 2 (L2) cache circuitry 676. In one example, memory access circuitry 664 may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to data TLB circuitry 672 in memory cell circuitry 670. Instruction cache circuitry 634 is further coupled to level 2 (L2) cache circuitry 676 in memory cell circuitry 670. In one example, instruction cache 634 and data cache 674 are combined into L2 cache circuitry 676, level 3 (L3) cache circuitry (not shown), and / or a single instruction and data cache in main memory (not shown). L2 cache circuitry 676 is coupled to one or more other levels of cache, and ultimately to main memory.

[0091] Core 690 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added with newer versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions, such as NEON)), including the instruction(s) described herein. In one example, core 690 includes logic to support compressed data instruction set architecture extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using compressed data.

[0092] Example Execution Unit(s) Circuitry

[0093] Figure 7 An example of execution unit circuitry, such as Figure 6B Execution unit circuit system 662. As shown, execution unit circuit system 662 may include one or more ALU circuits 701, optional vector / single instruction multiple data (SIMD) circuits 703, load / store circuits 705, branch / jump circuits 707, and / or floating point unit (FPU) circuits 709. ALU circuits 701 perform integer arithmetic and / or Boolean operations. Vector / SIMD circuits 703 perform vector / SIMD operations on compressed data (such as SIMD / vector registers). Load / store circuits 705 execute load and store instructions to load data from memory into registers or store data from registers to memory. Load / store circuits 705 may also generate addresses. Branch / jump circuits 707 cause branches or jumps to memory addresses depending on the instruction. FPU circuits 709 perform floating point arithmetic. The width of execution unit circuit system 662 varies depending on the example, and may range from 16 bits to 1024 bits, for example. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (eg, two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0094] Program code can be applied to input information, to perform functions described herein and generate output information. Output information can be applied to one or more output devices in a known manner. For purposes of this application, processing system includes any system with a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor or any combination thereof.

[0095] The program code can be implemented in a high-level programming language or an object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented in assembly language or machine language. In fact, the mechanism described herein is not limited to any specific programming language in scope. In any case, the language can be a compiled or interpreted language.

[0096] Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation methods. Examples may be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0097] One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium representing various logic within a processor, which, when read by a machine, causes the machine to fabricate logic to perform the techniques described herein. Such representations, referred to as "intellectual property (IP) cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities to be loaded into manufacturing machines that fabricate logic or processors.

[0098] Such machine-readable storage media may include, but are not limited to, a non-transitory tangible arrangement of an article manufactured or formed by a machine or apparatus, including storage media such as a hard disk, any other type of magnetic disk (including floppy disks, optical disks, compact disk-read only memory (CD-ROM), compact disk-rewritable (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM)), random access memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

[0099] Thus, examples also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description languages ​​(HDL), which define structures, circuits, devices, processors and / or system features described herein. Such examples may also be referred to as program products.

[0100] Simulation (including binary conversion, code deformation, etc.)

[0101] In some cases, the instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can convert instructions (e.g., using static binary conversion, including dynamic binary conversion of dynamic compilation), deform, simulate or otherwise convert to one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0102] Figure 8 1 is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source ISA to binary instructions in a target ISA according to an example. In the example shown, the instruction converter is a software instruction converter, although alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Figure 8 A program in a high-level language 802 is shown to be compiled using a first ISA compiler 804 to generate first ISA binary code 806 that can be natively executed by a processor having at least one first ISA core 816. A processor having at least one first ISA core 816 represents any processor that can perform operations with an Intel processor having at least one first ISA core by compatibly executing or otherwise processing (1) a substantial portion of the first ISA or (2) an object code version of an application or other software targeted to run on an Intel processor having at least one first ISA core. The first ISA compiler 804 represents a compiler operable to generate first ISA binary code 806 (e.g., object code) that can be executed on a processor having at least one first ISA core 816 with or without additional link processing. Similarly, Figure 8 It is shown that a program in a high-level language 802 can be compiled using an alternative ISA compiler 808 to generate an alternative ISA binary code 810 that can be executed natively by a processor without a first ISA core 814. An instruction converter 812 is used to convert the first ISA binary code 806 into code that can be executed natively by a processor without a first ISA core 814. The converted code is not necessarily the same as the alternative ISA binary code 810; however, the converted code will complete the general operation and consist of instructions from the alternative ISA. Therefore, the instruction converter 812 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first ISA processor or core to execute the first ISA binary code 806 through simulation, emulation, or any other process.

[0103] References to "one example," "an example," "one embodiment," "an embodiment," etc. indicate that the described example or embodiment may include a particular feature, structure, or characteristic, but every example or embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same example or embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an example or embodiment, it is claimed that it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other examples or embodiments, whether or not explicitly described.

[0104] Moreover, in the various examples above, unless otherwise specifically mentioned, disjunctive language such as phrases "at least one of A, B, or C" or "A, B and / or C" is intended to be understood to mean A, B, or C or any combination thereof (i.e., A and B, A and C, B and C, and A, B and C). As used in this specification and claims, and unless otherwise specified, the use of ordinal adjectives "first," "second," "third," etc. to describe an element merely indicates that a specific instance of the element or different instances of similar elements is referenced, and is not intended to imply that the elements so described must be in a particular sequence in time, space, ranking, or in any other manner. Moreover, as used in the description of the embodiments, the " / " character between the terms may indicate that the content described may include the first term and / or the second term (and / or any other additional terms) or be implemented using, utilizing, and / or according to the first term and / or the second term (and / or any other additional terms).

[0105] Moreover, the terms "bit", "flag", "field", "entry", "indicator", etc. may be used to describe any type or content of a storage location in a register, table, database, or other data structure, whether implemented in hardware or software, but are not meant to limit the embodiments to any particular type of storage location or the number of bits or other elements within any particular storage location. For example, the term "bit" may be used to refer to a bit position within a register and / or the data stored or to be stored at the bit position. The term "clear" may be used to indicate storing or otherwise causing a logical value of 0 to be stored in a storage location, and the term "set" may be used to indicate storing or otherwise causing a logical value of one, all, or some other specified value to be stored in a storage location; however, these terms are not meant to limit the embodiments to any particular logic convention, as any logic convention may be used within the embodiments.

[0106] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

Claims

1. A processor device for instruction prefix encoding, comprising: an instruction decoder for decoding a first instruction including a first prefix; as well as Cryptographic circuitry is configured to perform a cryptographic operation on data, the cryptographic operation being based at least in part on the first prefix and a relative enumeration in a pointer to the data.

2. The processor device according to claim 1, wherein: The instruction decoder is further configured to decode a second instruction including a second prefix based on a relative enumeration in the pointer.

3. The processor device according to claim 2, wherein: The data corresponds to members of the object.

4. The processor device according to claim 3, wherein: The first prefix is ​​associated with the member.

5. The processor device according to claim 3, wherein: The second prefix is ​​associated with the object.

6. The processor device according to claim 1, wherein: The cryptographic operation is based on at least a tweak derived from the first prefix and the relative enumeration.

7. The processor device according to claim 6, wherein: The fine adjustment is derived from a sum of the first prefix and the relative enumeration.

8. The processor device of claim 1, further comprising execution circuitry to perform one or more operations corresponding to the first instruction, the one or more operations comprising moving the data.

9. The processor device of claim 2, further comprising execution circuitry to perform one or more operations corresponding to the second instruction, the one or more operations comprising calculating an effective address of the data based at least in part on the pointer.

10. A method for instruction prefix encoding, comprising: decoding, by an instruction decoder of a processing device, a first instruction including a first prefix; as well as A cryptographic operation is performed, by cryptographic circuitry of the processing device, on data, the cryptographic operation being based at least in part on the first prefix and a relative enumeration in a pointer to the data.

11. The method according to claim 10, further comprising: A second instruction is decoded by the instruction decoder, the second instruction including a second prefix based on the relative enumeration in the pointer.

12. The method according to claim 11, wherein: The data corresponds to members of the object.

13. The method according to claim 12, wherein: The first prefix is ​​associated with the member.

14. The method according to claim 12, wherein: The second prefix is ​​associated with the object.

15. The method according to claim 10, wherein: The cryptographic operation is based on at least a tweak derived from the first prefix and the relative enumeration.

16. The method according to claim 15, wherein: The fine adjustment is derived from a sum of the first prefix and the relative enumeration.

17. The method according to claim 10, further comprising: One or more operations corresponding to the first instruction are performed, by the execution circuit system of the processing device, and the one or more operations include moving the data.

18. The method according to claim 11, further comprising: One or more operations corresponding to the second instruction are performed, by execution circuitry of the processing device, the one or more operations including calculating an effective address of the data based at least in part on the pointer.

19. A non-transitory machine-readable medium storing at least a single instruction, which, when executed by a machine, causes the machine to perform a method for instruction prefix encoding, the method comprising: decoding, by an instruction decoder of a processing device, a first instruction including a first prefix; as well as A cryptographic operation is performed, by cryptographic circuitry of the processing device, on data, the cryptographic operation being based at least in part on the first prefix and a relative enumeration in a pointer to the data.

20. The non-transitory machine-readable medium of claim 19, wherein: The method also includes decoding, by the instruction decoder, a second instruction including a second prefix based on the relative enumeration in the pointer.

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