Display device

Abstract

The display device includes: a display panel including a plurality of pixels, a first row of output pads electrically connected to the pixels and each of the first row of output pads is arranged along a first direction, a second row of output pads spaced apart from the first row of output pads in a second direction intersecting the first direction, and an input pad spaced apart from the second row of output pads in a second direction and arranged along the first direction; a driving chip including a first row of output bumps, a second row of output bumps and an input bump, the first row of output bumps being arranged along the first direction and connected to the first row of output pads, the second row of output bumps being spaced apart from the first row of output bumps in the second direction by a first distance and connected to the second row of output pads, and the input bumps being spaced apart from the second row of output bumps in the second direction and connected to the input pads; and a dummy pattern arranged between the second row of output pads and the input pads on a plane, and being connected to the display panel and the driving chip respectively and including an insulating material.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device having a driving chip mounted on a substrate. Background Art

[0002] Various display devices suitable for multimedia devices such as televisions, mobile phones, tablet computers, navigation, game consoles, etc. have been developed. Such display devices include multiple electronic components. The multiple electronic components may include a display panel, a driver chip, a circuit board, etc. Such electronic components are electrically connected in various ways. Summary of the invention

[0003] The present invention can provide a display device including a driving chip which will not cause cracks or damage on a substrate when installed.

[0004] According to an embodiment of the present invention, a display device is provided, comprising: a display panel, comprising a plurality of pixels, a first row of output pads, a second row of output pads and an input pad, wherein the first row of output pads is electrically connected to the pixels and each of the first row of output pads is arranged along a first direction, the second row of output pads is spaced apart from the first row of output pads in a second direction intersecting the first direction, and the input pads are spaced apart from the second row of output pads in the second direction and arranged along the first direction; a driving chip, comprising a first row of output bumps, a second row of output bumps and an input bump, wherein the first row of output bumps is arranged along the first direction and connected to the first row of output pads, the second row of output bumps is spaced apart from the first row of output bumps in the second direction and connected to the second row of output pads, and the input bumps are spaced apart from the second row of output bumps in the second direction and connected to the input pads; and a dummy pattern, which is arranged between the second row of output pads and the input pads on a plane, is connected to the display panel and the driving chip respectively and comprises an insulating material.

[0005] The following display device can be provided: the first row of output bumps and the second row of output bumps respectively include: a plurality of first bumps aligned along the first direction; and a plurality of second bumps aligned along the first direction and configured to be displaced a third distance from the first bumps in the second direction, the third distance being smaller than the first distance.

[0006] A display device may be provided in which the dummy pattern includes: a plurality of first dummy members aligned along the first direction; and a plurality of second dummy members aligned along the first direction and configured to be displaced from the first dummy members by a prescribed distance in the second direction.

[0007] A display device may be provided in which the dummy pattern is spaced apart from the second row of output bumps in the second direction by a second distance, the second distance being greater than the first distance.

[0008] A display device may be provided in which the first dummy components and the second dummy components are alternately arranged along the first direction, and a distance between a first bump of the second row of output bumps and the first dummy components in the second direction is the same as a distance between a second bump of the second row of output bumps and the second dummy components in the second direction.

[0009] A display device may be provided in which a width of each of the first and second dummy members in the first direction is less than or equal to a width of each of the first and second row output bumps in the first direction.

[0010] A display device may be provided in which the first bumps and the first dummy members are aligned along a first alignment line crossing the first direction, and the second bumps and the second dummy members are aligned along a second alignment line crossing the first direction.

[0011] A display device may be provided in which a plurality of dummy patterns are provided, the plurality of dummy patterns are arranged along the second direction, and at least one of the plurality of dummy patterns is arranged closer to the input pad than the second row of output pads.

[0012] A display device may be provided as follows: the dummy patterns include a plurality of dummy components, a portion of the dummy components being aligned with the first row of output bumps or the second row of output bumps along a direction intersecting the first direction, and another portion of the dummy components being aligned with the input pads along a direction intersecting the first direction.

[0013] A display device may be provided in which a plurality of dummy patterns are provided, and when viewed from the second direction, one of the dummy patterns overlaps with a plurality of pads.

[0014] A display device may be provided in which the dummy pattern has a single pattern shape when viewed from the first direction.

[0015] A display device may be provided in which the height of the dummy pattern is greater than the heights of the first to third rows of output pads.

[0016] The following display device can be provided: it also includes an input sensor arranged on the display panel, and the display panel and the input sensor respectively include: a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence in the thickness direction; a first conductive layer, arranged between the first insulating layer and the second insulating layer; and a second conductive layer, arranged between the second insulating layer and the third insulating layer, and the dummy pattern includes: a first dummy layer, containing the same substance as the first insulating layer of the display panel; a second dummy layer, arranged on the first dummy layer and containing the same substance as the second insulating layer of the display panel; and a third dummy layer, arranged on the second dummy layer and containing the same substance as the third insulating layer of the input sensor.

[0017] A display device may be provided in which the sides of the first to third dummy layers are aligned with each other.

[0018] A display device may be provided in which, among the side surfaces of the first to third dummy layers, a step is defined between the side surfaces of two adjacent dummy layers.

[0019] A display device may be provided in which the second dummy layer covers a side surface of the first dummy layer, and the third dummy layer covers a side surface of the second dummy layer.

[0020] According to an embodiment of the present invention, a display device is provided, comprising: a display panel, comprising a plurality of pixels, a first row of output pads, a second row of output pads, and an input pad, wherein the first row of output pads is electrically connected to the pixels and each of the first row of output pads is arranged along a first direction, the second row of output pads is spaced apart from the first row of output pads in a second direction intersecting the first direction, the input pads is spaced apart from the second row of output pads in the second direction and arranged along the first direction; a driving chip, comprising a first row of output bumps, a second row of output bumps, and an input bump, wherein the first row of output pads The bumps are arranged along the first direction and connected to the first row of output pads, the second row of output bumps are separated from the first row of output bumps by a first distance in the second direction and connected to the second row of output pads, and the input bumps are separated from the second row of output bumps by an interval in the second direction and connected to the input pads; and a dummy pattern is arranged between the second row of output pads and the input pads on the plane, and is respectively connected to the display panel and the driving chip, the dummy pattern is separated from the second row of output bumps by a second distance in the second direction, and the second distance is greater than the first distance.

[0021] A display device may be provided in which the dummy pattern includes a plurality of dummy members, the dummy members including: a plurality of first dummy members aligned along the first direction; and a plurality of second dummy members aligned along the first direction and configured to be displaced from the first dummy members by a prescribed distance in the second direction.

[0022] The following display device can be provided: the first row of output bumps and the second row of output bumps respectively include: a plurality of first bumps aligned along the first direction; and a plurality of second bumps aligned along the first direction and configured to be displaced from the first bumps in the second direction by a third distance, the third distance being smaller than the first distance, and a distance between the first bumps of the second row of output bumps and the first dummy component in the second direction and a distance between the second bumps of the second row of output bumps and the second dummy component in the second direction being the same.

[0023] A display device may be provided in which the first bump and the first dummy member are aligned along a direction intersecting the first direction, and the second bump and the second dummy member are aligned along a direction intersecting the first direction.

[0024] (Effects of the Invention)

[0025] According to the display device of one embodiment of the present invention, the driving chip is safely mounted on the substrate without causing cracks or damage on the substrate.

[0026] According to the display device of one embodiment of the present invention, it is possible to promote ultra-miniaturization of the display device and save manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A is a three-dimensional diagram of an electronic device according to an embodiment of the present invention.

[0028] Figure 1B It is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0029] Figure 2A and Figure 2B is a cross-sectional view of a display device according to an embodiment of the present invention.

[0030] Figure 3A FIG. 1 is a top view of a display panel according to an embodiment of the present invention.

[0031] Figure 3B is a cross-sectional view of a display device according to an embodiment of the present invention.

[0032] Figure 4 It is an exploded perspective view of a bonding area of ​​a display device according to an embodiment of the present invention.

[0033] Figure 5A and Figure 5B FIG. 1 is a top view of a chip region of a display device according to an embodiment of the present invention.

[0034] Fig. 6A This is a schematic diagram showing an enlarged chip region of a display device of a comparative example.

[0035] Figure 6B : is a graph showing the pressure applied to the chip region of the display device of the comparative example.

[0036] Figure 7 This is a schematic diagram showing an enlarged chip region of a display device according to an embodiment of the present invention.

[0037] Figure 8 This is an enlarged view of a chip region of a display device according to an embodiment of the present invention.

[0038] Fig. 9A and Fig. 9B This is an enlarged view of a dummy pattern of a display device according to an embodiment of the present invention.

[0039] FIG. 10A to FIG. 10D 1 is a schematic diagram showing the arrangement relationship between bumps and dummy patterns in a display device according to an embodiment of the present invention.

[0040] Description of Reference Numerals

[0041] DD: display device; DP: display panel; DC: driver chip; PD: pad; PB: bump; DMP: dummy pattern DETAILED DESCRIPTION

[0042] In this specification, when referring to a certain structural element (or region, layer, part, etc.) being "on" another structural element, "connected" or "combined with" another structural element, it means that the certain structural element can be directly configured / connected / combined above the other structural element, or a third structural element can be configured between them.

[0043] The same reference numerals represent the same structural elements. In addition, in the drawings, the thickness, ratio and size of the structural elements are exaggerated for effective description of the technical content. "And / or" includes all of the combinations of more than one that can be defined for the structural elements related to each other.

[0044] The terms first, second, etc. can be used to describe various structural elements, but the structural elements are not limited to the terms. The terms are used only for the purpose of distinguishing one structural element from other structural elements. For example, without exceeding the scope of the claims of the present invention, the first structural element can be referred to as the second structural element, and similarly, the second structural element can also be referred to as the first structural element. Unless the context clearly indicates a different meaning, a singular expression includes a plural expression.

[0045] Furthermore, terms such as “below”, “lower side”, “above”, and “upper side” are used to describe the relationship between the components shown in the drawings. The terms are relative concepts and are described based on the directions indicated in the drawings.

[0046] The terms “including” or “having” should be understood as intending to specify the existence of the features, numbers, steps, actions, structural elements, components or their combinations recorded in the specification, but are not intended to preclude the existence or additional possibilities of one or more other features, numbers, steps, actions, structural elements, components or their combinations.

[0047] Unless defined differently, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. Also, terms that are the same as those defined in generally used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and should not be interpreted as overly ideal or overly formal meanings unless explicitly defined.

[0048] Hereinafter, a display panel and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0049] Figure 1A is a three-dimensional diagram of an electronic device according to an embodiment of the present invention, Figure 1B It is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0050] In this specification, a mobile phone terminal is illustrated as an example of an electronic device ED. The electronic device ED of the present invention can be applied to large electronic devices such as televisions and monitors, and can also be applied to small and medium-sized electronic devices such as tablet computers, car navigation systems, game consoles, smart watches, etc.

[0051] Reference Figure 1A and Figure 1B, the electronic device ED can display an image IM through the display surface ED-IS. An icon image is shown as an example of the image IM. The display surface ED-IS can be parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface ED-IS and the thickness direction of the electronic device ED can be parallel to the third direction DR3.

[0052] The display surface ED-IS may include a display area ED-DA displaying an image IM and a non-display area ED-NDA adjacent to the display area ED-DA. The non-display area ED-NDA may be an area where no image is displayed. However, this is not limited thereto, and the non-display area ED-NDA may be adjacent to one side of the display area ED-DA or be omitted.

[0053] In this specification, the meaning of "when viewed from a plane or on a plane" may refer to the situation of viewing from the third direction DR3. The front side (or upper surface) and the back side (or lower surface) of each layer or unit described below may be divided by the third direction DR3. However, this is not limited to this, and the combination of the first to third directions DR1, DR2, and DR3 may be changed to other combinations.

[0054] Furthermore, the electronic device ED may include: a window WM, a display device DD, and a storage member BC. Although not shown, the electronic device ED may further include an optical member disposed between the window WM and the display device DD. The optical member may include a polarizing plate.

[0055] The window WM may be arranged on the upper part of the display device DD and allow the image provided by the display device DD to pass to the outside. The window WM may include a transmission area TA and a non-transmission area NTA. The transmission area TA overlaps with the display area ED-DA and may have a shape corresponding to the display area ED-DA. The window WM may include a base layer and a functional layer arranged on the base layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window WM may be composed of glass, sapphire, plastic, etc.

[0056] The non-transmitting area NTA may overlap with the non-display area ED-NDA and may have a shape corresponding to the non-display area ED-NDA. The non-transmitting area NTA may be an area having a relatively low light transmittance compared to the transmissive area TA. The non-transmitting area NTA may be defined by configuring a frame pattern in a portion of the base layer of the window WM, and an area not configured with a frame pattern may be defined as the transmissive area TA. However, the technical idea of ​​the present invention is not limited thereto, and the non-transmitting area NTA may be omitted.

[0057] According to an embodiment of the present invention, the display panel DP may be a liquid crystal display panel, an electrophoretic display panel, a MEMS display panel, an electrowetting display panel, an organic light emitting display panel, an inorganic light emitting display panel, and a quantum dot light emitting display panel, without being particularly limited. Hereinafter, the display panel DP may be described as an organic light emitting display panel.

[0058] The input sensor ISU may include a capacitive sensor, an optical sensor, an ultrasonic sensor, or an electromagnetic induction sensor. The input sensor ISU may be formed on the display panel DP through a continuous process, or may be manufactured separately and then attached to the upper side of the display panel DP through an adhesive layer, and is not limited to a particular embodiment.

[0059] Figure 2A and Figure 2B Each of them is a cross-sectional view of a display device according to an embodiment of the present invention.

[0060] Reference Figure 2A In one embodiment, the display device DD may include a driving chip DC and a circuit board CF. Although the driving chip DC is shown as an embodiment in which the display panel DP is mounted, it is not limited thereto. The driving chip DC may generate a driving signal required for the operation of the display panel DP based on a control signal transmitted from the circuit board CF.

[0061] The circuit board CF electrically bonded to the display panel DP may be bent and disposed on the back of the display panel DP. The receiving member BC may accommodate the display device DD and be combined with the window WM. The circuit board CF may be disposed at one end of the base substrate SUB and electrically connected to the circuit element layer DP-CL. Although not shown, the electronic device ED may also include a main board, an electronic module mounted on the main board, a camera module, a power module, and the like.

[0062] The display panel DP of an embodiment may include a bending area BA, and first and second non-bending areas NBA1 and NBA2 arranged at intervals in a second direction DR2 across the bending area BA.

[0063] The bending area BA may be defined as an area where the display panel DP is bent along a virtual bending axis BX extending in the first direction DR1. The first non-bending area NBA1 may be defined as an area adjacent to the transmission area TA (see Figure 1B ) overlapping area, the second non-bending area NBA2 can be defined as an area connected to the circuit board CF.

[0064] When the bending area BA is bent with the bending axis BX as a reference, the circuit board CF and the driving chip DC may be bent toward the back of the display panel DP and disposed on the back of the display panel DP. When the bending area BA is bent with the bending axis BX as a reference, the first non-bending area NBA1 and the second non-bending area NBA2 may be spaced apart in the third direction DR3.

[0065] Although not shown, an additional structure for compensating for a step generated between the circuit board CF and the back surface of the display panel DP due to the bent area BA may be provided.

[0066] According to an embodiment of the present invention, in the first direction DR1, the width of the first non-bending area NBA1 may be greater than the widths of the bending area BA and the second non-bending area NBA2. However, this is not limited thereto, and the width of the bending area BA in the first direction DR1 may be provided in a shape in which the width gradually narrows as it approaches the second non-bending area NBA2 from the first non-bending area NBA1, but this is not limited to a certain embodiment.

[0067] Reference Figure 2B The display panel DP may include a base substrate SUB, a circuit element layer DP-CL disposed on the base substrate SUB, a display element layer DP-ED, and an upper insulating layer TFL. The input sensor ISU may be disposed on the upper insulating layer TFL.

[0068] exist Figure 2B In the above, the Figure 2A The curved area BA in the display panel DP and the area corresponding to the second non-curved area NBA2.

[0069] The display panel DP may include a display area DP-DA and a non-display area DP-NDA. Figure 1A The display area ED-DA shown (refer to Figure 1A )or Figure 1B The transmission area TA shown (refer to Figure 1B ), the non-display area DP-NDA can be Figure 1A The non-display area ED-NDA shown (refer to Figure 1A )or Figure 1BThe non-transmitting area NTA shown (refer to Figure 1B )correspond.

[0070] The base substrate SUB may include at least one plastic film. The base substrate SUB may be a flexible substrate including a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0071] The display element layer DP-ED includes a plurality of organic light emitting diodes. The display element layer DP-ED may further include an organic layer such as a pixel definition film. The upper insulating layer TFL seals the display element layer DP-ED. As an example, the upper insulating layer TFL may include a thin film encapsulation layer. The thin film encapsulation layer may include a stacked structure of an inorganic layer / organic layer / inorganic layer. The upper insulating layer TFL protects the display element layer DP-ED from foreign matter such as moisture, oxygen, and dust particles. However, it is not limited thereto, and the upper insulating layer TFL may further include additional insulating layers other than the thin film encapsulation layer. For example, an optical insulating layer for controlling the refractive index may also be included.

[0072] In one embodiment of the present invention, a packaging substrate may be provided to replace the upper insulating layer TFL. In this case, the packaging substrate may be disposed on the display element layer DP-ED facing the base substrate SUB, and the packaging substrate has a higher rigidity than the upper insulating layer TFL. The packaging substrate may seal the display element layer DP-ED and protect the display element layer DP-ED from external impact.

[0073] The input sensor ISU may be directly disposed on the display panel DP. In the present specification, "the A structure is directly disposed on the B structure" may mean that no adhesive layer is disposed between the A structure and the B structure. In the present embodiment, the input sensor ISU may be manufactured through a continuous process with the display panel DP. However, the technical idea of ​​the present invention is not limited thereto, and the input sensor ISU may be provided as a separate panel and combined with the display panel DP through an adhesive layer. As another example, the input sensor ISU may be omitted.

[0074] Figure 3A is a top view of a display panel according to an embodiment of the present invention, Figure 3B is a cross-sectional view of a display device according to an embodiment of the present invention.

[0075] Reference Figure 3A The display panel DP may include a plurality of pixels PX, a gate driving circuit GDC, a plurality of signal lines SGL, and a plurality of display pads DP-PD, DP-CPD.

[0076] The pixels PX are arranged in the display area DP-DA. Each pixel PX includes an organic light emitting diode and a pixel driving circuit connected thereto. In addition, the display area DP-DA may be substantially an area where an organic light emitting diode is arranged. Therefore, the pixel driving circuit may be arranged in the display area DP-DA or in the non-display area DP-NDA. As long as it can be electrically connected to the organic light emitting diode, the pixel driving circuit may be arranged in various positions and is not limited to a certain embodiment.

[0077] The gate driving circuit GDC sequentially outputs gate signals to the plurality of gate lines GL. The gate driving circuit GDC may include a plurality of thin film transistors formed by the same process as the driving circuit of the pixel PX, for example, by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. The display panel DP may further include another driving circuit that provides a light emitting control signal to the pixel PX.

[0078] In addition, in the present embodiment, although the gate drive circuit GDC is illustrated as being arranged in the non-display area DP-NDA, it is not limited to this. For example, at least a portion of the gate drive circuit GDC may also be arranged to overlap with the display area DP-DA on a plane. Also, in the present embodiment, although the gate drive circuit GDC is illustrated as one, it may also be provided as a plurality. As long as it can be electrically connected to the pixel PX, the gate drive circuit GDC may be arranged at various positions and provided in various numbers, and is not limited to a certain embodiment.

[0079] The signal lines SGL include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. The gate lines GL are connected to corresponding pixels PX in the pixels PX, respectively, and the data lines DL are connected to corresponding pixels PX in the pixels PX, respectively. The power lines PL are connected to the pixels PX. The control signal lines CSL can provide control signals to the scan drive circuit.

[0080] The signal line SGL overlaps the display area DP-DA and the non-display area DP-NDA.

[0081] The display panel DP may include display pads. The display pads may include first display pads DP-PD and second display pads DP-CPD. According to an embodiment of the present invention, the first display pads DP-PD and the second display pads DP-CPD may be disposed on the second non-bending area NBA2.

[0082] The non-display area DP-NDA may include a chip area DCA and a first pad area PCA1 that are spaced apart from each other. The chip area DCA is used as a substrate for the driver chip DC (see Figure 2A ) is combined with the first display pad DP-PD, which may be the area configured with the first display pad DP-PD. The first pad area PCA1 is the area connected to the circuit board CF, which may be the area configured with the second display pad DP-CPD. The first display pad DP-PD is connected to the driving chip DC (refer to Figure 2A ) are electrically connected so as to transmit the electrical signal received from the driving chip DC to the signal line SGL.

[0083] The first display pads DP-PD include a first row of display pads DP-PD1 arranged along a first direction DR1 and second to x-th rows of display pads DP-PDx (x is a natural number greater than 2) arranged along the first direction DR1. The second to x-th rows of display pads DP-PDx are arranged in sequence with the first row of display pads DP-PD1 in the second direction DR2 and are separated from the first row of display pads DP-PD1 in sequence by a specified interval in the second direction DR2.

[0084] The first pad area PCA1 may be provided with second display pads DP-CPD. The second display pads DP-CPD may be arranged along the first direction DR1. The first display pads DP-PD may be connected to corresponding display pads of the second display pads DP-CPD through bridge signal lines S-CL.

[0085] The second display pads DP-CPD may also include row display pads arranged along the first direction DR1 similarly to the first display pads DP-PD.

[0086] The circuit board CF may include circuit pads CF-PD arranged along the first direction DR1. The circuit pads CF-PD may be configured in the second pad area PCA2 defined on the circuit board CF. The circuit pads CF-PD may be pads connected to the display panel DP.

[0087] Furthermore, when the second display pads DP-CPD are arranged in a row of pads in the first direction DR1, the circuit pads CF-PD included in the circuit board CF may also have an arrangement corresponding to the second display pads DP-CPD in a 1:1 manner, but is not limited to a certain embodiment.

[0088] A second pad area PCA2 of the circuit board CF may be disposed above the first pad area PCA1. The second display pad DP-CPD is electrically connected to the circuit pad CF-PD included in the circuit board CF to transmit an electrical signal received from the circuit board CF to the first display pad DP-PD. The circuit board CF may be rigid or flexible. For example, when the circuit board CF is flexible, it may be provided as a flexible printed circuit board.

[0089] The circuit board CF may include a timing control circuit for controlling the operation of the display panel DP. The timing control circuit may be mounted on the circuit board CF in the form of an integrated chip. Also, although not shown, the circuit board CF may include an input sensing circuit for controlling the input sensor ISU.

[0090] In addition, although the display panel DP is described as including Figure 2A The driver chip DC shown (refer to Figure 2A ) is mounted on the first display pad DP-PD, but is not limited thereto. The driving chip DC (refer to Figure 2A ) can be mounted on the circuit board CF, in which case the first display pad DP-PD can be omitted.

[0091] Figure 3B The example shown includes Figure 3A A certain pixel PX ( Figure 3A ) is a cross-section of a display device DD. The display device DD includes a display panel DP and an input sensor ISU (see Figure 2B ), the display panel DP includes a base layer BS, a circuit layer DP-CL, a display element layer DP-ED and a packaging layer TFE. In addition, a certain pixel PX ( Figure 3A ) can have an equivalent circuit including multiple transistors, a capacitor and a light-emitting element, and the equivalent circuit diagram of the pixel can be transformed into various forms. Figure 3B The pixel PX ( Figure 3A ) includes a transistor TR and a light emitting element LD.

[0092] The display panel DP of an embodiment may include a plurality of insulating layers, transistors, conductive patterns, signal wirings, and the like.

[0093] A plurality of inorganic films, a plurality of organic films, a semiconductor layer, and a conductive layer may be formed by coating, deposition, and the like. Subsequently, the inorganic film, the organic film, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography. In this way, it is possible to form: a plurality of insulating layers, formed from inorganic films and organic films, respectively; a transistor TR, including a semiconductor pattern formed from a semiconductor layer; and a circuit layer DP-CL, including a conductive pattern and signal wiring, etc., formed from a conductive layer.

[0094] Subsequently, a display element layer DP-ED including a light emitting element LD including a conductive pattern and the like may be formed over the circuit layer DP-CL, and an encapsulation layer TFE may be formed covering the display element layer DP-ED.

[0095] Reference Figure 3B The circuit layer DP-CL may include a shielding electrode BML, a buffer layer BFL, a plurality of insulating layers IOL1, IOL2, IOL3, IOL4 including inorganic films and a plurality of insulating layers OML1, OML2 including organic films, a transistor TR, connection electrodes CNE1, CNE2, a signal wiring SCL, and the like.

[0096] The shielding electrode BML may be disposed on the base layer BS. The shielding electrode BML may overlap with the transistor TR. In addition, in one embodiment, a shielding electrode BML may be disposed below the signal wiring SCL. The shielding electrode BML may block light incident from the bottom of the display panel DP to the transistor TR or the signal wiring SCL, thereby protecting the semiconductor pattern or conductive pattern of the transistor TR and the signal wiring SCL. The shielding electrode BML may include a conductive material. In one embodiment, the shielding electrode BML may overlap with the power line PL ( Figure 3A ) is connected to receive the applied voltage. When a voltage is applied to the shielding electrode BML, the threshold voltage of the transistor TR configured on the shielding electrode BML can be maintained. However, it is not limited thereto, and the shielding electrode BML can be a floating electrode. In one embodiment, the shielding electrode BML can also be omitted.

[0097] The buffer layer BFL may be disposed on the base layer BS and cover the shielding electrode BML. The buffer layer BFL may improve the bonding force between the semiconductor pattern or the conductive pattern disposed on the buffer layer BFL and the base layer BS. Furthermore, the buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BS to the semiconductor pattern or the conductive pattern.

[0098] The buffer layer BFL may be an inorganic film. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0099] The transistor TR may include a source SE, a channel AC, a drain DE, and a gate GT. The source SE, the channel AC, and the drain DE of the transistor TR may be formed from a semiconductor pattern. In a cross section, the source SE and the drain DE may extend from the channel AC in opposite directions to each other. Also, Figure 3B 1 shows a portion of a signal wiring SCL formed from a semiconductor pattern. Although not shown separately, the signal wiring SCL can be connected to the drain DE of the transistor TR on a plane.

[0100] The semiconductor pattern of the transistor TR may include polysilicon, amorphous silicon, or metal oxide, and is not limited to any one of them as long as it has semiconductor properties.

[0101] The semiconductor pattern may include a plurality of regions divided according to the strength of the conductivity. The region doped with a dopant or reduced with a metal oxide in the semiconductor pattern will have a stronger conductivity, which can essentially serve as the source electrode and the drain electrode of the transistor TR. The region with strong conductivity in the semiconductor pattern may be equivalent to the source SE and the drain DE of the transistor TR. The region that is not doped or doped with a low concentration or the region where the metal oxide is not reduced and has a weak conductivity may be equivalent to the channel AC (or active) of the transistor TR.

[0102] The first insulating layer IOL1 may cover the semiconductor pattern of the transistor TR and be disposed on the buffer layer BFL. The gate GT of the transistor TR may be disposed on the first insulating layer IOL1. The gate GT may overlap with the channel AC of the transistor TR. In one embodiment, the gate GT may serve as a mask in the process of doping the semiconductor pattern of the transistor TR.

[0103] The gate GT may include titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0104] The first insulating layer IOL1 may include an inorganic film. The first insulating layer IOL1 may also be referred to as a first inorganic film. For example, the first insulating layer IOL1 may be an inorganic film containing at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer IOL1 may have a single-layer or multi-layer structure. The first insulating layer IOL1 may be a structure in which multiple inorganic films are stacked. In the case where the first insulating layer IOL1 has a structure in which multiple layers are stacked, the first insulating layer IOL1 may also include a buffer inorganic film directly disposed under the inorganic film and having a relatively higher O content than the adjacent inorganic film. As for the buffer inorganic film, it may have physical properties similar to those of the buffer insulating layer of the above-mentioned input sensor.

[0105] Furthermore, in one embodiment, the first insulating layer IOL1 may include an organic film in addition to the inorganic film. In the case where the first insulating layer IOL1 includes a structure in which an inorganic film and an organic film are stacked, the first insulating layer IOL1 may also include a buffer inorganic film disposed between the inorganic film and the organic film adjacent to each other. In this case, the buffer inorganic film may have physical properties similar to those of the buffer insulating layer of the input sensor described above. For example, the buffer inorganic film may contain a relatively high content of O and C elements compared to the adjacent inorganic film.

[0106] In addition, the multilayer structure described in the first insulating layer IOL1 can also be introduced into the second to fourth insulating layers IOL2, IOL3, IOL4, etc. described later. Therefore, the stacked structure of the insulating layers of the above-mentioned multilayer structure, the structure of the buffer inorganic film in the multilayer structure, etc. can also be applied to the second to fourth insulating layers IOL2, IOL3, IOL4, etc. described later.

[0107] The second insulating layer IOL2 may be disposed on the first insulating layer IOL1 and cover the gate GT. The second insulating layer IOL2 may overlap the pixel in a shared manner. The second insulating layer IOL2 may include an inorganic film. The second insulating layer IOL2 may also be referred to as a second inorganic film. For example, the second insulating layer IOL2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating layer IOL2 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In one embodiment, the second insulating layer IOL2 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0108] The third insulating layer IOL3 may be disposed on the second insulating layer IOL2. The third insulating layer IOL3 may include an inorganic film. The third insulating layer IOL3 may also be referred to as a third inorganic film. The third insulating layer IOL3 may have a single-layer or multi-layer structure. For example, the third insulating layer IOL3 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0109] The first connection electrode CNE1 may be disposed on the third insulating layer IOL3 and connected to the signal wiring SCL through a first contact hole CH-1 that penetrates the first, second and third insulating layers IOL1, IOL2 and IOL3.

[0110] The fourth insulating layer IOL4 may be disposed on the third insulating layer IOL3. The fourth insulating layer IOL4 may include an inorganic film, and the fourth insulating layer IOL4 may also be referred to as a fourth inorganic film. The fourth insulating layer IOL4 may be a single-layer silicon oxide layer.

[0111] The fifth insulating layer OML1 may be disposed on the fourth insulating layer IOL4. The fifth insulating layer OML1 may include an organic film. The fifth insulating layer OML1 may be referred to as a first organic film. The first organic film may also include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0112] The second connection electrode CNE2 may be disposed on the fifth insulating layer OML1. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH-2 that penetrates the fourth insulating layer IOL4 and the fifth insulating layer OML1.

[0113] The sixth insulating layer OML2 may be disposed on the fifth insulating layer OML1 and cover the second connection electrode CNE2. The sixth insulating layer OML2 may include an organic film. The sixth insulating layer OML2 may be referred to as a second organic film. The second organic film may also include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0114] In addition, although not Figure 3B In the figure, the circuit layer may further include a plurality of transistors, and may further include signal wiring electrically connected to the plurality of transistors. The signal wiring may extend and be connected to the non-display area NDA ( Figure 3A ) is connected to the first display pad DP-PD of the non-sensing area. In addition, the signal wiring may be extended and connected to the sensing pad of the non-sensing area.

[0115] The display element layer DP-ED is disposed on the circuit layer DP-CL. The display element layer DP-ED may include a pixel definition layer PDL and a light emitting element LD. The light emitting element LD may include a first electrode AE, a light emitting layer EL and a second electrode CE.

[0116] The first electrode AE ​​may be disposed on the sixth insulating layer OML2. The first electrode AE ​​may be connected to the second connection electrode CNE2 through the third contact hole CH-3 that penetrates the sixth insulating layer OML2. The first electrode AE ​​may be electrically connected to the drain DE of the transistor TR through the first and second connection electrodes CNE1 and CNE2.

[0117] The first electrode AE ​​may be referred to as a pixel electrode. The first electrode AE ​​may be formed of a metal material, a metal alloy, or a conductive compound. The first electrode AE ​​may be an anode or a cathode. The first electrode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In the case where the first electrode AE ​​is a transmissive electrode, the first electrode AE ​​may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. In the case where the first electrode AE ​​is a semi-transmissive electrode or a reflective electrode, the first electrode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, or a compound or mixture thereof (e.g., a mixture of Ag and Mg).

[0118] Alternatively, the first electrode AE ​​may be a multi-layer structure including a reflective film or a semi-transparent film formed by the above-mentioned substances and a transparent conductive film formed by ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tinzinc oxide), etc. For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, but is not limited thereto. Furthermore, the embodiment is not limited thereto, and the first electrode AE ​​may include the above-mentioned metal material, a combination of two or more metal materials selected from the above-mentioned metal materials, or an oxide of the above-mentioned metal material, etc.

[0119] The pixel definition film PDL can be configured on the sixth insulating layer OML2. In one embodiment, the pixel definition film PDL can be formed by a polymer resin. For example, the pixel definition film PDL can include a polyacrylate resin or a polyimide resin. In addition to the polymer resin, the pixel definition film PDL can also include an inorganic substance. In addition, the pixel definition film PDL can be formed by including a light absorbing substance or by including a black pigment or a black dye. The pixel definition film PDL formed by including a black pigment or a black dye can realize a black pixel definition film. When forming the pixel definition film PDL, carbon black or the like can be used as the black pigment or the black dye, but the embodiment is not limited to this.

[0120] Furthermore, the pixel definition layer PDL may be formed of an inorganic material, for example, the pixel definition layer PDL may be formed including silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0121] The pixel definition film PDL may be defined with a pixel opening PX-OP that exposes a portion of the first electrode AE. In a display device DD of an embodiment, the pixel definition film PDL may be used to divide the light-emitting region PXA. The display device DD includes the light-emitting region PXA and the non-light-emitting region NPXA, and the non-light-emitting region NPXA may be a portion overlapping the pixel definition film PDL. The portion of the first electrode AE ​​corresponding to the portion exposed from the pixel opening PX-OP may be defined as the light-emitting region PXA.

[0122] In the light emitting element LD, the light emitting layer EL may be disposed on the first electrode AE. In this embodiment, the light emitting layer EL may emit light of at least one color of blue, red, and green. In addition, in one embodiment, in the entire display area DP-DA ( Figure 3A ) in which the light emitting layer EL may provide blue light.

[0123] The second electrode CE may be disposed on the light emitting layer EL. The second electrode CE may have an integral shape and be disposed in a common manner on a plurality of pixels PX ( Figure 3A ). The second electrode CE may be referred to as a common electrode. The second electrode CE may be a cathode or an anode. For example, when the first electrode AE ​​is an anode, the second electrode CE may be a cathode, and when the first electrode AE ​​is a cathode, the second electrode CE may be an anode.

[0124] The second electrode CE may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. When the second electrode CE is a transmissive electrode, the second electrode CE may be made of a transparent metal oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. Furthermore, the second electrode CE may be formed of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W or a compound or mixture thereof (e.g., a mixture of Ag and Mg).

[0125] Although not shown in the figure, a hole control layer may be arranged between the first electrode AE ​​and the light-emitting layer EL. The hole control layer may include a hole transport layer and a hole injection layer. An electron control layer may be arranged between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and an electron injection layer. The hole control layer and the electron control layer may be formed together on the plurality of pixels PX ( Figure 3A ).

[0126] The encapsulation layer TFE may be disposed on the display element layer DP-ED. The encapsulation layer TFE may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked in sequence. However, the layers constituting the encapsulation layer TFE are not limited thereto.

[0127] The inorganic layers IL1 and IL2 can protect the display element layer DP-ED from moisture and oxygen, and the organic layer OL can protect the display element layer DP-ED from foreign matter such as dust particles. The inorganic layers IL1 and IL2 can include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic layer OL can include an acrylic organic material. However, the types of materials constituting the inorganic layers IL1 and IL2 and the organic layer OL are not limited thereto.

[0128] An input sensor ISU may be configured on the encapsulation layer TFE. The input sensor ISU may be referred to as a sensor layer, an input sensing layer, or an input sensing panel. The input sensor ISU may include a plurality of sensor insulating layers ISL and a plurality of sensor conductive layers MTL. A portion of the insulating layers ISL-B of the plurality of sensor insulating layers ISL may be directly configured on the display panel DP. For example, in one embodiment, the input sensor ISU may include a first sensor insulating layer ISL-B, a first sensor conductive layer MTL1, a second sensor insulating layer ISL-C, a second sensor conductive layer MTL2, and a third sensor insulating layer ISL-T sequentially stacked along a third direction DR3 on the display panel DP.

[0129] The first sensor insulation layer ISL-B may include a base insulation layer. Furthermore, the first sensor insulation layer may include a buffer insulation layer. That is, the input sensor ISU may be a single layer structure consisting of only a base insulation layer or a buffer insulation layer, or a stacked structure including a buffer insulation layer and a base insulation layer, but is not limited to a certain embodiment.

[0130] The first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may have a multi-layer structure. The sensor conductive layer of the multi-layer structure may be a structure in which two or more transparent conductive layers and / or metal layers are stacked. For example, the sensor conductive layer of the multi-layer structure may also be a structure in which a transparent conductive layer and a metal layer are stacked, or a structure in which metal layers including different metals are stacked.

[0131] As an example, the transparent conductive layer included in the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), PEDOT, metal nanowires or graphite, etc. The metal layer included in the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include molybdenum, silver, titanium, copper, aluminum or alloys thereof.

[0132] The first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include sensing electrodes of the input sensor ISU, and may further include sensing wirings.

[0133] The second sensor insulating layer ISL-C may be disposed on the first sensor conductive layer MTL1. The third sensor insulating layer ISL-T may be disposed on the second sensor conductive layer MTL2. Each insulating layer in the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T may include an inorganic film. Furthermore, each insulating layer in the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T may also include an organic film.

[0134] Each of the first sensor insulating layer ISL-B, the second sensor insulating layer ISL-C, and the third sensor insulating layer ISL-T may include silicon nitride (SiN X ) and silicon oxynitride (SiO X N Y ). In addition, the first sensor insulating layer ISL-B, the second sensor insulating layer ISL-C, and the third sensor insulating layer ISL-T may include silicon oxide (SiO X In addition, the first sensor insulating layer ISL-B, the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T may also include at least one of aluminum oxide, titanium oxide, zirconium oxide and hafnium oxide as an inorganic film. X ), silicon oxynitride (SiO X N Y ) and silicon oxide (SiO X ), X and Y may be greater than 0 respectively.

[0135] When the first sensor insulating layer ISL-B, the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T include organic films, the organic films may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin and perylene resin.

[0136] In addition, although Figure 3B The input sensor ISU is shown as a stacked structure including a first sensor conductive layer MTL1 and a second sensor conductive layer MTL2, but the embodiment is not limited thereto. For example, in one embodiment, the input sensor ISU may include a sensor conductive layer MTL disposed on the first sensor insulating layer ISL-B. In this case, one of the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T may also be omitted.

[0137] In addition, Figure 3BIn the embodiment, although each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 is shown as a layer overlapped on the entire display panel DP in order to schematically show the stacked structure, the embodiment is not limited thereto. Each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may be formed by patterning.

[0138] According to an embodiment, the display device DD may include an optical layer. In an embodiment, the optical layer AF may be directly disposed on the third sensor insulation layer ISL-T. However, this is not limited thereto, and an adhesive may be included between the optical layer AF and the input sensor ISU, and this is not limited to a certain embodiment.

[0139] Figure 4 It is an exploded perspective view of a bonding area of ​​a display device according to an embodiment of the present invention.

[0140] Reference Figure 4 , the display panel DP includes: a first adhesive layer AF-C, which is arranged between the circuit board CF and the base substrate SUB; and a second adhesive layer AF-D, which is arranged between the driving chip DC and the base substrate SUB. The first adhesive layer AF-C can connect the circuit board CF and the display panel DP, and the second adhesive layer AF-D can connect the driving chip DC and the display panel DP. Each adhesive layer in the first adhesive layer AF-C and the second adhesive layer AF-D can have insulating properties. The first adhesive layer AF-C and the second adhesive layer AF-D can physically combine the circuit board CF and the driving chip DC with the display panel DP, respectively.

[0141] The circuit board CF includes an upper surface CF-US and a lower surface CF-DS. The lower surface CF-DS of the circuit board CF may be a surface opposite to the display panel DP. A plurality of substrate pads CF-PD may be arranged on the lower surface CF-DS of the circuit board CF and electrically connected to a plurality of second display pads DP-CPD of the display panel DP, respectively.

[0142] The driving chip DC includes an upper surface DC-US and a lower surface DC-DS. The lower surface DC-DS of the driving chip DC may be a surface opposite to the display panel DP. The driving chip DC includes a chip pad DC-PD configured on the lower surface DC-DS. The plurality of chip pads DC-PD are electrically connected to the plurality of first display pads DP-PD configured on the base substrate SUB.

[0143] The plurality of chip pads DC-PD may include: a first row of chip pads DC-PD1 arranged along a first direction DR1; a second row of chip pads DC-PD2 arranged along the first direction DR1 and spaced apart from the first row of chip pads DC-PD1 in a second direction DR2; and an nth row of chip pads (n is a natural number greater than 3) arranged along the first direction DR1 and spaced apart from the second row of chip pads DC-PD2 in a second direction DR2. The first row of chip pads DC-PD1 and the second row of chip pads DC-PD2 may have a shape exposed to the outside from the lower surface of the driving chip DC.

[0144] Although in Figure 4 The chip pads DC-PD are described as being arranged in four rows, but the present invention is not limited thereto. The chip pads DC-PD may be arranged in more than five rows based on the arrangement structure of the first display pads DP-PD.

[0145] Although the connection between the circuit board CF and the display panel DP is exemplarily shown below, the connection structure between the circuit board CF and the display panel DP described later may also be similarly applicable to the connection between the driving chip DC and the display panel DP.

[0146] Furthermore, the pad PD described below (refer to Figure 5A ) can be connected with the aforementioned first display pad DP-PD ( Figure 4 ) corresponds to the bump PB (refer to Figure 5A ) corresponds to the aforementioned chip pad DC-PD.

[0147] Figure 5A and Figure 5B 1 is a top view of a chip region of a display device according to an embodiment of the present invention. Specifically, Figure 5B yes Figure 5A Magnified view of section F5B.

[0148] Reference Figure 5A The display panel DP may include an input pad portion IPDR, a side pad portion SPDR, and an output pad portion OPDR. Each of the input pad portion IPDR, the side pad portion SPDR, and the output pad portion OPDR may include a plurality of pads PD.

[0149] The input pad portion IPDR includes a plurality of input pads IPD, and the side pad portion SPDR includes a plurality of side pads SPD.

[0150] A plurality of input pads IPD may be arranged along the first direction DR1 to form a row. A plurality of side pads SPD may be arranged along the second direction DR2 to form a column. An input bump IPB may be correspondingly configured at each input pad IPD, and a side bump SPB may be correspondingly configured at each side pad SPD.

[0151] The arrangement of the input pads IPD and the side pads SPD shown in the drawings is only an example and is not limited to what is shown in the drawings. The arrangement of the input pads IPD and the side pads SPD may be different depending on the design of the display panel DP or the driving chip DC and is not limited to a certain embodiment.

[0152] The input pad portion IPDR and the side pad portion SPDR may provide a display device DD (refer to Figure 1B ) Various signals provided from the outside. Various signals can be provided to the driving chip DC through a plurality of input bumps IPB configured corresponding to the input pad portion IPDR and a plurality of side bumps SPB configured corresponding to the side pad portion SPDR.

[0153] The output pad portion OPDR may include a plurality of output pads OPD. The plurality of output pads OPD may be arranged along a first direction DR1 and a second direction DR2. The plurality of output pads OPD arranged along the first direction DR1 may be respectively defined as output pad rows. The output pad rows OPD_R1, OPD-R2, OPD_R3, OPD_R4 may be arranged along the second direction DR2.

[0154] Although the output pad portion OPDR is shown in the drawings as a structure including only the first to fourth output pad rows OPD_R1, OPD-R2, OPD_R3, OPD_R4, it is not limited thereto and may include more than five output pad rows and is not limited to a certain embodiment.

[0155] The output pad portion OPDR can receive the output from the driver chip DC through a plurality of output bumps OPB arranged corresponding to the output pad portion OPDR (refer to Figure 4 ) Various signals outputted by the output pad portion OPDR. Various signals supplied to the output pad portion OPDR may be supplied to respective pixels arranged in the display area through a plurality of lines connected to the output pad portion OPDR.

[0156] The output pad part OPDR may include a greater number of output pads OPD than the number of input pads IPD of the input pad part IPDR or the number of side pads SPD of the side pad part SPDR, corresponding to the number of pixels PX.

[0157] The output pads OPD included in each of the output pad rows OPD_R1, OPD-R2, OPD_R3, and OPD_R4 may have the same shape and may be arranged side by side. That is, the output pads OPD arranged in the same row may be aligned along the first direction DR1.

[0158] Each of the output bumps OPB configured corresponding to the output pad portion OPDR may be configured to have a specific pattern. Specifically, the output bumps OPB may include output bump rows OPB_R1, OPB-R2, OPB_R3, OPB_R4 in which a plurality of output bumps OPB are arranged along the first direction DR1.

[0159] The output bumps OPB included in each output bump row OPB_R1, OPB-R2, OPB_R3, and OPB_R4 may have the same shape. The output bumps OPB arranged in the same row may be arranged in a zigzag staggered manner in the first direction DR1. That is, the output bumps OPB arranged in the same row and adjacent to each other may be arranged to be displaced by a specified distance in the second direction DR2 so that a portion is staggered. At this time, the specified distance of the displacement may be less than the distance between adjacent rows.

[0160] By arranging the output bumps OPB in a zigzag arrangement over the output pads OPD, cracks or breakage that may occur when mounting the driving chip DC can be minimized.

[0161] The chip area DCA may include: a pad area PDR, which is configured with pads PD of each pad part in the input pad part IPDR, the side pad part SPDR, and the output pad part OPDR; and a circuit area CR, which is configured with a circuit. In the accompanying drawings, although the dummy pattern (dummy pattern) DMP described later is illustrated as being configured only in the pad area PDR, it is not limited to this. The dummy pattern DMP may be configured only in the circuit area CR, or may be simultaneously stacked in the circuit area CR and the pad area PDR, and is not limited to a certain embodiment. That is, the dummy pattern DMP may overlap with the circuit configured in the circuit area CR on a plane, and is not limited to a certain embodiment.

[0162] According to an embodiment of the present invention, a plurality of dummy patterns DMP may be provided, and each dummy pattern DMPa, DMPb may be separated from the pad PD of the input pad portion IPDR or the pad PD of the output pad portion OPDR by a predetermined distance. The dummy pattern DMP may include an insulating material compared to the pad PD and the bump PB.

[0163] Reference Figure 5B The plurality of output pads OPD arranged along the first direction DR1 may be respectively defined as output pad rows. Also, the plurality of output bumps OPB arranged along the first direction DR1 may be respectively defined as output bump rows.

[0164] According to an embodiment of the present invention, the output pad rows may be spaced apart by a first distance D1 in the second direction DR2. That is, the distance in the second direction DR2 between the output pads OPD adjacent to each other in the second direction DR2 may be the first distance D1.

[0165] Reference Figure 5A and Figure 5B In one embodiment of the present invention, the output bump rows OPB_R1, OPB-R2, OPB_R3, and OPB_R4 may be separated by a second distance D2 in the second direction DR2. That is, the distance in the second direction DR2 between the adjacent output bumps OPB in the second direction DR2 may be the second distance D2.

[0166] Each output bump row OPB_R1, OPB-R2, OPB_R3, OPB_R4 may include a plurality of first bumps OPB1 and a plurality of second bumps OPB2. The plurality of first bumps OPB1 may be aligned along a first direction DR1. The plurality of second bumps OPB2 may be aligned along the first direction DR1. The first bumps OPB1 and the second bumps OPB2 may be arranged alternately.

[0167] The second bump OPB2 may be arranged by shifting the third distance D3 from the first bump OPB1 in the second direction DR2. The third distance D3 may be smaller than the second distance D2. The second bump OPB2 is arranged by shifting the third distance D3 relative to the first bump OPB1 in the second direction DR2, so that the first bump OPB1 and the second bump OPB2 may be arranged in a staggered manner.

[0168] When the bumps PB are not arranged in a zigzag pattern, the pads PD of the pad portion and the bumps PB of the bump portion are electrically connected to the driver chip DC (see Figure 4 ) When heat and pressure are applied, pressure (or stress) is concentrated on the display panel DP (refer to Figure 4 ) of the area adjacent to the bump PB, resulting in the display panel DP (refer to Figure 4 As the areas where pressure (or stress) is concentrated are aligned in a specific direction, the entire display panel DP may be deformed.

[0169] The bumps PB of the bump portion of one embodiment of the present invention are arranged in a zigzag shape in the first direction DR1, so as to avoid the areas where pressure (or stress) is concentrated from being aligned in a specific direction, so that the pressure (or stress) can be evenly distributed on the entire display panel DP, thereby preventing the entire display panel DP from being deformed.

[0170] According to an embodiment of the present invention, the bumps PB of different output bump rows may be aligned along the second direction DR2. The first bump OPB1 of the first bump row OPB_R1 and the first bump OPB1 of the second bump row OPB_R2 may be aligned along the second direction DR2. The second bump OPB2 of the first bump row OPB_R1 and the second bump OPB2 of the second bump row OPB_R2 may be aligned along the second direction DR2.

[0171] The first bump OPB1 of the second bump row OPB_R2 and the first bump OPB1 of the third bump row OPB_R3 may be aligned along the second direction DR2. The second bump OPB2 of the second bump row OPB_R2 and the second bump OPB2 of the third bump row OPB_R3 may be aligned along the second direction DR2. The first bump OPB1 of the third bump row OPB_R3 and the first bump OPB1 of the fourth bump row OPB_R4 may be aligned along the second direction DR2. The second bump OPB2 of the third bump row OPB_R3 and the second bump OPB2 of the fourth bump row OPB_R4 may be aligned along the second direction DR2.

[0172] In terms of adjacent bump rows, a distance between the first bumps OPB1 in the second direction DR2 and a distance between the second bumps OPB2 in the second direction DR2 may be a second distance D2 , respectively.

[0173] By aligning the plurality of bumps PB of the first to fourth bump rows OPB_R1 - OPB_R4 along the second direction DR2 , the density of the bumps PB can be increased, and ultra-miniaturization of the display device DD can be promoted.

[0174] Although the bumps PB of the first to fourth bump rows OPB_R1 -OPB_R4 are shown in the drawings as being aligned along the second direction DR2 , this is not limited thereto, and only the bumps PB of a portion of the bump rows may be aligned along the second direction DR2 . This is not limited to a certain embodiment.

[0175] According to an embodiment of the present invention, the dummy pattern DMP may be separated from the fourth row of bumps PB by a fourth distance D4. However, the present invention is not limited thereto, and when a fifth row of bumps PB is additionally arranged between the dummy pattern DMP and the fourth row of bumps PB, the distance between the dummy pattern DMP and the fifth row of bumps PB may be the fourth distance D4.

[0176] The length of the dummy pattern DMP in the second direction DR2 may be less than the length of the bump in the second direction DR2 , but is not limited thereto. The length of the dummy pattern DMP in the second direction DR2 may be equal to the length of the bump in the second direction DR2 , and is not limited to a certain embodiment.

[0177] Furthermore, the length of the dummy pattern DMP in the second direction DR2 may be less than the fourth distance D4 and the fifth distance D5. However, it is not limited thereto, and the length of the dummy pattern DMP in the second direction DR2 may be equal to the fourth distance D4 or the fifth distance D5, and is not limited to a certain embodiment.

[0178] The dummy pattern DMP may include a plurality of dummy members DMPa1, DMPa2. The plurality of dummy members may include a first dummy member DMPa1 and a second dummy member DMPa2. The first dummy member DMPa1 and the second dummy member DMPa2 may be aligned along a first direction DR1, respectively. The first dummy member DMPa1 and the second dummy member DMPa2 may be alternately arranged.

[0179] The second dummy component DMPa2 may be arranged to be displaced a predetermined distance from the first dummy component DMPa1 in the second direction DR2. The second dummy component DMPa2 may be arranged to be displaced a predetermined distance from the first dummy component DMPa1, so that the first dummy component DMPa1 and the second dummy component DMPa2 may be arranged alternately in a zigzag manner.

[0180] The distance between the first dummy member DMPa1 and the first pad PD may be a fifth distance D5, and the distance between the second dummy member DMPa2 and the second pad PD may be a fourth distance D4. According to an embodiment of the present invention, the fourth distance D4 and the fifth distance D5 may be the same. However, it is not limited thereto, and the fourth distance D4 and the fifth distance D5 may be different, and are not limited to a certain embodiment.

[0181] The fourth distance D4 and the fifth distance D5 may be greater than the third distance D3. However, this is not limited thereto, and the fourth distance D4 or the fifth distance D5 may be the same as the third distance D3, and is not limited to a certain embodiment.

[0182] Although the drawings only show the relationship between the first dummy pattern DMPa and the output pad OPD, the relationship between the first dummy pattern DMPa and the output pad OPD can also be applied to the relationship between the second dummy pattern DMPb and the input pad IPD, and is not limited to a certain embodiment.

[0183] However, the specific values ​​of the dummy pattern DMP, the dummy members DMPa1, DMPa2, the pad PD, and the bump PB may be changed according to the design of the display device DD (see FIG. 3 ), and the specific design values ​​of each structure may have a value that enables the display panel DP (see FIG. 3 ). Figure 4 ) is not limited to a particular embodiment.

[0184] Fig. 6Ais a schematic diagram showing an enlarged chip region of a display device of a comparative example. Figure 6B is a graph showing the pressure applied to the chip region of the display device of the comparative example, Figure 7 This is a schematic diagram showing an enlarged chip region of a display device according to an embodiment of the present invention.

[0185] Fig. 6A and Figure 7 The display devices shown in the figures are only diagrams showing a part of the structure. The structure of the display device of one embodiment of the present invention is not limited to Figure 7 Specifically, Figure 7 Show Figure 4 The schematic diagram shown is a cross-section taken along line II'.

[0186] Reference Fig. 6A , Figure 6B as well as Figure 7 , the upper layer UL may include a plurality of layers. The upper layer UL may include a first upper layer 10, a second upper layer 20 disposed on the first upper layer 10, and a third upper layer 30 disposed on the second upper layer 20. The first to third upper layers 10 to 30 may represent Figure 3B The circuit layer DP-CL mentioned above (refer to Figure 3B ), display element layer DP-ED (refer to Figure 3B )、Encapsulation layer TFE (refer to Figure 3B ) and input sensor ISU (refer to Figure 3B ) is not limited to a specific embodiment.

[0187] The driver chip DC may be coupled to the display panel DP by applying heat and pressure to the driver chip DC. The bump PB of the driver chip DC may apply pressure to the display panel DP toward the third direction DR3. At this time, the display panel DP is flexible and the driver chip DC is rigid, so the flexible display panel DP may be deformed. As an example, a part of the layer of the flexible display panel DP may be pushed or dragged in a direction intersecting the third direction DR3, causing deformation and cracks on the entire display panel DP.

[0188] Referring to the accompanying drawings, stress may be concentrated in the display panel DP or in an area adjacent to the position where the pad PD and the bump PB are connected. The area where stress is concentrated on the display panel DP may be located at a position corresponding to the arrangement of the bump PB. According to the arrangement of the bump PB, deformation and cracks may occur in the area where stress is concentrated, thereby causing deformation and cracks to occur in the entire range of the display panel DP.

[0189] Refer to Fig. 6A and Figure 6B, the maximum pressure applied to the area adjacent to the position where the pad PD and the bump PB meet can be 18.1 MPA, and the minimum pressure applied to the other areas can be 3.0 MPA. That is, since the pressure applied to the stress concentrated area is greater than the pressure applied to the other areas, deformation and cracks may occur in the area, and since multiple bumps PB apply pressure to the display panel DP, the display panel DP as a whole may be deformed and cracked.

[0190] Furthermore, in the pad regions IPDR and OPDR, since bumps are disposed adjacently, the display panel is deformed only in the fixed region DFMb, and the display panel DP is also deformed to a certain extent in the fixed region. However, since no bumps are disposed in the circuit region CR, when the display panel DP is deformed, the deformed region DFMa protrudes further toward the driver chip DC than the pad regions IPDR and OPDR.

[0191] Reference Fig. 6A and Figure 6B In the comparative example shown in FIG. 1 , no additional dummy pattern DMP is arranged in the circuit region CR (see FIG. 1 ). Figure 7 ), the display panel DP will protrude further toward the driver chip DC compared to the pad areas IPDR and OPDR.

[0192] In contrast, referring to Figure 7 In one embodiment of the present invention shown in FIG. 1 , a dummy pattern DMP is disposed in the circuit region CR, and the dummy pattern DMP supports the driver chip DC and the display panel DP, thereby preventing the display panel DP from protruding toward the driver chip DC. The dummy pattern DMP supports the driver chip DC and the display panel DP, thereby preventing stress from being concentrated in the circuit region CR, thereby preventing deformation and cracks from occurring in the circuit region CR.

[0193] At this time, only a portion of the upper surface of the dummy pattern DMP may be in contact with the driving chip DC. Depending on the degree of pressure applied to the driving chip DC, the upper surface of the dummy pattern DMP may be in contact with the driving chip DC in its entirety, which is not limited to a certain embodiment.

[0194] That is, comparing the embodiment of the present invention with the comparative example, the display panel DP of the comparative example without the dummy pattern DMP is closer to the driving chip DC in the circuit region CR, so the display panel DP is more likely to be deformed and cracked.

[0195] Furthermore, the present invention is not limited to the contents shown in the drawings, and by disposing the dummy pattern DMP at a position of the pad regions IPDR and OPDR adjacent to the circuit region CR, it is possible to similarly prevent the display panel DP from protruding toward the driving chip.

[0196] Figure 8 This is a schematic diagram showing an enlarged chip region of a display device according to an embodiment of the present invention.

[0197] Reference Figure 8 In one embodiment of the present invention, the dummy pattern DMP may be disposed on the display panel DP. Although the dummy pattern DMP is shown in the drawings as being disposed on the display panel DP and spaced apart from the driving chip DC, it is not limited thereto. The dummy pattern DMP may be disposed on the driving chip DC and spaced apart from the display panel DP, and is not limited to a certain embodiment.

[0198] An upper layer UL may be disposed on the base layer BS, a first insulating layer OML1 may be disposed on the upper layer UL, a second insulating layer OML2 may be disposed on the first insulating layer OML1, and a third insulating layer ISL-T may be disposed on the second insulating layer OML2. The first to third insulating layers OML1, OML2, and ISL-T may be organic layers. The present invention is not limited to the case where only the first to third insulating layers OML1, OML2, and ISL-T are disposed as shown in the figure. Multiple layers may be disposed between adjacent insulating layers in the first to third insulating layers OML1, OML2, and ISL-T, and the present invention is not limited to a certain embodiment.

[0199] According to an embodiment of the present invention, the first insulating layer OML1 may be Figure 3B The fifth insulating layer OML1 (see Figure 3B ), the second insulating layer OML2 may correspond to Figure 3B The sixth insulating layer OML2 (see Figure 3B ), the third insulating layer ISL-T can be Figure 3B The third sensor insulation layer ISL-T shown (refer to Figure 3B )correspond.

[0200] However, it is not limited thereto, and the first insulating layer OML1 to the second insulating layer OML2 may be equivalent to Figure 3B The circuit layer DP-CL and the display element layer DP-ED shown in FIG. Figure 3B )、Encapsulation layer TFE (refer to Figure 3B ) and input sensor ISU (refer to Figure 3B ) is an insulating layer among multiple layers and is not limited to a certain embodiment.

[0201] The dummy pattern DMP may be arranged on the upper layer UL. The pad lines OPL and IPL may be arranged on the upper layer. The pads OPD and IPD may be arranged on the upper layer and may be arranged on the pad lines OPL and IPL.

[0202] According to an embodiment of the present invention, the height of the dummy pattern DMP may be greater than the height of the pads OPD and IPD. The height of the dummy pattern DMP may be less than the height of the bumps OPB and IPB. By making the height of the dummy pattern DMP less than the height of the bumps OPB and IPB, after the pads OPD and IPD are combined with the bumps OPB and IPB, it is possible to prevent the dummy pattern DMP from applying pressure to the driver chip DC in the height direction of the dummy pattern DMP beyond a predetermined degree, thereby preventing the display panel DP from further deforming. However, it is not limited to this, and the height of the dummy pattern DMP may be the same as the height of the bumps OPB and IPB, and is not limited to a certain embodiment.

[0203] The dummy pattern DMP may include a plurality of layers, and may include a first dummy layer DMP1 disposed on the upper layer, a second dummy layer DMP2 disposed on the first dummy layer DMP1, and a third dummy layer DMP3 disposed on the second dummy layer DMP2.

[0204] According to an embodiment of the present invention, the first dummy layer DMP1 and the second dummy layer DMP2 may include the same material as one of the insulating layers of the display panel DP. Furthermore, the third dummy layer DMP3 may include the same material as one of the insulating layers of the input sensor. However, it is not limited thereto, and at least one of the first and second dummy layers DMP1 and DMP2 may include the same material as the insulating layer of the input sensor, and is not limited to a certain embodiment.

[0205] For example, the first dummy layer DMP1 may include the same material as the fifth insulating layer OML1, the second dummy layer DMP2 may include the same material as the sixth insulating layer OML2, and the third dummy layer DMP3 may include the same material as the third sensor insulating layer ISL-T.

[0206] However, the first to third dummy layers DMP1, DMP2, and DMP3 are not limited to the structures described above. As an example, the second dummy layer DMP2 may include the same material as the pixel definition layer PDL. That is, the first to third dummy layers DMP1, DMP2, and DMP3 may be a part of the insulating layer or organic layer of the display device other than the structures described above, and are not limited to a certain embodiment.

[0207] Each of the first to third dummy layers DMP1, DMP2, and DMP3 may be formed in the same process as the insulating layer of the display panel DP or the input sensor ISU and may contain the same material. By diversifying the patterns of masks used when depositing or patterning each layer, the dummy layers can be formed in the same process as the process of forming each insulating layer.

[0208] According to an embodiment of the present invention, the side surfaces of the first dummy layer DMP1 , the second dummy layer DMP2 , and the third dummy layer DMP3 may be substantially aligned along the third direction DR3 .

[0209] For ease of explanation, although the dummy pattern DMP is only illustrated as including three dummy layers DMP1, DMP2, and DMP3, it is not limited to this. The number of dummy layers of the dummy pattern DMP is not limited to three. The dummy pattern DMP may include less than three or more than three dummy layers and is not limited to a certain embodiment.

[0210] According to an embodiment of the present invention, a plurality of dummy patterns DMP may be provided. A first dummy pattern DMPa among the dummy patterns DMP may be disposed adjacent to the output bump OPB and the output pad OPD. A second dummy pattern DMPb may be disposed adjacent to the input bump IPB and the input pad IPD.

[0211] The first dummy pattern DMPa and the second dummy pattern DMPb may differ only in configuration position, which is not limited to that shown in the drawings and may be configured at a stress concentration position in the aforementioned pad area PDR or circuit area CR of the display panel DP and is not limited to a certain embodiment.

[0212] Fig. 9A and Fig. 9B 1 is an enlarged view of a dummy pattern DMP according to an embodiment of the present invention. Fig. 9A and Fig. 9B The dummy pattern DMP is shown as a structure consisting of three layers, but as mentioned above, the number of layers of the dummy pattern DMP is not limited thereto, and the dummy pattern DMP may be composed of less than three or more than three layers, and is not limited to a certain embodiment.

[0213] Reference Fig. 9A A step may be defined between the side EDL1 of the first dummy layer DMP1 and the side EDL2 of the second dummy layer DMP2 of the dummy pattern DMP. A step may be defined between the side EDL2 of the second dummy layer DMP2 and the side EDL3 of the third dummy layer DMP3.

[0214] Referring to the drawings, a side surface EDL1 of the first dummy layer DMP1 may protrude more than a side surface EDL2 of the second dummy layer DMP2 , and a side surface EDL2 of the second dummy layer DMP2 may protrude more than a side surface EDL3 of the third dummy layer DMP3 .

[0215] In the drawings, although it is shown that the area on the plane of the first dummy layer DMP1 is larger than the area on the plane of the second dummy layer DMP2, and the area on the plane of the second dummy layer DMP2 is larger than the area on the plane of the third dummy layer DMP3, the area on the plane of the first dummy layer DMP1 may be smaller than the area on the plane of the second dummy layer DMP2, and is not limited to a certain embodiment.

[0216] Reference Fig. 9B , a side surface EDL1 of the first dummy layer DMP1a of the dummy pattern DMP may be covered by the second dummy layer DMP2a, and a side surface EDL2 of the second dummy layer DMP2a may be covered by the third dummy layer DMP3a.

[0217] The alignment relationship of the side surfaces EDL1 , EDL2 , EDL3 of the first to third dummy layers DMP1 a , DMP2 a , DMP3 a may be changed according to the process of forming each of the first to third dummy layers DMP1 a , DMP2 a , DMP3 a , and is not limited to a certain embodiment.

[0218] FIG. 10A to FIG. 10D FIG. 1 is a schematic diagram showing an arrangement relationship between bumps and dummy patterns DMP in a display device according to an embodiment of the present invention.

[0219] For ease of explanation, FIG. 10A to FIG. 10D The output pad OPD and the input pad IPD are omitted, and the omitted output pad OPD and the input pad IPD can be respectively overlapped with the output bump OPB and the input bump IPB on the plane.

[0220] Reference Fig. 10A , the first dummy pattern DMPa may include a plurality of dummy components DMPa1 and DMPa2. The first dummy pattern DMPa may include a plurality of 1-1st and 1-2nd dummy components DMPa1 and DMPa2. The 1-1st dummy component DMPa1 and the 1-2nd dummy component DMPa2 may be alternately arranged along the first direction DR1. In the second direction DR2, the 1-2nd dummy component DMPa2 may be displaced by a predetermined distance relative to the 1-1st dummy component DMPa1.

[0221] The second dummy pattern DMPb may include a plurality of dummy members DMPb. The plurality of dummy members DMPb may be arranged along the first direction DR1.

[0222] According to an embodiment of the present invention, the first bump OPB1 and the 1-1 dummy component DMPa1 may be aligned along a first alignment line AGL1 intersecting the first direction DR1. The second bump OPB2 and the 1-2 dummy component DMPa2 may be aligned along a second alignment line AGL2 intersecting the first direction DR1. The first alignment line AGL1 and the second alignment line AGL2 may be parallel to each other, but are not limited thereto, and may be directions intersecting each other, and are not limited to a certain embodiment.

[0223] A portion of the input bumps IPB may be aligned with the 2-1st dummy component DMPb1 or the 2-2nd dummy component DMPb2 along a third alignment line AGL3 or other alignment lines crossing the first direction DR1 .

[0224] The length of each dummy component DMPa1, DMPa2, DMPb1, DMPb2 in the first direction DR1 (the width of each dummy component) may be configured to be less than or equal to each bump OPB, IPB or each pad OPD, IPD (refer to Figure 5A ) in the first direction DR1 (the width of each bump or each pad).

[0225] After the pad PD (refer to Figure 5A ), the bumps PB and the dummy components DMPa1, DMPa2, DMPb1, and DMPb2 are arranged along the alignment line to align the driver chip DC (refer to Figure 4 ) to the display panel DP (refer to Figure 4 ) pressure, the configuration of the driver chip DC (refer to Figure 4 ) and display panel DP (refer to Figure 4 ) between the adhesive layer AF-D (reference Figure 4 ) can be easily removed from the chip area DCA (refer to Figure 4 ) expands from the inside to the outside.

[0226] Furthermore, by configuring the widths of the dummy members DMPa1, DMPa2, DMPb1, and DMPb2 to be smaller than the bumps PB and pads PD, it is possible to prevent the adhesion layer AF-D from being disturbed (see Figure 4 )Expand from the inside out.

[0227] Reference Fig. 10B A plurality of dummy patterns DMPa- 1 and DMPb- 1 may be provided, and some of the plurality of dummy patterns DMPa- 1 and DMPb- 1 may be arranged at intervals along the first direction DR1 .

[0228] According to an embodiment of the present invention, when viewed from the second direction DR2, one of the dummy patterns DMPa-1 and DMPb-1 may be aligned with the plurality of bumps PB or pads PD (see FIG. Figure 5A As shown in the figure, a dummy pattern DMPa-1 may overlap with multiple columns of the first bump OPB1 and multiple columns of the second bump OPB2, but is not limited thereto, and may overlap with one column of the first bump OPB1 and one column of the second bump OPB2, and is not limited to a certain embodiment.

[0229] Reference Fig. 10C , the first dummy pattern DMPa may include a plurality of dummy components DMPa1, DMPa2, DMPa3, and DMPa4. The first dummy pattern DMPa may include a plurality of 1-1 to 1-4 dummy components DMPa1, DMPa2, DMPa3, and DMPa4. The 1-1 dummy component DMPa1 and the 1-2 dummy component DMPa2 may be arranged alternately in the first direction DR1. The 1-3 dummy component DMPa3 and the 1-4 dummy component DMPa4 may be arranged alternately in the first direction DR1. The 1-3 dummy component DMPa3 may be arranged at a predetermined interval from the 1-1 dummy component DMPa1 in the second direction DR2, and the 1-4 dummy component DMPa4 may be arranged at a predetermined interval from the 1-2 dummy component DMPa2 in the second direction DR2.

[0230] The 1-2nd dummy component DMPa2 may be displaced by a predetermined distance in the second direction DR2 relative to the 1-1st dummy component DMPa1 , and the 1-4th dummy component DMPa4 may be displaced by a predetermined distance in the second direction DR2 relative to the 1-3rd dummy component DMPa3 .

[0231] The second dummy pattern DMPb may include a plurality of dummy components DMPb1 and DMPb2. The second dummy pattern DMPb may include a plurality of 2-1st and 2-2nd dummy components DMPb1 and DMPb2. The 2-1st dummy component DMPb1 and the 2-2nd dummy component DMPb2 may be arranged along the first direction DR1, respectively. The 2-2nd dummy component DMPb2 may be arranged at a predetermined interval from the 2-1st dummy component DMPb1 in the second direction DR2.

[0232] According to an embodiment of the present invention, the first bump OPB1, the 1-1st dummy component DMPa1, and the 1-3rd dummy component DMPa3 may be aligned along a first alignment line AGL1 intersecting the first direction DR1. The second bump OPB2, the 1-2nd dummy component DMPa2, and the 1-4th dummy component DMPa4 may be aligned along a second alignment line AGL2 intersecting the first direction DR1. The first alignment line AGL1 and the second alignment line AGL2 may be parallel to each other, but are not limited thereto, and may be directions intersecting each other, and are not limited to a certain embodiment.

[0233] The input bump IPB may be aligned with the 2-1st dummy component DMPb1 and the 2-2nd dummy component DMPb2 along a third alignment line AGL3 crossing the first direction DR1 .

[0234] After the pad PD (refer to Figure 4 ), the bumps PB and the dummy members DMP are arranged along the alignment lines to align the driver chip DC (refer to Figure 4 ) to the display panel DP (refer to Figure 4 ) pressure, the configuration of the driver chip DC (refer to Figure 4 ) and display panel DP (refer to Figure 4 ) between the adhesive layer AF-D (reference Figure 4 ) can be easily removed from the chip area DCA (refer to Figure 4 ) expands from the inside to the outside.

[0235] Reference Fig. 10D A plurality of dummy patterns DMPa- 2 and DMPb- 2 may be provided, and the plurality of dummy patterns DMPa- 2 and DMPb- 2 may be arranged at intervals in the second direction DR2 .

[0236] According to an embodiment of the present invention, when viewed from the second direction DR2, one of the dummy patterns DMPa-2 and DMPb-2 may be aligned with the plurality of bumps PB or pads PD (see Figure 4 ). Fig. 10B Compared with an embodiment of the present invention, Fig. 10D The embodiment may have a single pattern shape in which a plurality of dummy patterns DMPa-2, DMPb-2 arranged along the first direction DR1 are integrated in the first direction DR1.

[0237] Although the drawings show that only one first dummy pattern DMPa-2 and one second dummy pattern DMPb-2 are provided, the present invention is not limited thereto. Multiple dummy patterns may be provided in the first dummy pattern DMPa-2 and the second dummy pattern DMPb-2, and the present invention is not limited to a certain embodiment.

[0238] Although the above description is made with reference to the preferred embodiments of the present invention, it is understood by those skilled in the art or those of ordinary skill in the art that various modifications and changes may be made to the present invention without departing from the concept of the present invention and the technical scope of the present invention as described in the attached claims. Therefore, the technical scope of the present invention should not be limited to the contents described in the specific embodiments of the specification, but should be defined by the attached claims.

Claims

1. A display device, in, include: The display panel comprises a plurality of pixels, a first row of output pads, a second row of output pads and an input pad, wherein the first row of output pads are electrically connected to the pixels and the first row of output pads are arranged along a first direction, the second row of output pads are spaced apart from the first row of output pads in a second direction intersecting the first direction, and the input pads are spaced apart from the second row of output pads in the second direction and are arranged along the first direction; A driving chip, comprising a first row of output bumps, a second row of output bumps and an input bump, wherein the first row of output bumps are arranged along the first direction and connected to the first row of output pads, the second row of output bumps are separated from the first row of output bumps by a first distance in the second direction and connected to the second row of output pads, and the input bumps are separated from the second row of output bumps by a gap in the second direction and connected to the input pads; as well as The dummy pattern is arranged between the second row output pads and the input pads on a plane, is connected to the display panel and the driving chip respectively, and includes an insulating material.

2. The display device according to claim 1, wherein: The dummy pattern is spaced apart from the second row of output bumps by a second distance in the second direction, and the second distance is greater than the first distance.

3. The display device according to claim 1, wherein: The first row of output bumps and the second row of output bumps respectively include: a plurality of first bumps aligned along the first direction; and A plurality of second bumps are aligned along the first direction and are configured to be displaced from the first bumps by a third distance in the second direction, wherein the third distance is smaller than the first distance.

4. The display device according to claim 3, wherein: The dummy pattern comprises: a plurality of first dummy components aligned along the first direction; and A plurality of second dummy components are aligned along the first direction and are configured to be displaced from the first dummy components by a predetermined distance in the second direction.

5. The display device according to claim 1, wherein: The virtual patterns are provided in plurality. A plurality of the dummy patterns are arranged along the second direction, At least one dummy pattern among the plurality of dummy patterns is disposed closer to the input pad than the second-row output pad.

6. The display device according to claim 1, wherein: The dummy patterns are provided in plurality. When viewed from the second direction, one of the dummy patterns overlaps a plurality of pads.

7. The display device according to claim 1, wherein: Also includes an input sensor configured on the display panel, The display panel and the input sensor respectively include: A first insulating layer, a second insulating layer, and a third insulating layer stacked in sequence in a thickness direction; A first conductive layer is disposed between the first insulating layer and the second insulating layer; and A second conductive layer is disposed between the second insulating layer and the third insulating layer, The dummy pattern comprises: A first dummy layer, comprising the same material as the first insulating layer of the display panel; a second dummy layer, disposed on the first dummy layer and comprising the same material as the second insulating layer of the display panel; and The third dummy layer is disposed on the second dummy layer and includes the same material as the third insulating layer of the input sensor.

8. The display device according to claim 7, wherein: On the side surfaces of the first dummy layer to the third dummy layer, a step is defined between the side surfaces of two adjacent dummy layers.

9. A display device, in, include: The display panel comprises a plurality of pixels, a first row of output pads, a second row of output pads and an input pad, wherein the first row of output pads are electrically connected to the pixels and the first row of output pads are arranged along a first direction, the second row of output pads are spaced apart from the first row of output pads in a second direction intersecting the first direction, and the input pads are spaced apart from the second row of output pads in the second direction and are arranged along the first direction; A driving chip, comprising a first row of output bumps, a second row of output bumps and an input bump, wherein the first row of output bumps are arranged along the first direction and connected to the first row of output pads, the second row of output bumps are separated from the first row of output bumps by a first distance in the second direction and connected to the second row of output pads, and the input bumps are separated from the second row of output bumps by a gap in the second direction and connected to the input pads; as well as The dummy pattern is arranged between the second row of output pads and the input pads on a plane, and is connected to the display panel and the driving chip respectively. The dummy pattern is spaced apart from the second row of output bumps by a second distance in the second direction, and the second distance is greater than the first distance.

10. The display device according to claim 9, wherein: The dummy pattern includes a plurality of dummy components. The dummy component comprises: a plurality of first dummy components aligned along the first direction; and A plurality of second dummy components are aligned along the first direction and are configured to be displaced from the first dummy components by a predetermined distance in the second direction.

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