Signal transmission circuits and electronic equipment

Abstract

The present application discloses a signal transmission circuit and an electronic device, and relates to the field of circuit technology. The signal transmission circuit includes a sending unit, a first receiving unit, and a second receiving unit. The sending unit is connected to a preset node through a first wire group, the first receiving unit is connected to a preset node through a second wire group, and the second receiving unit is connected to a preset node through a third wire group. Among them, the impedance of the first receiving unit and the impedance of the second receiving unit are both greater than the impedance of the sending unit, and the impedance between the second wire group and the first receiving unit is matched, and the impedance between the third wire group and the second receiving unit is matched, which can increase the voltage of the signal received by the first receiving unit and the second receiving unit in parallel, thereby improving the quality of the signal received by the first receiving unit and the second receiving unit.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a signal transmission circuit and an electronic device. Background Art

[0002] Electronic devices such as mobile phones, tablet computers, and laptops include system-level chips, display driver chips, and display screens. The display driver chip is connected between the system-level chip and the display screen to receive data signals output by the system-level chip and drive the display screen to display images.

[0003] In the related art, in order to realize the high resolution and high refresh rate characteristics of the display screen, the electronic device may include two display driver chips. Both display driver chips are connected between the system-level chip and the display screen, and the two display driver chips need to work simultaneously to jointly receive the data signal output by the system-level chip and drive the display screen to display images.

[0004] However, when the system-level chip has only one signal output terminal for connecting to the display driver chip, the two display driver chips need to be connected to one node with the signal output terminal of the system-level chip. In this case, the connection between the two display driver chips is in parallel, which will cause the voltage of the data signal received by each display driver chip to become smaller, affecting the quality of the data signal received by the display driver chip. Summary of the invention

[0005] The present application provides a signal transmission circuit and an electronic device, which can improve the quality of the signal received by the display driver chip when the connection between two display driver chips in the electronic device is in parallel. The technical solution is as follows:

[0006] In a first aspect, a signal transmission circuit is provided. The signal transmission circuit is applied to an electronic device and includes a transmitting unit, a first receiving unit and a second receiving unit.

[0007] The sending unit has a signal output terminal for sending signals. The sending unit can be a system-level chip in an electronic device, or an electrical component with a signal sending function composed of some electrical components in the system-level chip. The first receiving unit and the second receiving unit both have an input terminal for receiving signals. The first receiving unit and the second receiving unit can be a display driver chip in an electronic device, or an electrical component with a signal receiving function composed of some electrical components in the display driver chip.

[0008] The signal output end of the sending unit is connected to the preset node through the first wire group, the input end of the first receiving unit is connected to the preset node through the second wire group, and the input end of the second receiving unit is connected to the preset node through the third wire group. That is to say, the input ends of the two receiving units and the output end of the sending unit are connected to one node, and the connection between the two receiving units is in parallel. Here, the impedance of the sending unit, the impedance of the first receiving unit, and the impedance of the second receiving unit need to meet the following conditions: the impedance of the first receiving unit is greater than the impedance of the sending unit, and the impedance of the second receiving unit is greater than the impedance of the sending unit. In addition, the impedance of the second wire group needs to meet the following conditions: the difference between the impedance of the second wire group and the impedance of the first receiving unit is within the first impedance range. The impedance of the third wire group needs to meet the following conditions: the difference between the impedance of the third wire group and the impedance of the second receiving unit is within the second impedance range.

[0009] In the present application, the signal transmission circuit includes a sending unit, a first receiving unit and a second receiving unit. The sending unit is connected to a preset node through a first wire group, the first receiving unit is connected to a preset node through a second wire group, and the second receiving unit is connected to a preset node through a third wire group, so that the sending unit can send a signal to the first receiving unit and the second receiving unit. In an embodiment of the present application, the impedance of the first receiving unit and the impedance of the second receiving unit are both greater than the impedance of the sending unit. Since in the related art, the impedance of the first receiving unit, the impedance of the second receiving unit and the impedance of the sending unit are all equal, the present application increases the voltage of the signal received by the first receiving unit and the second receiving unit in parallel by increasing the impedance of the first receiving unit and the impedance of the second receiving unit, thereby improving the quality of the signal received by the first receiving unit and the second receiving unit. In addition, the difference between the impedance of the second wire group and the impedance of the first receiving unit is within the first impedance range, so that the impedance between the connected second wire group and the first receiving unit is matched, which can avoid the formation of signal reflection when the signal is transmitted from the second wire group to the first receiving unit, thereby improving the quality of the signal received by the first receiving unit. Similarly, the difference between the impedance of the third wire group and the impedance of the second receiving unit is within the second impedance range, which can also enable impedance matching between the connected third wire group and the second receiving unit, thereby improving the quality of the signal received by the second receiving unit.

[0010] In the signal transmission circuit provided in the present application, the transmitting unit and the first receiving unit and the second receiving unit can be connected via an interface using the MIPI_D-PHY protocol or via an interface using the MIPI_C-PHY protocol. These two situations are described below.

[0011] In the first case, the transmitting unit is connected to the first receiving unit and the second receiving unit via an interface using the MIPI_D-PHY protocol.

[0012] In this case, the sending unit may include a first impedance device and a second impedance device. The first receiving unit includes a third impedance device and a fourth impedance device. The second receiving unit includes a fifth impedance device and a sixth impedance device. The preset node includes a first node and a second node. The first wire group includes a first wire and a second wire. The second wire group includes a third wire and a fourth wire. The third wire group includes a fifth wire and a sixth wire.

[0013] Among them, the first end of the first impedance device can be connected to one of the preset voltage terminal and the ground wire. The second end of the first impedance device is connected to the first node through the first wire. The first end of the third impedance device is connected to the first node through the third wire. The second end of the third impedance device is connected to the second end of the fourth impedance device. The first end of the fifth impedance device is connected to the first node through the fifth wire. The second end of the fifth impedance device is connected to the second end of the sixth impedance device. The first end of the second impedance device can be connected to one of the preset voltage terminal and the ground wire. The second end of the second impedance device is connected to the second node through the second wire. The first end of the fourth impedance device is connected to the second node through the fourth wire. The first end of the sixth impedance device is connected to the second node through the sixth wire.

[0014] Based on the circuit structure, the impedance of the first receiving unit is greater than the impedance of the transmitting unit, which means that the sum of the impedance of the third impedance device plus the impedance of the fourth impedance device is greater than the sum of the impedance of the first impedance device plus the impedance of the second impedance device. The impedance of the second receiving unit is greater than the impedance of the transmitting unit, which means that the sum of the impedance of the fifth impedance device plus the impedance of the sixth impedance device is greater than the sum of the impedance of the first impedance device plus the impedance of the second impedance device.

[0015] In some embodiments, in the transmitting unit, the impedance of the first impedance device is equal to the impedance of the second impedance device. In the first receiving unit, the impedance of the third impedance device is equal to the impedance of the fourth impedance device. In the second receiving unit, the impedance of the fifth impedance device is equal to the impedance of the sixth impedance device. In this case, the impedance of the third impedance device = the impedance of the fourth impedance device > the impedance of the first impedance device = the impedance of the second impedance device; and the impedance of the fifth impedance device = the impedance of the sixth impedance device > the impedance of the first impedance device = the impedance of the second impedance device.

[0016] In some embodiments, the impedance of the third impedance device is greater than or equal to 1.2 times the impedance of the first impedance device, and less than or equal to 2 times the impedance of the first impedance device. The impedance of the fifth impedance device is also greater than or equal to 1.2 times the impedance of the first impedance device, and less than or equal to 2 times the impedance of the first impedance device. For example, if the impedance of the first impedance device is 50 ohms, the impedance of the third impedance device is between 60 ohms and 100 ohms (including the end value), and the impedance of the fifth impedance device is also between 60 ohms and 100 ohms (including the end value). In some specific embodiments, the impedance of the third impedance device and the impedance of the fifth impedance device are both twice the impedance of the first impedance device.

[0017] Based on the circuit structure, the first impedance range may include a first impedance sub-range and a second impedance sub-range, and the second impedance range may include a third impedance sub-range and a fourth impedance sub-range.

[0018] The difference between the impedance of the second conductor group and the impedance of the first receiving unit is within the first impedance range, which means that the difference between the characteristic impedance of the third conductor and the impedance of the third impedance device is within the first impedance sub-range, and the difference between the characteristic impedance of the fourth conductor and the impedance of the fourth impedance device is within the second impedance sub-range. The minimum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and -10%, and the maximum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and 10%. The minimum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and -10%, and the maximum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and 10%.

[0019] The difference between the impedance of the third conductor group and the impedance of the second receiving unit is within the second impedance range, which means that the difference between the characteristic impedance of the fifth conductor and the impedance of the fifth impedance device is within the third impedance sub-range, and the difference between the characteristic impedance of the sixth conductor and the impedance of the sixth impedance device is within the fourth impedance sub-range. The minimum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and -10%, and the maximum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and 10%. The minimum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and -10%, and the maximum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and 10%.

[0020] Based on the circuit structure, the difference between the impedance of the first wire group and the impedance of the sending unit is within the third impedance range. In other words, the impedances of the connected first wire group and the sending unit are matched.

[0021] Specifically, the third impedance range may include a fifth impedance sub-range and a sixth impedance sub-range. The difference between the impedance of the first conductor group and the impedance of the transmitting unit within the third impedance range means that: the difference between the characteristic impedance of the first conductor and the impedance of the first impedance device is within the fifth impedance sub-range, and the difference between the characteristic impedance of the second conductor and the impedance of the second impedance device is within the sixth impedance sub-range. The minimum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and -10%, and the maximum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and 10%. The minimum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and -10%, and the maximum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and 10%.

[0022] From the above description, it can be seen that the characteristic impedance of the first conductor is less than the characteristic impedance of the third conductor, and the characteristic impedance of the first conductor is less than the characteristic impedance of the fifth conductor. Based on this, on the printed circuit board of the electronic device, the width of the first conductor can be greater than the width of the third conductor, and the width of the first conductor can be greater than the width of the fifth conductor. Similarly, the characteristic impedance of the second conductor is less than the characteristic impedance of the fourth conductor, and the characteristic impedance of the second conductor is less than the characteristic impedance of the sixth conductor. Based on this, on the printed circuit board of the electronic device, the width of the second conductor can be greater than the width of the fourth conductor, and the width of the second conductor can be greater than the width of the sixth conductor.

[0023] In the second case, the transmitting unit is connected to the first receiving unit and the second receiving unit through an interface using the MIPI_C-PHY protocol.

[0024] In this case, the sending unit may include a first impedance device, a second impedance device, and a seventh impedance device. The first receiving unit includes a third impedance device, a fourth impedance device, and an eighth impedance device. The second receiving unit includes a fifth impedance device, a sixth impedance device, and a ninth impedance device. The preset node includes a first node, a second node, and a third node. The first wire group includes a first wire, a second wire, and a seventh wire. The second wire group includes a third wire, a fourth wire, and an eighth wire. The third wire group includes a fifth wire, a sixth wire, and a ninth wire.

[0025] Among them, the first end of the first impedance device can be connected to one of the preset voltage terminal and the ground wire. The second end of the first impedance device is connected to the first node through the first wire. The first end of the third impedance device is connected to the first node through the third wire. The second end of the third impedance device is connected to the second end of the fourth impedance device and the second end of the eighth impedance device. The first end of the fifth impedance device is connected to the first node through the fifth wire. The second end of the fifth impedance device is connected to the second end of the sixth impedance device and the second end of the ninth impedance device. The first end of the second impedance device can be connected to one of the preset voltage terminal and the ground wire. The second end of the second impedance device is connected to the second node through the second wire. The first end of the fourth impedance device is connected to the second node through the fourth wire. The first end of the sixth impedance device is connected to the second node through the sixth wire. The first end of the seventh impedance device can be connected to one of the preset voltage terminal and the ground wire. The second end of the seventh impedance device is connected to the third node through the seventh wire. The first end of the eighth impedance device is connected to the third node through the eighth wire. The first end of the ninth impedance device is connected to the third node through the ninth wire.

[0026] In some embodiments, in the transmitting unit, the impedance of the seventh impedance device, the impedance of the first impedance device, and the impedance of the second impedance device are all equal. In the first receiving unit, the impedance of the eighth impedance device, the impedance of the third impedance device, and the impedance of the fourth impedance device are all equal. In the second receiving unit, the impedance of the ninth impedance device, the impedance of the fifth impedance device, and the impedance of the sixth impedance device are all equal.

[0027] At the same time, the impedance of any impedance device in the first receiving unit is greater than the impedance of any impedance device in the sending unit, and the impedance of any impedance device in the second receiving unit is greater than the impedance of any impedance device in the sending unit.

[0028] In some embodiments, the impedance of the eighth impedance device is greater than or equal to 1.2 times the impedance of the seventh impedance device, and less than or equal to 2 times the impedance of the seventh impedance device. The impedance of the ninth impedance device is also greater than or equal to 1.2 times the impedance of the seventh impedance device, and less than or equal to 2 times the impedance of the seventh impedance device. For example, if the impedance of the seventh impedance device is 50 ohms, the impedance of the eighth impedance device is between 60 ohms and 100 ohms (including the end value), and the impedance of the ninth impedance device is also between 60 ohms and 100 ohms (including the end value). In some specific embodiments, the impedance of the eighth impedance device and the impedance of the ninth impedance device are both twice the impedance of the seventh impedance device.

[0029] Based on this circuit structure, the first impedance range may further include a seventh impedance sub-range, and the second impedance range may further include an eighth impedance sub-range.

[0030] The difference between the impedance of the second wire group and the impedance of the first receiving unit is within the first impedance range, and further includes: the difference between the characteristic impedance of the eighth wire and the impedance of the eighth impedance device is within the seventh impedance sub-range. The minimum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and -10%, and the maximum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and 10%.

[0031] The difference between the impedance of the third wire group and the impedance of the second receiving unit is within the second impedance range, and the difference between the characteristic impedance of the ninth wire and the impedance of the ninth impedance device is within the eighth impedance sub-range. The minimum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and -10%, and the maximum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and 10%.

[0032] Based on the circuit structure, the third impedance range may further include a ninth impedance sub-range. The difference between the impedance of the first conductor group and the impedance of the transmitting unit in the third impedance range also includes: the difference between the characteristic impedance of the seventh conductor and the impedance of the seventh impedance device in the ninth impedance sub-range. The minimum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and -10%, and the maximum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and 10%.

[0033] In a second aspect, an electronic device is also provided, comprising a signal transmission circuit as described in any one of the first aspects.

[0034] The technical effect obtained by the above-mentioned second aspect is similar to the technical effect obtained by the corresponding technical means in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the appearance of the first electronic device in the related art;

[0036] Figure 2 It is a schematic diagram of the appearance of a second electronic device in the related art;

[0037] Figure 3 It is a schematic diagram of the internal structure of the first electronic device in the related art;

[0038] Figure 4 It is a schematic diagram of the internal structure of a second electronic device in the related art;

[0039] Figure 5 It is a structural schematic diagram of the first signal transmission circuit in the related art;

[0040] Figure 6 It is a schematic diagram of the first data transmission process from SOC to DDIC in the related art;

[0041] Figure 7 It is a schematic diagram of the internal structure of a third electronic device in the related art;

[0042] Figure 8 It is a structural schematic diagram of a second signal transmission circuit in the related art;

[0043] Fig. 9 It is a schematic diagram of the second data transmission process from SOC to DDIC in the related art;

[0044] Fig.10 It is a simulation circuit diagram of the first signal transmission circuit in the related art;

[0045] Fig.11 It is a circuit diagram of the first signal transmission circuit in the related art;

[0046] Fig.12 It is a simulation circuit diagram of the second signal transmission circuit in the related art;

[0047] Fig.13 It is a circuit diagram of a third signal transmission circuit in the related art;

[0048] Fig.14 is a circuit diagram of a fourth signal transmission circuit in the related art;

[0049] Fig.15 is a circuit diagram of a fifth signal transmission circuit in the related art;

[0050] Fig.16 It is a diagram of impedance test results of a simulation circuit of a signal transmission circuit in the related art;

[0051] Fig.17 yes Fig.11 The eye diagram of the signal transmission circuit shown when performing signal transmission;

[0052] Fig.18 yes Fig.13 The eye diagram of the signal transmission circuit shown when performing signal transmission;

[0053] Fig.19 is a structural schematic diagram of a signal transmission circuit provided in an embodiment of the present application;

[0054] Fig. 20 is a circuit structure diagram of a first signal transmission circuit provided in an embodiment of the present application;

[0055] Fig.21 It is an impedance diagram of a first signal transmission circuit provided in an embodiment of the present application;

[0056] Fig. 22is a schematic diagram of a wire in a first signal transmission circuit provided in an embodiment of the present application;

[0057] Fig.23 This is an eye diagram of the first signal transmission circuit provided in an embodiment of the present application when performing signal transmission;

[0058] Fig.24 This is an eye diagram of the second signal transmission circuit provided in an embodiment of the present application when performing signal transmission;

[0059] Fig.25 This is an eye diagram of the third signal transmission circuit provided in an embodiment of the present application when performing signal transmission;

[0060] Fig.26 This is an eye diagram of the fourth signal transmission circuit provided in an embodiment of the present application when performing signal transmission;

[0061] Fig. 27 This is an eye diagram of the fifth signal transmission circuit provided in an embodiment of the present application when performing signal transmission;

[0062] Fig.28 This is an eye diagram of the sixth signal transmission circuit provided in an embodiment of the present application when performing signal transmission;

[0063] Fig.29 is a circuit structure diagram of a second signal transmission circuit provided in an embodiment of the present application;

[0064] Fig.30 is an impedance diagram of a second signal transmission circuit provided in an embodiment of the present application;

[0065] Fig.31 is a schematic diagram of a wire in a second signal transmission circuit provided in an embodiment of the present application;

[0066] Fig.32 It is a circuit structure diagram of the third signal transmission circuit provided in an embodiment of the present application.

[0067] The meanings of the figures are as follows:

[0068] Related technologies:

[0069] 10. electronic device; 102. total data signal; 1022. first data signal; 1023. first decompressed signal; 1024. second data signal; 1025. second decompressed signal; 12. signal transmission circuit; 110. display device; 112. display screen;

[0070] This application:

[0071] 20. signal transmission circuit; 210. transmitting unit; 212. first impedance device; 214. second impedance device; 216. seventh impedance device; 220. first receiving unit; 222. third impedance device; 224. fourth impedance device; 226. eighth impedance device; 230. second receiving unit; 232. fifth impedance device; 234. sixth impedance device; 236. ninth impedance device; 240. first wire group; 242. first wire; 244. second wire; 246. seventh wire; 250. second wire group; 252. third wire; 254. fourth wire; 256. eighth wire; 260. third wire group; 262. fifth wire; 264. sixth wire; 266. ninth wire. DETAILED DESCRIPTION

[0072] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0073] It should be understood that the "multiple" mentioned in this application refers to two or more. In the description of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of this application, the words "first" and "second" are used to distinguish between the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first" and "second" do not limit the quantity and execution order, and the words "first" and "second" do not limit them to be different.

[0074] Before explaining the signal transmission circuit provided in the embodiment of the present application in detail, the application scenarios and related technologies of the signal transmission circuit are first explained.

[0075] Electronic devices include mobile phones, tablets, laptops, etc. Figure 1 and Figure 2 1 is a schematic diagram of the appearance of two different electronic devices 10 in the related art. Figure 1 In the embodiment shown, the electronic device 10 is a mobile phone. Figure 2 In the embodiment shown, the electronic device 10 is a tablet computer. Figure 1 and Figure 2 As shown, the electronic device 10 has a display screen 112 for displaying images.

[0076] Figure 3 1 is a schematic diagram of the internal structure of an electronic device 10 in the related art. Figure 3 As shown, the electronic device 10 includes a system on chip (SOC) and a display device 110. The display device 110 includes a display driver integrated circuit (DDIC) and a display screen 112. The DDIC is connected between the SOC and the display screen 112. When the electronic device 10 is working, the DDIC can receive a data signal output by the SOC, and decompress the data signal to obtain a decompressed signal. The DDIC can also drive the display screen 112 to work according to the decompressed signal, so that the display screen 112 displays an image.

[0077] At present, the mobile industry processor interface (MIPI) protocol is a high-speed digital transmission protocol, which is usually used in the connection between the display device 110, camera and other devices of the electronic device 10 and the SOC. In the MIPI protocol, the display serial interface (DSI) protocol is an interface standard designed for the display device 110, which adopts the D-physical layer (PHY) or C-PHY underlying transmission protocol. That is to say, in the related art, the MIPI_D-PHY protocol or MIPI_C-PHY protocol is used to transmit communication signals between the SOC and the DDIC of the display device 110. Among them, the interface using the MIPI_D-PHY protocol is composed of 1 group of clock differential lines and 4 groups of data differential lines, the clock differential line is used to transmit the clock signal, and the data differential line is used to transmit the data signal; the interface using the MIPI_C-PHY protocol is composed of three groups of signal lines, each group of signal lines includes three signal lines, and the three signal lines in each group of signal lines are used to transmit clock signals and data signals.

[0078] In the related art, in order to realize the high resolution and high refresh rate characteristics of the display screen 112 of the electronic device 10 such as a mobile phone or a tablet computer, the entire signal transmission link needs to be able to support sufficient data bandwidth. For example, if the display screen 112 of the electronic device 10 needs to realize a 2K resolution and a 120 Hz (hertz) refresh rate, the entire signal transmission link needs to be able to support a data bandwidth of 8.29 Gbps (gigabits per second).

[0079] However, limited by factors such as the design cost and resources of the electronic device 10, the DDIC of the electronic device 10 often only supports the V1.1 standard of the MIPI_D-PHY protocol or the V1.0 standard of the MIPI_C-PHY protocol. Among them, for the V1.1 standard of the MIPI_D-PHY protocol, the maximum transmission rate of each group of data differential lines is 1.2 Gbps. Therefore, the maximum transmission rate of the interface using the MIPI_D-PHY protocol with 4 groups of data differential lines is 4.8 Gbps, which does not reach 8.29 Gbps. For the V1.0 standard of the MIPI_C-PHY protocol, the maximum transmission rate of each group of signal lines is 1.1 Gsps (gigabyte symbols per second), that is, about 2.5 Gbps. Therefore, the maximum transmission rate of the interface using the MIPI_C-PHY protocol with three groups of signal lines is 7.5 Gbps, which also does not reach 8.29 Gbps. Based on this, in this case, in order to enable the display screen 112 to achieve a 2K resolution and a 120Hz refresh rate, two DDICs need to be provided in the electronic device 10. Both DDICs are connected between the SOC and the display screen 112, and the two DDICs need to work simultaneously to jointly receive the data signal output by the SOC and drive the display screen 112 to display an image.

[0080] However, in the related art, the SOC may have two signal output terminals for connecting to the DDIC, or may have only one signal output terminal for connecting to the DDIC. When the SOC has two signal output terminals for connecting to the DDIC, the internal structure diagram of the electronic device 10 may be as follows: Figure 4 In this case, the signal transmission link from the SOC to the DDIC in the electronic device 10 (hereinafter referred to as the "signal transmission circuit 12") can be as follows Figure 5 As shown in Figure 2, the data transmission process from SOC to DDIC can be as follows: Figure 6 See Figures 4 to 6It can be seen that the SOC has two signal output terminals, namely the signal output terminal P1 and the signal output terminal P2; the electronic device 10 has two DDICs, namely DDIC1 and DDIC2. Among them, DDIC1 is connected between the signal output terminal P1 of the SOC and the display screen 112, and DDIC2 is connected between the signal output terminal P2 of the SOC and the display screen 112. When the electronic device 10 is working, the signal output terminal P1 of the SOC is used to output the first data signal 1022 to DDIC1. After receiving the first data signal 1022, DDIC1 can decompress the first data signal 1022 to obtain a first decompressed signal 1023. DDIC1 is also used to drive the upper half screen or the left half screen of the display screen 112 to work according to the first decompressed signal 1023. The signal output terminal P2 of the SOC is used to output the second data signal 1024 to DDIC2. After receiving the second data signal 1024, DDIC2 can decompress the second data signal 1024 to obtain a second decompressed signal 1025. DDIC2 is further used to drive the lower half screen or the right half screen of the display screen 112 to operate according to the second decompressed signal 1025 .

[0081] When the SOC has only one signal output terminal for connecting to the DDIC, the internal structure diagram of the electronic device 10 may be as follows: Figure 7 In this case, the signal transmission circuit 12 can be as shown. Figure 8 As shown in Figure 2, the data transmission process from SOC to DDIC can be as follows: Fig. 9 See Figures 7 to 9 It can be seen that the SOC has only one signal output terminal P0; the electronic device 10 has two DDICs, namely DDIC1 and DDIC2. Among them, DDIC1 and DDIC2 are both connected between the signal output terminal P0 of the SOC and the display screen 112. When the electronic device 10 is working, the signal output terminal P0 of the SOC is used to output the total data signal 102 to DDIC1 and DDIC2, and the total data signal 102 includes a first data signal 1022 and a second data signal 1024. After receiving the total data signal 102, DDIC1 only decompresses the first data signal 1022 to obtain a first decompressed signal 1023. DDIC1 is also used to drive the upper half screen or the left half screen of the display screen 112 to work according to the first decompressed signal 1023. After receiving the total data signal 102, DDIC2 only decompresses the second data signal 1024 to obtain a second decompressed signal 1025. DDIC2 is also used to drive the lower half screen or the right half screen of the display screen 112 to work according to the second decompressed signal 1025.

[0082] for Figures 7 to 9In the case shown, the problem in the related art is that since both DDIC1 and DDIC2 need to be connected to the signal output terminal P0 of the SOC, the connection between DDIC1 and DDIC2 is in parallel. In this case, due to the effect of parallel voltage division, the voltage of the data signal received by each DDIC (including DDIC1 and DDIC2) will become smaller, thereby affecting the quality of the data signal received by the DDIC.

[0083] The following is a detailed explanation of the problems existing in the above-mentioned related technologies for the interface using the MIPI_D-PHY protocol and the interface using the MIPI_C-PHY protocol.

[0084] 1. In the first case, the SOC and the DDIC are connected via an interface using the MIPI_D-PHY protocol. In this case, when the signal output terminal P0 of the SOC is connected to only one DDIC, the simulation circuit diagram of the signal transmission circuit 12 can be as follows: Fig.10 See Fig.10 , SOC includes five transmitting units TX, namely TX1, TX2, TX3, TX4, and TX5. One of the five transmitting units TX is used to send a clock signal, and the other four are used to send a data signal. DDIC includes five receiving units RX, namely RX1, RX2, RX3, RX4, and RX5. Similarly, one of the five receiving units RX is used to receive a clock signal, and the other four are used to receive a data signal. Based on Fig.10 The circuit diagram of the signal transmission circuit 12 formed by any transmitting unit TX and the corresponding receiving unit RX can be as shown in the simulation circuit shown in FIG. Fig.11 See Fig.11 , the sending unit TX includes a resistor Rp and a resistor Rn, the first end of the resistor Rp is used to be connected to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rp is connected to the first sub-port P01. The first end of the resistor Rn is used to be connected to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rn is connected to the second sub-port P02. Among them, the signal output terminal P0 of the SOC has multiple sub-ports, and the first sub-port P01 and the second sub-port P02 are both one of the sub-ports of the signal output terminal P0 of the SOC. The receiving unit RX includes a resistor RL1 and a resistor RL2. The first end of the resistor RL1 is used to be connected to the first sub-port P01, the second end of the resistor RL1 is connected to the second end of the resistor RL2, and the first end of the resistor RL2 is used to be connected to the second sub-port P02.

[0085] In the signal transmission circuit 12, the impedances of the resistors Rp, Rn, RL1, and RL2 are all 50Ω (ohms). When the signal transmission circuit 12 is working, if the first end of the resistor Rp is connected to the common voltage terminal VCOM, the first end of the resistor Rn is connected to the ground line GND. Taking the voltage of the common voltage terminal VCOM as 400mV (millivolts) as an example, the voltage difference between the first end of the resistor RL1 and the first end of the resistor RL2 at this time can be obtained as:

[0086]

[0087] Among them, V RX is the voltage of the signal received by the receiving unit RX, V com is the voltage of the common voltage terminal VCOM, R L1 is the impedance of resistor RL1, R L2 is the impedance of resistor RL2, R p is the impedance of resistor Rp, R n is the impedance of the resistor Rn. That is to say, at this time, the voltage difference between the first end of the resistor RL1 and the first end of the resistor RL2 is 200mV, and the voltage of the first end of the resistor RL1 is greater than the voltage of the first end of the resistor RL2. In this case, the voltage of the signal received by the receiving unit RX is +200mV, the first end of the resistor RL1 receives a high level signal, and the first end of the resistor RL2 receives a low level signal.

[0088] On the contrary, when the signal transmission circuit 12 is working, if the first end of the resistor Rp is connected to the ground line GND, the first end of the resistor Rn is connected to the common voltage terminal VCOM. Taking the voltage of the common voltage terminal VCOM as 400mV (millivolts) as an example, it can be obtained that: at this time, the voltage difference between the first end of the resistor RL1 and the first end of the resistor RL2 is 200mV, and the voltage of the first end of the resistor RL1 is less than the voltage of the first end of the resistor RL2. In this case, the voltage of the signal received by the receiving unit RX is -200mV, the first end of the resistor RL1 receives a low-level signal, and the first end of the resistor RL2 receives a high-level signal.

[0089] However, when the signal output terminal P0 of the SOC is connected to two DDICs, the simulation circuit diagram of the signal transmission circuit 12 may be as follows: Fig.12 See Fig.12, SOC includes five transmitting units TX, namely TX1, TX2, TX3, TX4, and TX5. One of the five transmitting units TX is used to send a clock signal, and the other four are used to send data signals. DDIC1 includes five receiving units RXA, namely RXA1, RXA2, RXA3, RXA4, and RXA5. One of the five receiving units RXA is used to receive a clock signal, and the other four are used to receive data signals. DDIC2 also includes five receiving units RXB, namely RXB1, RXB2, RXB3, RXB4, and RXB5. Each transmitting unit TX is connected to a receiving unit RXA in DDIC1, and to a receiving unit RXB in DDIC2. Based on Fig.12 The circuit diagram of the signal transmission circuit 12 formed by any one transmitting unit TX and two correspondingly connected receiving units RX can be as shown in FIG. Fig.13 See Fig.13 , the transmitting unit TX includes a resistor Rp and a resistor Rn, the first end of the resistor Rp is used to be connected to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rp is connected to the first sub-port P01. The first end of the resistor Rn is used to be connected to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rn is connected to the second sub-port P02. Among them, the signal output terminal P0 of the SOC has multiple sub-ports, and the first sub-port P01 and the second sub-port P02 are both one of the sub-ports of the signal output terminal P0 of the SOC. The receiving unit RXA in DDIC1 includes a resistor RL1 and a resistor RL2. The first end of the resistor RL1 is used to be connected to the first sub-port P01, the second end of the resistor RL1 is connected to the second end of the resistor RL2, and the first end of the resistor RL2 is used to be connected to the second sub-port P02. The receiving unit RXB in DDIC2 includes a resistor RL3 and a resistor RL4. The first end of the resistor RL3 is connected to the first sub-port P01, the second end of the resistor RL3 is connected to the second end of the resistor RL4, and the first end of the resistor RL4 is connected to the second sub-port P02. The node connected by the first end of the resistor RL1, the first sub-port P01, and the first end of the resistor RL3 is called node 1, and the node connected by the first end of the resistor RL2, the second sub-port P02, and the first end of the resistor RL4 is called node 2.

[0090] In the signal transmission circuit 12, the impedances of the resistors Rp, Rn, RL1, RL2, RL3 and RL4 are all 50Ω. Then the impedance between the node 1 and the node 2 can be obtained as:

[0091] Where R is the impedance between node 1 and node 2, R L3 is the impedance of resistor RL3, R L4is the impedance of resistor RL4.

[0092] When the signal transmission circuit 12 is working, if the first end of the resistor Rp is connected to the common voltage terminal VCOM, the first end of the resistor Rn is connected to the ground line GND. Taking the voltage of the common voltage terminal VCOM as 400mV (millivolts) as an example, the voltage difference between the node 1 and the node 2 at this time can be obtained as:

[0093] Among them, V 12 is the voltage difference between node 1 and node 2. That is to say, at this time, the voltage difference between node 1 and node 2 is 133mV, and the voltage of node 1 is greater than the voltage of node 2. In this case, the voltage of the signal received by the receiving unit RXA and the receiving unit RXB is +133mV, the first end of the resistor RL1 and the first end of the resistor RL3 both receive a high-level signal, and the first end of the resistor RL2 and the first end of the resistor RL4 both receive a low-level signal.

[0094] On the contrary, when the signal transmission circuit 12 is working, if the first end of the resistor Rp is connected to the ground line GND, the first end of the resistor Rn is connected to the common voltage terminal VCOM. Taking the voltage of the common voltage terminal VCOM as 400mV (millivolts) as an example, it can be obtained that: at this time, the voltage difference between node 1 and node 2 is 133mV, and the voltage of node 1 is less than the voltage of node 2. In this case, the voltage of the signal received by the receiving unit RXA and the receiving unit RXB is -133mV, the first end of the resistor RL1 and the first end of the resistor RL3 both receive low-level signals, and the first end of the resistor RL2 and the first end of the resistor RL4 both receive high-level signals.

[0095] From the above analysis, it can be seen that for the interface using the MIPI_D-PHY protocol, when the signal output terminal P0 of the SOC is connected to only one DDIC, the voltage of the signal received by each receiving unit RX in the DDIC is ±200mV; when the signal output terminal P0 of the SOC is connected to two DDICs, the voltage of the signal received by each receiving unit RX in the DDIC is ±133mV. Compared with the case where the signal output terminal P0 is only connected to one DDIC, when the signal output terminal P0 is connected to two DDICs, the attenuation amplitude of the signal received by each receiving unit RX in the DDIC is 20 times lg (133 / 200), where "lg" refers to the logarithm with base 10, and the result is approximately -3.5dB (decibel). It can be understood that for Fig.10 or Fig.12For the simulation circuit of the signal transmission circuit 12 shown, the voltages of the signals received by any two receiving units RX in each DDIC are the same and do not affect each other. Therefore, in the following description, "the voltage of the signal received by each receiving unit RX in the DDIC" is also referred to as "the voltage of the signal received by the DDIC".

[0096] 2. In the second case, the SOC and the DDIC are connected via an interface using the MIPI_C-PHY protocol. In this case, when the signal output terminal P0 of the SOC is connected to only one DDIC, the circuit diagram of the signal transmission circuit 12 can be as follows: Fig.14 As shown, only one set of signal lines is shown in the figure. Fig.14 , SOC includes resistor Ra, resistor Rb and resistor Rc, and SOC also includes resistor Rpu_ta, resistor Rpd_ta, resistor Rpu_tb, resistor Rpd_tb, resistor Rpu_tc and resistor Rpd_tc.

[0097] The first end of the resistor Ra is used to be connected to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Ra is connected to the first sub-port P01. The first end of the resistor Rb is used to be connected to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rb is connected to the second sub-port P02. The first end of the resistor Rc is used to be connected to the common voltage terminal VCOM or the ground line GND, and the second end of the resistor Rc is connected to the third sub-port P03. Among them, the signal output terminal P0 of the SOC has a plurality of sub-ports, and the first sub-port P01, the second sub-port P02, and the third sub-port P03 are all one of the sub-ports of the signal output terminal P0 of the SOC. The receiving unit RX includes a resistor RM1, a resistor RM2, and a resistor RM3. The first end of the resistor RM1 is used to be connected to the first sub-port P01, the first end of the resistor RM2 is used to be connected to the second sub-port P02, and the first end of the resistor RM3 is used to be connected to the third sub-port P03. The second end of the resistor RM1, the second end of the resistor RM2, and the second end of the resistor RM3 are connected together.

[0098] The resistor Rpu_ta and the resistor Rpd_ta are connected in series between the common voltage terminal VCOM and the ground line GND through the switch K1 and the switch K2, and the second end of the resistor Rpu_ta and the first end of the resistor Rpd_ta are both connected to the first sub-port P01. The resistor Rpu_tb and the resistor Rpd_tb are connected in series between the common voltage terminal VCOM and the ground line GND through the switch K3 and the switch K4, and the second end of the resistor Rpu_tb and the first end of the resistor Rpd_tb are both connected to the second sub-port P02. The resistor Rpu_tc and the resistor Rpd_tc are connected in series between the common voltage terminal VCOM and the ground line GND through the switch K5 and the switch K6, and the second end of the resistor Rpu_tc and the first end of the resistor Rpd_tc are both connected to the third sub-port P03.

[0099] In the signal transmission circuit 12, the impedances of the resistors Ra, Rb, Rc, RM1, RM2 and RM3 are all 50Ω. The impedances of the resistors Rpu_ta, Rpd_ta, Rpu_tb, Rpd_tb, Rpu_tc and Rpd_tc are all 100Ω. When the signal transmission circuit 12 is working, at the same time, one of the three sub-ports of the signal output terminal P0 of the SOC outputs a high-level signal, another outputs a low-level signal, and another outputs an intermediate-level signal, and the voltage of the intermediate-level signal is between the voltage of the high-level signal and the voltage of the low-level signal. Taking the voltage of the common voltage terminal VCOM as 400mV as an example, the working process of the signal transmission circuit 12 can specifically include the following six situations:

[0100] (1) The first end of the resistor Ra is connected to the common voltage terminal VCOM, and the first end of the resistor Rb is connected to the ground line GND. The resistor Rc is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K5 and K6 are closed, and switches K1, K2, K3, and K4 are all turned off. In this case, the first end of the resistor RM1 receives a high-level signal, the first end of the resistor RM2 receives a low-level signal, and the first end of the resistor RM3 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200mV.

[0101] (2) The first end of the resistor Ra is connected to the ground line GND, and the first end of the resistor Rb is connected to the common voltage terminal VCOM. The resistor Rc is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K5 and K6 are closed, and switches K1, K2, K3, and K4 are all turned off. In this case, the first end of the resistor RM1 receives a low-level signal, the first end of the resistor RM2 receives a high-level signal, and the first end of the resistor RM3 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200mV.

[0102] (3) The first end of the resistor Ra is connected to the common voltage terminal VCOM, and the first end of the resistor Rc is connected to the ground line GND. The resistor Rb is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K3 and K4 are closed, and switches K1, K2, K5, and K6 are all turned off. In this case, the first end of the resistor RM1 receives a high-level signal, the first end of the resistor RM3 receives a low-level signal, and the first end of the resistor RM2 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200mV.

[0103] (4) The first end of the resistor Ra is connected to the ground line GND, and the first end of the resistor Rc is connected to the common voltage terminal VCOM. The resistor Rb is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K3 and K4 are closed, and switches K1, K2, K5, and K6 are all turned off. In this case, the first end of the resistor RM1 receives a low-level signal, the first end of the resistor RM3 receives a high-level signal, and the first end of the resistor RM2 receives an intermediate-level signal. The difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 100mV, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is 100mV, and the difference between the voltage of the high-level signal and the voltage of the low-level signal is 200mV.

[0104] (5) The first end of the resistor Rb is connected to the common voltage terminal VCOM, and the first end of the resistor Rc is connected to the ground line GND. The resistor Ra is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K1 and K2 are closed, and switches K3, K4, K5, and K6 are all turned off. In this case, the first end of the resistor RM1 receives an intermediate level signal, the first end of the resistor RM3 receives a low level signal, and the first end of the resistor RM2 receives a high level signal. The difference between the voltage of the high level signal and the voltage of the intermediate level signal is 100mV, the difference between the voltage of the intermediate level signal and the voltage of the low level signal is 100mV, and the difference between the voltage of the high level signal and the voltage of the low level signal is 200mV.

[0105] (6) The first end of the resistor Rb is connected to the ground line GND, and the first end of the resistor Rc is connected to the common voltage terminal VCOM. The resistor Ra is neither connected to the common voltage terminal VCOM nor to the ground line GND. Switches K1 and K2 are closed, and switches K3, K4, K5, and K6 are all turned off. In this case, the first end of the resistor RM1 receives the intermediate level signal, the first end of the resistor RM3 receives the high level signal, and the first end of the resistor RM2 receives the low level signal. The difference between the voltage of the high level signal and the voltage of the intermediate level signal is 100mV, the difference between the voltage of the intermediate level signal and the voltage of the low level signal is 100mV, and the difference between the voltage of the high level signal and the voltage of the low level signal is 200mV.

[0106] However, when the signal output terminal P0 of the SOC is connected to two DDICs, the circuit diagram of the signal transmission circuit 12 may be as follows: Fig.15 See Fig.15 , wherein DDIC1 includes resistors RM1, RM2, and RM3, and DDIC2 includes resistors RM4, RM5, and RM6. The first end of resistor RM1 and the first end of resistor RM4 are both used to connect to the first sub-port P01, the first end of resistor RM2 and the first end of resistor RM5 are used to connect to the second sub-port P02, and the first end of resistor RM3 and the first end of resistor RM6 are both used to connect to the third sub-port P03. The second end of resistor RM1, the second end of resistor RM2, and the second end of resistor RM3 are connected together. The second end of resistor RM4, the second end of resistor RM5, and the second end of resistor RM6 are connected together.

[0107] In the signal transmission circuit 12, the impedances of the resistors RM1, RM2, RM3, RM4, RM5 and RM6 are all 50Ω. The working process of the signal transmission circuit 12 remains unchanged. According to the above analysis, when the voltage of the common voltage terminal VCOM is 400mV, and the signal output terminal P0 of the SOC is connected to two DDICs, the difference between the voltage of the high-level signal and the voltage of the intermediate-level signal is 66.5mV. Compared with the case where the signal output terminal P0 is only connected to one DDIC, the attenuation amplitude of the signal received by the DDIC is 20 times lg (66.5 / 100), and the result is about -3.5dB. Similarly, when the signal output terminal P0 of the SOC is connected to two DDICs, the difference between the voltage of the intermediate-level signal and the voltage of the low-level signal is also 66.5mV. Compared with the case where the signal output terminal P0 is only connected to one DDIC, the attenuation amplitude of the signal received by the DDIC is also about -3.5dB. When the signal output terminal P0 of the SOC is connected to two DDICs, the difference between the voltage of the high-level signal and the voltage of the low-level signal is 133mV. Compared with the case where the signal output terminal P0 is only connected to one DDIC, the attenuation amplitude of the signal received by the DDIC is also about -3.5dB.

[0108] To this end, an embodiment of the present application provides a signal transmission circuit 12 and an electronic device 10, which can improve the quality of the data signal received by the DDIC when the signal output end of the SOC in the electronic device 10 is connected to two DDICs, that is, when the connection between the two DDICs is in parallel.

[0109] Before explaining the signal transmission circuit provided in the embodiment of the present application in detail, it is also necessary to explain that: in the above two cases, the conclusion obtained that "when the signal output terminal P0 of the SOC is connected to only one DDIC, the voltage of the signal received by the DDIC is ±200mV; when the signal output terminal P0 of the SOC is connected to two DDICs, the voltage of the signal received by the DDIC is ±133mV" is only a theoretical calculation result. In practical applications, considering the inevitable loss in the signal transmission process, when the signal output terminal P0 of the SOC is connected to only one DDIC, the voltage of the signal received by the DDIC must be less than 200mV; when the signal output terminal P0 of the SOC is connected to two DDICs, the voltage of the signal received by the DDIC must also be less than 133mV.

[0110] For example, in one specific embodiment, Fig.13 Assume that the impedance of each resistor in the signal transmission circuit 12 is 50Ω. Fig.13 The circuit diagram of the signal transmission circuit 12 shown in FIG. 1 is simulated, and the impedance test is performed on the simulated circuit. The results are shown in FIG. Fig.16 As shown. Fig.16 It can be seen that before node 1, that is, the side of node 1 close to resistor Rp, the impedance of signal transmission circuit 12 is 50Ω; after node 1, that is, the side of node 1 close to resistor RL1, the impedance of signal transmission circuit 12 drops sharply to 25Ω. In other words, there is a large impedance mutation at the location of parallel node 1, which will affect the quality of signal transmission.

[0111] Taking the transmission rate of each set of data differential lines as 1 Gbps and the total length of each set of data differential lines as 245 mm (millimeter) as an example to simulate the signal loss of the actual electronic device 10, the oscilloscope is used to monitor the signal loss of the actual electronic device 10. Fig.11 The waveform of the signal transmission circuit 12 shown in FIG. 1 is displayed when the signal is transmitted, and the resulting eye diagram is shown in FIG. Fig.17 As shown in the eye diagram, the vertical axis is the voltage of the signal, in V (volts); the horizontal axis is time. Fig.17 It can be seen that when the signal output terminal P0 of the SOC is connected to only one DDIC, the voltage of the signal actually received by the DDIC is ±165mV. Fig.13 The waveform of the signal transmission circuit 12 shown in FIG. 1 is displayed when the signal is transmitted, and the resulting eye diagram is shown in FIG. Fig.18 As shown. Fig.18 It can be seen that when the signal output end of the SOC is connected to two DDICs, the voltage of the signal actually received by each DDIC is ±110mV. Therefore, it can be seen that the attenuation amplitude of the signal received by the DDIC is about -3.5dB.

[0112] The signal transmission circuit provided in the embodiment of the present application is explained in detail below. In each embodiment of the present application, the connection between any electrical unit and electronic device refers to electrical connection. The electrical connection here refers to connection through a wire so that electrical signals can be transmitted between two electrical units or / and electronic devices. The connection between two electrical units and electronic devices can be a direct connection or an indirect connection through other electrical units and / or electronic devices.

[0113] Fig.19 2 is a schematic diagram of a signal transmission circuit 20 provided in an embodiment of the present application. The signal transmission circuit 20 is suitable for Figure 7 The electronic device shown is an electronic device suitable for "DDIC1 and DDIC2 both need to be connected to the signal output terminal P0 of the SOC". The signal transmission circuit 20 is suitable for both the case where the SOC and DDIC (including DDIC1 and DDIC2) are connected via an interface using the MIPI_D-PHY protocol, and the case where the SOC and DDIC are connected via an interface using the MIPI_C-PHY protocol. Fig.19As shown, the signal transmission circuit 20 includes a sending unit 210 , a first receiving unit 220 , a second receiving unit 230 , a first wire group 240 , a second wire group 250 and a third wire group 260 .

[0114] The sending unit 210 is an electrical unit for sending signals, where the signals may be data signals and / or clock signals. The sending unit 210 may be a SOC in an electronic device, or an electrical component (such as a SOC) having a signal sending function and composed of some electrical components in the SOC. Fig.12 The transmitting unit 210 has a signal output terminal P0 for transmitting a signal.

[0115] The first receiving unit 220 is an electrical unit for receiving the signal sent by the sending unit 210. The first receiving unit 220 can be a DDIC in an electronic device, or an electrical component (such as a DDIC) having a signal receiving function and composed of some electrical components in the DDIC. Fig.12 The first receiving unit 220 has an input terminal Q1 for receiving a signal.

[0116] The second receiving unit 230 is also an electrical unit for receiving the signal sent by the sending unit 210. The second receiving unit 230 can be a DDIC in an electronic device, or an electrical component (such as a DDIC) having a signal receiving function and composed of some electrical components in the DDIC. Fig.12 The second receiving unit 230 has an input terminal Q2 for receiving a signal.

[0117] In the embodiment of the present application, the signal output terminal P0 of the sending unit 210, the input terminal Q1 of the first receiving unit 220, and the input terminal Q2 of the second receiving unit 230 are all connected to the same node. For ease of description, the node is referred to as "preset node Y". In other words, the signal output terminal P0 of the sending unit 210, the input terminal Q1 of the first receiving unit 220, and the input terminal Q2 of the second receiving unit 230 are all connected to the preset node Y, so that the first receiving unit 220 and the second receiving unit 230 can both receive the signal sent by the sending unit 210.

[0118] The signal output terminal P0 of the sending unit 210 is connected to the preset node Y through the first wire group 240. The first wire group 240 may include one or more wires, and the plurality of wires here refers to two or more integers. Specifically, the signal output terminal P0 of the sending unit 210 may include only one subport, or may include multiple subports independent of each other. The preset node Y may include only one subnode, or may include multiple subnodes independent of each other. Generally, the number of subports included in the signal output terminal P0 of the sending unit 210 is equal to the number of subnodes included in the preset node Y, and each subport in the signal output terminal P0 of the sending unit 210 needs to be connected to a subnode in the preset node Y through a wire. Based on this, all wires connected between the signal output terminal P0 of the sending unit 210 and the preset node Y can be referred to as the first wire group 240. Similarly, the input terminal of the first receiving unit 220 is connected to the preset node Y through the second wire group 250, and the input terminal Q2 of the second receiving unit 230 is connected to the preset node Y through the third wire group 260. The number of sub-ports included in the signal output terminal P0 of the sending unit 210 , the input terminal Q1 of the first receiving unit 220 , and the input terminal Q2 of the second receiving unit 230 are all equal and equal to the number of sub-nodes included in the preset node Y.

[0119] In the embodiment of the present application, the impedance of the transmitting unit 210, the impedance of the first receiving unit 220 and the impedance of the second receiving unit 230 need to meet the following conditions: the impedance of the first receiving unit 220 is greater than the impedance of the transmitting unit 210, and the impedance of the second receiving unit 230 is greater than the impedance of the transmitting unit 210. In addition, the impedance of the second wire group 250 needs to meet the following conditions: the difference between the impedance of the second wire group 250 and the impedance of the first receiving unit 220 is within the first impedance range. In this way, impedance matching can be achieved between the second wire group 250 and the first receiving unit 220. Among them, the impedance matching between one device and another device means that the difference in impedance between the two devices is within a certain impedance range, so that there is no impedance mutation after the two devices are connected. The impedance of the third wire group 260 needs to meet the following conditions: the difference between the impedance of the third wire group 260 and the impedance of the second receiving unit 230 is within the second impedance range. In this way, impedance matching can be achieved between the third wire group 260 and the second receiving unit 230.

[0120] In the signal transmission circuit 20, the impedance of the first receiving unit 220 and the impedance of the second receiving unit 230 are both greater than the impedance of the sending unit 210. Since in the related art, the impedance of the first receiving unit 220, the impedance of the second receiving unit 230 and the impedance of the sending unit 210 are all equal, the present application can increase the voltage of the signal received by the first receiving unit 220 and the second receiving unit 230 in parallel by increasing the impedance of the first receiving unit 220 and the impedance of the second receiving unit 230, thereby improving the quality of the signal received by the first receiving unit 220 and the second receiving unit 230. In addition, the impedance matching between the connected second wire group 250 and the first receiving unit 220 can avoid the formation of signal reflection when the signal is transmitted from the second wire group 250 to the first receiving unit 220, thereby improving the quality of the signal received by the first receiving unit 220. Similarly, the impedance matching between the connected third wire group 260 and the second receiving unit 230 can avoid the formation of signal reflection when the signal is transmitted from the third wire group 260 to the second receiving unit 230, thereby improving the quality of the signal received by the second receiving unit 230.

[0121] In some embodiments, the impedance of the first wire group 240 may also satisfy the following condition: the difference between the impedance of the first wire group 240 and the impedance of the sending unit 210 is within a third impedance range. In this way, impedance matching can be achieved between the first wire group 240 and the sending unit 210, so that signal reflection can be avoided when the signal is transmitted from the sending unit 210 to the first wire group 240, thereby improving the quality of the signal received by the first receiving unit 220 and the second receiving unit 230.

[0122] As mentioned above, the signal transmission circuit 20 is applicable to both the case where the SOC and DDIC are connected through an interface using the MIPI_D-PHY protocol, and the case where the SOC and DDIC are connected through an interface using the MIPI_C-PHY protocol. That is to say, the transmitting unit 210 and the first receiving unit 220 and the second receiving unit 230 can be connected through an interface using the MIPI_D-PHY protocol, or through an interface using the MIPI_C-PHY protocol. The signal transmission circuit 20 provided in the embodiment of the present application is explained in detail below for these two situations.

[0123] 1. In the first case, the transmitting unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 via an interface using the MIPI_D-PHY protocol.

[0124] Fig. 202 is a circuit structure diagram of a signal transmission circuit 20 provided in an embodiment of the present application, which shows a circuit structure in which a transmitting unit 210 is connected to a first receiving unit 220 and a second receiving unit 230 through an interface using the MIPI_D-PHY protocol. In this embodiment, the transmitting unit 210 is located in the SOC of the electronic device, the first receiving unit 220 is located in the DDIC1 of the electronic device, and the second receiving unit 230 is located in the DDIC2 of the electronic device. The connected SOC, DDIC1 and DDIC2 include at least two Fig. 20 The signal transmission circuit 20 shown in FIG. 1 is used to transmit a data signal and the other is used to transmit a clock signal. In some specific embodiments, the connected SOC, DDIC1 and DDIC2 include five Fig. 20 The signal transmission circuit 20 shown in FIG. 1 is connected to the SOC and the DDIC1 and DDIC2 as shown in FIG. Fig.12 As shown, no further elaboration is given.

[0125] like Fig. 20 As shown, the transmitting unit 210 may include a first impedance device 212 and a second impedance device 214. The first receiving unit 220 includes a third impedance device 222 and a fourth impedance device 224. The second receiving unit 230 includes a fifth impedance device 232 and a sixth impedance device 234. In some embodiments, each impedance device (including the first impedance device 212, the second impedance device 214...the sixth impedance device 234) may be a resistor. In other embodiments, each impedance device may also be a metal oxide semiconductor field effect transistor (MOSFET), and the impedance of the MOSFET may be controlled by controlling the conduction degree of the MOSFET.

[0126] The preset node Y includes a first node Y1 and a second node Y2. In this case, the signal output terminal P0 of the sending unit 210 includes two sub-ports, namely a first sub-port P01 and a second sub-port P02. The input terminal Q1 of the first receiving unit 220 also includes two sub-ports, namely a third sub-port Q11 and a fourth sub-port Q12. The input terminal Q2 of the second receiving unit 230 also includes two sub-ports, namely a fifth sub-port Q21 and a sixth sub-port Q22. The first wire group 240 includes a first wire 242 and a second wire 244. The second wire group 250 includes a third wire 252 and a fourth wire 254. The third wire group 260 includes a fifth wire 262 and a sixth wire 264.

[0127] The first end of the first impedance device 212 is used to be connected to the preset voltage terminal VCOM or the ground line GND. The preset voltage terminal VCOM here is the common voltage terminal in the related art, which is used to provide a positive voltage, such as a voltage of +400mV. The second end of the first impedance device 212 is connected to the first node Y1 through the first wire 242. In other words, the second end of the first impedance device 212 is the first sub-port P01. The first end of the third impedance device 222 is connected to the first node Y1 through the third wire 252. In other words, the first end of the third impedance device 222 is the third sub-port Q11. The second end of the third impedance device 222 is connected to the second end of the fourth impedance device 224. The first end of the fifth impedance device 232 is connected to the first node Y1 through the fifth wire 262. In other words, the first end of the fifth impedance device 232 is the fifth sub-port Q21. The second end of the fifth impedance device 232 is connected to the second end of the sixth impedance device 234. The first end of the second impedance device 214 can be connected to one of the preset voltage terminal VCOM and the ground line GND. The second end of the second impedance device 214 is connected to the second node Y2 through the second wire 244. That is, the second end of the second impedance device 214 is the second sub-port P02. The first end of the fourth impedance device 224 is connected to the second node Y2 through the fourth wire 254. That is, the first end of the fourth impedance device 224 is the fourth sub-port Q12. The first end of the sixth impedance device 234 is connected to the second node Y2 through the sixth wire 264. That is, the first end of the sixth impedance device 234 is the sixth sub-port Q22.

[0128] The following two aspects Fig. 20 The inventive concept of the signal transmission circuit 20 shown is described.

[0129] (1) Impedance relationship among the transmitting unit 210 , the first receiving unit 220 , and the second receiving unit 230 .

[0130] based on Fig. 20 In the circuit structure shown, the impedance of the first receiving unit 220 is greater than the impedance of the transmitting unit 210, which means that the sum of the impedance of the third impedance device 222 plus the impedance of the fourth impedance device 224 is greater than the sum of the impedance of the first impedance device 212 plus the impedance of the second impedance device 214. The impedance of the second receiving unit 230 is greater than the impedance of the transmitting unit 210, which means that the sum of the impedance of the fifth impedance device 232 plus the impedance of the sixth impedance device 234 is greater than the sum of the impedance of the first impedance device 212 plus the impedance of the second impedance device 214. For example, the impedance of the first impedance device 212 is R1, the impedance of the second impedance device 214 is R2, the impedance of the third impedance device 222 is R3, the impedance of the fourth impedance device 224 is R4, the impedance of the fifth impedance device 232 is R5, and the impedance of the sixth impedance device 234 is R6, then:

[0131] R3+R4>R1+R2, and R5+R6>R1+R2.

[0132] In some embodiments, in the transmitting unit 210, the impedance R1 of the first impedance device 212 may be equal to the impedance R2 of the second impedance device 214. In the first receiving unit 220, the impedance R3 of the third impedance device 222 is equal to the impedance R4 of the fourth impedance device 224. In the second receiving unit 230, the impedance R5 of the fifth impedance device 232 is equal to the impedance R6 of the sixth impedance device 234. That is:

[0133] R3=R4>R1=R2, and R5=R6>R1=R2.

[0134] In some embodiments, the impedance R3 of the third impedance device 222 is between 1.2 times and 2 times (including the end value) of the impedance R1 of the first impedance device 212. The impedance R5 of the fifth impedance device 232 is also between 1.2 times and 2 times (including the end value) of the impedance R1 of the first impedance device 212. For example, as described in the related art, the impedance R1 of the first impedance device 212 and the impedance R2 of the second impedance device 214 can both be equal to 50Ω. Then, the impedance R3 of the third impedance device 222 and the impedance R4 of the fourth impedance device 224 can both be equal to 60Ω, 70Ω, 80Ω, 90Ω or 100 ohms. The impedance R5 of the fifth impedance device 232 and the impedance R6 of the sixth impedance device 234 can also both be equal to 60Ω, 70Ω, 80Ω, 90Ω or 100 ohms.

[0135] In some specific embodiments, it can be seen from the above description of the related art that when the signal output terminal P0 of the SOC is connected to only one DDIC, without considering the loss in signal transmission, the voltage of the signal received by the DDIC is

[0136] And for Fig. 20 The signal transmission circuit 20 shown, that is, the sending unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 at the same time, then because the third impedance device 222 and the fourth impedance device 224 are connected in series, the impedance of the first receiving unit 220 is: R3+R4. Since the fifth impedance device 232 and the sixth impedance device 234 are connected in series, the impedance of the second receiving unit 230 is: R5+R6. Since the first receiving unit 220 and the second receiving unit 230 are connected in parallel between the first node Y1 and the second node Y2, the impedance R between the first node Y1 and the second node Y2 is:

[0137] In this case, the voltage difference U2 between the first node Y1 and the second node Y2 is: Without considering the loss in signal transmission, U2 is also the voltage of the signal received by the first receiving unit 220 and the second receiving unit 230 when the transmitting unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 at the same time.

[0138] It can be seen that when R3=R4=R5=R6=2R1=2R2, That is, in a preferred embodiment, the impedance of the first impedance device 212 is equal to the impedance of the second impedance device 214; the impedance of the third impedance device 222 is equal to the impedance of the fourth impedance device 224, and equal to the impedance of the fifth impedance device 232 is equal to the impedance of the sixth impedance device 234, and equal to twice the impedance of the first impedance device 212.

[0139] (2) Impedance matching relationship between the connected wire group and the electrical unit.

[0140] Fig.21 : is an impedance diagram of a signal transmission circuit 20 provided by an embodiment of the present application, wherein impedance Z1 is used to represent the characteristic impedance of the first wire 242, impedance Z2 is used to represent the characteristic impedance of the second wire 244, and impedance Z6 is used to represent the characteristic impedance of the sixth wire 264; resistor R1 is used to represent the first impedance device 212, resistor R2 is used to represent the second impedance device 214, and resistor R6 is used to represent the sixth impedance device 234. Fig.21 , the impedance matching relationship between the connected wire group and the electrical unit is explained.

[0141] In some embodiments, when the second wire group 250 includes the third wire 252 and the fourth wire 254, and the first receiving unit 220 includes the third impedance device 222 and the fourth impedance device 224, the first impedance range may include a first impedance sub-range and a second impedance sub-range. At this time, "the difference between the impedance of the second wire group 250 and the impedance of the first receiving unit 220 is within the first impedance range" means that the difference between the characteristic impedance Z3 of the third wire 252 and the impedance of the third impedance device 222 (i.e., the resistor R3) is within the first impedance sub-range, and the difference between the characteristic impedance Z4 of the fourth wire 254 and the impedance of the fourth impedance device 224 (i.e., the resistor R4) is within the second impedance sub-range.

[0142] The minimum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device 222 and -10%, and the maximum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device 222 and 10%. For example, if the impedance of the third impedance device 222 is 100Ω, the minimum value of the first impedance sub-range is -10Ω, and the maximum value of the first impedance sub-range is 10Ω. In other words, the characteristic impedance Z3 of the third wire 252 connected to the third impedance device 222 is at least 90Ω and at most 110 ohms. For another example, if the impedance of the third impedance device 222 is 60Ω, the characteristic impedance Z3 of the third wire 252 is at least 54Ω and at most 66 ohms.

[0143] Similarly, the minimum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device 224 and -10%, and the maximum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device 224 and 10%. For example, if the impedance of the fourth impedance device 224 is 70Ω, the characteristic impedance Z4 of the fourth wire 254 is 63Ω at the minimum and 77Ω at the maximum.

[0144] In some embodiments, when the third wire group 260 includes the fifth wire 262 and the sixth wire 264, and the second receiving unit 230 includes the fifth impedance device 232 and the sixth impedance device 234, the second impedance range may include the third impedance sub-range and the fourth impedance sub-range. At this time, "the difference between the impedance of the third wire group 260 and the impedance of the second receiving unit 230 is within the second impedance range" means that the difference between the characteristic impedance Z5 of the fifth wire 262 and the impedance of the fifth impedance device 232 (i.e., the resistor R5) is within the third impedance sub-range, and the difference between the characteristic impedance Z6 of the sixth wire 264 and the impedance of the sixth impedance device 234 (i.e., the resistor R6) is within the fourth impedance sub-range.

[0145] The minimum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device 232 and -10%, and the maximum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device 232 and 10%. The minimum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device 234 and -10%, and the maximum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device 234 and 10%, which will not be repeated.

[0146] In some embodiments, when the first wire group 240 includes the first wire 242 and the second wire 244, and the sending unit 210 includes the first impedance device 212 and the second impedance device 214, the third impedance range may include the fifth impedance sub-range and the sixth impedance sub-range. At this time, "the difference between the impedance of the first wire group 240 and the impedance of the sending unit 210 is within the third impedance range" means that the difference between the characteristic impedance Z1 of the first wire 242 and the impedance of the first impedance device 212 (i.e., the resistor R1) is within the fifth impedance sub-range, and the difference between the characteristic impedance Z2 of the second wire 244 and the impedance of the second impedance device 214 (i.e., the resistor R2) is within the sixth impedance sub-range.

[0147] The minimum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device 212 and -10%, and the maximum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device 212 and 10%. The minimum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device 214 and -10%, and the maximum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device 214 and 10%, which will not be repeated.

[0148] In some specific embodiments, the impedance of the resistor R1 and the resistor R2 are both 50Ω, and the impedance of the resistor R3, the resistor R4, the resistor R5, and the resistor R6 are all 100Ω. In this case, the characteristic impedance Z1 of the first wire 242 and the characteristic impedance Z2 of the second wire 244 are both between 45Ω and 55Ω, and the characteristic impedance Z3 of the third wire 252, the characteristic impedance Z4 of the fourth wire 254, the characteristic impedance Z5 of the fifth wire 262, and the characteristic impedance Z6 of the sixth wire 264 are all between 90Ω and 110Ω. It can be seen that the characteristic impedance Z1 of the first wire 242 is less than the characteristic impedance Z3 of the third wire 252, and the characteristic impedance Z1 of the first wire 242 is less than the characteristic impedance Z5 of the fifth wire 262. Similarly, the characteristic impedance Z2 of the second wire 244 is less than the characteristic impedance Z4 of the fourth wire 254, and the characteristic impedance Z2 of the second wire 244 is less than the characteristic impedance Z6 of the sixth wire 264.

[0149] The characteristic impedance of the wire can be adjusted by adjusting the dielectric constant, wire thickness, and wire width of the wire. In some specific embodiments, the characteristic impedance of the wire can be adjusted by adjusting the wire width. Based on this, Fig. 22As shown, on the printed circuit board (PCB) of the electronic device, the width of the first wire 242 can be greater than the width of the third wire 252, and the width of the first wire 242 can be greater than the width of the fifth wire 262. The width of the second wire 244 can be greater than the width of the fourth wire 254, and the width of the second wire 244 can be greater than the width of the sixth wire 264. The distance between the third wire 252 and the fourth wire 254 can be greater than the distance between the first wire 242 and the second wire 244. In this way, the electrical structure impedance formed by the first wire 242, the first impedance device 212, the second impedance device 214, and the second wire 244 is matched; the electrical structure impedance formed by the third wire 252, the third impedance device 222, the fourth impedance device 224, and the fourth wire 254 is matched; the electrical structure impedance formed by the fifth wire 262, the fifth impedance device 232, the sixth impedance device 234, and the sixth wire 264 is matched. In the entire signal transmission circuit 20, only the first node Y1 and the second node Y2 have impedance mutations, which can effectively reduce signal reflections caused by impedance mutations in the signal transmission circuit 20, thereby improving the quality of signals received by the first receiving unit 220 and the second receiving unit 230.

[0150] The following circuit simulation experiment is combined with Fig.21 The beneficial effects of the signal transmission circuit 20 shown are described.

[0151] In the first simulation experiment, the simulation conditions are: Fig.21 In the signal transmission circuit 20 shown, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 60Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, and the impedance of each conductor (including the first conductor 242, the second conductor 244...the sixth conductor 264) is not matched and controlled (in this case, the characteristic impedance of each conductor is much smaller than the impedance of each resistor). The signal loss of an actual electronic device is simulated under this simulation condition, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 is transmitting the signal is displayed by an oscilloscope. The resulting eye diagram is as follows: Fig.23 As shown. Fig.23 It can be known that the voltage of the signal received by the first receiving unit 220 is ±116 mV.

[0152] In the second simulation experiment, the simulation conditions are: Fig.21In the signal transmission circuit 20 shown, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 60Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, the characteristic impedances of the first wire 242 and the second wire 244 are both 50Ω, and the characteristic impedances of the third wire 252, the fourth wire 254, the fifth wire 262, and the sixth wire 264 are all 60Ω. The signal loss of an actual electronic device is simulated under this simulation condition, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 performs signal transmission is displayed by an oscilloscope, and the resulting eye diagram is as follows: Fig.24 As shown. Fig.24 It can be known that the voltage of the signal received by the first receiving unit 220 is ±124 mV.

[0153] In the third simulation experiment, the simulation conditions are: Fig.21 In the signal transmission circuit 20 shown, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 70Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, and no matching control is performed on the characteristic impedance of each conductor. The signal loss of an actual electronic device is simulated under this simulation condition, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 performs signal transmission is displayed by an oscilloscope. The resulting eye diagram is shown as follows: Fig.25 As shown. Fig.25 It can be known that the voltage of the signal received by the first receiving unit 220 is ±122 mV.

[0154] In the fourth simulation experiment, the simulation conditions are: Fig.21 In the signal transmission circuit 20 shown, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 70Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, the characteristic impedances of the first wire 242 and the second wire 244 are both 50Ω, and the characteristic impedances of the third wire 252, the fourth wire 254, the fifth wire 262, and the sixth wire 264 are all 70Ω. The signal loss of an actual electronic device is simulated under this simulation condition, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 performs signal transmission is displayed by an oscilloscope, and the resulting eye diagram is as follows: Fig.26 As shown. Fig.26 It can be known that the voltage of the signal received by the first receiving unit 220 is ±134 mV.

[0155] In the fifth simulation experiment, the simulation conditions are: Fig.21In the signal transmission circuit 20 shown, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 100Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, and no matching control is performed on the characteristic impedance of each conductor. The signal loss of an actual electronic device is simulated under this simulation condition, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 performs signal transmission is displayed by an oscilloscope. The resulting eye diagram is shown as follows: Fig. 27 As shown. Fig. 27 It can be known that the voltage of the signal received by the first receiving unit 220 is ±124 mV.

[0156] In the sixth simulation experiment, the simulation conditions are: Fig.21 In the signal transmission circuit 20 shown, the impedances of resistors R1 and R2 are both 50Ω, the impedances of resistors R3, R4, R5, and R6 are all 100Ω, the transmission rate of the data differential line is 1Gbps, the total length of the data differential line is 245mm, the characteristic impedances of the first wire 242 and the second wire 244 are both 50Ω, and the characteristic impedances of the third wire 252, the fourth wire 254, the fifth wire 262, and the sixth wire 264 are all 100Ω. The signal loss of an actual electronic device is simulated under this simulation condition, and the waveform of the signal received by the first receiving unit 220 when the signal transmission circuit 20 performs signal transmission is displayed by an oscilloscope, and the resulting eye diagram is as follows: Fig.28 As shown. Fig.28 It can be known that the voltage of the signal received by the first receiving unit 220 is ±155 mV.

[0157] contrast Fig.18 , Fig.23 , Fig.25 and Fig. 27 It can be seen that as the resistance values ​​of the resistors R3, R4, R5, and R6 gradually increase from 50Ω to 100Ω, the voltage of the signal received by the first receiving unit 220 gradually increases and approaches Fig.17 ±165mV in. Fig.23 and Fig.24 ,contrast Fig.25 and Fig.26 ,contrast Fig. 27 and Fig.28 It can be concluded that impedance matching between the connected wires and the impedance device can not only increase the voltage of the signal received by the receiving unit, but also converge the rising and falling edges of the eye diagram signal (that is, impedance matching makes the eye diagram clearer) and improve the signal's anti-noise ability. This shows that impedance matching between the connected wires and the impedance device is conducive to improving the quality of the signal received by the receiving unit. Fig.18 and Figure 23 to Figure 28 It can be seen that when the impedances of resistors R3, R4, R5, and R6 are all twice that of resistor R1, and impedance matching is achieved between the connected wires and the impedance device, the quality of the signal received by the receiving unit is the highest. Fig.23 and Fig.24 ,contrast Fig.25 and Fig.26 ,contrast Fig. 27 and Fig.28 It can also be concluded that when impedance matching is not achieved between the connected wires and the impedance device, the voltage of the signal received by the first receiving unit 220 will be affected, and the problem of inter-code crosstalk will be caused due to signal reflection.

[0158] In addition, combined Figure 23 to Figure 28 It can be seen that when the differential signal received by the first receiving unit 220 changes from a low level (negative voltage) to a high level (positive voltage), the voltage of the signal received by the first receiving unit 220 does not change suddenly, but has a rising process. Based on this, the process of the signal changing from a low level to a high level can be divided into two stages, namely, a voltage change stage and a voltage stabilization stage. For example, for Fig.28 For curve ① in the eye diagram shown, the voltage conversion stage is from 0.2 time units to 1.0 time units, and the voltage stabilization stage is from 1.0 time units to 2.0 time units. Fig.23 and Fig.24 ,contrast Fig.25 and Fig.26 ,contrast Fig. 27 and Fig.28 It can be concluded that the increase in the characteristic impedance of the wire will only affect the duration of the voltage change phase, but will not affect the voltage of the signal received by the first receiving unit 220 in the voltage stabilization phase. In other words, the impedance matching between the connected wire and the impedance device will not affect the voltage of the signal received in the voltage stabilization phase. In the voltage stabilization phase, the voltage of the signal received by the first receiving unit 220 is only related to the impedance size of each resistor. In fact, in the voltage stabilization phase, the characteristic impedance of the wire can be regarded as 0.

[0159] 2. In the second case, the sending unit 210 is connected to the first receiving unit 220 and the second receiving unit 230 via an interface using the MIPI_C-PHY protocol.

[0160] Fig.292 is a circuit structure diagram of another signal transmission circuit 20 provided in an embodiment of the present application, which shows a circuit structure in which a transmitting unit 210 is connected to a first receiving unit 220 and a second receiving unit 230 through an interface using the MIPI_C-PHY protocol. In this embodiment, the transmitting unit 210 is located in the SOC of the electronic device, the first receiving unit 220 is located in the DDIC1 of the electronic device, and the second receiving unit 230 is located in the DDIC2 of the electronic device. The connected SOC, DDIC1 and DDIC2 may include three Fig.29 The signal transmission circuit 20 shown is used to transmit data signals and clock signals interspersed together.

[0161] Compared to Fig. 20 The signal transmission circuit 20 shown, Fig.29 In the signal transmission circuit 20 shown, the sending unit 210 further includes a seventh impedance device 216. The first receiving unit 220 further includes an eighth impedance device 226. The second receiving unit 230 further includes a ninth impedance device 236. The preset node Y also includes a third node Y3. In this case, the signal output terminal P0 of the sending unit 210 includes three sub-ports, namely, a first sub-port P01, a second sub-port P02, and a seventh sub-port P03. The input terminal Q1 of the first receiving unit 220 also includes three sub-ports, namely, a third sub-port Q11, a fourth sub-port Q12, and an eighth sub-port Q13. The input terminal Q2 of the second receiving unit 230 also includes three sub-ports, namely, a fifth sub-port Q21, a sixth sub-port Q22, and a ninth sub-port Q23. The first wire group 240 also includes a seventh wire 246. The second wire group 250 also includes an eighth wire 256. The third wire group 260 also includes a ninth wire 266.

[0162] The first end of the seventh impedance device 216 can be connected to one of the preset voltage terminal VCOM and the ground line GND. The second end of the seventh impedance device 216 is connected to the third node Y3 through the seventh wire 246. In other words, the second end of the seventh impedance device 216 is the seventh sub-port P03. The first end of the eighth impedance device 226 is connected to the third node Y3 through the eighth wire 256. In other words, the first end of the eighth impedance device 226 is the eighth sub-port Q13. The second end of the eighth impedance device 226 is connected to the second end of the third impedance device 222 and the second end of the fourth impedance device 224. The first end of the ninth impedance device 236 is connected to the third node Y3 through the ninth wire 266. In other words, the first end of the ninth impedance device 236 is the ninth sub-port Q23. The second end of the ninth impedance device 236 is connected to the second end of the fifth impedance device 232 and the second end of the sixth impedance device 234.

[0163] When the signal transmission circuit 20 is working, one of the first end of the first impedance device 212, the first end of the second impedance device 214, and the first end of the seventh impedance device 216 is connected to the preset voltage terminal VCOM, one is connected to the ground line GND, and the last one is neither connected to the preset voltage terminal VCOM nor to the ground line GND.

[0164] The following two aspects Fig.29 The inventive concept of the signal transmission circuit 20 shown is described.

[0165] (1) Impedance relationship among the transmitting unit 210 , the first receiving unit 220 , and the second receiving unit 230 .

[0166] based on Fig.29 In the circuit structure shown, the impedance of the first receiving unit 220 is greater than the impedance of the transmitting unit 210, and the sum of the impedance of the third impedance device 222 plus the impedance of the eighth impedance device 226 is greater than the sum of the impedance of the first impedance device 212 plus the impedance of the seventh impedance device 216; and the sum of the impedance of the fourth impedance device 224 plus the impedance of the eighth impedance device 226 is greater than the sum of the impedance of the second impedance device 214 plus the impedance of the seventh impedance device 216. The impedance of the second receiving unit 230 is greater than the impedance of the transmitting unit 210, and the sum of the impedance of the fifth impedance device 232 plus the impedance of the ninth impedance device 236 is greater than the sum of the impedance of the first impedance device 212 plus the impedance of the seventh impedance device 216; and the sum of the impedance of the sixth impedance device 234 plus the impedance of the ninth impedance device 236 is greater than the sum of the impedance of the second impedance device 214 plus the impedance of the seventh impedance device 216. Taking the impedance of the seventh impedance device 216 as R7, the impedance of the eighth impedance device 226 as R8, and the impedance of the ninth impedance device 236 as R9 as an example, we have:

[0167] and,

[0168] In some embodiments, in the transmitting unit 210, the impedance R7 of the seventh impedance device 216, the impedance R1 of the first impedance device 212, and the impedance R2 of the second impedance device 214 are all equal. In the first receiving unit 220, the impedance R8 of the eighth impedance device 226, the impedance R3 of the third impedance device 222, and the impedance R4 of the fourth impedance device 224 are all equal. In the second receiving unit 230, the impedance R9 of the ninth impedance device 236, the impedance R5 of the fifth impedance device 232, and the impedance R6 of the sixth impedance device 234 are all equal. At the same time, the impedance of any impedance device in the first receiving unit 220 is greater than the impedance of any impedance device in the transmitting unit 210, and the impedance of any impedance device in the second receiving unit 230 is greater than the impedance of any impedance device in the transmitting unit 210. That is, R3=R4=R8>R1=R2=R7, and R5=R6=R9>R1=R2=R7.

[0169] In some embodiments, the impedance R8 of the eighth impedance device 226 is between 1.2 times and 2 times (including the end value) of the impedance R7 of the seventh impedance device 216. The impedance R9 of the ninth impedance device 236 is between 1.2 times and 2 times (including the end value) of the impedance R7 of the seventh impedance device 216. For example, as described in the related art, the impedance R7 of the seventh impedance device 216 can be equal to 50Ω, then the impedance R8 of the eighth impedance device 226 can be equal to 60Ω, 70Ω, 80Ω, 90Ω or 100 ohms. The impedance R9 of the ninth impedance device 236 can also be equal to 60Ω, 70Ω, 80Ω, 90Ω or 100 ohms. In some specific embodiments, R3=R4=R5=R6=R8=R9=2R1=2R2=2R7.

[0170] (2) Impedance matching relationship between the connected wire group and the electrical unit.

[0171] Fig.30 : is another impedance diagram of a signal transmission circuit 20 provided in an embodiment of the present application, wherein an impedance Z7 is used to represent the characteristic impedance of the seventh wire 246, an impedance Z8 is used to represent the characteristic impedance of the eighth wire 256, and an impedance Z9 is used to represent the characteristic impedance of the ninth wire 266; a resistor R7 is used to represent the seventh impedance device 216, a resistor R8 is used to represent the eighth impedance device 226, and a resistor R9 is used to represent the ninth impedance device 236. Fig.30 , the impedance matching relationship between the connected wire group and the electrical unit is explained.

[0172] In some embodiments, when the second wire group 250 further includes the eighth wire 256 and the first receiving unit 220 further includes the eighth impedance device 226, the first impedance range may further include the seventh impedance sub-range. At this time, "the difference between the impedance of the second wire group 250 and the impedance of the first receiving unit 220 is within the first impedance range" also includes: the difference between the characteristic impedance Z8 of the eighth wire 256 and the impedance of the eighth impedance device 226 (i.e., the resistor R8) is within the seventh impedance sub-range. The minimum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device 226 and -10%, and the maximum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device 226 and 10%, which will not be repeated.

[0173] In some embodiments, when the third wire group 260 further includes the ninth wire 266 and the second receiving unit 230 further includes the ninth impedance device 236, the second impedance range may further include the eighth impedance sub-range. At this time, "the difference between the impedance of the third wire group 260 and the impedance of the second receiving unit 230 is within the second impedance range" also includes: the difference between the characteristic impedance Z9 of the ninth wire 266 and the impedance of the ninth impedance device 236 (i.e., the resistor R9) is within the eighth impedance sub-range. The minimum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device 236 and -10%, and the maximum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device 236 and 10%, which will not be repeated.

[0174] In some embodiments, when the first wire group 240 further includes the seventh wire 246 and the sending unit 210 further includes the seventh impedance device 216, the third impedance range may further include a ninth impedance sub-range. At this time, "the difference between the impedance of the first wire group 240 and the impedance of the sending unit 210 is within the third impedance range" also includes: the difference between the characteristic impedance Z7 of the seventh wire 246 and the impedance of the seventh impedance device 216 (i.e., the resistor R7) is within the ninth impedance sub-range. The minimum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device 216 and -10%, and the maximum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device 216 and 10%, which will not be repeated.

[0175] In some specific embodiments, the impedance of the resistor R7 is 50Ω, and the impedances of the resistors R8 and R9 are both 100Ω. In this case, the characteristic impedance of the seventh wire 246 is between 45Ω and 55Ω, and the characteristic impedances of the eighth wire 256 and the ninth wire 266 are both between 90Ω and 110Ω. It can be seen that the characteristic impedance Z7 of the seventh wire 246 is less than the characteristic impedance Z8 of the eighth wire 256, and the characteristic impedance Z7 of the seventh wire 246 is less than the characteristic impedance Z9 of the ninth wire 266. Based on this, Fig.31As shown, on the printed circuit board of the electronic device, the width of the seventh wire 246 can be greater than the width of the eighth wire 256, and the width of the seventh wire 246 can be greater than the width of the ninth wire 266. The distance between the third wire 252 and the fourth wire 254 can be greater than the distance between the first wire 242 and the second wire 244. The distance between the fourth wire 254 and the eighth wire 256 can be greater than the distance between the second wire 244 and the seventh wire 246. In this way, the electrical structure impedance formed by the first wire 242, the first impedance device 212, the second impedance device 214, the second wire 244, the seventh wire 246, and the seventh impedance device 216 is matched; the electrical structure impedance formed by the third wire 252, the third impedance device 222, the fourth impedance device 224, the fourth wire 254, the eighth wire 256, and the eighth impedance device 226 is matched; the electrical structure impedance formed by the fifth wire 262, the fifth impedance device 232, the sixth impedance device 234, the sixth wire 264, the ninth wire 266, and the ninth impedance device 236 is matched. In the entire signal transmission circuit 20, only the first node Y1, the second node Y2, and the third node Y3 have impedance mutations, which can effectively reduce the signal reflection caused by the impedance mutation in the signal transmission circuit 20, thereby improving the quality of the signal received by the first receiving unit 220 and the second receiving unit 230.

[0176] Understandably, in Fig.29 and Fig.30 In the embodiment shown, only the first impedance device 212 or resistor R1, the second impedance device 214 or resistor R2, and the seventh impedance device 216 or resistor R7 are shown in the transmitting unit 210. In some other embodiments, such as Fig.32 As shown, the sending unit 210 may further include a resistor Rpu_ta, a resistor Rpd_ta, a resistor Rpu_tb, a resistor Rpd_tb, a resistor Rpu_tc, and a resistor Rpd_tc. The resistors Rpu_ta, Rpd_ta, Rpu_tb, Rpd_tb, Rpu_tc, and Rpd_tc are used to output intermediate level signals to the first receiving unit 220 and the second receiving unit 230 when the signal transmission circuit 20 is working. Its working process is as described in the related art above, and will not be repeated here. It can be understood that when the signal transmission circuit 20 is working, the resistors Rpu_ta, Rpd_ta, Rpu_tb, Rpd_tb, Rpu_tc, and Rpd_tc will neither affect the voltage of the signal received by the first receiving unit 220 and the second receiving unit 230, nor affect the impedance matching relationship between each wire and the impedance device.

[0177] The present application also provides an electronic device, which includes a signal transmission circuit 20 as in any one of the above embodiments. Figure 1 or Figure 2 shown.

[0178] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A signal transmission circuit, characterized in that: The signal transmission circuit includes a sending unit, a first receiving unit and a second receiving unit; The signal output end of the sending unit is connected to a preset node through a first wire group, the input end of the first receiving unit is connected to the preset node through a second wire group, and the input end of the second receiving unit is connected to the preset node through a third wire group; The impedance of the first receiving unit and the impedance of the second receiving unit are both greater than the impedance of the sending unit, and the difference between the impedance of the second wire group and the impedance of the first receiving unit is within a first impedance range, and the difference between the impedance of the third wire group and the impedance of the second receiving unit is within a second impedance range.

2. The signal transmission circuit according to claim 1, characterized in that: The sending unit includes a first impedance device and a second impedance device, the first receiving unit includes a third impedance device and a fourth impedance device, and the second receiving unit includes a fifth impedance device and a sixth impedance device; the preset node includes a first node and a second node, the first wire group includes a first wire and a second wire, the second wire group includes a third wire and a fourth wire, and the third wire group includes a fifth wire and a sixth wire; The first end of the first impedance device can be connected to one of the preset voltage terminal and the ground wire; the second end of the first impedance device is connected to the first node through the first wire; the first end of the third impedance device is connected to the first node through the third wire; the second end of the third impedance device is connected to the second end of the fourth impedance device; the first end of the fifth impedance device is connected to the first node through the fifth wire; the second end of the fifth impedance device is connected to the second end of the sixth impedance device; the first end of the second impedance device can be connected to one of the preset voltage terminal and the ground wire; the second end of the second impedance device is connected to the second node through the second wire; the first end of the fourth impedance device is connected to the second node through the fourth wire; the first end of the sixth impedance device is connected to the second node through the sixth wire.

3. The signal transmission circuit according to claim 2, characterized in that: The impedance of the first impedance device is equal to the impedance of the second impedance device, the impedance of the third impedance device is equal to the impedance of the fourth impedance device, and the impedance of the fifth impedance device is equal to the impedance of the sixth impedance device.

4. The signal transmission circuit according to claim 3, characterized in that: The impedance of the third impedance device is at least 1.2 times the impedance of the first impedance device, and the impedance of the third impedance device is at most 2 times the impedance of the first impedance device; The impedance of the fifth impedance device is at least 1.2 times the impedance of the first impedance device, and the impedance of the fifth impedance device is at most 2 times the impedance of the first impedance device.

5. The signal transmission circuit according to any one of claims 2 to 4, characterized in that: The first impedance range includes a first impedance sub-range and a second impedance sub-range; the difference between the characteristic impedance of the third conductor and the impedance of the third impedance device is within the first impedance sub-range, and the difference between the characteristic impedance of the fourth conductor and the impedance of the fourth impedance device is within the second impedance sub-range; The second impedance range includes a third impedance sub-range and a fourth impedance sub-range; the difference between the characteristic impedance of the fifth conductor and the impedance of the fifth impedance device is within the third impedance sub-range, and the difference between the characteristic impedance of the sixth conductor and the impedance of the sixth impedance device is within the fourth impedance sub-range.

6. The signal transmission circuit according to claim 5, characterized in that: The minimum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and -10%, and the maximum value of the first impedance sub-range is equal to the product of the impedance of the third impedance device and 10%; the minimum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and -10%, and the maximum value of the second impedance sub-range is equal to the product of the impedance of the fourth impedance device and 10%; the minimum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and -10%, and the maximum value of the third impedance sub-range is equal to the product of the impedance of the fifth impedance device and 10%; the minimum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and -10%, and the maximum value of the fourth impedance sub-range is equal to the product of the impedance of the sixth impedance device and 10%.

7. The signal transmission circuit according to any one of claims 2 to 6, characterized in that: A difference between an impedance of the first conductor group and an impedance of the transmitting unit is within a third impedance range.

8. The signal transmission circuit according to claim 7, characterized in that: The third impedance range includes a fifth impedance sub-range and a sixth impedance sub-range; the difference between the characteristic impedance of the first conductor and the impedance of the first impedance device is within the fifth impedance sub-range, and the difference between the characteristic impedance of the second conductor and the impedance of the second impedance device is within the sixth impedance sub-range.

9. The signal transmission circuit according to claim 8, characterized in that: The minimum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and -10%, and the maximum value of the fifth impedance sub-range is equal to the product of the impedance of the first impedance device and 10%; The minimum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and -10%, and the maximum value of the sixth impedance sub-range is equal to the product of the impedance of the second impedance device and 10%.

10. The signal transmission circuit according to any one of claims 2 to 9, characterized in that: The width of the first wire is greater than that of the third wire, and the width of the first wire is greater than that of the fifth wire; the width of the second wire is greater than that of the fourth wire, and the width of the second wire is greater than that of the sixth wire.

11. The signal transmission circuit according to any one of claims 2 to 10, characterized in that: The sending unit further includes a seventh impedance device, the first receiving unit further includes an eighth impedance device, and the second receiving unit further includes a ninth impedance device; the preset node further includes a third node; the first wire group further includes a seventh wire, the second wire group further includes an eighth wire, and the third wire group further includes a ninth wire; The first end of the seventh impedance device can be connected to the preset voltage terminal and one of the ground wires; the second end of the seventh impedance device is connected to the third node through the seventh wire; the first end of the eighth impedance device is connected to the third node through the eighth wire; the second end of the eighth impedance device is connected to the second end of the third impedance device and the second end of the fourth impedance device; the first end of the ninth impedance device is connected to the third node through the ninth wire; the second end of the ninth impedance device is connected to the second end of the fifth impedance device and the second end of the sixth impedance device.

12. The signal transmission circuit according to claim 11, characterized in that: The impedance of the seventh impedance device, the impedance of the first impedance device and the impedance of the second impedance device are all equal; the impedance of the eighth impedance device, the impedance of the third impedance device and the impedance of the fourth impedance device are all equal; the impedance of the ninth impedance device, the impedance of the fifth impedance device and the impedance of the sixth impedance device are all equal; The impedance of the eighth impedance device is at least 1.2 times the impedance of the seventh impedance device, and the impedance of the eighth impedance device is at most 2 times the impedance of the seventh impedance device; The impedance of the ninth impedance device is at least 1.2 times the impedance of the seventh impedance device, and the impedance of the ninth impedance device is at most 2 times the impedance of the seventh impedance device.

13. The signal transmission circuit according to claim 11 or 12, characterized in that: The first impedance range includes a seventh impedance sub-range, and the difference between the characteristic impedance of the eighth conductor and the impedance of the eighth impedance device is within the seventh impedance sub-range; the minimum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and -10%, and the maximum value of the seventh impedance sub-range is equal to the product of the impedance of the eighth impedance device and 10%; The second impedance range includes an eighth impedance sub-range, and the difference between the characteristic impedance of the ninth conductor and the impedance of the ninth impedance device is within the eighth impedance sub-range; the minimum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and -10%, and the maximum value of the eighth impedance sub-range is equal to the product of the impedance of the ninth impedance device and 10%.

14. The signal transmission circuit according to any one of claims 11 to 13, characterized in that: The difference between the characteristic impedance of the seventh conductor and the impedance of the seventh impedance device is within a ninth impedance sub-range, the minimum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and -10%, and the maximum value of the ninth impedance sub-range is equal to the product of the impedance of the seventh impedance device and 10%.

15. An electronic device, characterized in that: Comprising the signal transmission circuit as claimed in any one of claims 1 to 14.

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