Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises multiple stages of shifting registers. The shift register comprises an input module, a first potential control module, a second potential control module, a first output module and a second output module, the first output module is used for outputting a second clock signal as a first gate driving signal in response to the potential of the first node, or outputting a second potential signal as the first gate driving signal in response to the potential of the second node; the second output module is used for outputting the frequency control signal as a second gate driving signal in response to the potential of the first node, or outputting the first potential signal as the second gate driving signal in response to the potential of the third node; wherein the frequency control signal controls the frequency of the conduction level in the second gate drive signal by controlling the potential of the output end of the second output module.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the application scenarios of display devices are increasing, and users' display requirements for display devices are becoming more and more diverse. Based on the release of products such as foldable mobile phones and foldable laptops, the application scenarios of display devices have been further expanded. In response to users' demand for simultaneous display of multiple applications on terminal products, some interfaces in the display screen (such as game interfaces) need to be displayed at high frequency to ensure the smoothness of the picture, and some interfaces can meet the display requirements with low frequency. This part expects to use low-frequency display to reduce product power consumption. However, the scanning drive circuit in the prior art only supports the full-screen switching frequency of the display panel, which cannot meet the user's demand for the terminal product to display multiple scenes on one screen, cannot realize the partitioned frequency display of the display device, and cannot adjust the partition position. Summary of the invention

[0003] The present invention provides a display panel and a display device, so that the display device has a partition multi-frequency display function, and the partition position is adjustable.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising: a gate driving circuit, the gate driving circuit comprising a multi-stage shift register; the shift register comprising: an input module, a first potential control module, a second potential control module, a first output module, and a second output module; the output end of the input module is connected to a first node, and is used to respond to a first clock signal and transmit the input signal to the first node; the first potential control module is connected between the first node and the second node, and is used to respond to the potential of the first node and transmit the first potential signal or the second potential signal to the second node; the second potential control module is connected between the second node and the third node, and is used to transmit the second potential signal or the second potential signal to the second node according to the first potential signal and the first clock signal. The potential of the node is transmitted to the third node; the first output module is connected to the first node and the second node respectively, and is used to respond to the potential of the first node and output the second clock signal as the first gate drive signal, or respond to the potential of the second node and output the second potential signal as the first gate drive signal; the second output module is connected between the first node and the third node, and is used to respond to the potential of the first node and output the frequency control signal as the second gate drive signal, or respond to the potential of the third node and output the first potential signal as the second gate drive signal; wherein the frequency control signal controls the frequency of the conduction level in the second gate drive signal by controlling the potential of the output end of the second output module.

[0005] In a second aspect, an embodiment of the present invention provides a display device, including the display panel provided by any embodiment of the present invention.

[0006] The display panel provided by the embodiment of the present invention includes a gate drive circuit, and the gate drive circuit includes a plurality of shift registers, each of which includes: an input module, a first potential control module, a second potential control module, a first output module, and a second output module. The conduction state of the transistor in the second output module can be controlled by the potential of the first node and the potential of the third node, so that the output end of the second output module outputs a second gate drive signal, and the high and low level states of the second gate drive signal can be controlled by controlling the high and low level states of the frequency control signal, so as to realize the control of the shift register working mode. By controlling the potential jump process of the frequency control signal, the working mode combination mode of each shift register can be controlled to be different, so that the frequency of the conduction level in the second gate drive signal output by at least two shift registers is different, so as to realize the partitioned frequency display of the display panel. At the same time, the shift register can generate two gate drive signals at the same time, and compared with the traditional shift register that can only generate a single gate drive signal, the number of shift registers used in the display panel can be reduced. The reduction in the number of shift registers helps to reduce the frame size of the display panel, improve the screen ratio of the display panel, bring a better visual experience to the user, and thus improve the user experience.

[0007] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 It is a schematic diagram of the composition of a display frame at different refresh frequencies;

[0010] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0011] Figure 3 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0012] Figure 4 is a driving timing diagram of a shift register provided by an embodiment of the present invention;

[0013] Figure 5is a driving timing diagram of another shift register provided by an embodiment of the present invention;

[0014] Figure 6 is a schematic diagram of a three-part screen of a display panel provided by an embodiment of the present invention;

[0015] Figure 7 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0016] Figure 8 is a schematic diagram of the frequency control signal jump between the first display frame and the second display frame provided by an embodiment of the present invention;

[0017] Fig. 9 is a structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0018] Fig.10 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0019] Fig.11 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0020] Fig.12 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0021] Fig.13 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0022] Fig.14 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0023] Fig.15 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0024] Fig.16 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0025] Fig.17 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0026] Fig.18 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0027] Fig.19 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0028] Fig. 20 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0029] Fig.21 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0030] Fig. 22 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0031] Fig.23 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0032] Fig.24 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0033] Figure 25 to Figure 28 They are respectively schematic diagrams of the working process of the shift register provided by the embodiments of the present invention at each stage;

[0034] Fig.29 It is a simulation waveform diagram of each key node of a shift register provided by an embodiment of the present invention working in a high-frequency working mode;

[0035] Fig.30 It is a simulation waveform diagram of each key node of a shift register provided by an embodiment of the present invention working in a low-frequency working mode;

[0036] Fig.31 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0037] Fig.32 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0038] Fig.33 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0039] Fig.34 It is a structural schematic diagram of another display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0042] The display panel generally includes a display panel and a pixel circuit arrayed in the display area of ​​the display panel. The display panel includes a plurality of shift registers arranged in cascade, and the pixel circuit cooperates with the light-emitting device to form a sub-pixel. Each level of shift register is connected to at least one gate drive signal line, and provides a gate drive signal to the corresponding row of sub-pixels through the gate drive signal line, and each column of sub-pixels is connected to a data line.

[0043] During the picture display process, data is written to each pixel circuit by scanning line by line, that is, the shift register provides the pixel circuit with a gate drive signal through the gate drive signal line, and the data voltage on the data line is transmitted to the corresponding pixel circuit corresponding to the on-potential duration of the gate drive signal to realize data writing, and each pixel circuit outputs a drive current according to the data voltage to drive the light-emitting device to emit light for display. When the gate drive signal line provides the off-potential, the data voltage on the data line cannot be transmitted to the corresponding pixel circuit, and data writing is not performed.

[0044] In the prior art, for a display panel capable of switching display frequency, the display frame of a sub-pixel can be divided into a refresh frame and a hold frame. In the refresh frame, the shift register provides an on-state potential to the pixel circuit so that the data voltage is written into the pixel circuit; in the hold frame, the shift register provides an off-state potential to the pixel circuit so that the pixel circuit no longer writes data.

[0045] The refresh rate can be understood as the number of refresh frames contained in a unit time. For example, the high frequency display may only include refresh frames. Figure 1, a refresh frame is represented by a shaded box, and a hold frame is represented by a blank box. At the refresh frequency f, the display frame of the display panel only includes refresh frames. Exemplarily, when f=60Hz, the display panel refreshes 60 display frames within 1 second. The low-frequency refresh is implemented as follows: when the refresh frequency is reduced, a hold frame is inserted between adjacent refresh frames, the total number of display frames contained in a unit time remains unchanged, and the display duration of each display frame remains unchanged. When the refresh frequency is f / 2, 1 hold frame is inserted between every two adjacent refresh frames. When the refresh frequency is f / 3, 2 hold frames are inserted between every two adjacent refresh frames. Similarly, when the refresh frequency is f / (N+1), N hold frames are inserted between every two adjacent refresh frames.

[0046] In the driving process of the existing display device, the input signal provided to the first-stage shift register in the scan drive circuit is usually adjusted to control whether the shift registers of each stage output the conduction potential of the gate drive signal, thereby realizing the frequency switching of the whole screen. However, in the prior art, there can only be one refresh frequency for the whole screen of the display panel in one frame display, so only the frequency switching of the whole screen can be realized, and it is impossible to support the display of different frequencies in multiple partitions of the display device in one screen.

[0047] In order to solve the above technical problem, an embodiment of the present invention provides a display panel. Figure 2 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 2 The display panel includes: pixel circuits PX arranged in an array, at least one gate driving circuit 210, multiple gate driving signal lines LS and multiple clock signal lines. The gate driving circuit 210 is electrically connected to the pixel circuits PX of the corresponding row through the multiple gate driving signal lines LS; the multiple clock signal lines are electrically connected to at least one gate driving circuit 210.

[0048] For example, see Figure 2 The display panel includes a display area AA and a non-display area NAA. The display area AA is provided with pixel circuits PX arranged in an array, and the gate driving circuit 210 is provided in the non-display area NAA.

[0049] The display panel also includes a driver chip, which is connected to the gate driving circuit via a clock signal line to output a clock pulse signal to the gate driving circuit. The driver chip can input clock pulse signals to at least two clock signal lines, and the clock signal lines can transmit the clock pulse signals to the gate driving circuit 210.

[0050] The pixel circuit PX may have the structure of any existing pixel driving circuit. The gate driving circuit 210 may include a plurality of cascaded shift registers, and each shift register may be connected to a functional module in one or more rows of pixel circuits PX through a corresponding gate driving signal line LS, such as a functional module in the pixel circuit PX for controlling the gate of the driving transistor for initialization. Exemplarily, a row of pixel circuits PX may also correspond to two shift registers, wherein a first shift register may also be connected to a functional module in an odd-numbered column pixel circuit PX in a row of pixel circuits PX through a corresponding gate driving signal line LS, and another shift register may also be connected to a functional module in an even-numbered column pixel circuit PX in a row of pixel circuits PX through a corresponding gate driving signal line LS.

[0051] The gate drive circuit 210 may be a scanning circuit or a light emitting control drive circuit. The gate drive circuit 210 is used to output a gate drive signal based on at least an input signal and a clock pulse signal. The gate drive signal is transmitted to the pixel unit of the display panel display area AA through the gate drive signal line LS, and is used to drive the pixel unit to display. Among them, the pixel unit includes a pixel circuit PX and a light emitting element. Exemplarily, the gate drive signal may include a gate drive signal, and may also include a light emitting control signal. Exemplarily, when the display panel includes multiple rows of pixel circuits PX, multiple shift registers in each gate drive circuit are cascaded. Multiple cascaded shift registers provide gate drive signals for at least one row of pixel circuits PX respectively. Among them, the input signal of the first-stage shift register may include an input signal provided by the driver chip to the start signal line STV, and the input signal of the other-stage shift register may be a gate drive signal output by the previous-stage shift register.

[0052] For example, Figure 2 The example shows that the multiple clock signal lines may include a first clock signal line CK1 and a second clock signal line CK2, which is not limited in any way. The first clock signal line CK1 may be set to provide a first clock signal to an odd-numbered shift register, and a second clock signal to an even-numbered shift register. The second clock signal line CK2 may be set to provide a second clock signal to an odd-numbered shift register, and a first clock signal to an even-numbered shift register.

[0053] Figure 3 Schematic diagram of a gate drive circuit provided by an embodiment of the present invention. Figure 3 As shown, the gate driving circuit includes: a multi-stage shift register 10, for example, a plurality of shift registers 10 arranged in cascade. The shift registers 10 at each stage may have the same or similar structure. Figure 3The first two stages of shift registers 10 are exemplarily given in FIG. The shift register 10 (each shift register 10 in at least one shift register 10) may include: an input module 11, a first potential control module 12, a second potential control module 13, a first output module 14 and a second output module 15.

[0054] The output end of the input module 11 is connected to the first node N1, and is used to transmit the input signal SIN to the first node N1 in response to the first clock signal SCK1. The first potential control module 12 is connected between the first node N1 and the second node N2, and is used to transmit the first potential signal VGL or the second potential signal VGH to the second node N2 in response to the potential of the first node N1. The second potential control module 13 is connected between the second node N2 and the third node N3, and is used to transmit the potential of the second node N2 to the third node N3 according to the first potential signal VGL and the first clock signal SCK1. The first output module 14 is connected to the first node N1 and the second node N2, respectively, and is used for responding to the potential of the first node N1 to output the second clock signal SCK2 as the first gate drive signal S1, or responding to the potential of the second node N2 to output the second potential signal VGH as the first gate drive signal S1; the second output module 15 is connected between the first node N1 and the third node N3, and is used for responding to the potential of the first node N1 to output the frequency control signal VFE as the second gate drive signal S2, or responding to the potential of the third node N3 to output the first potential signal VGL as the second gate drive signal S2; wherein the frequency control signal VFE controls the frequency of the conduction level appearing in the second gate drive signal S2 by controlling the potential of the output end of the second output module 15.

[0055] Optionally, when the display panel includes multiple rows of pixel units, multiple shift registers 10 are cascaded to provide gate drive signals for at least one row of pixel units respectively. The input signal SIN of the first-stage shift register may be an input signal provided by the driver chip to the input end of the input module 11 of the first-stage shift register, and the input signal SIN of the other-stage shift register is the first gate drive signal S1 output by the previous-stage shift register. In other words, the output end out1 of the first output module 14 of the previous-stage shift register is connected to the input end of the input module 11 of the next-stage shift register to provide the input signal SIN for the next-stage shift register.

[0056] Exemplarily, the first potential signal VGL is the cut-off level of the functional module connected to the gate drive signal in the pixel circuit, and the second potential signal VGH is the on-level of the functional module connected to the gate drive signal in the pixel circuit, and the functional module is, for example, a functional module that controls the data voltage writing process of the gate of the driving transistor in the pixel circuit. The first potential signal VGL and the second potential signal VGH can both be DC voltage signals, for example, the first potential signal VGL is a low level, and the second potential signal VGH is a high level. The first clock signal SCK1 and the second clock signal SCK2 can include a low level and a high level.

[0057] Exemplarily, the first control terminal of the first output module 14 is connected to the first node N1, the second control terminal of the first output module 14 is connected to the second node N2, the first input terminal of the first output module 14 is connected to the second potential signal VGH, the second input terminal of the first output module 14 is connected to the second clock signal SCK2, and the output terminal of the first output module 14 outputs the first gate drive signal S1. Then, the first output module 14 can control whether the second input terminal is connected to the output terminal according to the potential of the first control terminal (the first node N1), thereby controlling whether the second clock signal SCK2 is output as the first gate drive signal S1; and control whether the first input terminal is connected to the output terminal according to the potential of the second control terminal (i.e., the second node N2), thereby controlling whether the second potential signal VGH is output as the first gate drive signal S1.

[0058] The third node N3 is connected to the third node N3, the second control terminal of the second output module 15 is connected to the first node N1, the first input terminal of the second output module 15 is connected to the first potential signal VGL, the second input terminal of the second output module 15 is connected to the frequency control signal VFE, and the output terminal of the second output module 15 outputs the second gate drive signal S2. Then, the second output module 15 can control whether the first input terminal and the output terminal are connected according to the potential of its first control terminal (i.e., the third node N3), thereby controlling whether the first potential signal VGL is output as the second gate drive signal S2; and according to the potential of the second control terminal (i.e., the first node N1), control whether the second input terminal and the output terminal are connected, thereby controlling whether the frequency control signal VFE is output as the second gate drive signal S2.

[0059] When the second output module 15 controls the connection between the second input terminal and the output terminal according to the potential of its second control terminal, if the frequency control signal VFE is an on-level signal (such as a high-level signal), then the second gate drive signal S2 is also an on-level signal, which is equivalent to the second gate drive signal S2 including an on-level in the display frame; if the frequency control signal VFE is an off-level signal (such as a low-level signal), then the second gate drive signal S2 is an off-level signal, which is equivalent to the gate drive signal not including an on-level in the display frame. Therefore, the frequency control signal VFE can control the working mode of the shift register 10 by controlling the state of the second gate drive signal S2 output by the second output module 15. Among them, the frequency of the gate drive signal can be considered as the pulse frequency of the on-level in the gate drive signal. The on-level is the level at which the functional module in the pixel circuit is turned on, and the off-level is the level at which the functional module in the pixel circuit is turned off. The on-level can be a high level and the off-level is a low level; or, the on-level can be a low level and the off-level is a high level.

[0060] For the convenience of explanation, the working mode in which the shift register 10 can realize the shift output of the conduction level in the input signal SIN is called the high-frequency working mode, and the working mode in which the shift register 10 cannot realize the shift output of the conduction level in the input signal is called the low-frequency working mode. Then, the frequency control signal VFE can control the working mode of the shift register 10 by controlling the state of the second gate drive signal S2 output by the second output module 15. When a certain level of shift register 10 always works in the high-frequency working mode, it can realize the shift output of the conduction level in its input signal SIN, so that the frequency of the second gate drive signal S2 is the same as the frequency of the input signal SIN; when a certain level of shift register 10 is in the low-frequency working mode for at least part of the time period, the frequency of the second gate drive signal S2 output by the shift register 10 is lower than the frequency of the input signal SIN connected thereto.

[0061] Figure 4 is a driving timing diagram of a shift register provided by an embodiment of the present invention, which can be used to drive Figure 3 The shift register shown in Figure 1 is referenced Figure 3 and Figure 4, the driving timing of the shift register includes five stages, namely the first stage P1, the second stage P2, the third stage P3 and the fourth stage P4. Take the signal input by the first potential signal VGL as a low-level signal and the second potential signal VGH as a high-level signal as an example. In the high-frequency working mode, the frequency control signal VFE is a conduction level signal. The frequency control signal VFE can control the second gate drive signal S2 output by the second output module 15 to include a high-level state, which is equivalent to including a high-level pulse signal. The effective potential of the pulse signal is a high level, and the ineffective potential of the pulse signal is a low level. The specific process is as follows:

[0062] In the first stage P1, the input signal SIN and the first clock signal SCK1 are at a low level, and the second clock signal SCK2 is at a high level. The input module 11 is turned on in response to the low-level first clock signal, and the input signal SIN is transmitted to the first node N1. The first potential control module 12 responds to the low level of the first node N1, and transmits the second potential signal VGH (i.e., a high level) to the second node N2, so that the potential of the second node N2 is a high level. The first output module 14 responds to the potential of the first node N1, and outputs the high level of the second clock signal SCK2 as the first gate drive signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the conduction level signal (such as a high level signal) of the frequency control signal VFE as the second gate drive signal S2. That is, in the first stage P1, the first gate drive signal S1 output by the first output module 14 is consistent with the second gate drive signal S2 output by the second output module 15, and both are high-level signals. That is to say, at this time, the second gate drive signal S2 output by the second gate drive signal output terminal of the shift register is a high level. Thereby, the shift output of the input signal SIN can be realized, that is, in the current frame, the pixel unit corresponding to the shift register is normally displayed according to the second gate driving signal, so that the display refresh rate of the display panel is the same as the frequency of the input signal SIN.

[0063] In the second stage P2, the input signal SIN and the first clock signal SCK1 jump to a high level, and the second clock signal SCK2 jumps to a low level. The first node N1 remains at a low level, the first potential control module 12 responds to the low level of the first node N1, and transmits the second potential signal VGH (i.e., a high level) to the second node N2, so that the potential of the second node N2 is a high level. The first output module 14 responds to the potential of the first node N1, and outputs the low level of the second clock signal SCK2 as the first gate drive signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the conduction level signal (such as a high level signal) of the frequency control signal VFE as the second gate drive signal S2. That is, in the second stage P2, the first gate drive signal S1 output by the first output module 14 is a low level signal, and the second gate drive signal S2 output by the second output module 15 is a high level signal.

[0064] In the third stage P3, the input signal SIN maintains a high level, the first clock signal SCK1 jumps to a low level, and the second clock signal SCK2 jumps to a high level. The first node N1 jumps to a high level, the first potential control module 12 responds to the high level of the first node N1, and transmits the first potential signal VGL (i.e., a low level) to the second node N2, so that the potential of the second node N2 is a low level. The second potential control module 13 is turned on according to the first potential signal VGL and the first clock signal SCK1, and transmits the low level of the second node N2 to the third node N3, so that the potential of the third node N3 is a low level. The first output module 14 responds to the potential of the second node N2 and outputs the second potential signal VGH as the first gate drive signal S1. The second output module 15 responds to the potential of the third node N3 and outputs the first potential signal VGL as the second gate drive signal S2. That is, in the third stage P3, the first gate drive signal S1 output by the first output module 14 is a high level signal, and the second gate drive signal S2 output by the second output module 15 is a low level signal.

[0065] In the fourth stage P4, the input signal SIN maintains a high level, the first clock signal SCK1 jumps to a high level, and the second clock signal SCK2 jumps to a low level. The first node N1 maintains a high level, the first potential control module 12 responds to the high level of the first node N1, and transmits the first potential signal VGL (i.e., a low level) to the second node N2, so that the potential of the second node N2 is a low level. The second potential control module 13 is turned on according to the first potential signal VGL and the first clock signal SCK1, and transmits the low level of the second node N2 to the third node N3, so that the potential of the third node N3 is a low level. The first output module 14 responds to the potential of the second node N2 and outputs the second potential signal VGH as the first gate drive signal. The second output module 15 responds to the potential of the third node N3 and outputs the first potential signal VGL as the second gate drive signal. That is, in the fourth stage P4, the first gate drive signal S1 output by the first output module 14 is a high level signal, and the second gate drive signal S2 output by the second output module 15 is a low level signal.

[0066] Figure 5 is another driving timing diagram of a shift register provided by an embodiment of the present invention, which can be used to drive Figure 3 The shift register shown in Figure 1 is referenced Figure 3 and Figure 5 , the driving timing of the shift register includes five stages, namely the first stage P1, the second stage P2, the third stage P3 and the fourth stage P4. Take the signal input by the first potential signal VGL as a low-level signal and the second potential signal VGH as a high-level signal as an example. In the low-frequency working mode, the frequency control signal VFE is a turn-off level signal, and the frequency control signal VFE controls the second gate drive signal S2 output by the second output module 15 to include only a low-level state (the output is maintained at the non-effective potential of the pulse signal). The specific process is as follows:

[0067] In the first stage P1, the input signal SIN and the first clock signal SCK1 are at a low level, and the second clock signal SCK2 is at a high level. The input module 11 is turned on in response to the low-level first clock signal, and transmits the input signal SIN to the first node N1. The first potential control module 12 responds to the low level of the first node N1, and transmits the second potential signal VGH (i.e., a high level) to the second node N2, so that the potential of the second node N2 is a high level. The first output module 14 responds to the potential of the first node N1, and outputs the high level of the second clock signal SCK2 as the first gate drive signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the off-level signal (such as a low-level signal) of the frequency control signal VFE as the second gate drive signal S2. That is, in the first stage P1, the first gate drive signal S1 output by the first output module 14 is a high-level signal, and the second gate drive signal S2 output by the second output module 15 is a low-level signal. That is to say, at this time, the second gate drive signal S2 outputted from the second gate drive signal output terminal of the shift register is at a low level, and the shift output of the input signal SIN cannot be realized, that is, in the current frame, the pixel unit corresponding to the shift register cannot be displayed normally according to the second gate drive signal S2, so that the display refresh rate of the display panel is lower than the frequency of the input signal SIN, thereby realizing the control of the display refresh rate of the pixel unit corresponding to the current shift register.

[0068] In the second stage P2, the input signal SIN and the first clock signal SCK1 jump to a high level, and the second clock signal SCK2 jumps to a low level. The first node N1 remains at a low level, the first potential control module 12 responds to the low level of the first node N1, and transmits the second potential signal VGH (i.e., a high level) to the second node N2, so that the potential of the second node N2 is a high level. The first output module 14 responds to the potential of the first node N1, and outputs the low level of the second clock signal SCK2 as the first gate drive signal S1. The second output module 15 responds to the potential of the first node N1, and outputs the conduction level signal (such as a high level signal) of the frequency control signal VFE as the second gate drive signal S2. That is, in the second stage P2, the first gate drive signal S1 output by the first output module 14 is consistent with the second gate drive signal S2 output by the second output module 15, and both are low level signals.

[0069] In the third stage P3, the input signal SIN maintains a high level, the first clock signal SCK1 jumps to a low level, and the second clock signal SCK2 jumps to a high level. The first node N1 jumps to a high level, the first potential control module 12 responds to the high level of the first node N1, and transmits the first potential signal VGL (i.e., a low level) to the second node N2, so that the potential of the second node N2 is a low level. The second potential control module 13 is turned on according to the first potential signal VGL and the first clock signal SCK1, and transmits the low level of the second node N2 to the third node N3, so that the potential of the third node N3 is a low level. The first output module 14 responds to the potential of the second node N2 and outputs the second potential signal VGH as the first gate drive signal S1. The second output module 15 responds to the potential of the third node N3 and outputs the first potential signal VGL as the second gate drive signal S2. That is, in the third stage P3, the first gate drive signal S1 output by the first output module 14 is a high level signal, and the second gate drive signal S2 output by the second output module 15 is a low level signal.

[0070] In the fourth stage P4, the input signal SIN maintains a high level, the first clock signal SCK1 jumps to a high level, and the second clock signal SCK2 jumps to a low level. The first node N1 maintains a high level, the first potential control module 12 responds to the high level of the first node N1, and transmits the first potential signal VGL (i.e., a low level) to the second node N2, so that the potential of the second node N2 is a low level. The second potential control module 13 is turned on according to the first potential signal VGL and the first clock signal SCK1, and transmits the low level of the second node N2 to the third node N3, so that the potential of the third node N3 is a low level. The first output module 14 responds to the potential of the second node N2 and outputs the second potential signal VGH as the first gate drive signal. The second output module 15 responds to the potential of the third node N3 and outputs the first potential signal VGL as the second gate drive signal. That is, in the fourth stage P4, the first gate drive signal S1 output by the first output module 14 is a high level signal, and the second gate drive signal S2 output by the second output module 15 is a low level signal.

[0071] Take the second gate drive signal S2 output by each shift register 10 as an example, which is transmitted to the functional module related to the data voltage writing process in each row of pixel circuits through each row of gate drive signal lines. When a certain level of shift register 10 works in a high-frequency working mode, since the second gate drive signal S2 includes a conduction level, the pixel circuit of the corresponding row can be controlled to refresh the data, so that the current frame of the pixel circuit of the row is a refresh frame; and when a certain level of shift register 10 works in a low-frequency working mode, since the second gate drive signal S1 does not include a conduction level, the pixel circuit of the corresponding row cannot refresh the data, so that the current frame of the pixel circuit of the row is a hold frame. Therefore, the frequency of the gate drive signal determines the data refresh frequency of the pixel circuit. Based on this, the working mode of each shift register 10 can be controlled in each frame display by controlling the potential jump of the frequency control signal VFE to realize the display of different frequencies of the partitions of the display device in the column direction.

[0072] by Figure 6Take the three-part screen in as an example, assuming that the display panel is divided into the first display partition A1, the second display partition A2 and the third display partition A3 from top to bottom, and the refresh frequencies of the three display partitions are, for example, the first refresh frequency f1, the second refresh frequency f2 and the first refresh frequency f1, f1>f2. Then, from the first display partition A1 to the second display partition A2 is equivalent to realizing the frequency division display of the display frequency from high to low, and from the second display partition A2 to the third display partition A3 is equivalent to realizing the frequency division display of the display frequency from low to high. Among them, the size of each display partition is determined by the number of shift registers 10 that provide the second gate drive signal S2 of the corresponding frequency. Taking the example of each display partition corresponding to the two-stage shift register 10, the frequency of the second gate drive signal S2 output by the shift register 10 corresponding to the first display partition A1 and the third display partition A3 is the first refresh frequency f1, for example, the first-stage, second-stage, fifth-stage and sixth-stage shift registers 10 are set to work in the high-frequency working mode in each display frame. The frequency of the second gate drive signal S2 output by the shift register 10 corresponding to the second display partition A2 is the second refresh frequency f2. For example, the third and fourth shift registers 10 are set to work in the high-frequency working mode in part of the display frame, and work in the low-frequency working mode in part of the display frame. That is, by controlling the frequency control signal VFE to keep the second gate drive signal S2 output by the second output module 15 including the off level in part of the display frame, the shift register 10 can work in the low-frequency working mode in part of the display frame. By controlling the frequency control signal VFE to perform potential jump in part of the display frame, the second gate drive signal S2 output by the second output module 15 in part of the display frame can include the on level, and the shift register 10 can work in the high-frequency working mode in part of the display frame, so that the frequencies of the second gate drive signals S2 output by at least two shift registers 10 are different, so as to realize the partitioned frequency display of the display panel. Furthermore, by adjusting the potential jump time of the frequency control signal VFE in one frame display, the boundary position of the shift register 10 working mode switching can be adjusted, thereby adjusting the display partition position of the display panel. The first-level shift register 10 is connected to at least one row of pixel circuits, and the number of shift registers 10 in the high-frequency working mode in one frame determines the number of pixel circuit rows refreshed in this frame.

[0073] The gate drive circuit provided in the embodiment of the present invention includes a plurality of shift registers, each of which includes: an input module, a first potential control module, a second potential control module, a first output module, and a second output module. The conduction state of the transistor in the second output module can be controlled by the potential of the first node and the potential of the third node, so that the output end of the second output module outputs the second gate drive signal, and the high and low level states of the second gate drive signal can be controlled by controlling the high and low level states of the frequency control signal, so as to realize the control of the shift register working mode. By controlling the potential jump process of the frequency control signal, the working mode combination of each shift register can be controlled to be different, so that the frequency of the conduction level in the second gate drive signal output by at least two shift registers is different, so as to realize the partitioned frequency display of the display panel. At the same time, the shift register can generate two gate drive signals at the same time, and compared with the traditional shift register that can only generate a single gate drive signal, the number of shift registers used in the display panel can be reduced. The reduction in the number of shift registers helps to reduce the frame size of the display panel, improve the screen ratio of the display panel, bring a better visual experience to the user, and thus improve the user experience.

[0074] Optionally, continue to refer to Figure 2 The display panel further includes at least one frequency control signal line ENL, which is used to provide a frequency control signal VFE to the shift register 10.

[0075] Figure 7 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 7 Optionally, the display panel includes k frequency control signal lines, the gate drive circuit includes a plurality of cascaded shift register groups 20, the shift register group 20 includes k cascaded shift register units 21, k is an integer greater than or equal to 2, the shift register unit 21 includes m shift registers 10, m is an integer greater than or equal to 1, different shift register units 21 in the same shift register group 20 are electrically connected to different frequency control signal lines, and different shift register groups 20 are connected to the same k frequency control signal lines;

[0076] The display partition includes a plurality of pixel circuit groups 30; the pixel circuit group 30 includes k sub-pixel circuit groups 31, and the sub-pixel circuit group 31 includes a plurality of rows of pixel circuits PX; the sub-pixel circuit groups 31 are electrically connected to the shift register unit 21 in a one-to-one correspondence; the output end of the primary shift register 10 is electrically connected to r rows of pixel circuits PX, where r is an integer greater than or equal to 1. Optionally, m is greater than or equal to 8, and k is greater than or equal to 4. Optionally, the number of rows of pixel circuits PX in each pixel circuit group 30 is the same.

[0077] in, Figure 7The case where k=4 is schematically shown in FIG. 4 . For example, m may be 16, and r may be 1. Each shift register group 20 may control the display conditions of k*m*r rows of pixel circuits. Figure 7 The shift register group 20 of the gate driving circuit in the display panel shown can be regarded as including four cascaded shift register units 21 and four frequency control signal lines, namely ENL1, EN2, ENL3 and ENL4. One frequency control signal line is connected to m shift registers 10 in one shift register unit 21. Each frequency control signal line can drive m*r rows of pixel circuits driven by one shift register unit 21, and the number of rows driven by four frequency control signal lines is one cycle.

[0078] Optionally, continue to refer to Figure 2 The display area AA of the display panel includes at least two display partitions, and the at least two display partitions include a first display partition A1 and a second display partition A2; the refresh frequency of the first display partition A1 is a first refresh frequency, and the refresh frequency of the second display partition A2 is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.

[0079] Figure 8 is a schematic diagram of the frequency control signal jump between the first display frame and the second display frame provided by an embodiment of the present invention, with reference to Figure 8 , in the first display frame, the moment when the pulse of the frequency control signal VFE of the k frequency control signal lines jumps to the conduction level NVGH is delayed in sequence; in the second display frame, the frequency control signals on the k frequency control signal lines are the conduction level NVGH. Among them, the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition, and is a refresh frame for the second display partition; the second display frame is a refresh frame for the first display partition and the second display partition; in the second display frame, the first display partition is refreshed before the second display partition;

[0080] Specifically, combined Figure 7 and Figure 8 The first display frame F1 is a refresh frame of at least one display partition and a hold frame of at least one display partition. Figure 8Taking the illustrated case as an example, the pixel circuit connected to the shift register corresponding to the off level NVGL works in the hold frame, and the pixel circuit connected to the shift register corresponding to the on level NVGH works in the refresh frame. In this case, the moment when the pulse of the signal on the k frequency control signal lines jumps to the enable level is delayed in sequence, so as to facilitate the completion of the partition multi-frequency control. The second display frame F2 is the refresh frame of each display partition. In the second display frame F2, the signal on the k frequency control signal lines is the on level, which can ensure that each display partition can be refreshed in the second display frame, and the signal on the frequency control signal line does not need to jump. The first frequency control signal line ENL1 transmits the first frequency control signal VFE1 to the corresponding shift register. The second frequency control signal line ENL2 transmits the second frequency control signal VFE2 to the corresponding shift register. The third frequency control signal line ENL3 transmits the third frequency control signal VFE3 to the corresponding shift register. The fourth frequency control signal line ENL4 transmits the fourth frequency control signal VFE4 to the corresponding shift register.

[0081] Optionally, k-1 shift register units 21 are connected between two adjacent shift register units 21 connected to the same frequency control signal line.

[0082] Specifically, the sub-pixel rows connected to the k partition enable signal lines are arranged periodically. Exemplarily, the number of sub-pixel rows connected to the first partition enable signal line ENL1 is 1 to 16 rows, 65 to 80 rows... The number of sub-pixel rows connected to the second partition enable signal line ENL2 is 17 to 32 rows, 81 to 96 rows... The number of sub-pixel rows connected to the third partition enable signal line ENL3 is 33 to 48 rows, 97 to 112 rows... The number of sub-pixel rows connected to the fourth partition enable signal line ENL4 is 49 to 64 rows, 98 to 128 rows...

[0083] Based on the above embodiments, continue to refer to Figure 4 and Figure 5 Optionally, the waveform of the second clock signal SCK2 is the same as the waveform of the first clock signal SCK1. That is, the duty cycle of the first clock signal SCK1 and the second clock signal SCK2 is the same, that is, in one cycle, the duration of the low level of the first clock signal SCK1 and the second clock signal SCK2 is the same, and the duration of the high level of the first clock signal SCK1 and the second clock signal SCK2 is the same.

[0084] Based on the above embodiments, continue to refer to Figure 4 and Figure 5Optionally, the period of the second clock signal SCK2 is the same as the period of the first clock signal SCK1. For example, the period of the first clock signal SCK1 and the second clock signal SCK2 is two line times, and the line time is related to the refresh frequency and resolution of the display panel, that is, the line time can be calculated according to the refresh frequency and resolution.

[0085] Based on the above embodiments, continue to refer to Figure 4 and Figure 5 Optionally, the waveform of the second clock signal SCK2 is delayed relative to the waveform of the first clock signal SCK1. In this way, when the first clock signal SCK1 is at a valid level (such as a low level), the second clock signal ECK2 is at an invalid level (such as a high level), and when the second clock signal SCK2 is at a valid level, the first clock signal SCK1 is at an invalid level. The first clock signal SCK1 and the second clock signal SCK2 will not be at a valid level at the same time, so that each module can be accurately controlled to avoid control disorder.

[0086] Based on the above embodiments, continue to refer to Figure 4 and Figure 5 Optionally, the waveform of the second clock signal SCK2 is half a cycle later than the waveform of the first clock signal SCK1. In this way, when the first clock signal SCK1 just controls the input module 11 to be turned on, the second clock signal SCK2 is at an invalid level, and will not couple and control the potential of the first node N1 to be a more effective level. Then, the input signal SIN is at a valid level and will not control the first output module 14 to be fully turned on, so that the first output module 14 can be shifted relative to the input signal SIN, so that the shift register can shift the input signal SIN to output.

[0087] Based on the above embodiments, continue to refer to Figure 4 and Figure 5 Optionally, the duration of the low level in the first clock signal SCK1 is less than or equal to half a cycle, and the duration of the high level in the first clock signal SCK1 is greater than half a cycle. Optionally, the duration of the low level in the second clock signal SCK2 is less than or equal to half a cycle, and the duration of the high level in the second clock signal SCK2 is greater than half a cycle. This arrangement can ensure that the turn-on time of the first clock signal SCK1 will not be too long, and the turn-on time of the second clock signal SCK2 will not be too long. There can be a blank area between the low level of the first clock signal SCK1 and the second clock signal SCK2, so as to avoid each module from responding to the low level actions of the first clock signal SCK1 and the second clock signal SCK2 at the same time, which is conducive to ensuring the accuracy of control.

[0088] Fig. 9 Schematic diagram of the structure of a shift register provided by an embodiment of the present invention. Fig. 9As shown, optionally, the first potential control module 12 includes a first inverter, and the first inverter includes a first transistor T1 and a second transistor T2.

[0089] The gate of the first transistor T1 is connected to the first node N1, the first electrode of the first transistor N1 is connected to the first potential signal VGL, and the second electrode of the first transistor T1 is connected to the second node N2. The gate of the second transistor T1 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the second potential signal VGH, and the second electrode of the second transistor T2 is connected to the second node N2.

[0090] Specifically, the first transistor T1 is turned on or off according to the potential of the first node N1 connected to its gate, and transmits the first potential signal VGL to the second node N2 when it is turned on. The second transistor T2 is turned on or off according to the potential of the first node N1 connected to its gate, and transmits the second potential signal VGH to the first node N1 when it is turned on. Among them, the channel types of the first transistor T1 and the second transistor T2 are different. For example, when the first transistor is an N-channel type transistor and the second transistor is a P-channel type transistor, the first transistor T1 is turned on when the potential of the first node N1 is a high potential, and the second transistor T2 is turned on when the potential of the first node N1 is a low potential. The potential of the second node N2 can be controlled by the first transistor T1 and the second transistor T2, and then the on or off state of the first output module 14 and the second output module 15 can be controlled, so as to realize the output control of the first gate drive signal S1 and the second gate drive signal S2. In addition, the structure of the transistor is simple and the manufacturing process is simple. When the shift register is applied to a display panel, the transistors in the shift register and the transistors on the display panel can be manufactured in the same process flow, thereby saving process flow and reducing costs.

[0091] Fig.10 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.10 As shown, optionally, the second potential control module 13 includes a third transistor T3 and a fourth transistor T4.

[0092] The gate of the third transistor T3 is connected to the first clock signal SCK1, the first electrode of the third transistor T3 is connected to the second node N2, the second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4. The gate of the fourth transistor T4 is connected to the first potential signal VGL, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0093] Specifically, the third transistor T3 is turned on or off according to the first clock signal SCK1 connected to its gate, and transmits the potential of the second node N2 to the first pole of the fourth transistor T4 when it is turned on. The fourth transistor T4 is turned on or off according to the first potential signal VGL connected to its gate, and transmits the potential of the first pole of the fourth transistor T4 to the third node N3 when it is turned on. Among them, the third transistor T3 and the fourth transistor T4 can be either P-type transistors or N-type transistors. For example, when the third transistor T3 and the fourth transistor T4 are both P-type transistors, and when the first clock signal SCK1 is a low potential signal, the third transistor T3 is always in a conducting state when the low potential signal input at the gate, and the fourth transistor T4 is turned on when the first potential signal VGL is a low potential signal, thereby transmitting the potential of the second node N2 to the third node N3. The second potential control module 13 is provided to include the third transistor T3 and the fourth transistor T4, so that the potential of the third node N3 can be effectively controlled. In addition, the structure of the transistor is simple and the manufacturing process is simple. When the shift register is applied to a display panel, the transistors in the shift register and the transistors on the display panel can be manufactured in the same process flow, thereby saving process flow and reducing costs.

[0094] Fig.11 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.11 As shown, optionally, the first output module 14 includes a first output unit 141 and a second output unit 142. The first output unit 141 is connected to the second node N2, and is used to output the second potential signal VGH as the first gate drive signal S1 according to the potential of the second node N2. The second output unit 142 is connected to the first node N1, and is used to output the second clock signal SCK2 as the first gate drive signal S1 according to the potential of the first node N1.

[0095] As a preferred implementation provided by the embodiment of the present invention, Fig.12 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.12 As shown, optionally, the first output unit 141 includes a fifth transistor T5, a gate of the fifth transistor T5 is connected to the second node N2, a first electrode of the fifth transistor T5 is connected to the second potential signal VGH, and a second electrode of the fifth transistor T5 serves as an output end of the first output unit 141.

[0096] The second output unit 142 includes a sixth transistor T6 and a first capacitor C1. The gate of the sixth transistor T6 is connected to the first node N1 and the first end of the first capacitor C1 respectively. The first electrode of the sixth transistor T6 is connected to the second end of the first capacitor C1 and serves as the output end of the second output unit 142. The second electrode of the sixth transistor T6 is connected to the second clock signal SCK2.

[0097] Among them, the fifth transistor T5 and the sixth transistor T6 can be P-type transistors or N-type transistors. The fifth transistor T5 is turned on or off in response to the potential of the second node N2, and when turned on, transmits the second potential signal VGH to the first gate drive signal output terminal out 1 of the shift register. The sixth transistor T6 is turned on or off in response to the potential of the first node N1, and when turned on, transmits the second clock signal SCK2 to the first gate drive signal output terminal out1 of the shift register. The first capacitor C1 has a storage function to achieve a charge retention effect. When the input signal SIN is transmitted to the first node N1, the first capacitor C1 will be charged and discharged to maintain the potential of the first node N1 to be the same as the potential of the previous stage when no input signal SIN is transmitted to the first node N1.

[0098] Fig.13 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.13 As shown, optionally, the second output module 15 includes a second inverter, and the second inverter includes a third output unit 151 and a fourth output unit 152 .

[0099] The third output unit 151 is connected to the first node N1, and is used to output the frequency control signal VFE as the second gate driving signal S2 according to the potential of the first node N1. The fourth output unit 152 is connected to the third node N3, and is used to output the first potential signal VGL as the second gate driving signal S2 according to the potential of the third node N3.

[0100] As a preferred implementation provided by the embodiment of the present invention, Fig.14 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.14 As shown, optionally, the third output unit 151 includes a seventh transistor T7, a gate of the seventh transistor T7 is connected to the first node N1, a first electrode of the seventh transistor T7 is connected to the frequency control signal VFE, and a second electrode of the seventh transistor T7 serves as an output end of the third output unit 151.

[0101] The fourth output unit 152 includes an eighth transistor T8 , a gate of the eighth transistor T8 is connected to the third node N3 , the eighth transistor T8 serves as an output end of the fourth output unit 152 , and a second electrode of the eighth transistor T8 is connected to the first potential signal VGL.

[0102] The seventh transistor T7 and the eighth transistor T8 may be P-type transistors or N-type transistors. The seventh transistor T7 is turned on or off in response to the potential of the first node N1, and when turned on, transmits the frequency control signal VFE to the second gate drive signal output terminal out2 of the shift register. The eighth transistor T8 is turned on or off in response to the potential of the third node N3, and when turned on, transmits the first potential signal VGL to the second gate drive signal output terminal out2 of the shift register.

[0103] Fig.15 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.15 As shown, optionally, the shift register further includes a pull-down module 16. The pull-down module 16 is connected between the first node N1 and the third node N3, and is used to control the potential of the third node N3 at least according to the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2.

[0104] The pull-down module 16 controls the potential of the third node N3 according to the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2, which means that the pull-down module 16 can control the potential of the third node N3 according to the potential of the first node N1, the first potential signal VGL and the second clock signal SCK2 when the potential of the second clock signal SCK2 jumps. For example, the pull-down module 16 can pull the potential of the third node N3 down to a potential lower than the potential corresponding to the second potential signal VGH. Since the second output module 15 can transmit the first potential signal VGL to the second gate drive signal output terminal out2 of the shift register in response to the potential of the third node N3 (such as a low level signal), if the potential of the third node N3 is not low enough (that is, the absolute value of the difference between the potential of the third node N3 and the second potential signal VGH is greater than the set threshold), the first potential signal VGL transmitted by the second output module 15 to the second gate drive signal output terminal out2 of the shift register will have a level loss. In the embodiment of the present invention, when the second output module 15 transmits the first potential signal VGL to the second gate drive signal output terminal out2 of the shift register in response to the low level signal of the third node N3, the pull-down module 16 is used to pull down the potential of the third node N3 to a potential lower than the second potential signal VGH, so that the potential of the third node N3 can reach a sufficiently low potential (the sufficiently low potential satisfies: the absolute value of the difference between the potential of the third node N3 and the second potential signal VGH is less than the set threshold), thereby reducing the level loss of the low level signal output from the second gate drive signal output terminal out2 of the shift register. When the second output module 15 includes a transistor whose gate is connected to the third node N3, whose first electrode is connected to the first potential signal VGL, and whose second electrode is connected to the second gate drive signal output terminal out2 of the shift register, the set threshold can be equal to the threshold voltage of the transistor.

[0105] Fig.16 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.16 As shown, optionally, the pull-down module 16 includes a first control unit 161 and a second control unit 162 .

[0106] The first control unit 161 is connected between the first node N1 and the fourth node N4, and is used to control the potential of the fourth node N4 according to the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2. The second control unit 162 is connected between the third node N3 and the fourth node N4, and is used to control the potential of the third node N3 according to the potential of the fourth node N4.

[0107] Fig.17 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.17As shown, optionally, the pull-down module further includes a third control unit 163, which is connected between the second node N2 and the fourth node N4, and is used to transmit the potential of the second node N2 to the fourth node N4 according to the first clock signal SCK1 and the first potential signal VGL.

[0108] As a preferred implementation provided by the embodiment of the present invention, Fig.18 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.18 As shown, optionally, the first control unit 161 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2.

[0109] The gate of the ninth transistor T9 is connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the second clock signal SCK2, and the second electrode of the ninth transistor T9 and the first electrode of the tenth transistor T10 are connected to the fifth node N5. The gate of the tenth transistor T10 is connected to the fourth node N4, and the second electrode of the tenth transistor T10 is connected to the second potential signal VGH. The first end of the second capacitor C2 is connected to the fourth node N4, and the second end of the second capacitor C2 is connected to the fifth node N5.

[0110] The second control unit 162 includes an eleventh transistor T11; the gate of the eleventh transistor T11 is connected to the first electrode of the eleventh transistor T11 and the gate of the ninth transistor T9 and serves as the first end of the second control unit 162, and the second electrode of the eleventh transistor T11 is connected to the third node N3.

[0111] Specifically, when the potential of the first node N1, the second potential signal VGH and the second clock signal SCK2 change, the tenth transistor T10 is turned on or off according to the potential of the first node N1. If the tenth transistor T10 is turned on, the second potential signal VGH will affect the potential of the first electrode of the tenth transistor T10. At the same time, the ninth transistor T9 controls its on or off according to the potential of the fourth node N4 and the state of the second clock signal SCK2, thereby affecting the potential of the fourth node N4. The second capacitor C2 plays the role of storing charge and stabilizing the potential in this process. For example, when the potential changes, it can maintain a certain potential state by charging and discharging, so that the potential change of the fourth node N4 is more stable and controllable.

[0112] The potential change of the fourth node N4 will directly affect the conduction state of the eleventh transistor T11. When the potential of the fourth node N4 reaches an ultra-low potential, the diode formed by the eleventh transistor T11 is forward biased, and the potential of the fourth node N4 will pull down the potential of the third node N3, and compensate the charge to the third node N3, so as to maintain the third node N3 at an ultra-low potential, thereby ensuring that the second output module 15 can accurately output the second gate drive signal S2 according to the potential of the third node N3, and avoid the output error of the second gate drive signal S2 due to the abnormal potential of the third node N3.

[0113] Optionally, continue to refer to Fig.18 The third control unit 163 includes: a twelfth transistor T12 and a thirteenth transistor T13; the gate of the twelfth transistor T12 is connected to the first clock signal SCK1, the first electrode of the twelfth transistor T12 is connected to the first node N1, and the second electrode of the twelfth transistor T12 is connected to the first electrode of the thirteenth transistor T13. The gate of the thirteenth transistor T13 is connected to the first potential signal VGL, and the second electrode of the thirteenth transistor T13 is connected to the fourth node N4.

[0114] The twelfth transistor T12 and the thirteenth transistor T13 are used to provide an initial low potential before the fourth node N4 is pulled down. The thirteenth transistor T13 is a protection transistor to prevent the twelfth transistor T12 from being affected by the ultra-low potential of the fourth node N4 for a long time, causing reliability problems.

[0115] Fig.19 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.19 As shown, optionally, the shift register further includes a third potential control module 17, which is connected between the first node N1 and the second node N2 and is used to control the potential of the first node N1 according to the potential of the second node N2.

[0116] Specifically, the third potential control module 17 is used to be turned on when the second node N2 is at a low level, and stably transmit the high level of the second potential signal VGH to the first node N1 to ensure that the first node N1 and the second node N2 are not at a low level at the same time, thereby ensuring that the output state of the first output module 14 is stable.

[0117] Fig. 20 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, such as Fig. 20As shown, optionally, the third potential control module 17 includes a fourteenth transistor T14; the gate of the fourteenth transistor T14 is connected to the second node N2, the first electrode of the fourteenth transistor T14 is connected to the second potential signal VGH, and the second electrode of the fourteenth transistor T14 is connected to the first node N1. In this embodiment, the third potential control module 17 is configured to be composed of one transistor, so that the third potential control module 17 has a simple structure and is easy to implement.

[0118] Fig.21 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.21 As shown, optionally, the third potential control module 17 also includes a fifteenth transistor T15; the gate of the fifteenth transistor T15 is connected to the second clock signal SCK2, the first electrode of the fifteenth transistor T15 is connected to the second electrode of the fourteenth transistor T14, and the second electrode of the fifteenth transistor T15 is connected to the first node N1.

[0119] This embodiment is configured to avoid signal competition caused by the two transmission paths of the third potential control module 17 and the input module 11. Specifically, when the second node N2 is at a low level and the first node N1 is at a low level, if the input signal SIN jumps to a low level, when the first clock signal SCK1 is set low, the low level of the input signal SIN is transmitted to the first node N1. The first potential control module 12 responds to the low level of the first node N1 and transmits the high level of the second potential signal VGH to the second node N2, so that the second node N2 jumps to a high level. Before the second node N2 jumps to a high level, the fourteenth transistor T14 remains turned on. If the fifteenth transistor T15 is not set, the fourteenth transistor T14 attempts to transmit a high level to the first node N1, and the third transistor M3 transmits a low level to the first node N1, which will cause signal competition and even cause the potential of the first node N1 to be unable to be normally pulled down. After the fifteenth transistor T15 is set, before the first clock signal SCK1 jumps to a low level, the second clock signal SCK2 has already jumped to a high level, and the fifteenth transistor T15 is controlled to be turned off, cutting off the transmission path of the third potential control module 17, which can effectively avoid signal competition.

[0120] Fig. 22 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig. 22 As shown, optionally, the shift register also includes a potential isolation module 18, the control end of the potential isolation module 18 is connected to the first potential signal VGL, the first end of the potential isolation module 18 is connected to the first node N1, the second end of the potential isolation module 18 is connected to the first control end of the first output module 14, and the potential isolation module 18 is used to turn on or off according to the potential difference between the first potential signal VGL and the first node N1.

[0121] This embodiment is set up in this way, so that the transmission of the extremely low potential generated by the coupling effect of the capacitor at the first control point of the first output module 14 to the first node N1 can be blocked, and the impact of the extremely low potential on each transistor connected to the first node N1 can be avoided. Specifically, when the first node N1 is at a low potential, since the first potential signal VGL is also at a low potential, the potential difference between the control end and the first end of the potential isolation module 18 is substantially 0, so that the potential isolation module 18 is in a critical off state. Then, when the capacitor in the first output module 14 pulls the first control end of the first output module 14 down to an extremely low potential, since the potential isolation module 18 is critically off, the extremely low potential cannot be transmitted to the first node N1, and will not impact the transistors in the input module 11 and the first potential control module 12. When the first node N1 is at a high potential, the potential difference between the control end and the first end of the potential isolation module 18 is greater than 0, so that the potential isolation module 18 is turned on, and the high potential of the first node N1 can be effectively transmitted to the first control end of the first output module 14. Therefore, the potential isolation module 18 only blocks the transmission path of the extremely low voltage to the first node N1 and does not affect the normal transmission of the high potential.

[0122] Optionally, the potential isolation module 18 includes a sixteenth transistor T16; the gate of the sixteenth transistor T16 serves as the control end of the potential isolation module 18, the first electrode of the sixteenth transistor T16 serves as the first end of the potential isolation module 18, and the second electrode of the sixteenth transistor T16 serves as the second end of the potential isolation module 18. In this embodiment, the potential isolation module 18 is configured to be composed of one transistor, so that the potential isolation module 18 has a simple structure and is easy to implement.

[0123] Fig.23 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.23 As shown, optionally, the input module 11 includes: a seventeenth transistor T17; the gate of the seventeenth transistor T17 is connected to the first clock signal SCK1, the first electrode of the seventeenth transistor T17 is connected to the input signal SIN, and the second electrode of the seventeenth transistor T17 is connected to the first node N1. In this embodiment, the input module 11 is configured to be composed of one transistor, so that the input module 11 has a simple structure and is easy to implement.

[0124] Fig.24 FIG. 1 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention. Fig.24 As shown, optionally, the shift register includes: an input module 11 , a first potential control module 12 , a second potential control module 13 , a first output module 14 and a second output module 15 .

[0125] Optionally, the first potential control module 12 includes a first transistor T1 and a second transistor T2. The second potential control module 13 includes a third transistor T3 and a fourth transistor T4.

[0126] Optionally, the first output module 14 includes a first output unit 141 and a second output unit 142. The first output unit 141 includes a fifth transistor T5, and the second output unit 142 includes a sixth transistor T6 and a first capacitor C1. Optionally, the second output module 15 includes a third output unit 151 and a fourth output unit 152. Optionally, the third output unit 151 includes a seventh transistor T7, and the fourth output unit 152 includes an eighth transistor T8.

[0127] Optionally, the shift register further includes a pull-down module 16. The pull-down module 16 includes a first control unit 161, a second control unit 162 and a third control unit 163. The first control unit 161 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2. The second control unit 162 includes an eleventh transistor T11. The third control unit 163 includes a twelfth transistor T12 and a thirteenth transistor T13.

[0128] Optionally, the shift register further includes a third potential control module 17, and the third potential control module 17 includes a fourteenth transistor T14 and a fifteenth transistor T15.

[0129] Optionally, the shift register further comprises a potential isolation module 18, and the potential isolation module 18 comprises a sixteenth transistor T16. Optionally, the input module 11 comprises a seventeenth transistor T17.

[0130] The second electrode of the sixteenth transistor T16, the gate of the sixth transistor T6 and the first end of the first capacitor C1 are connected to the sixth node N6.

[0131] Figure 4 and Figure 5 The driving timing of the shift register shown also applies to Fig.24 The shift register shown. The second transistor T2 to the seventeenth transistor T17 in the shift register may be P-type transistors, and the first transistor T1 may be an N-type transistor. The first potential signal VGL is a low-level signal and the second potential signal VGH is a high-level signal. Figure 2 and Fig.15 The driving timing of the shift register includes a first stage P1, a second stage P2, a third stage P3 and a fourth stage P4.

[0132] Figure 25 to Figure 28The following are schematic diagrams of the working process of the shift register provided by the embodiment of the present invention at each stage, in which the arrows indicate the direction of current flow, the circles indicate that the transistor is turned on, and the crosses indicate that the transistor is turned off. Figure 4 and Fig.25 , in the first stage P1, the input signal SIN and the first clock signal SCK1 are low level, the second clock signal SCK2 is high level, and the frequency control signal VFE is a high level signal. The seventeenth transistor T17 is turned on in response to the low level first clock signal SCK1, and the input signal SIN is transmitted to the first node N1, and the sixth transistor T6 is turned on, that is, the sixth transistor T6 responds to the potential of the first node N1, and outputs the high level of the second clock signal SCK2 as the first gate drive signal S1. The second transistor T2 responds to the low level of the first node N1, and transmits the second potential signal VGH (i.e., high level) to the second node N2, so that the potential of the second node N2 is high level, and the fifth transistor T5 is turned off. The fourteenth transistor T14 is turned off to prevent the second potential signal VGH from being written to the first node N1. The high level of the second node N2 is written to the third node N3, and the eighth transistor T8 is turned off. The seventh transistor T7 responds to the potential of the first node N1, and outputs the frequency control signal VFE as a high level signal as the second gate drive signal S2. That is, in the first phase P1 , the first gate driving signal S1 output by the first output module 14 is consistent with the second gate driving signal S2 output by the second output module 15 , and both are high level signals.

[0133] refer to Figure 4 and Fig.26In the second stage P2, the input signal SIN and the first clock signal SCK1 jump from low level to high level, the second clock signal SCK2 jumps from high level to low level, and the frequency control signal VFE is a high level signal. The first node N1 maintains the low level of the first stage P1, the sixth transistor T6 is turned on, and the potential of the sixth node N6 is pulled down to an ultra-low potential through the bootstrap effect of the first capacitor C1, thereby improving the output capacity of the sixth transistor T6, so that the first gate drive signal output end out1 of the shift register outputs the low level of the second clock signal SCK2 as the first gate drive signal S1. Since the second clock signal SCK2 is bootstrapped through the first capacitor C1, the sixth node N6 is at an ultra-low potential, the eleventh transistor T11 is a protection transistor, the first node N1 is at a low potential, the seventh transistor T7 is kept turned on, and the second gate drive signal output end out2 of the shift register continues to output the high level signal of the frequency control signal VFE as the second gate drive signal S2; since the first node N1 is at a low potential, the second transistor T2 remains turned on, the second potential signal VGH is continuously written into the second node N2, and the fifth transistor T5 is kept turned off; the first clock signal SCK1 is set high, the third transistor T3 is turned off, the second capacitor C2 maintains the potential of the third node N3 at a high level, and the eighth transistor T8 is kept turned off. That is, in the second stage P2, the first gate drive signal S1 output by the first output module 14 is a low level signal, and the second gate drive signal S2 output by the second output module 15 is a high level signal.

[0134] refer to Figure 4 and Fig. 27In the third stage P3, the first clock signal SCK1 is set low, the seventeenth transistor T17 is turned on, the high level of the input signal SIN is written into the first node N1 and the sixth node N6, the sixth transistor T6 is turned off, and the seventh transistor T7 is turned off; since the first node N1 is at a high level, the second transistor T2 is turned off, the first transistor T1 is turned on, the first potential signal VGL is written into the second node, the fifth transistor T5 is turned on, and the first gate drive signal output terminal out1 of the shift register continues to output the second potential signal VGH (i.e., a high level signal) as the first gate drive signal S1; the first clock signal SCK1 is set low, the third transistor T3 is turned on, the potential of the second node N2 is written into the third node N3 through the third transistor T3, and the eighth transistor T8 is gradually turned on. The second gate drive signal output terminal out2 of the shift register starts to output a low potential. At the same time, the second gate drive signal output terminal out2 of the shift register pulls down the potential of the third node N3 through the bootstrap effect of the gate-source parasitic capacitance of the eighth transistor T8 (an additional capacitor can also be added to improve its bootstrap capability). The output capacity of the eighth transistor T8 is increased, so that the second gate drive signal output terminal out2 of the shift register can output the first potential signal VGL; the first clock signal SCK1 is set low, the twelfth transistor T12 is turned on, and the first potential signal VGL of the second node N2 is written into the fourth node N4, preparing for the second clock signal SCK2 in the next stage to pull down the fourth node N2 through the ninth transistor T9 using the second capacitor C2 coupling. Since the first node N1 is at a high potential, the tenth transistor T10 is turned off, the fourth node N4 and the fifth node N5 maintain the high potential of the second stage P2, and the gate source of the eleventh transistor T11 is short-circuited, which is equivalent to a diode. When the potential of the third node N6 is continuously reduced by the second gate drive signal output terminal out2 of the shift register, since the diode formed by the eleventh transistor T11 is in a reverse cut-off state, it can be ensured that the third node N3 is not affected by the fourth node N4. That is, in the third stage P3, the first gate drive signal S1 output by the first output module 14 is a high-level signal, and the second gate drive signal S2 output by the second output module 15 is a low-level signal.

[0135] refer to Figure 4 and Fig.28In the fourth stage P4, the first clock signal SCK1 is set high, the seventeenth transistor T17 is turned off, the first node N1 and the sixth node N6 maintain the high potential of the third stage P3, and the seventh transistor T7, the tenth transistor T10 and the sixth transistor T6 remain turned off; since the potential of the first node N1 is high, the first transistor T1 continues to be turned on, the first potential signal VGL continues to be written into the second node N2, and the second node N2 maintains a low potential; since the second node N2 maintains a low potential, the fourteenth transistor T14 is turned on, the second clock signal SCK2 is set low to turn on the fifteenth transistor T15, and the second potential signal VGL is continuously written into the second node N2, and the second node N2 maintains a low potential; since the second node N2 maintains a low potential, the fourteenth transistor T14 is turned on, and the second clock signal SCK2 is set low to turn on the fifteenth transistor T15, and the second potential signal VGL is continuously written into the second node N2, and the second node N2 maintains a low potential. The signal VGH is continuously written into the first node N1, keeping the first node N1 at a high potential; the first clock signal SCK1 is set high, the third transistor T3 and the twelfth transistor T12 are turned off, the fourth node N4 maintains the low potential of the previous stage, and the second clock signal SCK2 switches from a high level to a low level. In this process, the bootstrap effect coupled by the second capacitor C2 is used to pull down the potential of the fourth node N4 to an ultra-low potential. At this time, the diode formed by the eleventh transistor T11 is forward biased, and the fourth node N4 will pull down the third node N3, compensate the charge to the third node N3, and keep the third node N3 at an ultra-low potential. That is, in the fourth stage P4, the first gate drive signal S1 output by the first output module 14 is a high-level signal, and the second gate drive signal S2 output by the second output module 15 is a low-level signal. The third stage P3 and the fourth stage P4 are repeated continuously.

[0136] Fig.29 It is a simulation waveform diagram of each key node of a shift register provided by an embodiment of the present invention working in a high-frequency working mode. Fig.30 1 is a simulation waveform diagram of each key node of a shift register provided by an embodiment of the present invention when working in a low-frequency working mode. Fig.29 and Fig.30 It can be seen that the output waveforms of the first gate driving signal S1 outputted from the first gate driving signal output terminal out1 of the shift register and the second gate driving signal S2 outputted from the second gate driving signal output terminal out2 of the shift register are in line with expectations.

[0137] Fig.31 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Fig.31 As shown, optionally, the pixel circuit includes a driving module 110, a threshold compensation module 120 and a data writing module 130; the data writing module 130 is connected between the data line Data and the first end of the driver 110.

[0138] The control end of the data writing module 130 in the pixel circuit of the nth row is electrically connected to the first gate driving signal output end out1 of the nth shift register in the gate driving circuit 210;

[0139] The threshold compensation module 120 is connected between the control end and the second end of the driving module 110, and the control end of the threshold compensation module 120 in the nth row pixel circuit is electrically connected to the second gate driving signal output end out2 of the nth shift register in the gate driving circuit 210; n is an integer greater than or equal to 1.

[0140] Specifically, in the data writing and threshold compensation stage, the data writing module 130 is turned on in response to the first gate driving signal S1 output from the first gate driving signal output terminal out1 of the shift register 10. The threshold compensation module 120 is turned on in response to the second gate driving signal S2 output from the second gate driving signal output terminal out2 of the shift register 10. The data writing module 130 transmits the data signal on the data line Data to the first terminal of the driving module 110, and writes the data signal to the control terminal of the driving module 110 through the threshold compensation module 120.

[0141] Optionally, the pixel circuit further includes a first initialization module 140, which is connected between the first end of the driving module 110 and the first initialization line Vref1, and the first initialization modules 140 in the pixel circuits of the n+1th row and the n+2th row are electrically connected to the second gate driving signal output end out2 of the nth shift register in the gate driving circuit 210. The first initialization module 140 is used to write a first initialization voltage to the control end of the driving module 110 according to the third gate driving signal S3.

[0142] Optionally, the pixel circuit further includes a second initialization module 150, which is connected between the first end of the light emitting module 160 and the second initialization line Vref2. The second initialization module 150 is used to write a second initialization voltage to the light emitting module 160 according to the fourth gate driving signal S4.

[0143] Optionally, the pixel circuit further includes a third initialization module 170 connected between the first terminal of the driving module 110 and the third initialization line Vref3. The third initialization module 170 is used to write a third initialization voltage to the first terminal of the driving module 110 according to the fourth gate driving signal S4.

[0144] Optionally, the pixel circuit also includes a first light-emitting control module 180 and a second light-emitting control module 190, the first light-emitting control module 180 is connected between the first end of the driving module 110 and the first power line VDD, the second light-emitting control module 190 is connected between the second end of the driving module 110 and the first end of the light-emitting module 160, and the second end of the light-emitting module 160 is electrically connected to the second power line VSS.

[0145] Optionally, the pixel circuit further includes a storage module 200 . The storage module 200 is connected between the first power line VDD and the control terminal of the driving module 110 , and is used to store the voltage of the control terminal of the driving module 110 .

[0146] Fig.32 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Fig.32 The light emitting module 160 includes a light emitting element D1 , an anode of the light emitting element D1 serves as a first end of the light emitting module 160 , and a cathode of the light emitting element D1 serves as a second end of the light emitting module 160 .

[0147] The driving module 110 may include a driving transistor DTFT, which may be, for example, an NMOS transistor or a PMOS transistor, and a gate, a first electrode, and a second electrode of the driving transistor DTFT may respectively serve as a control terminal, a first terminal, and a second terminal of the driving module 110. The driving module 110 may generate a driving current according to a voltage between its control terminal and the first terminal, and the light-emitting element D1 emits light in response to the driving current.

[0148] The threshold compensation module 120 includes a threshold compensation transistor M1, which is an NMOS transistor. The gate of the threshold compensation transistor M1 is connected to the second gate drive signal S2, the first electrode of the threshold compensation transistor M1 is connected to the second end of the driving module 110, and the second electrode of the threshold compensation transistor T6 is connected to the control end of the driving module 110.

[0149] The data writing module 130 includes a data writing transistor M2, for example, the data writing transistor M2 is an NMOS transistor or a PMOS transistor, the first electrode of the data writing transistor M2 is connected to the first end of the driving module 110, the second electrode of the data writing transistor M2 is connected to the data line Data, and the gate of the data writing transistor M1 is connected to the first gate driving signal S1.

[0150] Optionally, the first initialization module 140 includes a first initialization transistor M3, which is an NMOS transistor. The first electrode of the first initialization transistor M3 is connected to the control end of the driving module 110, the second electrode of the first initialization transistor M3 is connected to the first initialization signal line Vref1, and the gate of the first initialization transistor M3 is connected to the third gate drive signal S3.

[0151] Optionally, the second initialization module 150 includes a second initialization transistor M4, the gate of the second initialization transistor M4 is connected to the fourth gate drive signal S4, the first electrode of the second initialization transistor M4 is connected to the second initialization signal line Vref2, and the second electrode of the second initialization transistor T5 is connected to the anode of the light emitting element D1. The second initialization transistor M4 can be an NMOS transistor or a PMOS transistor.

[0152] Optionally, the third initialization module 170 includes a third initialization transistor M5, a gate of the third initialization transistor M5 is connected to the fourth gate drive signal S4, a first electrode of the third initialization transistor M5 is connected to the third initialization signal line Vref3, and a second electrode of the third initialization transistor M5 is connected to the first end of the driving module 110. The third initialization transistor M5 can be an NMOS transistor or a PMOS transistor.

[0153] Optionally, the first light emission control module 180 includes a first light emission control transistor M6, which is a PMOS transistor or an NMOS transistor, a first electrode of the first light emission control transistor M6 is connected to the first end of the driving module 110, a second electrode of the first light emission control transistor M6 is connected to the first power line VDD, and a gate of the first light emission control transistor M6 is connected to the light emission control signal EM. The first light emission control transistor M6 can be an NMOS transistor or a PMOS transistor.

[0154] Optionally, the second light-emitting control module 190 includes a second light-emitting control transistor M7, which is a PMOS transistor or an NMOS transistor, a first electrode of the second light-emitting control transistor M7 is connected to the second end of the driving module 110, a second electrode of the second light-emitting control transistor M7 is connected to the anode of the light-emitting element D1, and a gate of the second light-emitting control transistor M7 is connected to the light-emitting control signal EM. The second light-emitting control transistor M7 can be an NMOS transistor or a PMOS transistor.

[0155] The storage module 20 includes a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the first power line VDD so that the first electrode of the storage capacitor Cst is connected to the first power voltage, and a second electrode of the storage capacitor Cst is connected to the control end of the driving module 110 .

[0156] Fig.33 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Fig.33 The drive timing shown is applicable to drive Fig.32 The pixel circuit shown in the figure works. Fig.32 and Fig.33 , the working principle of the pixel circuit provided by the embodiment of the present invention is described. Exemplarily, the working process of the pixel circuit in a display frame at least includes a first initialization stage t1, a data writing and threshold compensation stage t2, a second initialization stage t3 and a light emitting stage t4. After the end of the i-1th display frame, the i-th display frame is entered. i is an integer greater than or equal to 2.

[0157] In the first initialization phase t1 of the i-th display frame, the first initialization module 140 is turned on, the threshold compensation module 120, the data writing module 130, the second initialization module 150, the third initialization module 170, the first light emission control module 180 and the second light emission control module 190 are turned off. That is, the first initialization transistor M3 is turned on, and the threshold compensation transistor M1, the second initialization transistor M4, the third initialization transistor M5, the first light emission control transistor M6 and the second light emission control transistor M7 are turned off. The first initialization voltage transmitted by the first initialization signal line Vref1 is written into the gate of the driving transistor DTFT through the first initialization transistor M3, the gate voltage of the driving transistor DTFT is reset to the first initialization voltage, and the driving transistor DTFT is controlled to be turned on.

[0158] In the data writing and threshold compensation phase t2 of the i-th display frame, the data writing module 130 and the threshold compensation module 120 are turned on, and the first initialization module 140, the second initialization module 150, the third initialization module 170, the first light emission control module 180 and the second light emission control module 190 are turned off. That is, the threshold compensation transistor M1 and the data writing transistor M2 are turned on, and the first initialization transistor M3, the second initialization transistor M4, the third initialization transistor M5, the first light emission control transistor M6 and the second light emission control transistor M7 are turned off. The data voltage transmitted by the data line Data is sequentially written into the gate of the driving transistor DTFT through the data writing transistor M2, the driving transistor DTFT and the threshold compensation transistor M1, so that the gate voltage of the driving transistor DTFT is related to both the data voltage and the threshold voltage of the driving transistor DTFT, and the gate voltage of the driving transistor DTFT is stored through the storage capacitor Cst.

[0159] In the light-emitting phase t3 of the i-th display frame, the second initialization module 150 and the third initialization module 170 are turned on, and the threshold compensation module 120, the data writing module 130, the first initialization module 140, the first light-emitting control module 180 and the second light-emitting control module 190 are turned off. That is, the second initialization transistor M4 and the third initialization transistor M5 are turned on, and the threshold compensation transistor M1, the data writing transistor M2, the first initialization transistor M3, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are turned off. The second initialization voltage transmitted by the second initialization signal line Vref2 is written into the anode of the light-emitting element D1 through the second initialization transistor M4. The second initialization voltage transmitted by the third initialization signal line Vref3 is written into the first electrode of the driving transistor DTFT through the third initialization transistor M5.

[0160] In the light-emitting stage t4 of the i-th display frame, the driving module 110, the first light-emitting control module 180 and the second light-emitting control module 190 are turned on, and the threshold compensation module 120, the data writing module 130, the first initialization module 140, the second initialization module 150 and the third initialization module 170 are turned off. That is to say, the first light-emitting control transistor M6, the second light-emitting control transistor M7 and the driving transistor DTFT are turned on, and the threshold compensation transistor M1, the data writing transistor M2, the first initialization transistor M3, the second initialization transistor M4 and the third initialization transistor M5 are turned off. The driving transistor DTFT generates a driving current according to its own gate voltage, thereby driving the light-emitting element D1 to emit light with a corresponding brightness. In the light-emitting stage t4, since the gate voltage of the driving transistor DTFT is related to the data voltage and the threshold voltage of the driving transistor DTFT, it is helpful to compensate for the influence of the threshold voltage of the driving transistor DTFT on the driving current, thereby improving the display uniformity of the light-emitting stage.

[0161] Fig.34 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.34 Optionally, the display panel also includes a scanning circuit 220 and a plurality of gate drive signal lines LS, and the scanning circuit is electrically connected to the control end of the second initialization module 150 and the control end of the third initialization module 170 through the gate drive signal line LS, and is used to provide a fourth gate drive signal S4 to the control end of the second initialization module 150 and the control end of the third initialization module 170.

[0162] Optionally, the display panel further includes a light emitting control driving circuit 230 ; the light emitting control driving circuit 230 is electrically connected to a control end of the first light emitting control module 180 and a control end of the second light emitting control module 190 through a gate driving signal line LS.

[0163] Optionally, the scanning circuit 220 and the light emitting control driving circuit 230 each include a plurality of cascaded shift registers. Fig.32 The schematic diagram shows the situation in which the gate driving circuit 210 is driven at both ends, the first-level shift register drives a row of pixel circuits PX, the scanning circuit 220 is driven at single end, the first-level shift register drives two rows of pixel circuits PX, and the light emitting control driving circuit 230 is driven at single end, and the first-level shift register drives two rows of pixel circuits PX.

[0164] Based on the same inventive concept, the present invention also provides a display device, including a display panel provided by any embodiment of the present invention. It can be understood that the display device provided by the embodiment of the present invention can be a display device with a display function such as a mobile phone, a wearable product, a computer, a television, a car display device, etc., and the present invention does not impose specific restrictions on this. The display device provided by the embodiment of the present invention has the beneficial effects of the display panel provided by the embodiment of the present invention. For details, please refer to the specific description of the display in the above embodiments, and the embodiments of the present invention will not be repeated here.

[0165] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A gate drive circuit, the gate drive circuit comprising a multi-stage shift register; The shift register comprises: an input module, a first potential control module, a second potential control module, a first output module and a second output module; The output end of the input module is connected to the first node, and is used to transmit the input signal to the first node in response to the first clock signal; The first potential control module is connected between the first node and the second node, and is used to transmit the first potential signal or the second potential signal to the second node in response to the potential of the first node; The second potential control module is connected between the second node and the third node, and is used to transmit the potential of the second node to the third node according to the first potential signal and the first clock signal; The first output module is connected to the first node and the second node respectively, and is used to respond to the potential of the first node and output the second clock signal as the first gate driving signal, or respond to the potential of the second node and output the second potential signal as the first gate driving signal; The second output module is connected between the first node and the third node, and is used to respond to the potential of the first node and output the frequency control signal as the second gate drive signal, or respond to the potential of the third node and output the first potential signal as the second gate drive signal; wherein the frequency control signal controls the frequency of the conduction level appearing in the second gate drive signal by controlling the potential of the output end of the second output module.

2. The display panel according to claim 1, characterized in that: The display panel further includes at least one frequency control signal line for providing the frequency control signal to the shift register.

3. The display panel according to claim 2, characterized in that: The display panel includes k frequency control signal lines, the gate drive circuit includes a plurality of cascaded shift register groups, the shift register group includes k cascaded shift register units, k is an integer greater than or equal to 2, the shift register unit includes m shift registers, m is an integer greater than or equal to 1, different shift register units in the same shift register group are electrically connected to different frequency control signal lines, and different shift register groups are connected to the same k frequency control signal lines; The display partition includes multiple pixel circuit groups; the pixel circuit group includes k sub-pixel circuit groups, and the sub-pixel circuit group includes multiple rows of pixel circuits; the sub-pixel circuit groups are electrically connected to the shift register units in a one-to-one correspondence; the output end of the first-level shift register is electrically connected to the r-row pixel circuits, where r is an integer greater than or equal to 1.

4. The display panel according to claim 3, characterized in that: The display area of ​​the display panel includes at least two display partitions, and the at least two display partitions include a first display partition and a second display partition; the refresh frequency of the first display partition is a first refresh frequency, and the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency; In the first display frame, the moments when the pulses of the frequency control signals of the k frequency control signal lines jump to the on level are delayed sequentially; in the second display frame, the frequency control signals on the k frequency control signal lines are at the on level; The first display frame is a holding frame for at least part of the row pixel circuits in the first display partition, and is a refresh frame for the second display partition; the second display frame is a refresh frame for the first display partition and the second display partition; In the second display frame, the first display partition is refreshed before the second display partition; Preferably, k-1 shift register units are connected between two adjacent shift register units connected to the same frequency control signal line; Preferably, m is greater than or equal to 8, and k is greater than or equal to 4; Preferably, the number of rows of the pixel circuits in each of the pixel circuit groups is the same.

5. The display panel according to claim 1, characterized in that: The first potential control module includes a first inverter, and the first inverter includes a first transistor and a second transistor; The gate of the first transistor is connected to the first node, the first electrode of the first transistor is connected to the first potential signal, and the second electrode of the first transistor is connected to the second node; The gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the second potential signal, and the second electrode of the second transistor is connected to the second node; Preferably, the first transistor and the second transistor have different channel types; Preferably, the first transistor is an N-channel transistor, and the second transistor is a P-channel transistor. Preferably, the second potential control module includes a third transistor and a fourth transistor; The gate of the third transistor is connected to the first clock signal, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the first electrode of the fourth transistor; The gate of the fourth transistor is connected to the first potential signal, and the second electrode of the fourth transistor is connected to the third node; Preferably, the third transistor and the fourth transistor are both P-channel transistors. Preferably, the first output module comprises: a first output unit and a second output unit; The first output unit is connected to the second node, and is used to output the second potential signal as the first gate driving signal according to the potential of the second node; The second output unit is connected to the first node, and is used to output the second clock signal as the first gate driving signal according to the potential of the first node; Preferably, the first output unit comprises: a fifth transistor, a gate of the fifth transistor is connected to the second node, a first electrode of the fifth transistor is connected to the second potential signal, and a second electrode of the fifth transistor serves as an output end of the first output unit; The second output unit includes: a sixth transistor and a first capacitor, the gate of the sixth transistor is respectively connected to the first node and the first end of the first capacitor, the first electrode of the sixth transistor is connected to the second end of the first capacitor and serves as the output end of the second output unit, and the second electrode of the sixth transistor is connected to the second clock signal. Preferably, the second output module comprises a second inverter, and the second inverter comprises a third output unit and a fourth output unit; The third output unit is connected to the first node, and is used to output the frequency control signal as the second gate driving signal according to the potential of the first node; The fourth output unit is connected to the third node, and is used to output the first potential signal as the second gate driving signal according to the potential of the third node; Preferably, the third output unit comprises: a seventh transistor, a gate of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to the frequency control signal, and a second electrode of the seventh transistor serves as an output end of the third output unit; The fourth output unit includes: an eighth transistor, a gate of the eighth transistor is connected to the third node, the eighth transistor serves as an output end of the fourth output unit, and a second electrode of the eighth transistor is connected to the first potential signal.

6. The display panel according to claim 1, characterized in that: Also includes drop-down modules; The pull-down module is connected between the first node and the third node, and is used to control the potential of the third node at least according to the potential of the first node, the second potential signal and the second clock signal; Preferably, the waveform of the second clock signal is the same as the waveform of the first clock signal; Preferably, the period of the second clock signal is the same as the period of the first clock signal; Preferably, the waveform of the second clock signal is delayed relative to the waveform of the first clock signal; Preferably, the waveform of the second clock signal is half the period later than the waveform of the first clock signal; Preferably, the duration of the low level in the first clock signal is less than or equal to half of the cycle, and the duration of the high level in the first clock signal is greater than half of the cycle; Preferably, the duration of the low level in the second clock signal is less than or equal to half of the cycle, and the duration of the high level in the second clock signal is greater than half of the cycle; Preferably, the low level is the same as the first potential signal, and the high level is the same as the second potential signal.

7. The display panel according to claim 6, characterized in that: The pull-down module includes a first control unit and a second control unit; The first control unit is connected between the first node and the fourth node, and is used to control the potential of the fourth node according to the potential of the first node, the second potential signal and the second clock signal; The second control unit is connected between the third node and the fourth node, and is used to control the potential of the third node according to the potential of the fourth node; Preferably, the pull-down module further includes a third control unit, which is connected between the second node and the fourth node and is used to transmit the potential of the second node to the fourth node according to the first clock signal and the first potential signal; Preferably, the first control unit comprises: a ninth transistor, a tenth transistor and a second capacitor; The gate of the ninth transistor is connected to the first node, the first electrode of the ninth transistor is connected to the second clock signal, and the second electrode of the ninth transistor and the first electrode of the tenth transistor are connected to the fifth node; The gate of the tenth transistor is connected to the fourth node, and the second electrode of the tenth transistor is connected to the second potential signal; The first end of the second capacitor is connected to the fourth node, and the second end of the second capacitor is connected to the fifth node; The second control unit includes: an eleventh transistor; a gate of the eleventh transistor is connected to a first electrode of the eleventh transistor and a gate of the ninth transistor and serves as a first end of the second control unit, and a second electrode of the eleventh transistor is connected to the third node; Preferably, the third control unit comprises: a twelfth transistor and a thirteenth transistor; the gate of the twelfth transistor is connected to the first clock signal, the first electrode of the twelfth transistor is connected to the first node, and the second electrode of the twelfth transistor is connected to the first electrode of the thirteenth transistor; The gate of the thirteenth transistor is connected to the first potential signal, and the second electrode of the thirteenth transistor is connected to the fourth node.

8. The display panel according to claim 1, characterized in that: The device further comprises a third potential control module, the third potential control module is connected between the first node and the second node, and is used to control the potential of the first node according to the potential of the second node; Preferably, the third potential control module comprises: a fourteenth transistor; the gate of the fourteenth transistor is connected to the second node, the first electrode of the fourteenth transistor is connected to the second potential signal, and the second electrode of the fourteenth transistor is connected to the first node; Preferably, the third potential control module further includes: a fifteenth transistor; the gate of the fifteenth transistor is connected to the second clock signal, the first electrode of the fifteenth transistor is connected to the second electrode of the twelfth transistor, and the second electrode of the fifteenth transistor is connected to the first node; Preferably, the shift register further comprises a potential isolation module, a control end of the potential isolation module is connected to the first potential signal, a first end of the potential isolation module is connected to the first node, a second end of the potential isolation module is connected to the first control end of the first output module, and the potential isolation module is used to turn on or off according to the potential difference between the first potential signal and the first node; Preferably, the potential isolation module comprises: a sixteenth transistor; the gate of the sixteenth transistor serves as the control end of the potential isolation module, the first electrode of the sixteenth transistor serves as the first end of the potential isolation module, and the second electrode of the sixteenth transistor serves as the second end of the potential isolation module; Preferably, the input module comprises: a seventeenth transistor; a gate of the seventeenth transistor is connected to the first clock signal, a first electrode of the seventeenth transistor is connected to the input signal, and a second electrode of the seventeenth transistor is connected to the first node.

9. The display panel according to claim 1, characterized in that: Also included are pixel circuits arranged in an array; The pixel circuit includes a driving module, a threshold compensation module and a data writing module; the data writing module is connected between the data line and the first end of the driving module; A control end of the data writing module in the pixel circuit of the nth row is electrically connected to a first gate driving signal output end of the nth shift register in the gate driving circuit; The threshold compensation module is connected between the control terminal and the second terminal of the driving module, and the control terminal of the threshold compensation module in the pixel circuit of the nth row is electrically connected to the second gate driving signal output terminal of the nth shift register in the gate driving circuit; n is an integer greater than or equal to 1; Preferably, the pixel circuit further comprises a first initialization module, the first initialization module is connected between the first end of the driving module and the first initialization line, and the first initialization modules in the pixel circuits in the n+1th row and the n+2th row are electrically connected to the second gate driving signal output end of the nth shift register in the gate driving circuit; Preferably, the pixel circuit further comprises a second initialization module, wherein the second initialization module is connected between the first end of the light emitting module and the second initialization line; Preferably, the pixel circuit further comprises a third initialization module, wherein the third initialization module is connected between the first end of the driving module and the third initialization line; Preferably, the display panel further comprises a scanning circuit and a plurality of gate drive signal lines, and the scanning circuit is electrically connected to the control end of the second initialization module and the control end of the third initialization module through the gate drive signal lines; Preferably, the pixel circuit also includes a first light-emitting control module and a second light-emitting control module, the first light-emitting control module is connected between the first end of the driving module and the first power line, the second light-emitting control module is connected between the second end of the driving module and the first end of the light-emitting module, and the second end of the light-emitting module is electrically connected to the second power line. Preferably, the display panel further comprises a light emitting control driving circuit; the light emitting control driving circuit is electrically connected to a control end of the first light emitting control module and a control end of the second light emitting control module through the gate driving signal line.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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