Multi-IGBT parallel drive signal synchronization circuit

Abstract

The invention relates to the technical field of semiconductors, in particular to a multi-IGBT (Insulated Gate Bipolar Transistor) parallel driving signal synchronization circuit, which comprises a push-pull power amplification circuit, which is used for carrying out push-pull amplification on an input first driving signal to obtain a plurality of second driving signals and driving a plurality of IGBTs connected in parallel according to the plurality of second driving signals, the second driving signals are in one-to-one correspondence with the IGBTs. By the adoption of the scheme, the consistency and synchronism of the multi-IGBT parallel drive signals can be achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a multi-IGBT parallel drive signal synchronization circuit. Background Art

[0002] Insulate-Gate Bipolar Transistor (IGBT) combines the advantages of Giant Transistor (GTR) and Power MOSFET, has good characteristics, and is widely used. However, in the prior art, when driving multiple IGBTs connected in parallel, the consistency and synchronization of the parallel driving signals of multiple IGBTs are not considered, which easily causes inconsistent conduction of IGBT devices. Summary of the invention

[0003] The present disclosure provides a multi-IGBT parallel drive signal synchronization circuit, the main purpose of which is to achieve consistency and synchronization of multi-IGBT parallel drive signals.

[0004] According to one aspect of the present disclosure, a multi-IGBT parallel drive signal synchronization circuit is provided, comprising:

[0005] The push-pull power amplifier circuit is used to push-pull amplify the input first drive signal to obtain multiple second drive signals, and drive multiple IGBTs connected in parallel according to the multiple second drive signals, wherein the second drive signals correspond to the IGBTs one by one.

[0006] Optionally, in one embodiment of the present disclosure, the push-pull power amplifier circuit includes an NPN transistor, a PNP transistor, and a logic gate module; wherein,

[0007] The bases of the NPN transistor and the PNP transistor are used to receive the first driving signal, the collector of the NPN transistor is used to receive the first power supply voltage, the collector of the PNP transistor is used to receive the second power supply voltage, the connection point between the emitter of the NPN transistor and the emitter of the PNP transistor is connected to the input end of the logic gate module, and the output end of the logic gate module is respectively connected to the gates of the multiple IGBTs;

[0008] The amplification factor of the push-pull power amplifier circuit when performing push-pull amplification on the first driving signal is determined by the first power supply voltage and the second power supply voltage.

[0009] Optionally, in one embodiment of the present disclosure, the first power supply voltage is +15V, and the second power supply voltage is -15V.

[0010] Optionally, in one embodiment of the present disclosure, it further includes:

[0011] The signal preprocessing circuit is used to receive a third driving signal and preprocess the third driving signal to obtain the first driving signal.

[0012] Optionally, in one embodiment of the present disclosure, the signal preprocessing circuit includes a current limiting module and a filtering module; wherein,

[0013] The first end of the current limiting module is used to receive the third driving signal, the second end of the current limiting module is connected to the first end of the filtering module, and the second end of the filtering module is connected to the input end of the push-pull power amplifier circuit.

[0014] Optionally, in an embodiment of the present disclosure, the current limiting module includes a first resistor, and the filtering module includes a second resistor and a first capacitor; wherein,

[0015] The first end of the first resistor is used to receive the third driving signal, the second end of the first resistor is connected to the first end of the second resistor, the connection point between the second end of the second resistor and the first end of the first capacitor is connected to the input end of the push-pull power amplifier circuit, and the second end of the first capacitor is grounded.

[0016] Optionally, in one embodiment of the present disclosure, it further includes:

[0017] The signal clamping circuit is used for clamping and protecting the plurality of second driving signals.

[0018] Optionally, in an embodiment of the present disclosure, the signal clamping circuit includes a plurality of signal clamping modules, the signal clamping modules correspond one to one with the second driving signal, and the signal clamping modules include a first diode and a second diode; wherein,

[0019] The cathode of the first diode is used to receive a third power supply voltage, the anode of the second diode is used to receive a fourth power supply voltage, and a connection point between the anode of the first diode and the cathode of the second diode is connected to the output end of the push-pull power amplifier circuit and the gate of the IGBT respectively;

[0020] The third power supply voltage and the fourth power supply voltage are determined by the second driving signal.

[0021] Optionally, in one embodiment of the present disclosure, it further includes:

[0022] The overvoltage protection circuit is used to perform overvoltage protection on the multiple second driving signals.

[0023] Optionally, in an embodiment of the present disclosure, the overvoltage protection circuit includes a plurality of overvoltage protection modules, the overvoltage protection modules correspond to the second driving signal one by one, and the overvoltage protection modules include a third diode and a third resistor; wherein,

[0024] A connection point between the first end of the third diode and the first end of the third resistor is connected to the output end of the push-pull power amplifier circuit;

[0025] A connection point between the second end of the third diode and the second end of the third resistor is connected to the gate of the IGBT.

[0026] In summary, the multi-IGBT parallel drive signal synchronization circuit provided in the embodiment of the present invention, by adopting a push-pull power amplifier circuit to drive multiple IGBTs connected in parallel according to multiple second drive signals, can ensure that the multiple IGBTs connected in parallel are turned on and turned off synchronously, thereby achieving consistency and synchronization of the multi-IGBT parallel drive signals and avoiding instantaneous overcurrent problems caused by inconsistent conduction and pipe sections.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0029] Figure 1 A schematic diagram of a multi-IGBT parallel drive signal synchronization circuit provided by an embodiment of the present disclosure;

[0030] Figure 2 A schematic structural diagram of a multi-IGBT parallel drive signal synchronization circuit provided by another embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Some embodiments of the present disclosure will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. Various changes, modifications and equivalents of the structures described herein will become apparent after understanding the present disclosure. For example, the connection relationships of the structures described herein are merely examples and are not limited to those connection relationships set forth herein, but can be changed as becomes apparent after understanding the present disclosure, except for connections that must be made with specific connection relationships. In addition, for clarity and brevity, descriptions of features known in the art may be omitted.

[0032] The embodiments described in some embodiments of the present disclosure below do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of structures consistent with some aspects of the present disclosure as detailed in the appended claims.

[0033] The present disclosure is described in detail below with reference to specific embodiments.

[0034] Figure 1 This is a schematic diagram of a multi-IGBT parallel drive signal synchronization circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the multi-IGBT parallel drive signal synchronization circuit includes:

[0035] The push-pull power amplifier circuit is used to push-pull amplify the input first drive signal to obtain multiple second drive signals, and drive multiple IGBTs connected in parallel according to the multiple second drive signals, wherein the second drive signals correspond to the IGBTs one by one.

[0036] According to some embodiments, the first driving signal refers to a signal that needs to be processed synchronously with the driving signal. The first driving signal may be, for example, a pulse signal.

[0037] It is easy to understand that by using a push-pull power amplifier circuit to drive multiple IGBTs connected in parallel according to multiple second drive signals, it is possible to ensure that the multiple IGBTs connected in parallel are turned on and off synchronously, achieve consistency and synchronization of multiple IGBT parallel drive signals, and avoid instantaneous overcurrent problems caused by inconsistent conduction and tube sections.

[0038] Optionally, in one embodiment of the present disclosure, Figure 2 This is a schematic diagram of a multi-IGBT parallel drive signal synchronization circuit provided by an embodiment of the present disclosure. Figure 2 As shown, the multi-IGBT parallel drive signal synchronization circuit includes N N-type IGBTs from IGBT1 to IGBTN, where N is a positive integer greater than 1. The collectors of the N N-type IGBTs are all connected to the positive DC power supply DC+, and the emitters of the N IGBTs are all connected to the negative DC power supply DC-, thereby realizing parallel connection of the N N-type IGBTs.

[0039] It should be noted that if the multiple IGBTs connected in parallel are P-type IGBTs, the emitters of the P-type IGBTs are all connected to the positive DC power supply DC+, and the collectors of the P-type IGBTs are all connected to the negative DC power supply DC-.

[0040] Optionally, in one embodiment of the present disclosure, Figure 2 As shown, the push-pull power amplifier circuit includes an NPN transistor V1, a PNP transistor V2, and a logic gate module U1; wherein,

[0041] The bases of the NPN transistor V1 and the PNP transistor V2 are used to receive the first drive signal, the collector V1 of the NPN transistor is used to receive the first power supply voltage, the collector of the PNP transistor V2 is used to receive the second power supply voltage, the connection point between the emitter of the NPN transistor V1 and the emitter of the PNP transistor V2 is connected to the input end of the logic gate module U1, and the output end of the logic gate module U1 is respectively connected to the gates of multiple IGBTs.

[0042] According to some embodiments, the first power supply voltage and the second power supply voltage are opposite to each other. For example, when the first power supply voltage is +15V, the second power supply voltage is -15V.

[0043] In some embodiments, the amplification factor of the push-pull power amplifier circuit when performing push-pull amplification on the first driving signal is determined by the first power supply voltage and the second power supply voltage.

[0044] For example, a 0-5V pulse signal can generate a ±15V pulse signal after passing through the NPN transistor V1 and the PNP transistor V2.

[0045] According to some embodiments, the logic gate module U1 can further shape the signals generated by the NPN transistor V1 and the PNP transistor V2 to generate a second driving signal that meets the accurate driving requirement.

[0046] For example, the logic gate module U1 can further shape the ±15V pulse signal generated by the NPN transistor V1 and the PNP transistor V2 to generate a pulse light signal whose rising and falling edges meet the accurate driving requirements.

[0047] In some embodiments, the logic gates used in the logic gate module U1 include but are not limited to AND gates, OR gates, NOT gates, etc. The logic gates may be formed by high-precision triggers.

[0048] It should be noted that the NPN transistor V1, the PNP transistor V2, and the logic gate module U1 may be made of high-precision devices, thereby further improving the accuracy of generating the second driving signal.

[0049] It is easy to understand that when the number of IGBTs in parallel increases, the output load capacity of the push-pull module composed of the NPN transistor V1 and the PNP transistor V2 will be insufficient, and the slopes of the rising and falling edges of the drive signal will become larger, which is not conducive to the on-and-off control of the IGBT. In severe cases, it will cause incomplete and inconsistent on-and-off of the IGBT device, and even cause the upper and lower IGBT devices to be directly connected and burn the device. In this case, by using a logic gate module to achieve IGBT drive signal synchronization and shaping, the shape of the drive signal can be significantly improved, so as to achieve stable drive control when multiple IGBT devices are connected in parallel.

[0050] Optionally, in one embodiment of the present disclosure, the multi-IGBT parallel drive signal synchronization circuit further includes:

[0051] The signal preprocessing circuit is used to receive the third driving signal and preprocess the third driving signal to obtain the first driving signal.

[0052] According to some embodiments, the signal preprocessing circuit includes a current limiting module and a filtering module; wherein,

[0053] The first end of the current limiting module is used to receive the third driving signal, the second end of the current limiting module is connected to the first end of the filtering module, and the second end of the filtering module is connected to the input end of the push-pull power amplifier circuit.

[0054] The current limiting module is used to limit the current of the third driving signal, and the filtering module is used to filter the third driving signal.

[0055] In some embodiments, the third driving signal may be generated by a pulse width modulation (PWM) controller, for example.

[0056] Taking a scenario as an example, a high-power wind power converter includes multiple stages of parallel-connected IGBT devices. The IGBT device is a power semiconductor device in the converter main circuit and is responsible for power conversion. Since the converter core controller, PWM controller and IGBT device are far apart and there is a high voltage and high current environment, the drive signal needs to be transmitted using optical fiber. The PWM optical signal output by the PWM controller can be converted into an electrical signal through photoelectric conversion and output. The electrical signal after photoelectric conversion is the third drive signal.

[0057] According to some embodiments, Figure 2 As shown, the current limiting module includes a first resistor R1, and the filtering module includes a second resistor R2 and a first capacitor C1; wherein,

[0058] The first end of the first resistor R1 is used to receive the third driving signal, the second end of the first resistor R1 is connected to the first end of the second resistor R2, the connection point between the second end of the second resistor R2 and the first end of the first capacitor C1 is connected to the input end of the push-pull power amplifier circuit, and the second end of the first capacitor C1 is grounded.

[0059] The connection point between the second end of the second resistor R2 and the first end of the first capacitor C1 is connected to the input end of the push-pull power amplifier circuit, and specifically can be connected to the bases of the NPN transistor V1 and the PNP transistor V2.

[0060] The second resistor R2 and the first capacitor C1 form an RC filter, which can filter out interference signals in the third driving signal and avoid the problem of false triggering of the IGBT.

[0061] It should be noted that the second resistor R2 can also cooperate with the first resistor R1 to play a current limiting role, thereby further improving the current limiting effect.

[0062] Optionally, in one embodiment of the present disclosure, the multi-IGBT parallel drive signal synchronization circuit further includes:

[0063] The signal clamping circuit is used to clamp and protect the plurality of second drive signals, thereby improving the reliability of the multi-IGBT parallel drive signal synchronization circuit.

[0064] According to some embodiments, Figure 2 As shown, the signal clamping circuit includes a plurality of signal clamping modules, each of which corresponds to the second driving signal one by one, and the signal clamping module includes a first diode D1 and a second diode D2; wherein,

[0065] The cathode of the first diode is used to receive the third power supply voltage, the anode of the second diode is used to receive the fourth power supply voltage, and the connection point between the anode of the first diode and the cathode of the second diode is respectively connected to the output end of the push-pull power amplifier circuit and the gate of the IGBT.

[0066] In some embodiments, the first diode in the first signal clamping module in the signal clamping circuit is D11, and the second diode is D21; the first diode in the Nth signal clamping module is D1N, and the second diode is D2N. Figure 2 As shown, the connection point between the positive electrode of D11 and the negative electrode of D21 is respectively connected to the output end of the logic gate module U1 and the gate of IGBT1, and the connection point between the positive electrode of D1N and the negative electrode of D2N is respectively connected to the output end of the logic gate module U1 and the gate of IGBTN.

[0067] In some embodiments, the third power supply voltage and the fourth power supply voltage are determined by the second driving signal.

[0068] For example, when the second driving signal is a pulse signal of ±15V, the third power supply voltage is +15V, and the fourth power supply voltage is -15V.

[0069] It is easy to understand that by adopting the signal clamping module composed of the first diode D1 and the second diode D2, the stability of the voltage level of the second drive signal can be guaranteed, the effective triggering and shutdown of the IGBT can be ensured, and the reliability of the multi-IGBT parallel drive signal synchronization circuit can be improved.

[0070] Optionally, in one embodiment of the present disclosure, the multi-IGBT parallel drive signal synchronization circuit further includes:

[0071] The overvoltage protection circuit is used to perform overvoltage protection on the plurality of second drive signals, thereby improving the reliability of the multi-IGBT parallel drive signal synchronization circuit.

[0072] According to some embodiments, Figure 2 As shown, the overvoltage protection circuit includes a plurality of overvoltage protection modules, each of which corresponds to the second driving signal one by one, and the overvoltage protection module includes a third diode D3 and a third resistor R3; wherein,

[0073] A connection point between the first end of the third diode D3 and the first end of the third resistor R3 is connected to the output end of the push-pull power amplifier circuit;

[0074] A connection point between the second end of the third diode D3 and the second end of the third resistor R3 is connected to the gate of the IGBT.

[0075] In some embodiments, the third diode in the first overvoltage protection module in the overvoltage protection circuit is D31, and the third resistor is R31; the third diode in the Nth overvoltage protection module is D3N, and the third resistor is R3N. Figure 2 As shown, the connection point between the first end of D31 and the first end of R31 is respectively connected to the output end of the logic gate module U1, the positive electrode of D11, and the negative electrode of D21, and the connection point between the second end of D31 and the second end of R31 is connected to the gate of IGBT1; the connection point between the first end of D3N and the first end of R3N is respectively connected to the output end of the logic gate module U1, the positive electrode of D1N, and the negative electrode of D2N, and the connection point between the second end of D3N and the second end of R3N is connected to the gate of IGBTN.

[0076] It is easy to understand that the third diode D3 is anti-parallel to the two ends of the third resistor R3, which can be used to protect the components in the multi-IGBT parallel drive signal synchronization circuit, avoid overvoltage, absorb overvoltage energy in the circuit, and improve the reliability of the multi-IGBT parallel drive signal synchronization circuit.

[0077] In addition, the word "exemplary" is used herein to indicate serving as an example, instance, or diagram. Any aspect or design described as "exemplary" in this article is not necessarily understood to be advantageous compared to other aspects or designs. On the contrary, the use of the word exemplary is intended to present concepts in a specific way. As used herein, the term "or" is intended to represent an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X applies A or B" is intended to represent any one of the natural inclusive arrangements. That is, if X applies A; X applies B; or X applies both A and B, "X applies A or B" is satisfied under any of the aforementioned examples. In addition, unless otherwise specified or clearly pointed to a singular form from the context, the articles "one" and "an" as used in this application and the appended claims are generally understood to mean "one or more".

[0078] Likewise, although the present disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art after reading and understanding the specification and drawings. The present disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components (e.g., elements, resources, etc.) described above, unless otherwise noted, the terms used to describe such components are intended to correspond to any component (functionally equivalent) that performs the specific functions of the described components, even if the structure is not equivalent to the disclosed structure. In addition, although the specific features of the present disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations as may be desired and conducive to any given or specific application. In addition, with respect to "including", "having", "having", "having", or variations thereof used in the specific embodiments or claims, such terms are intended to be inclusive in a manner similar to the term "comprising".

[0079] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0080] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A multi-IGBT parallel drive signal synchronization circuit, characterized in that: include: The push-pull power amplifier circuit is used to push-pull amplify the input first drive signal to obtain multiple second drive signals, and drive multiple IGBTs connected in parallel according to the multiple second drive signals, wherein the second drive signals correspond to the IGBTs one by one.

2. The multi-IGBT parallel drive signal synchronization circuit according to claim 1, characterized in that: The push-pull power amplifier circuit includes an NPN transistor, a PNP transistor, and a logic gate module; wherein, The bases of the NPN transistor and the PNP transistor are used to receive the first driving signal, the collector of the NPN transistor is used to receive the first power supply voltage, the collector of the PNP transistor is used to receive the second power supply voltage, the connection point between the emitter of the NPN transistor and the emitter of the PNP transistor is connected to the input end of the logic gate module, and the output end of the logic gate module is respectively connected to the gates of the multiple IGBTs; The amplification factor of the push-pull power amplifier circuit when performing push-pull amplification on the first driving signal is determined by the first power supply voltage and the second power supply voltage.

3. The multi-IGBT parallel drive signal synchronization circuit according to claim 2, characterized in that: The first power supply voltage is +15V, and the second power supply voltage is -15V.

4. The multi-IGBT parallel drive signal synchronization circuit according to claim 1, characterized in that: Also includes: The signal preprocessing circuit is used to receive a third driving signal and preprocess the third driving signal to obtain the first driving signal.

5. The multi-IGBT parallel drive signal synchronization circuit according to claim 4, characterized in that: The signal preprocessing circuit includes a current limiting module and a filtering module; wherein, The first end of the current limiting module is used to receive the third driving signal, the second end of the current limiting module is connected to the first end of the filtering module, and the second end of the filtering module is connected to the input end of the push-pull power amplifier circuit.

6. The multi-IGBT parallel drive signal synchronization circuit according to claim 5, characterized in that: The current limiting module includes a first resistor, and the filtering module includes a second resistor and a first capacitor; wherein, The first end of the first resistor is used to receive the third driving signal, the second end of the first resistor is connected to the first end of the second resistor, the connection point between the second end of the second resistor and the first end of the first capacitor is connected to the input end of the push-pull power amplifier circuit, and the second end of the first capacitor is grounded.

7. The multi-IGBT parallel drive signal synchronization circuit according to claim 1, characterized in that: Also includes: The signal clamping circuit is used for clamping and protecting the plurality of second driving signals.

8. The multi-IGBT parallel drive signal synchronization circuit according to claim 7, characterized in that: The signal clamping circuit includes a plurality of signal clamping modules, each of which corresponds to the second driving signal one by one, and each of which includes a first diode and a second diode; wherein, The cathode of the first diode is used to receive a third power supply voltage, the anode of the second diode is used to receive a fourth power supply voltage, and a connection point between the anode of the first diode and the cathode of the second diode is connected to the output end of the push-pull power amplifier circuit and the gate of the IGBT respectively; The third power supply voltage and the fourth power supply voltage are determined by the second driving signal.

9. The multi-IGBT parallel drive signal synchronization circuit according to claim 1, characterized in that: Also includes: The overvoltage protection circuit is used to perform overvoltage protection on the multiple second driving signals.

10. The multi-IGBT parallel drive signal synchronization circuit according to claim 9, characterized in that: The overvoltage protection circuit includes a plurality of overvoltage protection modules, each of which corresponds to the second driving signal one by one, and each of which includes a third diode and a third resistor; wherein, A connection point between the first end of the third diode and the first end of the third resistor is connected to the output end of the push-pull power amplifier circuit; A connection point between the second end of the third diode and the second end of the third resistor is connected to the gate of the IGBT.

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