Digital Audio Data Optimization Method Based on FPGA
Through the Iir stopband filter combined with pipeline structure and power compensation, the problems of insufficient stopband suppression and high resource consumption of FPGA filters when filtering and removing interfering signals are solved, achieving the effect of high-efficiency filtering and resource saving.
Patent Information
- Application Number
- CN202411537816.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-04-04
AI Technical Summary
When filtering and removing interfering signals, the existing FPGA filters have insufficient stopband suppression and large stopband bandwidth, which cannot effectively retain the original signal and high resource consumption.
The iir stopband filter is combined with the pipeline structure, and the filter parameters are updated through real-time calculation and power compensation operation, and interfering signals are filtered and the original signals are retained.
It realizes efficient filtering and removing interfering signals while retaining the original signal to the greatest extent, reducing resource consumption, and the stopband bandwidth and frequency can be set at will.
Smart Images
Figure CN119766197A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of waveform processing technology, and in particular to a digital audio data optimization method based on FPGA. Background Technology
[0002] FPGAs use band-stop filters to filter out interference signals in the data.
[0003] When using a band-stop filter to filter out interference signals, the band-stop filter should meet the requirements of high stopband rejection, small stopband bandwidth, small passband ripple, high data throughput, zero passband gain, and low data processing delay, so as to ensure that interference signals can be completely filtered out and the impact on the original signal is minimized.
[0004] Existing technologies use low-pass or high-pass FIR filters multiplied by the frequency offset to form band-stop filters. However, FIR filters have limited stopband depth and large stopband bandwidth. They cannot guarantee effective filtering of interference signals and minimize the impact on the original signal. Furthermore, FIR filters require significant resources, and the tap coefficients cannot be arbitrarily set, making them extremely inconvenient to use. Summary of the Invention
[0005] The present invention provides a digital audio data optimization method based on FPGA, which can retain the original signal to the greatest extent while filtering out interference signals.
[0006] To achieve the above objectives, this invention provides a digital audio data optimization method based on FPGA, the key of which includes the following steps:
[0007] Step 1: The data acquisition module in the host computer acquires the digital audio signal x(n) in real time and transmits the digital audio signal x(n) to the IRR stopband filter;
[0008] Step 2: The parameter calculation module in the host computer calculates the parameter based on the preset center frequency f. c Stopband bandwidth b w and the sampling rate f of the digital audio signal x(n) s The parameter information of the IRR stopband filter is calculated and updated in real time and transmitted to the IRR stopband filter.
[0009] Step 3: The IRR stopband filter performs filtering and power compensation operations on the digital audio signal x(n) sequentially using the parameter information, and outputs the optimized digital audio signal y(n);
[0010] The output expression of the IRR stopband filter is as follows:
[0011] y(n) = g(n) * scale
[0012] g(n)=[b1x(n)+b2x(n-1)+b3x(n-3)-a2g(n-1)-a3g(n-2)] / a1
[0013] Where y(n) represents the optimized digital audio signal, x(n) represents the input digital audio signal, g(n) represents the iterative signal without power compensation, and n represents the time sequence number; a1, a2, a3, b1, b2, b3, and scale represent the seven parameters of the IRR stopband filter.
[0014] Through the above design, using an IIR stopband filter + pipeline structure, a large data throughput is achieved. The IIR stopband filter solves the problems of low stopband suppression and large stopband bandwidth of the FIR filter.
[0015] The parameter calculation module can accurately calculate the parameters required for the IIR stopband filter based on the frequency, bandwidth, and sampling rate input by the user, and update them in real time, solving the problem that the parameters of the FIR filter cannot be set arbitrarily.
[0016] Preferably, the expression for the iterative signal g(n) is:
[0017] b1x(n)+b2x(n-1)+b3x(n-2)=a1g(n)+a2g(n-1)+a3g(n-2)
[0018] Performing a z-transform on the above equation yields:
[0019] b1X(z)+b2X(z)z -1 +b3X(z)z -2 =a1G(z)+a2G(z)z -1 +a3G(z)z -2
[0020] in,
[0021] z = e jw
[0022] Where z represents the independent variable in the Z-domain, j represents the imaginary unit, w represents the angular frequency, and e represents the natural base;
[0023] The transfer function of the iterative signal g(n) is:
[0024]
[0025] The amplitude-frequency response function for the iterative signal g(n) is constructed as follows:
[0026]
[0027] Let H(z) = F(z), then the parameter update expression for the IRR stopband filter is as follows:
[0028] b1 = 1
[0029] b2 = 2p0
[0030] b3 = p0 2
[0031] a1 = 1
[0032] a2 = 2sp *
[0033] a3 = s 2 p * 2
[0034]
[0035] Where p0 is the zero point, p * is the pole; s is an undetermined parameter, ranging from 0 to 1; P(b) is the out-of-band average gain of the irr stopband filter, and b is the normalized bandwidth.
[0036] Preferably, the zero point p0 is equal to the pole p. * The expression is as follows:
[0037]
[0038] w c =2πf c / f s
[0039] Among them, w c This is the normalized center angular frequency;
[0040] The expression for the undetermined parameter s is as follows:
[0041]
[0042] in,
[0043]
[0044] The expression for the out-of-band average gain P(b) of the IRR stopband filter is as follows:
[0045]
[0046] in,
[0047]
[0048] Among them, f cf is the center frequency. s b is the sampling rate. w This refers to the stopband bandwidth.
[0049] Preferably, the IRR stopband filter is located in the FPGA.
[0050] Preferably, in step 3, the IRR stopband filter sequentially performs filtering and power compensation operations on the digital audio signal x(n), with the specific steps as follows:
[0051] Step A1: The first-order input unit in the IRR stopband filter acquires the digital audio signal x(n) and passes it to the first multiplier and the second-order input unit;
[0052] The second-order input unit delays the digital audio signal x(n) by one unit to obtain second-order input data x(n-1), and then passes it to the second multiplier and the third-order input unit;
[0053] The third-order input unit delays the second-order input data x(n-1) by one unit to obtain the third-order input data x(n-2), and then passes it to the third multiplier;
[0054] Step A2: The first multiplier multiplies the digital audio signal x(n) with parameter b1 to obtain the first multiplier, and then passes it to the arithmetic unit;
[0055] The second multiplier multiplies the second-order input data x(n-1) with the parameter b2 to obtain the second multiplier, and then passes it to the arithmetic unit;
[0056] The third multiplier multiplies the third-order input data x(n-2) with the parameter b3 to obtain the third multiplier, and then passes it to the arithmetic unit.
[0057] Step A3: The first-order iterative unit initializes and generates first-order iterative data g(n), which is then passed to the second-order iterative unit;
[0058] The second-order iterative unit delays the first-order iterative data g(n) by one unit to obtain the second-order iterative data g(n-1), and then passes it to the third-order iterative unit and the fourth multiplier.
[0059] The third-order iterative unit delays the second-order iterative data g(n-1) by one unit to obtain the third-order iterative data g(n-2), and then passes it to the fifth multiplier;
[0060] Step A4: The fourth multiplier multiplies the second-order iterative data g(n-1) with the parameter a2 to obtain the fourth multiplier, and then passes it to the arithmetic unit;
[0061] The fifth multiplier multiplies the third-order iterative data g(n-2) with the parameter a3 to obtain the fifth multiplier, and then passes it to the arithmetic unit;
[0062] Step A5: The arithmetic unit adds the first, second, and third multipliers, and subtracts the fourth and fifth multipliers to obtain filtered data, which is then passed to the sixth multiplier.
[0063] Step A6: The sixth multiplier combines the filtered data with the parameters. Multiply them to obtain the sixth multiplier, and pass it to the first-order iterative unit;
[0064] Step A7: The first-order iterative unit takes the sixth multiplier as new first-order iterative data and passes it to the power compensation multiplier and the second-order iterative unit;
[0065] Step A8: The power compensation multiplier multiplies the new first-order iterative data with the parameter scale and outputs the optimized digital audio signal y(n).
[0066] Through the above design, interference signals in the digital audio signal x(n) are effectively filtered out, and power compensation of the filtered signal is achieved.
[0067] Preferably, in step A3, the initial value of the first-order iterative data g(n) is zero.
[0068] The beneficial effects of this invention are:
[0069] 1. It can filter out interference signals while preserving the original signal to the greatest extent possible;
[0070] 2. The stopband bandwidth and stopband frequency can be set arbitrarily, making it more convenient for users;
[0071] 3. IIR stopband filters require less DSP resources and have lower operating costs. Attached Figure Description
[0072] Figure 1 This is a schematic diagram of the process of the present invention;
[0073] Figure 2 This is a schematic diagram of the algorithm structure of the IRR stopband filter in the embodiment;
[0074] Figure 3 This is the Z-domain plot of the amplitude-frequency response in the embodiment;
[0075] Figure 4 The above is a MATLAB simulation diagram from the embodiment.
[0076] Figure 5 This is a simulation diagram of the FPGA in the embodiment. Detailed Implementation
[0077] The present invention will be further described in detail below with reference to the accompanying drawings and specific examples. The following embodiments or drawings are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
[0078] like Figure 1 As shown: A digital audio data optimization method based on FPGA includes the following steps:
[0079] Step 1: The data acquisition module in the host computer acquires the digital audio signal x(n) in real time and transmits the digital audio signal x(n) to the IRR stopband filter;
[0080] Step 2: The parameter calculation module in the host computer calculates the parameter based on the preset center frequency f. c Stopband bandwidth b w and the sampling rate f of the digital audio signal x(n) s The parameter information of the IRR stopband filter is calculated and updated in real time and transmitted to the IRR stopband filter.
[0081] Step 3: The IRR stopband filter performs filtering and power compensation operations on the digital audio signal x(n) sequentially using the parameter information, and outputs the optimized digital audio signal y(n);
[0082] like Figure 2 As shown: In step 3, the IRR stopband filter sequentially performs filtering and power compensation operations on the digital audio signal x(n). The specific steps are as follows:
[0083] Step A1: The first-order input unit in the IRR stopband filter acquires the digital audio signal x(n) and passes it to the first multiplier and the second-order input unit;
[0084] The second-order input unit delays the digital audio signal x(n) by one unit to obtain second-order input data x(n-1), and then passes it to the second multiplier and the third-order input unit;
[0085] The third-order input unit delays the second-order input data x(n-1) by one unit to obtain the third-order input data x(n-2), and then passes it to the third multiplier;
[0086] Step A2: The first multiplier multiplies the digital audio signal x(n) with parameter b1 to obtain the first multiplier, and then passes it to the arithmetic unit;
[0087] The second multiplier multiplies the second-order input data x(n-1) with the parameter b2 to obtain the second multiplier, and then passes it to the arithmetic unit;
[0088] The third multiplier multiplies the third-order input data x(n-2) with the parameter b3 to obtain the third multiplier, and then passes it to the arithmetic unit.
[0089] Step A3: The first-order iterative unit initializes and generates first-order iterative data g(n), which is then passed to the second-order iterative unit;
[0090] The second-order iterative unit delays the first-order iterative data g(n) by one unit to obtain the second-order iterative data g(n-1), and then passes it to the third-order iterative unit and the fourth multiplier.
[0091] The third-order iterative unit delays the second-order iterative data g(n-1) by one unit to obtain the third-order iterative data g(n-2), and then passes it to the fifth multiplier;
[0092] Step A4: The fourth multiplier multiplies the second-order iterative data g(n-1) with the parameter a2 to obtain the fourth multiplier, and then passes it to the arithmetic unit;
[0093] The fifth multiplier multiplies the third-order iterative data g(n-2) with the parameter a3 to obtain the fifth multiplier, and then passes it to the arithmetic unit;
[0094] Step A5: The arithmetic unit adds the first, second, and third multipliers, and subtracts the fourth and fifth multipliers to obtain filtered data, which is then passed to the sixth multiplier.
[0095] Step A6: The sixth multiplier combines the filtered data with the parameters. Multiply them to obtain the sixth multiplier, and pass it to the first-order iterative unit;
[0096] Step A7: The first-order iterative unit takes the sixth multiplier as new first-order iterative data and passes it to the power compensation multiplier and the second-order iterative unit;
[0097] Step A8: The power compensation multiplier multiplies the new first-order iterative data with the parameter scale and outputs the optimized digital audio signal y(n).
[0098] Figure 2 In the middle, z -1 It indicates a delay of one unit of time.
[0099] In step A3, the initial value of the first-order iterative data g(n) is zero.
[0100] The IRR stopband filter is configured in the FPGA.
[0101] The output expression of the IRR stopband filter is as follows:
[0102] y(n) = g(n) * scale
[0103] g(n)=[b1x(n)+b2x(n-1)+b3x(n-3)-a2g(n-1)-a3g(n-2)] / a1
[0104] Where y(n) represents the optimized digital audio signal, x(n) represents the input digital audio signal, g(n) represents the iterative signal without power compensation, and n represents the time sequence number; a1, a2, a3, b1, b2, b3, and scale represent the seven parameters of the IRR stopband filter.
[0105] The discrete structure expression of the IIR stopband filter is as follows:
[0106] b1x(n)+b2x(n-1)+b3x(n-2)=a1g(n)+a2g(n-1)+a3g(n-2) (1)
[0107] Equation (1) is obtained by z-transform:
[0108] b1X(z)+b2X(z)z -1 +b3X(z)z -2 =a1G(z)+a2G(z)z -1 +a3G(z)z -2 (2)
[0109] in,
[0110] z = e jw
[0111] Where z represents the independent variable in the Z-domain, j represents the imaginary unit, w represents the angular frequency, and e represents the natural base.
[0112] The transfer function of the iir stopband filter is:
[0113]
[0114] The amplitude-frequency response function of the iir stopband filter is:
[0115]
[0116] Expanding formula 4, we get:
[0117]
[0118] Let H(z) = F(z), then the parameter update expression for the IRR stopband filter is as follows:
[0119] b1 = 1
[0120] b2 = 2p0
[0121] b3 = p0 2
[0122] a1 = 1
[0123] a2 = 2sp *
[0124] a3 = s 2 p * 2
[0125]
[0126] Where p0 is the zero point, p * is the pole, s is the parameter to be determined (range 0 to 1), P(b) is the out-of-band average gain of the irr stopband filter, and b is the normalized bandwidth.
[0127] The zero point p0 and the pole p * The expression is as follows:
[0128]
[0129] w c =2πf c / f s
[0130] The stopband bandwidth is based on a 3dB decrease, that is... or
[0131] When the following equation is satisfied:
[0132] 20lg F(z) ≥-3(7)
[0133] Substituting formula (4) into formula (7), we get:
[0134]
[0135] Substitute formula (9) into Figure 3 In this context, s is a point on line segment Op0;
[0136]
[0137] Depend on Figure 3 It can be seen that the magnitude of s is independent of the position of p0, and only depends on the magnitude of bw. For ease of calculation, f is substituted into this expression. c =0, therefore:
[0138] p0 = p * =e j0=(1,0)
[0139] sp * =(s,0)
[0140] z = (cos(w), jsin(w))
[0141] in,
[0142]
[0143] Substituting formulas 11 and 12 into formula 10, we get:
[0144]
[0145] That is: the distance from point z to point p0 is greater than or equal to 10. -0.075 The distance from point z to point s.
[0146] make
[0147]
[0148] at this time,
[0149]
[0150] Where n is an integer
[0151] 1. When or hour, For Δzsp * The longest edge of p0.
[0152]
[0153] Inequality (13) is always satisfied.
[0154] That is: s∈(0,1)
[0155] when or hour, For Δzsp * The longest side of O.
[0156]
[0157] Inequality (13) is always satisfied.
[0158] That is: s∈(0,1)
[0159] 2. When hour,
[0160]
[0161] and
[0162]
[0163] make
[0164] a = cos(w)
[0165]
[0166] From Cauchy's inequality, we get
[0167] (Equality holds when a = b)
[0168] Let a = b
[0169] but
[0170] Solving for:
[0171] now that:
[0172] Furthermore, due to the stability of the Z-transform, s < 1.
[0173] 3. When hour,
[0174]
[0175] now that:
[0176] now that:
[0177] now that:
[0178] now that:
[0179] In summary:
[0180]
[0181] in, In practical applications, a value closer to the origin should be chosen.
[0182] The out-of-band average gain P(b) of the iir stopband filter
[0183]
[0184] Where z = e jw
[0185]
[0186] Where c is or The length of the curve at time z. For
[0187] Substituting z, we get:
[0188]
[0189] make but:
[0190]
[0191] Since F(z) varies periodically with respect to 2π, we have:
[0192]
[0193] Since F(z) is symmetric about the zeros, therefore
[0194]
[0195] so
[0196]
[0197] The magnitude of P(b) is independent of the position of the zero point, and depends only on b. w The size is related; for ease of calculation, f is substituted here. c =0
[0198] p0 = (1,0)
[0199]
[0200] Therefore, the expression for the out-of-band average gain P(b) of the IRR stopband filter is as follows:
[0201]
[0202] in,
[0203]
[0204] Among them, f c f is the center frequency. s b is the sampling rate. w This refers to the stopband bandwidth.
[0205] When the sampling rate f s =76800Hz, center frequency f c = -3000Hz, stopband bandwidth data b w The MATLAB simulation graph at 200Hz is shown below. Figure 4 As shown, the FPGA simulation diagram is as follows: Figure 5 As shown. Figure 5 In this context, din_i is the input signal and dou_i is the output signal.
[0206] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A digital audio data optimization method based on FPGA, characterized in that: The following steps are involved: Step 1: The data acquisition module in the host computer collects the digital audio signal x(n) in real time, and passes the digital audio signal x(n) to the irr stopband filter; Step 2: The parameter calculation module in the host computer calculates the center frequency f according to the preset center frequency f c , stopband bandwidth b w , and the sampling rate f of the digital audio signal x(n) s , calculate and update the parameter information of the irr stopband filter in real time, and pass it to the irr stopband filter; Step 3: the irr stopband filter performs filtering and power compensation operations on the digital audio signal x(n) in sequence according to the parameter information, and outputs an optimized digital audio signal y(n); The output expression of the irr stopband filter is as follows: y(n)=g(n)*scale g(n)=[b1x(n)+b2x(n-1)+b3x(n-3)-a2g(n-1)-a3g(n-2)] / a1 Among them, y(n) represents the optimized digital audio signal, x(n) represents the input digital audio signal, g(n) represents the iterative signal without power compensation, n represents the time sequence number; a1, a2, a3, b1, b2, b3, and scale represent the 7 parameters of the irr stopband filter.
2. The FPGA-based digital audio data optimization method according to claim 1, characterized in that: The expression of the iterative signal g(n) is: b1x(n)+b2x(n-1)+b3x(n-2)=a1g(n)+a2g(n-1)+a3g(n-2) Performing z-transformation on the above equation yields: b1X(z)+b2X(z)z -1 +b3X(z)z -2 =a1G(z)+a2G(z)z -1 +a3G(z)z -2 in, with=e jw Among them, z represents the Z-domain independent variable, j represents the imaginary unit, w represents the angular frequency, and e represents the natural base; The transfer function of the iterative signal g(n) is: The amplitude-frequency response function constructed for the iterative signal g(n) is: Let H(z)=F(z), and the parameter update expression of the irr stopband filter is as follows: b1＝1 b2=2p0 <h2 style=";text-align:left;direction:ltr">b3 = p0<h2 style=";text-align:left;direction:ltr"> 2 a1＝1 <h2 style=";text-align:left;direction:ltr">a2 = 2sp<h2 style=";text-align:left;direction:ltr"> * a3=s 2 p * 2 Among them, p0 is the zero point, p * is the pole; s is a parameter to be determined, ranging from 0 to 1; P(b) is the out-of-band average gain of the irr stopband filter, and b is the normalized bandwidth.
3. The FPGA-based digital audio data optimization method according to claim 2, characterized in that: The zero point p0 is equal to the pole p * , the expression is as follows: w c =2πf c / f s The expression of the undetermined parameter s is as follows: in, The expression of the out-of-band average gain P(b) of the irr stopband filter is as follows: in, Among them, f c is the center frequency, f s is the sampling rate, b w is the stopband bandwidth.
4. The FPGA-based digital audio data optimization method according to claim 1, characterized in that: The irr stopband filter is arranged in the FPGA.
5. The FPGA-based digital audio data optimization method according to claim 2, characterized in that: In step 3, the irr stopband filter performs filtering and power compensation operations on the digital audio signal x(n) in sequence, and the specific steps are as follows: Step A1: the first-order input unit in the irr stopband filter obtains the digital audio signal x(n) and passes it to the first multiplier and the second-order input unit; The second-order input unit delays the digital audio signal x(n) by one unit to obtain second-order input data x(n-1), and transmits the data to the second multiplier and the third-order input unit; The third-order input unit delays the second-order input data x(n-1) by one unit to obtain third-order input data x(n-2), and transmits the third-order input data to the third multiplier; Step A2: the first multiplier multiplies the digital audio signal x(n) by the parameter b1 to obtain a first multiplier, and transmits the first multiplier to the operator; The second multiplier multiplies the second-order input data x(n-1) by the parameter b2 to obtain a second multiplier, and transmits the second multiplier to the operator; The third multiplier multiplies the third-order input data x(n-2) by parameter b3 to obtain a third multiplier, and transmits the third multiplier to the operator; Step A3: The first-order iteration unit is initialized to generate the first-order iteration data g(n) and passed to the second-order iteration unit; The second-order iteration unit delays the first-order iteration data g(n) by one unit to obtain second-order iteration data g(n-1), and transmits the delay to the third-order iteration unit and the fourth multiplier; The third-order iteration unit delays the second-order iteration data g(n-1) by one unit to obtain third-order iteration data g(n-2), and transmits the third-order iteration data g(n-2) to the fifth multiplier; Step A4: the fourth multiplier multiplies the second-order iterative data g(n-1) by parameter a2 to obtain a fourth multiplier, and transmits the fourth multiplier to the operator; The fifth multiplier multiplies the third-order iterative data g(n-2) by parameter a3 to obtain a fifth multiplier, and transmits the fifth multiplier to the operator; Step A5: the operator adds the first multiplier, the second multiplier and the third multiplier, and subtracts the fourth multiplier and the fifth multiplier to obtain filtered data, and transmits the filtered data to the sixth multiplier; Step A6: The sixth multiplier multiplies the filtered data and the parameter Multiply them together to obtain the sixth multiplier, and pass it to the first-order iteration unit; Step A7: the first-order iteration unit uses the sixth multiplier as new first-order iteration data, and transmits it to the power compensation multiplier and the second-order iteration unit; Step A8: The power compensation multiplier multiplies the new first-order iterative data by the parameter scale, and outputs an optimized digital audio signal y(n).
6. The FPGA-based digital audio data optimization method according to claim 5, characterized in that: In the step A3, the initial value of the first-order iterative data g(n) is zero.