Channel management module based on embedded CPU

Abstract

The invention relates to a channel management module based on an embedded CPU, and the module comprises an optical fiber interface which receives downlink optical fiber data of a module; the system control unit is used for analyzing data of a plurality of input optical fibers, packaging the data in an interruption form and sending the data to the embedded CPU; an embedded CPU (Central Processing Unit) is used for receiving data transmitted by the FPGA according to the interrupt instruction and finishing corresponding processing according to a system working mode; the network interface is used for respectively completing network sending of the channel calibration result and the component BIT according to a system working mode; cPU software is embedded in the FPGA, and the FPGA receives data transmitted by the FPGA according to the interrupt instruction, completes data analysis and judges the working mode of the system. According to the invention, by using the characteristics of strong interface capability of the FPGA and flexible processing of the CPU, the functional requirement of channel management is completed, the tasks of BIT packaging and sending, channel calibration processing and the like of the component are covered, and the application requirements of various phased-array antennas are met.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing, and in particular to a channel management module based on an embedded CPU. Background Art

[0002] Phased array radar antennas are composed of multiple antenna units, and each antenna unit can be arranged in different forms such as lines, planes, spheres, cylinders, and conformal surfaces according to system design. By controlling the phase of the transmitted signal of each antenna unit, energy is transmitted in a specified direction. Similarly, by controlling the phase of the received signal of each antenna unit, the energy reflected from the specified direction can be received. The quality of each antenna unit will ultimately affect the quality of the transmit lobe and the receive lobe. In order to ensure the quality of the transmit lobe and the receive lobe, the working conditions of each channel need to be managed.

[0003] Phased array radar antennas vary in size, from dozens of antenna units to tens of thousands or even hundreds of thousands of antenna units, depending on system requirements. Each antenna unit corresponds to a channel. In large phased array radar antennas, there are many antenna units, that is, many channels, which brings challenges to channel management. Therefore, it is necessary to design a channel management module that can meet the channel management requirements of tens to hundreds of thousands of channels and realize real-time monitoring of the working conditions of each channel. Summary of the invention

[0004] In order to solve the existing technical problems, the present invention provides a channel management module based on an embedded CPU.

[0005] The specific contents of the present invention are as follows: A channel management module based on an embedded CPU, comprising: Optical fiber interface, receiving the downlink optical fiber data of the component; The system control unit parses the data of multiple input optical fibers and sends them to the embedded CPU in the form of interrupts; The embedded CPU receives the data transmitted by the FPGA according to the interrupt instruction and completes the corresponding processing according to the system working mode; The network interface completes the network transmission of channel calibration results and component BIT according to the system working mode; The embedded CPU software receives the data transmitted by the FPGA according to the interrupt instructions, completes the data analysis, and determines the system working mode.

[0006] Furthermore, the optical fiber data includes timing, control words, channel data and component BIT data.

[0007] Furthermore, the embedded CPU completes the channel calibration processing of multiple channels and the packaging of channel calibration results in the channel calibration working mode; completes the real-time packaging of component BIT data of multiple components in the component BIT forwarding working mode; and completes the periodic packaging of component BIT data of multiple components in the system normal working mode.

[0008] Further, the working process includes: determining the maximum number of receivable optical fibers of the optical fiber interface according to the bandwidth of the data to be processed and the transmission bandwidth of the network; The optical fiber interface receives optical fiber data of multiple optical fibers input externally in real time. The system control unit parses the data of the multiple input optical fibers to parse out timing, control words, channel data, and component BIT data.

[0009] Furthermore, in the system channel calibration working mode, the system control unit intercepts a part of the channel data of each input channel, and generates an interrupt signal according to the timing signal, and packages the control word and the intercepted channel data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and channel data transmitted by the FPGA into the local memory, performs channel calibration on the channel data, and packages the channel calibration results and sends them.

[0010] Furthermore, in the system component BIT forwarding working mode, the system control unit generates an interrupt signal based on the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and component BIT data transmitted by the FPGA into the local memory, and repackages the component BIT data before sending it; all packaged and sent data are output through the network interface.

[0011] Furthermore, in the normal operating mode of the system, the system control unit generates an interrupt signal based on the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, and stores the control word and component BIT data transmitted by the FPGA into the local memory. The input is scheduled by frame, and the output is cyclical. There are multiple frames of input in one cycle, and only the component BIT data of the last frame in the cycle is repackaged and sent; all packaged and sent data are output through the network interface.

[0012] Furthermore, the output is performed with a period of 3 seconds.

[0013] The channel management module and method based on the embedded CPU of the present invention designs a channel management processing architecture, and utilizes the strong FPGA interface capability and flexible CPU processing characteristics to complete the functional requirements of channel management, including tasks such as component BIT packaging and outbound delivery and channel calibration processing. It can meet the application requirements of various phased array antennas through flexible addition and cutting. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The specific implementation of the present invention will be further explained below in conjunction with the accompanying drawings.

[0015] Figure 1 It is a block diagram of the channel management architecture based on the embedded CPU of the present invention; Figure 2 This is the channel management software architecture of the embedded CPU of the present invention. DETAILED DESCRIPTION

[0016] Combination Figure 1 and Figure 2 The present invention provides a channel management module and method based on an embedded CPU, comprising: Optical fiber interface 1 is used to receive the downlink optical fiber data of the component, which includes timing, control words, channel data, component BIT data, etc.; The system control unit 2 completes the parsing of multiple input optical fiber data, parses the timing, control word, channel data, component BIT data, etc. from each optical fiber, and packages and sends them to the embedded CPU 3 in the form of interrupts; The embedded CPU3 receives the data transmitted from the FPGA according to the interrupt instruction, and completes the corresponding processing according to the system working mode. In the channel calibration working mode, the channel calibration processing of multiple channels and the packaging of channel calibration results are completed. In the component BIT forwarding working mode, the component BIT data of multiple components are packaged in real time. In the normal working mode of the system, the component BIT data of multiple components are packaged periodically.

[0017] Network interface 4, according to the system working mode, completes the network transmission of channel calibration results and component BIT respectively; Embedded CPU software 5, according to the interrupt instruction, receives the data transmitted from FPGA, completes data analysis, and determines the system working mode. In the channel calibration working mode, completes the channel calibration processing of multiple channels and the packaging of channel calibration results. In the component BIT forwarding working mode, completes the real-time packaging of component BIT data of multiple components. In the normal working mode of the system, completes the periodic packaging of component BIT data of multiple components.

[0018] The implementation method and steps of this architecture are as follows: The maximum number of optical fibers that can be received by the optical fiber interface 1 is determined according to the bandwidth of the data to be processed and the transmission bandwidth of the network.

[0019] The optical fiber interface 1 receives the optical fiber data of multiple optical fibers input externally in real time (the number of optical fibers changes according to the array size), and the system control unit 2 parses the data of multiple input optical fibers to parse out the timing, control words, channel data, and component BIT data.

[0020] In the system channel calibration working mode, the system control unit 2 intercepts a part of the channel data of each input channel, and generates an interrupt signal according to the timing signal, and packages the control word and the intercepted channel data in the form of an interrupt and sends them to the embedded CPU 3. The embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction, stores the control word and channel data transmitted by the FPGA into the local memory, performs channel calibration on the channel data, and packages the channel calibration results and sends them.

[0021] In the system component BIT forwarding working mode, the system control 2 generates an interrupt signal according to the timing signal, and packages the control word and component BIT data to the embedded CPU 3 in the form of an interrupt. The embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction, stores the control word and component BIT data transmitted by the FPGA into the local memory, and repackages the component BIT data before sending. All packaged and sent data are output through the network interface 4.

[0022] In the normal working mode of the system, the system control unit 2 generates an interrupt signal according to the timing signal, and packages the control word and component BIT data to the embedded CPU 3 in the form of an interrupt. The embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction and stores the control word and component BIT data transmitted by the FPGA into the local memory. The input in this mode is scheduled by frame, and the output is performed in a 3s cycle. There will be multiple frames of input in a 3s cycle, and only the component BIT data of the last frame in the 3s cycle will be repackaged and sent.

[0023] All the data sent in packets are output through the network interface 4.

[0024] In order to further illustrate the specific implementation of the present invention, an example of a channel management module and method based on an embedded CPU is given.

[0025] In this example, fiber interface 1 contains 16 input fibers, and the data packaged in the fibers include: control words, component BIT, and channel data. Each input fiber packages 16 channels, for a total of 256 channels. The amount of component BIT data packaged in each input fiber is: 64*32bit. The fiber input data is scheduled by frame, with a frame period of 64ms.

[0026] In the channel calibration working mode, the optical fiber interface 1 receives 16 optical fiber data, and the system control unit 2 parses each input optical fiber data to parse out the control word, component BIT, and channel data. After parsing a complete frame period of data, an interrupt signal is generated to the embedded CPU 3, and the parsed control word and channel data are sent to the embedded CPU 3. After receiving the interrupt instruction, the embedded CPU software 5 running in the embedded CPU 3 stores the control word and channel data sent by the system control 2 into the local memory. The embedded CPU software 5 calibrates each channel according to the control requirements in the control word, and then sends the channel calibration results to the network interface 4, which is sent through the network interface 4. The total amount of data sent is: 16384*32bit.

[0027] In the component BIT forwarding working mode, the optical fiber interface 1 receives 16 optical fiber data, and the system control unit 2 parses each input optical fiber data to parse out the control word, component BIT, and channel data. After parsing a complete frame cycle of data, an interrupt signal is generated to the embedded CPU 3, and the parsed control word and component BIT data are sent to the embedded CPU 3. After the embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction, the control word and component BIT data transmitted by the system control unit 2 are stored in the local memory. The embedded CPU software 5 performs component BIT packaging according to the control requirements in the control word, and sends the component BIT data to the network interface 4, and sends it through the network interface 4. In the component BIT forwarding working mode, data is scheduled by frame, and component BIT data is sent in each frame. The total amount of data sent in each frame is: 1024*32bit.

[0028] In the normal working mode of the system, the optical fiber interface 1 receives 16 optical fiber data, and the system control unit 2 parses each input optical fiber data to parse out the control word, component BIT, and channel data. After parsing the data of each complete frame period, an interrupt signal is generated to the embedded CPU 3, and the parsed control word and component BIT data are sent to the embedded CPU 3. After the embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction, it stores the control word and channel data transmitted by the system control unit 2 into the local memory. The input in this mode is scheduled by frame, and the output is carried out in a cycle of 3s. There will be multiple frames input within a cycle of 3s, and only the component BIT data of the last frame within the 3s cycle will be repackaged, and the repackaged component BIT data will be sent to the network interface 4 and sent through the network interface 4. The total amount of data sent each time is: 1024*32bit.

[0029] The channel management module of the present invention can be expanded according to demand, and the system is highly flexible, which solves the engineering problem of channel management of large phased array antennas; it adopts FPGA embedded CPU, does not require additional hardware, and effectively reduces the design cost; it uses a standard gigabit network to send data, which is convenient for other systems to access.

[0030] Many specific details are described in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A channel management module based on an embedded CPU, characterized in that: include: Optical fiber interface, receiving the downlink optical fiber data of the component; The system control unit parses the data of multiple input optical fibers and sends them to the embedded CPU in the form of interrupts; The embedded CPU receives the data transmitted by the FPGA according to the interrupt instruction and completes the corresponding processing according to the system working mode; The network interface completes the network transmission of channel calibration results and component BIT according to the system working mode; The embedded CPU software receives the data transmitted by the FPGA according to the interrupt instructions, completes the data analysis, and determines the system working mode.

2. The channel management module based on embedded CPU according to claim 1, characterized in that: The optical fiber data includes timing, control words, channel data and component BIT data.

3. The channel management module based on embedded CPU according to claim 1, characterized in that: In the channel calibration working mode, the embedded CPU completes the channel calibration processing of multiple channels and the packaging of channel calibration results; in the component BIT forwarding working mode, it completes the real-time packaging of component BIT data of multiple components; in the normal system working mode, it completes the periodic packaging of component BIT data of multiple components.

4. The channel management module based on embedded CPU according to claim 3 is characterized in that: The working process includes: determining the maximum number of optical fibers that can be received by the optical fiber interface according to the bandwidth of the data to be processed and the transmission bandwidth of the network; The optical fiber interface receives optical fiber data of multiple optical fibers input externally in real time. The system control unit parses the data of the multiple input optical fibers to parse out timing, control words, channel data, and component BIT data.

5. The channel management module based on embedded CPU according to claim 4 is characterized in that: In the system channel calibration working mode, the system control unit intercepts a part of the channel data of each input channel, and generates an interrupt signal according to the timing signal, and packages the control word and the intercepted channel data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and channel data transmitted by the FPGA into the local memory, performs channel calibration on the channel data, and packages the channel calibration results and sends them.

6. The channel management module based on embedded CPU according to claim 4, characterized in that: In the system component BIT forwarding working mode, the system control unit generates an interrupt signal based on the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and component BIT data transmitted by the FPGA into the local memory, and repackages the component BIT data before sending it; all packaged and sent data are output through the network interface.

7. The channel management module based on embedded CPU according to claim 4, characterized in that: In the normal working mode of the system, the system control unit generates an interrupt signal according to the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, and stores the control word and component BIT data transmitted by the FPGA into the local memory. The input is scheduled by frame, and the output is cyclical. There are multiple frames of input in one cycle, and only the component BIT data of the last frame in the cycle is repackaged and sent; all packaged and sent data are output through the network interface.

8. The channel management module based on embedded CPU according to claim 7, characterized in that: The output is performed in a cycle of 3s.

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