A communication chip testing device, system and method

Abstract

The present disclosure relates to a communication chip testing device, system and method. The device includes a digital control module and an FPGA module, wherein the digital control module is used to receive a general control signal provided by an automatic test device, and send a test control signal to the FPGA module according to the general control signal; the FPGA module is used to generate a modulation signal according to the test control signal, and send the modulation signal to the communication chip. The communication chip testing device provided by the present disclosure can reduce the requirements for the functions and performance of the automatic test equipment, and thus can perform efficient, fast and low-cost functional testing on the communication chip, which can reduce the test cost while reducing the test time, improving the test efficiency and improving the reliability of the test results.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic circuit technology, and in particular to a communication chip testing device, system and method. Background Art

[0002] In the field of modern communication technology, the signal receiving capability of communication chips is one of the key indicators to measure their performance. With the rapid development of wireless communication technology, the emergence of emerging technologies such as 5G and the Internet of Things (IoT) has put forward higher requirements for the receiving sensitivity, anti-interference ability and signal processing speed of communication chips. However, existing communication chips often show problems such as unstable signal reception and insufficient sensitivity in complex electromagnetic environments, which limits the overall performance and reliability of the communication system. Therefore, testing the various capabilities of communication chips is of great significance to improving communication quality and enhancing system stability. Summary of the invention

[0003] In order to solve the above technical problems, the present disclosure provides a communication chip testing device, system and method.

[0004] The present disclosure provides a communication chip testing device, including a digital control module and an FPGA module, wherein the digital control module is used to receive a general control signal provided by an automatic testing device, and send a test control signal to the FPGA module according to the general control signal; the FPGA module is used to generate a modulation signal according to the test control signal, and send the modulation signal to the communication chip.

[0005] Optionally, the communication chip is an NFC chip, and the modulated signal is used to test a data receiving function and / or a data sending function of the NFC chip.

[0006] Optionally, the digital control module includes a digital-to-analog converter and a transformer; the digital-to-analog converter is used to output an analog differential signal according to the total control signal; and the transformer is used to convert the analog differential signal into the test control signal with a single-ended output.

[0007] Optionally, the FPGA module is specifically used to generate the modulation signal having a target frequency, a target carrier amplitude and a target modulation depth according to the test control signal.

[0008] Optionally, the communication chip testing device is further used to receive a test start signal provided by the automatic testing equipment, and provide a start signal to the communication chip according to the test start signal.

[0009] Optionally, the communication chip testing device also includes a radio frequency interface and a digital interface; the FPGA module is connected to the communication chip via the radio frequency interface; and the digital control module is connected to the automatic testing equipment via the digital interface.

[0010] Optionally, the communication chip testing device further includes a power supply interface, which is connected to the automatic testing equipment and receives a power supply signal provided by the automatic testing equipment.

[0011] Based on the same inventive concept, the present disclosure also provides a communication chip testing system, including the communication chip testing device and the automatic testing equipment; the automatic testing equipment is also used to receive a feedback signal generated by the communication chip according to the modulation signal.

[0012] Optionally, the communication chip testing system further includes a testing board, wherein one testing board is used to carry a plurality of the communication chips.

[0013] Based on the same inventive concept, the present disclosure also provides a communication chip testing method, including: using automatic testing equipment to send a general control signal to a digital control module; using the digital control module to send a test control signal to an FPGA module according to the general control signal; using the FPGA module to generate a modulation signal according to the test control signal, and sending the modulation signal to the communication chip.

[0014] Compared with the prior art, the technical solution provided by the present invention has the following advantages: the communication chip testing device provided by the present invention can reduce the requirements for the functions and performance of automatic testing equipment, and thus can perform efficient, fast and low-cost functional testing on communication chips, which can reduce testing costs while reducing testing time, improving testing efficiency and improving the reliability of test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 A schematic diagram of the structure of a communication chip testing device and a communication chip testing system provided in an embodiment of the present disclosure;

[0018] Figure 2A schematic diagram of the structure of another communication chip testing device and a communication chip testing system provided by an embodiment of the present disclosure;

[0019] Figure 3 A schematic diagram of a circuit principle of a digital-to-analog converter provided in an embodiment of the present disclosure;

[0020] Figure 4 A schematic diagram of a circuit principle of a transformer provided in an embodiment of the present disclosure;

[0021] Figure 5 A schematic diagram of the structure of another communication chip testing device and a communication chip testing system provided by an embodiment of the present disclosure;

[0022] Figure 6 A flow chart of a communication chip testing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to more clearly understand the above-mentioned purposes, features and advantages of the embodiments of the present disclosure, the scheme of the embodiments of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other without conflict.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present disclosure, but the embodiments of the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0025] An embodiment of the present disclosure provides a communication chip testing device 10, such as Figure 1 As shown, it includes a digital control module 11 and an FPGA module 12.

[0026] The digital control module 11 is used to receive a general control signal provided by the automatic test equipment 20 and send a test control signal to the FPGA module 12 according to the general control signal.

[0027] The FPGA module 12 is used to generate a modulation signal according to the test control signal, and send the modulation signal to the communication chip 30 .

[0028] Specifically, FPGA (Field Programmable Gate Array) is a highly flexible integrated circuit that allows users to configure internal logic blocks and interconnection resources through programming to achieve specific digital circuit functions. It includes programmable input and output units, configurable logic blocks, digital clock management modules, embedded block RAM, wiring resources, embedded dedicated hard cores, bottom-level embedded functional units and other structures, which can generate the debugging signals required in the above embodiments.

[0029] Specifically, the automatic test equipment 20 can be an ATE tester. The ATE (Automatic Test Equipment) tester is a highly specialized electronic test platform, which is widely used in semiconductor manufacturing, consumer electronics production, automotive electronics, aerospace and other fields. It performs functional and performance tests on integrated circuits (ICs), printed circuit boards (PCBs), modules and system-level products in an automated manner to ensure that they meet design specifications and quality standards, and can improve test efficiency, enhance test accuracy and reduce the risk of errors caused by manual intervention. However, in related technologies, testers used to test communication chips often need to integrate more functions, and the corresponding detection accuracy requirements are also high, which greatly increases the test cost of communication chips.

[0030] The embodiment of the present disclosure implements the test of the communication chip through the communication chip testing device 10 which is external to the automatic testing equipment 20. At this time, the selected automatic testing equipment 20 does not need to integrate multiple functions and can be a relatively low-end device, or a device originally used for other tests, thereby saving testing costs.

[0031] The communication chip testing device 10 provided in the embodiment of the present disclosure can reduce the requirements for the functions and performance of the automatic testing equipment 20, and thus can perform efficient, fast, and low-cost functional testing on the communication chip, which can reduce the testing cost while reducing the testing time, improving the testing efficiency, and improving the reliability of the test results.

[0032] In some embodiments, Figure 1 As shown, the automatic test equipment 20 is also used to receive a feedback signal generated by the communication chip 30 according to the modulation signal, thereby verifying the signal receiving function of the communication chip 30 .

[0033] Specifically, if the signal receiving function of the communication chip 30 is normal, a corresponding feedback signal will be generated according to the received modulation signal. The automatic testing equipment 20 compares the information contained in the feedback signal with the expected information by comparing the waveform, frequency and other information of the modulation signal and the feedback signal. If it is confirmed that the two are consistent, it means that the signal receiving function of the communication chip 30 is normal.

[0034] In some embodiments, multiple communication chips 30 are located on a test board, and the test board includes a general receiving port and a general sending port. The ports of the multiple communication chips 30 for receiving signals are connected to the general receiving port and receive the above-mentioned modulated signal together; the ports of the multiple communication chips 30 for sending signals are connected to the general sending port and send the above-mentioned feedback signal together.

[0035] In some embodiments, the communication chip 30 is an NFC chip, and the modulated signal is used to test the data receiving function and / or the data sending function of the NFC chip.

[0036] NFC (Near Field Communication) chip, also known as near field communication chip, is an integrated circuit chip used to support data transmission and communication of NFC technology. NFC technology allows short-range communication and data exchange between devices through wireless radio frequency identification. NFC chips are usually built into devices such as smartphones, tags or cards, and can achieve fast, secure and convenient data transmission. The working principle of NFC chips is based on wireless radio frequency identification technology. When two devices that support NFC communication are close to each other, a short-range wireless communication link will be established between them. NFC chips can exchange data by receiving and sending radio frequency signals to achieve fast information transmission.

[0037] Specifically, the PICC (Proximity Integrated Circuit Card) and PCD (Proximity Coupling Device) functions of the NFC chip are two core concepts in NFC technology, which define the role and behavior of NFC devices in the communication process.

[0038] PICC refers to the device that plays the role of being identified in NFC communication. In the NFC system, PICC can be passive. It receives radio frequency energy from PCD to obtain power and communicate with PCD. PCD refers to the party that plays the role of card reader or the device that initiates communication in NFC communication. PCD can be active. It sends radio frequency signals to activate PICC and establish communication with it. These two functions of PICC and PCD support two-way communication and data exchange of NFC technology.

[0039] During specific implementation, the above-mentioned modulated signal can be used to test the PICC data receiving function and / or data sending function of the NFC chip, and can also be used to test the PCD data receiving function and / or data sending function of the NFC chip.

[0040] In some embodiments, the FPGA module 12 is specifically used to generate a modulation signal having a target frequency, a target carrier amplitude, and a target modulation depth according to a test control signal, thereby being able to meet the working requirements of different communication chips.

[0041] In another specific embodiment, the FPGA module 12 can generate a 16-bit+ adjustable RAP / SINE wave (sine wave and random noise) signal to test the ADC (analog-to-digital conversion) performance of the communication chip, thereby ensuring that the communication chip can accurately convert analog signals into digital signals under different signal conditions.

[0042] During specific implementation, the FPGA module 12 may adopt an XC6SLX150 chip, and those skilled in the art may also adopt other types of chips as FPGA modules, which are not further limited here.

[0043] In some embodiments, Figure 2 As shown, the digital control module 11 includes a digital-to-analog converter 111 and a transformer 112, wherein the circuit schematic diagram of the digital-to-analog converter 111 is as shown in FIG. Figure 3 As shown, the circuit schematic diagram of the transformer 112 is as follows Figure 4 shown.

[0044] The digital-to-analog converter 111 is used to output an analog differential signal according to the total control signal, so that the signal in the device can be transmitted stably and without interference. Figure 3 As shown, the 22nd pin DAC_IOUA and the 21st pin DAC_IOUB of the chip used by the digital-to-analog converter 111 are used to output analog differential signals.

[0045] The transformer 112 is used to convert the analog differential signal into a single-ended output test control signal, so that the FPGA module 12 can receive the test control signal. Figure 4 As shown, the DAC_IOUA terminal and the DAC_IOUB terminal of the transformer 112 are used to receive analog differential signals, and the DAC_OUT terminal is used to output a test control signal.

[0046] Specifically, Figure 3 As shown, the main body of the digital-to-analog converter 111 can adopt the AD9744 chip, and those skilled in the art can also adopt other types of chips as the digital-to-analog converter 111, which is not limited here; at the same time, those skilled in the art can also know Figure 3 and Figure 4 The arrangement principles of other peripheral circuit components except the AD9744 chip and the transformer 112 in the illustrated embodiment will not be elaborated here.

[0047] In some embodiments, the communication chip testing device 10 is further configured to receive a test start signal provided by the automatic testing equipment 20 and provide a start signal to the communication chip 30 according to the test start signal, so that the communication chip 30 starts the data receiving and sending functions.

[0048] In a specific implementation, the automatic test equipment 20 sends a test start signal to the chip test device 10 based on the I2C communication protocol. I2C (Inter-Integrated Circuit) is a serial communication protocol that allows multiple devices (called nodes) to communicate through only two lines: one is a serial data line (SDA) and the other is a serial clock line (SCL).

[0049] Those skilled in the art may also select other communication protocols as the communication protocol between the chip testing device 10 and the automatic testing equipment 20 , which is not limited here.

[0050] In some embodiments, Figure 5 As shown, the communication chip testing device 10 further includes a radio frequency interface 41 and a digital interface 42 ; the FPGA module 12 is connected to the communication chip 30 via the radio frequency interface 41 , and the digital control module 11 is connected to the automatic testing equipment 20 via the digital interface 42 .

[0051] In some embodiments, Figure 5 As shown, the communication chip test device 10 further includes a power interface 43, which is connected to the automatic test equipment 20 and receives a power signal provided by the automatic test equipment 20, so that the communication chip test device 10 does not need to be equipped with a separate power supply, further saving costs. Figure 5 As shown, the communication chip testing device 10 further includes a power module 50 for connecting to the power interface 43 and receiving power from the automatic testing equipment 20 , and providing power to other modules of the communication chip testing device 10 .

[0052] In other embodiments, multiple communication chips 30 are located on a test board, and the test board includes a power module. While the power module of the test board supplies power to the multiple communication chips 30, it is also connected to the power interface 43 of the communication chip test device 10 and supplies power to the communication chip test device 10, so that the communication chip test device 10 does not need to be equipped with a separate power module, further saving costs.

[0053] In a specific embodiment, Figure 5 As shown, the communication chip testing device 10 also includes a key control module 60 for modifying the frequency, carrier amplitude and modulation depth of the output signal of the FPGA module 12, and controlling the on or off of the signal output.

[0054] In a specific embodiment, Figure 5 As shown, the communication chip test device 10 further includes a self-test module 70 and a debug interface 80 . The self-test module 70 is used to test the function of the communication chip test device 10 itself, and the debug interface 80 is used to download the driver and program required by the FPGA module 12 .

[0055] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides a communication chip testing system, including the communication chip testing device 10 and the automatic testing equipment 20 in any of the above-mentioned embodiments.

[0056] The automatic test equipment is also used to receive a feedback signal generated by the communication chip according to the modulation signal, thereby verifying the signal receiving function of the communication chip 30 .

[0057] Specifically, if the signal receiving function of the communication chip 30 is normal, a corresponding feedback signal will be generated according to the received modulation signal. The automatic testing equipment 20 compares the information contained in the feedback signal with the expected information by comparing the waveform, frequency and other information of the modulation signal and the feedback signal. If it is confirmed that the two are consistent, it means that the signal receiving function of the communication chip 30 is normal.

[0058] The communication chip testing system provided by the embodiments of the present disclosure can reduce the requirements for the functions and performance of automatic testing equipment, and thus can perform efficient, fast, and low-cost functional testing on communication chips. It can reduce testing costs while reducing testing time, improving testing efficiency, and improving the reliability of test results.

[0059] In some embodiments, the communication chip testing system further includes a testing board, and one testing board is used to carry a plurality of communication chips 30 .

[0060] In some embodiments, multiple communication chips 30 are located on a test board, and the test board 13 includes a general receiving port and a general sending port. The ports of the multiple communication chips 30 for receiving signals are connected to the general receiving port and receive the above-mentioned modulated signal together; the ports of the multiple communication chips 30 for sending signals are connected to the general sending port and send the above-mentioned feedback signal together.

[0061] The system of the above embodiment includes the corresponding communication chip testing device in any of the above embodiments, and has the beneficial effects of the corresponding embodiment, which will not be described in detail here.

[0062] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a communication chip testing method, such as Figure 6 As shown, including:

[0063] S1. Use automatic test equipment to send a total control signal to the digital control module.

[0064] S2. Use the digital control module to send a test control signal to the FPGA module according to the total control signal.

[0065] S3. Use the FPGA module to generate a modulation signal according to the test control signal, and send the modulation signal to the communication chip.

[0066] The method provided by the embodiment of the present disclosure can reduce the requirements for the functions and performance of automatic testing equipment, and thus can perform efficient, fast, and low-cost functional testing on communication chips. It can reduce testing costs while reducing testing time, improving testing efficiency, and improving the reliability of test results.

[0067] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the above method.

[0068] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0069] The method of the above embodiment is implemented based on the corresponding communication chip testing device in any of the above embodiments, and has the beneficial effects of the corresponding embodiment, which will not be described in detail here.

[0070] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the existence of other identical elements in the process, method, article or device including the above elements.

[0071] The above are only specific embodiments of the present disclosure, which enable those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described above, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A communication chip testing device, characterized in that: It includes digital control module and FPGA module, including: The digital control module is used to receive a general control signal provided by an automatic test device, and send a test control signal to the FPGA module according to the general control signal; The FPGA module is used to generate a modulation signal according to the test control signal, and send the modulation signal to the communication chip.

2. The communication chip testing device according to claim 1, characterized in that: The communication chip is an NFC chip, and the modulated signal is used to test a data receiving function and / or a data sending function of the NFC chip.

3. The communication chip testing device according to claim 1, characterized in that: The digital control module includes a digital-to-analog converter and a transformer; The digital-to-analog converter is used to output an analog differential signal according to the total control signal; The transformer is used to convert the analog differential signal into the test control signal of single-ended output.

4. The communication chip testing device according to claim 1, characterized in that: The FPGA module is specifically used to generate the modulation signal having a target frequency, a target carrier amplitude and a target modulation depth according to the test control signal.

5. The communication chip testing device according to claim 1, characterized in that: It is also used to receive a test start signal provided by the automatic test equipment, and provide a start signal to the communication chip according to the test start signal.

6. The communication chip testing device according to claim 1, characterized in that: It also includes radio frequency interface and digital interface; The FPGA module is connected to the communication chip via the radio frequency interface; The digital control module is connected to the automatic test equipment via the digital interface.

7. The communication chip testing device according to claim 1, characterized in that: It also includes a power interface, which is connected to the automatic testing equipment and receives a power signal provided by the automatic testing equipment.

8. A communication chip testing system, characterized in that: A communication chip testing device comprising any one of claims 1 to 7 and the automatic testing equipment; The automatic test equipment is also used to receive a feedback signal generated by the communication chip according to the modulation signal.

9. The communication chip testing system according to claim 8, characterized in that: It also includes a test board, where one test board is used to carry a plurality of the communication chips.

10. A communication chip testing method, characterized in that: include: Sending a total control signal to a digital control module using automatic test equipment; Using the digital control module to send a test control signal to the FPGA module according to the total control signal; The FPGA module is used to generate a modulation signal according to the test control signal, and the modulation signal is sent to the communication chip.

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