A quantum-resistant cryptographic signature algorithm execution optimization method, system and electronic device

Abstract

The present invention relates to the field of quantum computer technology, and more particularly to a method, system, and electronic device for optimizing the execution of a quantum-resistant cryptographic signature algorithm. In this application, a first FIFO memory for storing a first random coefficient corresponding to a secret polynomial and a second FIFO memory for storing a second random coefficient corresponding to the secret polynomial are provided on computing hardware. By caching, the number of times the secret polynomial is written to and read from the storage unit is reduced. Furthermore, a third FIFO memory is provided to cache intermediate operation results. By caching, the number of times the operation results are written to and read from a BRAM is reduced, thereby reducing the additional power consumption caused by memory access. Furthermore, a BRAM for storing a public polynomial is provided. The combination of the two balances data execution speed. Furthermore, the data storage method changes the order in which data is executed, thereby balancing data execution speed overall and reducing the overall execution time required for the calculation.

Description

Technical Field

[0001] The present invention relates to the field of quantum computer technology, and in particular to a method, system, and electronic device for optimizing the execution of a quantum-resistant cryptographic signature algorithm. Background Art

[0002] Many secure communications devices and hardware infrastructure utilize classical cryptographic systems for security and confidentiality. However, with the advent of the quantum crisis, these devices are no longer secure, necessitating new cryptographic systems to resist attacks from quantum computers. Since the National Institute of Standards and Technology (NIST) in the United States launched a solicitation and transformation plan for post-quantum cryptographic algorithms in 2016, a growing number of post-quantum cryptographic algorithms have been proposed. For example, the Dilithium signature algorithm, a quantum-resistant signature algorithm, performs numerous steps in key pair generation, signing, and signature verification, requiring numerous polynomial and hash operations. Executing these polynomial calculations sequentially takes a considerable amount of time, making it difficult to rapidly generate keys and encrypt data. Therefore, optimizing polynomial calculations is crucial. Summary of the Invention

[0003] The present invention provides a method, system and electronic device for optimizing the execution of a quantum-resistant cryptographic signature algorithm, which are used to solve the problem that the existing quantum-resistant signature algorithm requires a large number of polynomial and hash operations, and it takes a long time to execute these polynomial calculations in sequence.

[0004] The embodiments of this specification provide a method for optimizing the execution of a quantum-resistant cryptographic signature algorithm, including:

[0005] Obtain the public polynomial and secret polynomial in the quantum-resistant cryptographic signature algorithm;

[0006] The public polynomial is sampled using a first sampling unit to obtain a polynomial matrix, and the secret polynomial is sampled using a second sampling unit to obtain a first random coefficient and a second random coefficient; the polynomial matrix is ​​stored in a BRAM (Block Random Access Memory), the first random coefficient is cached in a first FIFO (First In First Out) memory, and the second random coefficient is cached in a second FIFO memory;

[0007] Performing a number theory transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory using an NTT module to obtain a number theory transformation result;

[0008] Performing a point multiplication operation and a modular addition operation on the number theory transformation result and the polynomial matrix in the BRAM, and caching the operation result in a third FIFO memory; and performing an inverse number theory transformation on the operation result in the third FIFO memory to obtain polynomial coefficients on a finite field, where the polynomial coefficients on the finite field are used to determine a public key and a private key generated by a quantum-resistant cryptographic signature algorithm.

[0009] Optionally, obtaining a public polynomial and a secret polynomial in a quantum-resistant cryptographic signature algorithm includes:

[0010] Receive a random seed generated by a random number generator;

[0011] Perform hash operation on the received random seed to obtain a hash operation result;

[0012] Two Keccak operation units are used to perform Keccak operation on the random seeds of the public polynomial and the random seeds of the secret polynomial in the hash operation result respectively to obtain the public polynomial and the secret polynomial.

[0013] Optionally, storing the polynomial matrix in a BRAM includes:

[0014] The polynomial matrix is ​​cached in a fourth FIFO memory, and the BRAM stores the polynomial matrix in the fourth FIFO memory in a matrix order after the polynomial matrix is ​​transposed.

[0015] Optionally, the NTT (Number Theoretic Transform) module includes a first NTT unit and a second NTT unit; the number theoretic transformation result includes a first number theoretic transformation result and a second number theoretic transformation result;

[0016] The using the NTT module to perform a number theory transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory to obtain a number theory transformation result includes:

[0017] Performing a number-theoretic transformation on the first random coefficient in the first FIFO memory using a first NTT unit to obtain a first number-theoretic transformation result, and caching the first number-theoretic transformation result in a fifth FIFO memory;

[0018] A second NTT unit is used to perform a number theory transformation on the second random coefficient in the second FIFO memory to obtain a second number theory transformation result.

[0019] Optionally, performing a point multiplication operation and a modular addition operation on the number theory transformation result and the polynomial matrix in the BRAM, and caching the operation result in a third FIFO memory, includes:

[0020] Performing a dot multiplication operation on the first number theory transformation result in the fifth FIFO memory and the polynomial matrix in the BRAM to obtain a dot multiplication operation result;

[0021] Perform a modular addition operation on the dot product operation result and the second number theory transformation result to obtain the operation result, and cache the operation result in a third FIFO memory.

[0022] Optionally, after obtaining the polynomial coefficients over the finite field, the method further includes:

[0023] The polynomial coefficients over the finite field are cached in a sixth FIFO memory.

[0024] Optionally, the polynomial coefficients over the finite field are used to determine the public key and private key generated by the quantum-resistant cryptographic signature algorithm, including:

[0025] Decomposing the polynomial coefficients in the sixth FIFO memory by a coefficient decomposition unit to obtain first polynomial sub-coefficients and second polynomial sub-coefficients;

[0026] Encoding the second polynomial sub-coefficients and the random seed of the public polynomial to obtain a public key of a quantum-resistant cryptographic signature algorithm;

[0027] Performing a hash operation on the public key to obtain a hash value;

[0028] The hash value, the random seed of the public polynomial, the key in the hash operation result, the first random coefficient, the second random coefficient, and the first polynomial sub-coefficient are encoded to obtain a private key of the quantum-resistant cryptographic signature algorithm, and the public key and the private key are bit-width converted using a seventh FIFO memory to store them in the BRAM.

[0029] Optionally, the method further includes:

[0030] When the first NTT unit and / or the second NTT unit is in an idle state, and there is data to be processed that requires number theoretic transformation and is not generated by hash operation, the first NTT unit and / or the second NTT unit in the idle state is used to perform number theoretic transformation on the data to be processed, and the number theoretic transformation result is stored in the BRAM.

[0031] Optionally, the method further includes:

[0032] When the polynomial coefficients on the finite field are polynomial coefficients generated during the signing process, a checking unit is used to perform a norm check on the polynomial coefficients. When the norm check is qualified, the polynomial coefficients meet the requirements.

[0033] The embodiments of this specification also provide a system for optimizing the execution of a quantum-resistant cryptographic signature algorithm, including:

[0034] A hash operation unit, used to obtain the public polynomial and secret polynomial in the quantum-resistant cryptographic signature algorithm;

[0035] A first sampling unit is configured to sample the common polynomial to obtain a polynomial matrix; and store the polynomial matrix in a polynomial matrix area in the BRAM;

[0036] a second sampling unit, configured to sample the secret polynomial to obtain a first random coefficient and a second random coefficient; the first random coefficient is cached in a first FIFO memory, and the second random coefficient is cached in a second FIFO memory;

[0037] An NTT module, configured to perform a number theory transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory using the NTT module to obtain a number theory transformation result;

[0038] A multiplication-addition operation unit is configured to perform a point multiplication operation and a modular addition operation on the number-theoretic transformation result and the polynomial matrix in the BRAM, and cache the operation result in a third FIFO memory; and perform an inverse number-theoretic transformation on the operation result in the third FIFO memory to obtain polynomial coefficients over a finite field, where the polynomial coefficients over the finite field are used to determine a public key and a private key generated by a quantum-resistant cryptographic signature algorithm.

[0039] An electronic device includes a memory and a processor, wherein the memory stores computer instructions, and the processor is configured to run the computer instructions to execute the method described above.

[0040] A storage medium stores computer instructions, wherein the computer instructions are configured to execute the above method when executed.

[0041] The beneficial effect is that the present application provides a first FIFO memory for storing the first random coefficient corresponding to the secret polynomial and a second FIFO memory for storing the second random coefficient corresponding to the secret polynomial on the computing hardware. Through caching, the number of times the secret polynomial is written to and read from the storage unit is reduced. In addition, a third FIFO memory is provided to cache intermediate calculation results, which reduces the number of times the calculation results are written to and read from the BRAM through caching. Furthermore, a BRAM for storing the public polynomial is provided. The combination of these two balances data execution speed. This data storage arrangement not only reduces the number of data access and storage times, reducing the additional power consumption caused by memory access, but also reduces the high latency problem between modules. Furthermore, the data storage method changes the order in which data is executed, overall balancing the data execution speed and reducing the overall execution time required for the calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0043] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0044] Figure 1 A flowchart of a method for optimizing the execution of a quantum-resistant cryptographic signature algorithm provided in an embodiment of this specification;

[0045] Figure 2 A hardware architecture diagram for optimizing the execution of a quantum-resistant cryptographic signature algorithm provided in an embodiment of this specification;

[0046] Figure 3 A schematic diagram of the structure of a quantum-resistant cryptographic signature algorithm execution optimization system provided in an embodiment of this specification;

[0047] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this specification;

[0048] Figure 5 A schematic diagram of a computer-readable medium provided in accordance with an embodiment of this specification. DETAILED DESCRIPTION

[0049] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0050] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0051] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0052] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0053] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0054] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0055] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0056] Reference Figure 1 A schematic diagram of the principle of a method for optimizing execution of a quantum-resistant cryptographic signature algorithm provided in an embodiment of this specification includes: S101: obtaining a public polynomial and a secret polynomial in the quantum-resistant cryptographic signature algorithm; S102: using a first sampling unit to sample the public polynomial to obtain a polynomial matrix, and using a second sampling unit to sample the secret polynomial to obtain a first random coefficient and a second random coefficient; and storing the polynomial matrix in a BRAM, caching the first random coefficient in a first FIFO memory, and caching the second random coefficient in a second FIFO memory.

[0057] In an optional embodiment, in the process of generating a public key and a private key by a quantum-resistant cryptographic signature algorithm, taking the calculation process of A*s1+s2 in the key generation process as an example, first, a random seed generated by a random number generator is received, and then a hash operation is performed on the received random seed to obtain a hash operation result, wherein the hash operation result includes a random seed ρ of a public polynomial, a random seed ρ′ of a secret polynomial, and a key K for the quantum cryptographic signature algorithm. Afterwards, two Keccak operation units are used to perform Keccak operations on the random seed ρ of the public polynomial and the random seed ρ′ of the secret polynomial in the hash operation result, respectively, to obtain a public polynomial and a secret polynomial. Then, a first sampling unit is used to sample the public polynomial to obtain a polynomial matrix A, and a second sampling unit is used to sample the secret polynomial to obtain a first random coefficient s1 and a second random coefficient s2; as shown in FIG. Figure 2 As shown, the polynomial matrix A is finally stored in the polynomial matrix area of ​​the BRAM, the first random coefficient s1 is cached in the first FIFO memory, and the second random coefficient s2 is cached in the second FIFO memory; a first FIFO memory for storing the first random coefficient s1 corresponding to the secret polynomial and a second FIFO memory for storing the second random coefficient s2 corresponding to the secret polynomial are set on the computing hardware. Through the caching method, the number of times the secret polynomial is written into the storage unit and read from the storage unit is reduced.

[0058] S103: Use the NTT module to perform a number theoretic transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory to obtain a number theoretic transformation result; S104: Perform a point multiplication and a modular addition operation on the number theoretic transformation result and the polynomial matrix in the BRAM, and then cache the operation result in the third FIFO memory; and perform an inverse number theoretic transformation on the operation result in the third FIFO memory to obtain the polynomial coefficients on the finite field. The polynomial coefficients on the finite field are used to determine the public key and private key generated by the quantum-resistant cryptographic signature algorithm.

[0059] In an alternative embodiment, Figure 2 As shown, the NTT module is used to perform number theory transformation on the first random coefficient s1 and the second random coefficient s2, that is, to perform positive transformation on s1 and s2 to obtain the number theory transformation result. Then, the number theory transformation result is subjected to point multiplication and modular addition operations with the polynomial matrix A in the polynomial matrix area in the BRAM. After that, as shown in FIG. Figure 3As shown, the calculation results are cached in a third FIFO memory; and the INTT unit is used to perform an inverse number theory transformation on the calculation results in the third FIFO memory to obtain the polynomial coefficient t on a finite field. The polynomial coefficient t on the finite field is used to determine the public key and private key generated by the quantum-resistant cryptographic signature algorithm. A third FIFO memory is set up to cache intermediate calculation results. The caching method reduces the number of times the calculation results are written to and read from the BRAM. At the same time, a BRAM is set up to store the public polynomial. The combination of the two balances the data execution speed. By using the above data storage configuration, on the one hand, the number of data access and storage times is reduced, reducing the additional power consumption caused by memory access. On the other hand, the high latency problem between modules is reduced. Furthermore, the data storage method changes the order in which data is executed, which overall balances the data execution speed and reduces the overall execution time required for the calculation.

[0060] Specifically, the polynomial coefficients on the finite field are used to determine the public key and the private key generated by the quantum-resistant cryptographic signature algorithm, including: using a coefficient decomposition unit to perform coefficient decomposition on the polynomial coefficients in the sixth FIFO memory to obtain a first polynomial sub-coefficient and a second polynomial sub-coefficient; using a data processing unit to encode the second polynomial sub-coefficient and the random seed of the public polynomial to obtain a public key of the quantum-resistant cryptographic signature algorithm; performing a hash operation on the public key to obtain a hash value; using the data processing unit to encode the hash value, the random seed of the public polynomial, the key in the hash operation result, the first random coefficient, the second random coefficient, and the first polynomial sub-coefficient to obtain a private key of the quantum-resistant cryptographic signature algorithm, and using a seventh FIFO memory to perform bit width conversion on the public key and the private key for storage in the BRAM.

[0061] In an alternative embodiment, Figure 2As shown, the coefficient decomposition unit is used to decompose the high and low bits of the polynomial coefficients in the sixth FIFO memory to obtain the first polynomial sub-coefficient t0 and the second polynomial sub-coefficient t1; wherein, the high and low bit decomposition refers to the process of decomposing a numerical value into its high and low bits. For example, for a 32-bit integer, the low 16 bits can be represented as the low bit part, and the high 16 bits can be represented as the high bit part; then, the second polynomial sub-coefficient t1 and the random seed ρ of the public polynomial are encoded, that is, (ρ, t1) is encoded to obtain the public key pk of the quantum-resistant cryptographic signature algorithm, and then the public key pk is hashed to obtain the hash value tr. Finally, the hash value tr, a random seed ρ of the public polynomial, a key K in the hash operation result, a first random coefficient s1, a second random coefficient s2, and a first polynomial sub-coefficient t0 are encoded, that is, (ρ, K, tr, s1, s2, t0) is encoded to obtain a private key sk of the quantum-resistant cryptographic signature algorithm, and the public key pk and the private key sk are bit-width converted using the seventh FIFO memory, and the public key pk and the private key sk after the bit-width conversion are written into the address corresponding to the key data area in the BRAM. When there is data that needs to be signed and verified using the quantum-resistant signature algorithm, the public key pk and the private key sk can be directly extracted from the address corresponding to the key data area in the BRAM for use. By using the seventh FIFO memory to achieve the bit-width conversion of the public key pk and the private key sk, it is ensured that the public key pk and the private key sk are stored in the key data area in the BRAM according to the set bit width, which facilitates data storage and transmission.

[0062] In an alternative embodiment, Figure 2 As shown, the polynomial matrix is ​​cached in a fourth FIFO memory, and the BRAM stores the polynomial matrix in the fourth FIFO memory in the matrix order after the transposition of the polynomial matrix. By setting the fourth FIFO memory, the pipeline speed of the polynomial matrix A is balanced, so that each module and / or unit does not generate a large delay when calculating the polynomial matrix A.

[0063] Optionally, the NTT module includes a first NTT unit and a second NTT unit; the number theoretic transformation result includes a first number theoretic transformation result and a second number theoretic transformation result; the use of the NTT module to perform a number theoretic transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory to obtain a number theoretic transformation result includes: using the first NTT unit to perform a number theoretic transformation on the first random coefficient in the first FIFO memory to obtain a first number theoretic transformation result, and caching the first number theoretic transformation result to a fifth FIFO memory; using the second NTT unit to perform a number theoretic transformation on the second random coefficient in the second FIFO memory to obtain a second number theoretic transformation result.

[0064] Optionally, performing a point multiplication operation and a modular addition operation on the number theory transformation result and the polynomial matrix in the BRAM, and caching the operation result in a third FIFO memory, includes:

[0065] In an alternative embodiment, Figure 2 As shown, two NTT units are used to perform number-theoretic transformations on the first random coefficient s1 in a first FIFO memory and the second random coefficient s2 in a second FIFO memory, respectively, ensuring that the two random coefficients are processed separately to avoid data confusion during subsequent point multiplication and modular addition operations. A fifth FIFO memory is also provided to cache the result of the first number-theoretic transformation. Then, a point multiplication operation is performed on the first number-theoretic transformation result in the fifth FIFO memory and the polynomial matrix in the BRAM to obtain the point multiplication result. Finally, a modular addition operation is performed on the point multiplication result and the second number-theoretic transformation result to obtain the operation result, which is then cached in a third FIFO memory. By caching the second number-theoretic transformation result and retrieving the polynomial matrix A from the polynomial matrix area in the BRAM, the addition of memory changes the order of data execution, reduces the overall execution time required for the calculation, and reduces the high latency problem between modules and / or units.

[0066] Optionally, after obtaining the polynomial coefficients over the finite field, the method further includes: caching the polynomial coefficients over the finite field into a sixth FIFO memory.

[0067] In an alternative embodiment, Figure 2 As shown, by setting the sixth FIFO memory to cache the polynomial coefficients on the finite field, each module and / or unit will not generate a large delay during the polynomial calculation, effectively balancing the data execution speed.

[0068] Optionally, the method further includes: when the first NTT unit and / or the second NTT unit is in an idle state, and there is data to be processed that requires number theoretic transformation and is not generated by hash operation, using the first NTT unit and / or the second NTT unit in the idle state to perform number theoretic transformation on the data to be processed, and storing the number theoretic transformation result in the BRAM.

[0069] In an alternative embodiment, Figure 2As shown, when there is data to be processed that requires number theoretic transformation and is not generated by hash operations, if the first NTT unit and / or the second NTT unit is in an idle state, the parallel processing method between modules is used to allow the first NTT unit and / or the second NTT unit to process the data to be processed of the current external input, and the processing results are written to the operation data area of ​​the BRAM. For example, during the signing process, it is necessary to decompress the private key to obtain the various polynomial coefficients therein, and then perform NTT transformation on the polynomial coefficients therein. At this time, the idle first NTT unit and / or the second NTT unit can be used to perform NTT transformation on these polynomials. The above scheduling method can better utilize each NTT unit, making the execution process of the entire algorithm more compact, and preventing a large delay in a unit or module, that is, avoiding the decrease in the execution speed of the overall quantum-resistant cryptographic signature algorithm due to the delay of a unit or module.

[0070] Optionally, the method further includes: when the polynomial coefficients on the finite field are polynomial coefficients generated during the signing process, using a checking unit to perform a norm check on the polynomial coefficients; when the norm check is qualified, the polynomial coefficients meet the requirements.

[0071] In an optional embodiment, the checking unit is responsible for performing a norm check on a specific polynomial. For example, during the signing process using a quantum-resistant signature algorithm, the checking unit performs a norm check on the specific polynomial coefficient z. If any coefficient fails the check, a fail signal is returned to the state machine, and the signing process is repeated. If the norm check passes, the specific polynomial coefficient z meets the requirements and can be used for signing using the quantum-resistant cryptographic signature algorithm. Simultaneously, the polynomial coefficients over the finite field are cached in a sixth FIFO memory, which can balance the checking unit's checking time during the norm check process and improve the checking unit's execution efficiency.

[0072] In an optional embodiment, the entire polynomial matrix A may be written into the polynomial matrix area of ​​the BRAM in advance, so that the process of calculating the polynomial matrix A does not need to be repeated, thereby achieving the effect of increasing storage area in exchange for data calculation execution speed.

[0073] This application provides a first FIFO memory for storing the first random coefficient corresponding to the secret polynomial and a second FIFO memory for storing the second random coefficient corresponding to the secret polynomial on the computing hardware. By caching, the number of times the secret polynomial is written to and read from the storage unit is reduced. Furthermore, a third FIFO memory is provided to cache intermediate calculation results, which reduces the number of times the calculation results are written to and read from the BRAM. Furthermore, a BRAM for storing the public polynomial is provided. These two combined methods balance data execution speed. This data storage arrangement reduces the number of data access and storage times, reducing the additional power consumption caused by memory access, and reduces the high latency between modules. Furthermore, the data storage method changes the order in which data is executed, balancing data execution speed overall and reducing the overall execution time required for the calculation.

[0074] Reference Figure 3 The embodiments of this specification also provide a system for optimizing the execution of a quantum-resistant cryptographic signature algorithm, including:

[0075] Hash operation unit 201, used to obtain the public polynomial and secret polynomial in the quantum-resistant cryptographic signature algorithm;

[0076] A first sampling unit 202 is configured to sample the common polynomial to obtain a polynomial matrix; and store the polynomial matrix in a polynomial matrix area of ​​a BRAM;

[0077] A second sampling unit 203 is configured to sample the secret polynomial to obtain a first random coefficient and a second random coefficient; the first random coefficient is cached in a first FIFO memory, and the second random coefficient is cached in a second FIFO memory;

[0078] An NTT module 204 is configured to perform a number theory transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory using an NTT module to obtain a number theory transformation result;

[0079] The multiplication and addition unit 205 is configured to perform a point multiplication and a modular addition operation on the number theory transformation result and the polynomial matrix in the BRAM, and cache the operation result in a third FIFO memory; and perform an inverse number theory transformation on the operation result in the third FIFO memory to obtain polynomial coefficients over a finite field, where the polynomial coefficients over the finite field are used to determine the public key and private key generated by the quantum-resistant cryptographic signature algorithm.

[0080] Optionally, the hash operation unit 201 includes:

[0081] A random seed receiving unit, configured to receive a random seed generated by a random number generator;

[0082] A hash operation subunit, configured to perform a hash operation on the received random seed to obtain a hash operation result;

[0083] The Keccak operation unit is used to use two Keccak operation units to perform Keccak operation on the random seed of the public polynomial and the random seed of the secret polynomial in the hash operation result respectively to obtain the public polynomial and the secret polynomial.

[0084] Optionally, the first sampling unit 202 includes:

[0085] The first cache unit is configured to cache the polynomial matrix into a fourth FIFO memory, and the BRAM stores the polynomial matrix in the fourth FIFO memory in a matrix order after the polynomial matrix is ​​transposed.

[0086] Optionally, the NTT module includes a first NTT unit and a second NTT unit; the number theory transformation result includes a first number theory transformation result and a second number theory transformation result; the NTT module 204 includes:

[0087] a first number theory transformation unit, configured to perform a number theory transformation on the first random coefficient in the first FIFO memory using the first NTT unit to obtain a first number theory transformation result, and cache the first number theory transformation result in a fifth FIFO memory;

[0088] The second number theory transformation unit is used to use the second NTT unit to perform number theory transformation on the second random coefficient in the second FIFO memory to obtain a second number theory transformation result.

[0089] Optionally, the multiplication and addition unit 205 includes:

[0090] a point multiplication operation unit, configured to perform a point multiplication operation on the first number theory transformation result in the fifth FIFO memory and the polynomial matrix in the BRAM to obtain a point multiplication operation result;

[0091] A modular addition operation unit is used to perform a modular addition operation on the point product operation result and the second number theory transformation result to obtain the operation result, and cache the operation result in a third FIFO memory.

[0092] Optionally, after obtaining the polynomial coefficients on the finite field, the apparatus further includes:

[0093] The second cache unit is used to cache the polynomial coefficients over the finite field into a sixth FIFO memory.

[0094] Optionally, the multiplication and addition unit 205 further includes:

[0095] a coefficient decomposition unit, configured to perform coefficient decomposition on the polynomial coefficients in the sixth FIFO memory using the coefficient decomposition unit to obtain first polynomial sub-coefficients and second polynomial sub-coefficients;

[0096] A first encoding unit is configured to encode the second polynomial sub-coefficients and the random seed of the public polynomial to obtain a public key of a quantum-resistant cryptographic signature algorithm;

[0097] A hash value calculation unit, configured to perform a hash operation on the public key to obtain a hash value;

[0098] A second encoding unit is configured to encode the hash value, the random seed of the public polynomial, the key in the hash operation result, the first random coefficient, the second random coefficient, and the first polynomial sub-coefficient to obtain a private key of the quantum-resistant cryptographic signature algorithm, and perform bit width conversion on the public key and the private key using a seventh FIFO memory for storage in the BRAM.

[0099] Optionally, the device further includes:

[0100] The processing unit for processing data to be processed is used to use the first NTT unit and / or the second NTT unit in the idle state to perform number theoretic transformation on the data to be processed when the first NTT unit and / or the second NTT unit are in an idle state and there is data to be processed that requires number theoretic transformation and is not generated by hash operation, and store the number theoretic transformation result in the BRAM.

[0101] Optionally, the device further includes:

[0102] The norm checking unit is used to perform a norm check on the polynomial coefficients on the finite field when the polynomial coefficients are the polynomial coefficients generated in the signing process. When the norm check is qualified, the polynomial coefficients meet the requirements.

[0103] Regarding the system in the above embodiment, the process of executing the operation in each step has been described in detail in the embodiment of the method, and will not be elaborated here.

[0104] Based on the same inventive concept, an embodiment of this specification also provides an electronic device.

[0105] The following describes an electronic device embodiment of the present invention, which can be considered a specific physical implementation of the method and apparatus embodiments of the present invention described above. Details described in the electronic device embodiment of the present invention should be considered supplementary to the above-mentioned method or apparatus embodiments; details not disclosed in the electronic device embodiment of the present invention can be implemented with reference to the above-mentioned method or apparatus embodiments.

[0106] Reference Figure 4 This is a schematic diagram of the structure of an electronic device provided in the embodiment of this specification. Figure 4 The electronic device 300 according to this embodiment of the present invention will be described. Figure 4 The electronic device 300 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0107] like Figure 4 As shown, electronic device 300 is implemented as a general-purpose computing device. Components of electronic device 300 may include, but are not limited to, at least one processing unit 310, at least one storage unit 320, a bus 330 connecting various device components (including storage unit 320 and processing unit 310), and a display unit 340.

[0108] The storage unit stores program codes that can be executed by the processing unit 310, so that the processing unit 310 performs the steps according to various exemplary embodiments of the present invention described in the above processing method section of this specification. For example, the processing unit 310 can perform the following steps: Figure 1 Steps shown.

[0109] The storage unit 320 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 3201 and / or a cache memory unit 3202 , and may further include a read-only memory unit (ROM) 3203 .

[0110] The storage unit 320 may also include a program / utility 3204 having a set (at least one) of program modules 3205, such program modules 3205 including but not limited to: operating means, one or more application programs, other program modules and program data, each of which or some combination may include an implementation of a network environment.

[0111] Bus 330 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0112] The electronic device 300 may also communicate with one or more external devices 400 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device 300, and / or any device that enables the electronic device 300 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed through an input / output (I / O) interface 350. Furthermore, the electronic device 300 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 360. The network adapter 360 may communicate with other modules of the electronic device 300 through the bus 330. It should be understood that although Figure 4 Not shown, other hardware and / or software modules may be used in conjunction with the electronic device 300, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID devices, tape drives, and data backup storage devices.

[0113] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the exemplary embodiments described in the present invention can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solution according to the embodiment of the present invention can be embodied in the form of a software product, which can be stored in a computer-readable storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, or a network device, etc.) to execute the above method according to the present invention. When the computer instructions are executed by a data processing device, the computer-readable medium is enabled to implement the above method of the present invention, that is: Figure 1 The method shown.

[0114] Reference Figure 5 A schematic diagram of a computer-readable medium provided in accordance with an embodiment of this specification.

[0115] accomplish Figure 1The computer instructions of the illustrated method can be stored on one or more computer-readable media. The computer-readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor device, device or component, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0116] The computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein the readable program code is carried. The data signal propagated may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution device, device, or component. The program code contained on the readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0117] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0118] In summary, the present invention can be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that general data processing equipment such as a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the embodiments of the present invention. The present invention can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for executing a part or all of the methods described herein. Such a program for implementing the present invention can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0119] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the present invention is not inherently related to any specific computer, virtual device, or electronic device, and various general-purpose devices can also implement the present invention. The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

[0120] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0121] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A method for optimizing the execution of a quantum-resistant cryptographic signature algorithm, characterized in that: include: Obtain the public polynomial and secret polynomial in the quantum-resistant cryptographic signature algorithm; Using a first sampling unit to sample the public polynomial to obtain a polynomial matrix, and using a second sampling unit to sample the secret polynomial to obtain a first random coefficient and a second random coefficient; and storing the polynomial matrix in a BRAM, caching the first random coefficient in a first FIFO memory, and caching the second random coefficient in a second FIFO memory; Performing a number theory transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory using an NTT module to obtain a number theory transformation result; Performing a point multiplication operation and a modular addition operation on the number theory transformation result and the polynomial matrix in the BRAM, and caching the operation result in a third FIFO memory; and performing an inverse number theory transformation on the operation result in the third FIFO memory to obtain polynomial coefficients on a finite field, where the polynomial coefficients on the finite field are used to determine a public key and a private key generated by a quantum-resistant cryptographic signature algorithm.

2. The method according to claim 1, wherein The method of obtaining the public polynomial and the secret polynomial in the quantum-resistant cryptographic signature algorithm includes: Receive a random seed generated by a random number generator; Perform hash operation on the received random seed to obtain a hash operation result; Two Keccak operation units are used to perform Keccak operation on the random seeds of the public polynomial and the random seeds of the secret polynomial in the hash operation result respectively to obtain the public polynomial and the secret polynomial.

3. The method according to claim 1, wherein Storing the polynomial matrix in BRAM includes: The polynomial matrix is ​​cached in a fourth FIFO memory, and the BRAM stores the polynomial matrix in the fourth FIFO memory in a matrix order after the polynomial matrix is ​​transposed.

4. The method according to claim 1, wherein The NTT module includes a first NTT unit and a second NTT unit; the number theory transformation result includes a first number theory transformation result and a second number theory transformation result; The using the NTT module to perform a number theory transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory to obtain a number theory transformation result includes: Performing a number theory transformation on the first random coefficient in the first FIFO memory using a first NTT unit to obtain a first number theory transformation result, and caching the first number theory transformation result in a fifth FIFO memory; A second NTT unit is used to perform a number theory transformation on the second random coefficient in the second FIFO memory to obtain a second number theory transformation result.

5. The method according to claim 4, wherein The step of performing a point multiplication operation and a modular addition operation on the number theory transformation result and the polynomial matrix in the BRAM, and caching the operation result in a third FIFO memory, includes: Performing a dot multiplication operation on the first number theory transformation result in the fifth IFFO memory and the polynomial matrix in the BRAM to obtain a dot multiplication operation result; Perform a modular addition operation on the dot product operation result and the second number theory transformation result to obtain the operation result, and cache the operation result in a third FIFO memory.

6. The method according to claim 2, wherein After obtaining the polynomial coefficients on the finite field, the method further includes: The polynomial coefficients over the finite field are cached in a sixth FIFO memory.

7. The method according to claim 6, wherein The polynomial coefficients on the finite field are used to determine the public key and private key generated by the quantum-resistant cryptographic signature algorithm, including: Decomposing the polynomial coefficients in the sixth FIFO memory by a coefficient decomposition unit to obtain first polynomial sub-coefficients and second polynomial sub-coefficients; Encoding the second polynomial sub-coefficients and the random seed of the public polynomial to obtain a public key of a quantum-resistant cryptographic signature algorithm; Performing a hash operation on the public key to obtain a hash value; The hash value, the random seed of the public polynomial, the key in the hash operation result, the first random coefficient, the second random coefficient, and the first polynomial sub-coefficient are encoded to obtain a private key of the quantum-resistant cryptographic signature algorithm, and the public key and the private key are bit-width converted using a seventh FIFO memory to store them in the BRAM.

8. The method according to claim 3, wherein The method further comprises: When the first NTT unit and / or the second NTT unit is in an idle state, and there is data to be processed that requires number theoretic transformation and is not generated by hash operation, the first NTT unit and / or the second NTT unit in the idle state is used to perform number theoretic transformation on the data to be processed, and the number theoretic transformation result is stored in the BRAM.

9. The method according to claim 1, wherein The method further comprises: When the polynomial coefficients on the finite field are polynomial coefficients generated during the signing process, a checking unit is used to perform a norm check on the polynomial coefficients. When the norm check is qualified, the polynomial coefficients meet the requirements.

10. A quantum-resistant cryptographic signature algorithm execution optimization system, characterized in that ,include: A hash operation unit, used to obtain the public polynomial and secret polynomial in the quantum-resistant cryptographic signature algorithm; A first sampling unit is configured to sample the common polynomial to obtain a polynomial matrix; and store the polynomial matrix in a polynomial matrix area in the BRAM; a second sampling unit, configured to sample the secret polynomial to obtain a first random coefficient and a second random coefficient; the first random coefficient is cached in a first FIFO memory, and the second random coefficient is cached in a second FIFO memory; An NTT module, configured to perform a number theory transformation on the first random coefficient in the first FIFO memory and the second random coefficient in the second FIFO memory using the NTT module to obtain a number theory transformation result; A multiplication-addition operation unit is configured to perform a point multiplication operation and a modular addition operation on the number-theoretic transformation result and the polynomial matrix in the BRAM, and cache the operation result in a third FIFO memory; and perform an inverse number-theoretic transformation on the operation result in the third FIFO memory to obtain polynomial coefficients over a finite field, where the polynomial coefficients over the finite field are used to determine a public key and a private key generated by a quantum-resistant cryptographic signature algorithm.

11. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores computer instructions, and the processor is configured to execute the computer instructions to perform the method according to any one of claims 1 to 9.

12. A storage medium, characterized in that: The storage medium stores computer instructions, which are configured to execute the method according to any one of claims 1 to 9 when executed.

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