Anti-quantum cryptographic algorithm FPGA (Field Programmable Gate Array) structure and processing method

Abstract

The invention provides an FPGA structure of an anti-quantum cryptographic algorithm and a processing method, and relates to the technical field of quantum information security. The structure comprises the following steps: an XDMA module obtains a quantum cryptography data packet from a host end according to a DMA descriptor queue; the logic control module is connected with the XDMA module and the logic anti-quantum cryptography algorithm module, and sends a control signal to the logic anti-quantum cryptography algorithm module according to the received quantum operation request and operation instruction; the XDMA module is connected with the storage controller to store the quantum cryptography data packet into a storage mapping area; the logic anti-quantum cryptographic algorithm module is connected with the storage controller to obtain operation data from the storage mapping area, executes an operation instruction on the operation data to obtain a quantum operation result, and stores the quantum operation result to the storage mapping area; and the XDMA module obtains the quantum operation result from the storage mapping area and sends the quantum operation result to the host end. According to the method, the anti-quantum cryptography algorithm requirements of high security and efficient calculation can be met.

Description

Technical Field

[0001] The present application relates to the field of quantum information security technology, and more specifically, to an FPGA structure and processing method for a quantum cryptographic algorithm. Background Art

[0002] With the rapid development of quantum computing technology, traditional public key cryptographic algorithms such as ECC (Elliptic Curve Cryptography) and RSA (Rivest-Shamir-Adleman) are facing unprecedented security threats. Quantum computers can use Shor's algorithm to crack algorithms that rely on integer factorization and discrete logarithm problems in polynomial time, thus seriously weakening the security of existing encryption systems.

[0003] To meet this challenge, the global cryptography community is actively exploring post-quantum cryptography (PQC) algorithms. Among them, the Modular Lattice-based Key Encapsulation Mechanism (ML-KEM) algorithm based on the Modular Learning With Errors (MLWE) problem has become one of the standard post-quantum cryptography schemes recommended by the National Institute of Standards and Technology (NIST) of the United States due to its security and efficiency in the field of key exchange.

[0004] At present, although there are software implementations of the ML-KEM algorithm, there are significant deficiencies in security, processing speed and efficiency. Especially when dealing with quantum computing threats, software implementations are difficult to provide sufficient protection. Summary of the invention

[0005] The purpose of this application is to provide an FPGA structure and processing method for a quantum-resistant cryptographic algorithm to address the deficiencies in the above-mentioned prior art, so as to achieve the requirements of a quantum-resistant cryptographic algorithm with high security and efficient computing through a hardware FPGA structure.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides an FPGA structure of an anti-quantum cryptographic algorithm, the FPGA structure comprising: a logic control module, an XDMA module, a storage controller, and a logic anti-quantum cryptographic algorithm module;

[0008] The XDMA module is connected to the host side through the PCIe interface, and is used to receive the DMA descriptor queue and the quantum operation request sent by the host side, so that the XDMA module obtains the quantum cryptographic data packet corresponding to the quantum operation request from the memory of the host side according to the DMA descriptor queue;

[0009] The logic control module is connected to the XDMA module and the logic anti-quantum cryptographic algorithm module, and is used to receive the quantum operation request and the operation instruction of the quantum cryptographic data packet from the XDMA module, and send a control signal corresponding to the operation instruction to the logic anti-quantum cryptographic algorithm module according to the quantum operation request and the operation instruction;

[0010] The XDMA module is also connected to the storage controller, and is used to store the quantum cryptography data packet into a storage mapping area in the external memory through the storage controller;

[0011] The logic anti-quantum cryptographic algorithm module is also connected to the storage controller, and is used to obtain the operation data of the quantum cryptographic data packet from the storage mapping area through the storage controller according to the control signal corresponding to the operation instruction, and execute the operation instruction on the operation data to obtain the quantum operation result, and store the quantum operation result in the storage mapping area through the storage controller;

[0012] The XDMA module is also used to obtain the quantum operation result from the storage mapping area through the storage controller, and send the quantum operation result to the host end.

[0013] Optionally, the FPGA structure further includes: a logic instruction detection module and a logic instruction parsing module;

[0014] The logic instruction detection module and the logic instruction parsing module are connected between the XDMA module and the logic control module, and the logic instruction detection module is used to detect the quantum cryptography data packet and obtain instruction data from the operation instruction field of the quantum cryptography data packet;

[0015] The logic instruction parsing module is used to parse the instruction data to obtain the operation instruction.

[0016] Optionally, the FPGA structure further includes: a logic arbitration module;

[0017] The logic arbitration module is respectively connected to the XDMA module, the logic anti-quantum cryptographic algorithm module and the storage controller, and is used to determine the request processing order when receiving data read and write requests from the XDMA module and the logic anti-quantum cryptographic algorithm module at the same time.

[0018] Optionally, the FPGA structure further includes: a logic timing module;

[0019] The logic timing module is respectively connected to the logic arbitration module and the logic anti-quantum cryptographic algorithm module, and is used to perform time domain conversion on the operation data or the quantum operation result.

[0020] Optionally, the FPGA structure further includes: a logic protocol conversion module;

[0021] The logic protocol conversion module is connected to the logic arbitration module and the logic anti-quantum cryptographic algorithm module respectively, and is used to perform data format conversion between the logic arbitration module and the logic anti-quantum cryptographic algorithm module.

[0022] Optionally, the FPGA structure further includes: an input first-in first-out module;

[0023] The input first-in-first-out module is respectively connected to the logic timing module and the logic anti-quantum cryptographic algorithm module, and is used to cache the operation data.

[0024] Optionally, the FPGA structure further includes: an output first-in-first-out module;

[0025] The output first-in-first-out module is respectively connected to the logic timing module and the logic anti-quantum cryptographic algorithm module, and is used to cache the quantum operation result.

[0026] Optionally, the FPGA structure further includes: a random number chip driving module and a random number first-in-first-out module;

[0027] The random number chip driving module is externally connected to a random number chip, and the random number chip driving module is also connected to the logic timing module to send the random number obtained by the random number chip to the logic timing module for time domain conversion;

[0028] The random number first-in-first-out module is connected to the logic timing module and the anti-quantum cryptographic algorithm module respectively, and is used for caching the random number and then sending it to the anti-quantum cryptographic algorithm module.

[0029] Optionally, the logic anti-quantum cryptographic algorithm module includes: a hash module, a binomial distribution sampling module, a number theory transformation sampling module, a number theory transformation module and a polynomial multiplication module;

[0030] The hash module is respectively connected to the binomial distribution sampling module and the number theory transformation sampling module, the binomial distribution sampling module is also connected to the number theory transformation module, the number theory transformation sampling module is also connected to the polynomial multiplication module, the number theory transformation module is also connected to the polynomial multiplication module, and the polynomial multiplication module is used to output the quantum operation result.

[0031] In a second aspect, an embodiment of the present application further provides a method for processing a quantum-resistant cryptographic algorithm, which is applied to an FPGA structure of a quantum-resistant cryptographic algorithm as described in any one of the first aspects, and the method includes:

[0032] The XDMA module receives the DMA descriptor queue and quantum operation request sent by the host;

[0033] The XDMA module obtains a quantum cryptography data packet from the memory of the host end according to the DMA descriptor queue, and stores the quantum cryptography data packet in a storage mapping area in the external memory through a storage controller;

[0034] The logic control module generates a control signal corresponding to the operation instruction according to the quantum operation request received from the XDMA module and the operation instruction of the quantum cryptographic data packet;

[0035] The logic anti-quantum cryptographic algorithm module obtains the operation data of the quantum cryptographic data packet from the storage mapping area through the storage controller, and executes the operation instruction on the operation data according to the control signal corresponding to the operation instruction to obtain the quantum operation result;

[0036] The logic anti-quantum cryptographic algorithm module stores the quantum operation result in the storage mapping area through the storage controller;

[0037] The XDMA module obtains the quantum operation result from the storage mapping area and sends the quantum operation result to the host end.

[0038] The beneficial effects of this application are:

[0039] The FPGA structure and processing method of the quantum-resistant cryptographic algorithm provided in this application, due to the flexible programmability and high performance of FPGA, adopts a hardware structure to implement the quantum-resistant cryptographic algorithm, which has higher security than software implementation and is not easy to be cracked, and can ensure the security and efficient calculation of the implementation of the quantum-resistant cryptographic algorithm; when there is sufficient FPGA resource surplus, it is easy to transplant and expand to a parallel design. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 Schematic diagram of the structure of the FPGA structure of the quantum-resistant cryptographic algorithm provided in the embodiment of the present application Figure 1 ;

[0042] Figure 2 A schematic diagram of a storage mapping area of ​​an external memory provided in an embodiment of the present application;

[0043] Figure 3 Schematic diagram of the structure of the FPGA structure of the quantum-resistant cryptographic algorithm provided in the embodiment of the present application Figure 2 ;

[0044] Figure 4 A schematic diagram of the structure of a logic anti-quantum cryptographic algorithm module provided in an embodiment of the present application;

[0045] Figure 5 A schematic diagram of a process for processing a quantum-resistant cryptographic algorithm provided in an embodiment of the present application;

[0046] Figure 6 An interactive block diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0048] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0049] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0051] Before introducing the field-programmable gate array (FPGA) structure of the quantum-resistant cryptographic algorithm provided in the present application, it should be noted that each logic function module in the FPGA structure of the quantum-resistant cryptographic algorithm of the present application is a function module composed of logic operation units.

[0052] Figure 1 Schematic diagram of the structure of the FPGA structure of the quantum-resistant cryptographic algorithm provided in the embodiment of the present application Figure 1 ,like Figure 1 As shown, the FPGA structure includes: a logic control module 11, an XDMA module 12, a storage controller 13 and a logic anti-quantum cryptographic algorithm module 14.

[0053] The XDMA module 12 is connected to the host side through the PCIe interface, and is used to receive the DMA descriptor queue and quantum operation request sent by the host side, so that the XDMA module 12 obtains the quantum cryptographic data packet corresponding to the quantum operation request from the memory of the host side according to the DMA descriptor queue.

[0054] The logic control module 11 is connected to the XDMA module 12 and the logic anti-quantum cryptographic algorithm module 14, and is used to receive quantum operation requests and operation instructions of quantum cryptographic data packets from the XDMA module 12, and send control signals corresponding to the operation instructions to the logic anti-quantum cryptographic algorithm module 14 according to the quantum operation requests and operation instructions.

[0055] The XDMA module 12 is also connected to the storage controller 13, and is used to store the quantum cryptography data packet into the storage mapping area in the external memory through the storage controller 13.

[0056] The logic anti-quantum cryptographic algorithm module 14 is also connected to the storage controller 13, and is used to obtain the operation data of the quantum cryptographic data packet from the storage mapping area through the storage controller 13 according to the control signal corresponding to the operation instruction, and execute the operation instruction on the operation data to obtain the quantum operation result, and store the quantum operation result to the storage mapping area through the storage controller 13.

[0057] The XDMA module 12 is also used to obtain the quantum operation result from the storage mapping area through the storage controller 13, and send the quantum operation result to the host end.

[0058] In this embodiment, an XDMA IP core is integrated in the high-speed interface module as an XDMA module 12. The XDMA module 12 communicates with the host end through a high-speed communication interface. When the host end needs to request the FPGA structure to execute an anti-quantum cryptographic algorithm, a quantum operation request is sent to the XDMA module 12 through the high-speed communication interface, and a DMA descriptor queue indicating the storage location of a quantum cryptographic data packet used for the anti-quantum cryptographic algorithm is sent to the XDMA module 12.

[0059] The high-speed communication interface may be, for example, a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interface. When the host side needs to request the FPGA structure to execute the anti-quantum cryptographic algorithm, the quantum cryptographic data packets used for the anti-quantum cryptographic algorithm are stored in multiple memory blocks on the host side, and a DMA descriptor queue indicating the addresses of the multiple memory blocks is generated, and the DMA descriptor queue is sent to the XDMA module 12. The PCIe interface may be, for example, a PCIe3.0x8 interface.

[0060] After receiving the DMA descriptor queue, the XDMA module 12 obtains the quantum cryptography data packet from the memory block of the host according to the data storage address recorded in each DMA descriptor in the DMA descriptor queue.

[0061] Among them, the operation instructions and operation data carried in the quantum cryptographic data packet are different according to the different quantum operation requests to be executed. For example, if the quantum operation request is a key generation request, the operation instruction in the quantum cryptographic data packet is a key generation instruction, and the operation data in the quantum cryptographic data packet is a random number; if the quantum operation request is a key encapsulation request, the operation instruction in the quantum cryptographic data packet is an encapsulation instruction, and the operation data in the quantum cryptographic data packet is a random number and a public key; if the quantum operation request is a key decapsulation request, the operation instruction in the quantum cryptographic data packet is a decapsulation instruction, and the operation data in the quantum cryptographic data packet is a ciphertext and a private key.

[0062] In some embodiments, the operation data of the quantum cryptographic data packet may not carry random numbers, and the logical anti-quantum cryptographic algorithm module obtains random numbers from the random number chip when executing the corresponding operation instructions.

[0063] After obtaining the quantum cryptography data packet from the memory block on the host side, the XDMA module 12 determines the address information of the storage mapping area of ​​the quantum cryptography data packet in the external memory connected to the FPGA structure according to the type of quantum operation request and the storage mapping relationship of the FPGA structure, and sends the quantum cryptography data packet and the address information of the storage mapping area to the storage controller 13. The storage controller 13 stores the quantum cryptography data packet in the corresponding storage mapping area in the external memory according to the address information of the storage mapping area.

[0064] For example, Figure 2 A schematic diagram of a storage mapping area of ​​an external memory provided in an embodiment of the present application, such as Figure 2 As shown, addresses 0000_0000 to 0000_1000 are used to store the operation state of the logic anti-quantum cryptographic algorithm module 14; addresses 0000_2000 to 0000_3000 are used to store key generation input instructions / data, that is, the operation instructions and operation data in the quantum cryptographic data packet corresponding to the key generation request; addresses 0000_4000 to 0000_5000 store the key generation output data of the logic anti-quantum cryptographic algorithm module 14, that is, the key obtained by executing the key generation instruction; addresses 0000_6000 to 0000_7000 are used to store The address range from 0000_8000 to 0000_9000 is used to store the encapsulation input instruction / data, i.e., the operation instruction and operation data in the quantum cryptographic data packet corresponding to the key encapsulation request. The address range from 0000_8000 to 0000_9000 is used to store the encapsulation output data, i.e., the ciphertext obtained by executing the encapsulation instruction. The address range from 0000_A000 to 0000_B000 is used to store the decapsulation input instruction / data, i.e., the operation instruction and operation data in the quantum cryptographic data packet corresponding to the key decapsulation request. The address range from 0000_C000 to 0000_D000 is used to store the decapsulation output data, i.e., the plaintext obtained by executing the decapsulation instruction.

[0065] In addition to sending the quantum cryptographic data packet to the storage mapping area of ​​the external memory through the storage controller 13, the XDMA module 12 also sends the quantum operation request and the operation instruction in the quantum cryptographic data packet to the logic control module 11. The logic control module 11 determines that a control signal for the anti-quantum cryptographic algorithm module 14 needs to be generated according to the quantum operation request, and determines to generate a control signal corresponding to the operation instruction according to the type of the operation instruction. If the operation instruction is a key generation instruction, the control signal is a key generation control signal. If the operation instruction is an encapsulation instruction, the control signal is a key encapsulation control signal. If the operation instruction is a decapsulation instruction, the control signal is a key decapsulation control signal.

[0066] The logic anti-quantum cryptographic algorithm module 14 is a PQC algorithm module, which is used to execute the PQC algorithm, specifically to execute the ML-KEM cryptographic operation process. After receiving the control signal sent by the logic control module 11, the logic anti-quantum cryptographic algorithm module 14 obtains the operation data in the quantum cryptographic data packet from the storage mapping area through the storage controller 13, and executes the operation instruction on the operation data according to the PQC algorithm to obtain the quantum operation result.

[0067] After executing the operation instruction and obtaining the quantum operation result, the logic anti-quantum cryptographic algorithm module 14 sends the quantum operation result to the storage controller 13, and the storage controller 13 stores the quantum operation result in a storage device such as a storage device. Figure 2 In the corresponding storage mapping area in the external memory shown, the XDMA module 12 accesses the storage mapping area through the storage controller 13 to obtain the quantum operation result, and sends the quantum operation result to the memory block corresponding to the quantum cryptographic data packet corresponding to the quantum operation result in the host memory according to the address information of the memory block described in the DMA descriptor queue. The host can read the quantum operation result from the corresponding memory block.

[0068] In some embodiments, Figure 1 As shown, the XDMA module 12 may include: a PCIe IP core and a direct memory access (Data Memory Access, DAM), the PCIe IP core performs data transmission with the host-side memory through a PCIe interface, the PCIe IP core converts a quantum cryptography data packet in a PCIe format into a quantum cryptography data packet in an AXI format and sends it to the DMA, the DMA determines the address information of the storage mapping area of ​​the quantum cryptography data packet in the external memory, and sends the quantum cryptography data packet and the address information of the storage mapping area to the storage controller 13.

[0069] In some embodiments, the external memory may be a double data rate (DDR) memory, specifically a DDR4 memory, and the memory controller 13 may be a DDR controller.

[0070] In one possible implementation, Figure 3 Schematic diagram of the structure of the FPGA structure of the quantum-resistant cryptographic algorithm provided in the embodiment of the present application Figure 2 ,like Figure 3 As shown, the FPGA structure may further include: a logic instruction detection module 15 and a logic instruction parsing module 16.

[0071] The logic instruction detection module 15 and the logic instruction parsing module 16 are connected between the XDMA module 12 and the logic control module 11. The logic instruction detection module 15 is used to detect the quantum cryptography data packet and obtain the instruction data from the operation instruction field of the quantum cryptography data packet; the logic instruction parsing module 16 is used to parse the instruction data to obtain the operation instruction.

[0072] In this embodiment, if Figure 3 As shown, the XDMA module 12 is connected to the logic instruction detection module 15, the logic instruction parsing module 16 and the logic control module 11 in sequence. The logic instruction detection module 15 detects the quantum cryptography data packet, determines the operation instruction field in the quantum cryptography data packet, and extracts the instruction data representing the operation instruction from the operation instruction field, and sends the instruction data to the logic instruction parsing module 16.

[0073] The logic instruction parsing module 16 determines the operation instruction corresponding to the instruction data according to the correspondence between the predefined instruction data and the operation instruction. For example, Table 1 shows the content of the quantum cryptographic data packet provided in the embodiment of the present application. As shown in Table 1, instruction 0XAA70_0000 is a key generation instruction, carrying random number 1 and random number 2, instruction 0XAA40_000 is an encapsulation instruction, carrying random number 1 and a public key, and instruction 0XAA50_000 is a decapsulation instruction, carrying a ciphertext and a private key, wherein the length of the random number, public key, private key, and ciphertext can be defined by oneself, and the length shown in Table 1 is not the only limitation.

[0074] Table 1 Contents of quantum cryptography data packet

[0075]

[0076] In some embodiments, the logic instruction detection module 15 and the logic instruction parsing module 16 may be integrated into the same module, or may be integrated into the same module with the logic control module 11 , and this implementation does not impose any limitation on this.

[0077] In one possible implementation, Figure 3 As shown, the FPGA structure may further include: a logic arbitration module 17; the logic arbitration module 17 is respectively connected to the XDMA module 12, the logic anti-quantum cryptographic algorithm module 14 and the storage controller 13, and is used to determine the request processing order when data read and write requests from the XDMA module 12 and the logic anti-quantum cryptographic algorithm module 14 are received at the same time.

[0078] In this embodiment, one side of the logic arbitration module 17 is connected to the XDMA module 12 and the logic anti-quantum cryptographic algorithm module 14, and is used to receive data read and write requests from the XDMA module and the logic anti-quantum cryptographic algorithm module 14. The other side of the logic arbitration module 17 is connected to the storage controller 13, and is used to read and write data to the external memory through the storage controller 13 according to the data read and write request.

[0079] When the data read / write request is a data write request, the data to be written sent by the XDMA module 12 or the logic anti-quantum cryptography algorithm module 14 is received. The data to be written sent by the XDMA module 12 is a quantum cryptography data packet, and the data to be written sent by the logic anti-quantum cryptography algorithm module 14 is a quantum operation result. The data to be written is written into the storage mapping area of ​​the external memory through the storage controller 13.

[0080] When the data read / write request is a data read request, the identifier of the data to be read sent by the XDMA module 12 or the logic anti-quantum cryptography algorithm module 14 is received, the data to be read of the XDMA module 12 is the quantum operation result, and the data to be read of the logic anti-quantum cryptography algorithm module 14 is the operation data in the quantum cryptography data packet. The data to be read is obtained from the storage mapping area of ​​the external memory through the storage controller 13, and sent to the XDMA module 12 or the logic anti-quantum cryptography algorithm module 14.

[0081] When the logic arbitration module 17 receives data read and write requests sent by the XDMA module 12 and the logic anti-quantum cryptographic algorithm module 14 at the same time, it is necessary to determine which data read and write request is sent to the storage controller 13 first according to the predefined priorities of the XDMA module 12 and the logic anti-quantum cryptographic algorithm module 14. If the priority of the XDMA module 12 is higher than that of the logic anti-quantum cryptographic algorithm module 14, the data read and write request of the XDMA module 12 is sent to the storage controller 13 first; if the priority of the logic anti-quantum cryptographic algorithm module 14 is higher than that of the XDMA module 12, the data read and write request of the logic anti-quantum cryptographic algorithm module 14 is sent to the storage controller 13 first.

[0082] In some embodiments, the logic arbitration module 17 may be an interconnect, and specifically may be an AXI_interconnect using the AXI protocol.

[0083] In a possible implementation, the FPGA structure may further include: a logic timing module 18; the logic timing module 18 is respectively connected to the logic arbitration module 17 and the logic anti-quantum cryptographic algorithm module 14, and is used to perform time domain conversion on the operation data or quantum operation results.

[0084] In this embodiment, the logic timing module 18 receives the operation data in the quantum cryptography data packet obtained from the external memory, and performs time domain conversion on the operation data so that the frequency of the operation data meets the operation frequency requirement of the logic anti-quantum cryptography algorithm module 14.

[0085] The logic timing module 18 also receives the quantum operation result output by the logic anti-quantum cryptographic algorithm module 14, and performs time domain conversion on the quantum operation result so that the frequency of the quantum operation result meets the storage requirement of the external memory.

[0086] In some embodiments, if the FPGA structure does not include the logic arbitration module 17 , the logic timing module 18 may be directly connected to the storage controller 13 , which is not limited in this embodiment.

[0087] In one possible implementation, Figure 3 As shown, the FPGA structure may further include: a logic protocol conversion module 19; the logic protocol conversion module 19 is respectively connected to the logic arbitration module 17 and the logic anti-quantum cryptographic algorithm module 14, and is used to perform data format conversion between the logic arbitration module 17 and the logic anti-quantum cryptographic algorithm module 14.

[0088] In this embodiment, the storage protocol executed by the external memory is the AXI protocol, and the protocol executed by the logical anti-quantum cryptographic algorithm module 14 is the PQC algorithm protocol. In order to ensure that the data format meets the respective protocol requirements, it is necessary to set a logical protocol conversion module 19 between the logical arbitration module 17 and the logical anti-quantum cryptographic algorithm module 14, wherein the user side of the logical protocol conversion module 19 is used to convert the operation data into the protocol format that meets the logical anti-quantum cryptographic algorithm module 14, and the IP side of the logical protocol conversion module 19 is used to convert the quantum operation result into the protocol format of the external memory.

[0089] In some embodiments, if the FPGA structure does not include the logic arbitration module 17 , the logic protocol conversion module 19 may be directly connected to the storage controller 13 .

[0090] In some other embodiments, if the FPGA structure includes a logic timing module 18 , the user side of the logic protocol conversion module 19 can be connected to the logic timing module 18 .

[0091] In one possible implementation, Figure 3 As shown, the FPGA structure may further include: an input first-in first-out module 20; the input first-in first-out module 20 is respectively connected to the logic timing module 18 and the logic anti-quantum cryptographic algorithm module 14, and is used to cache the operation data.

[0092] In this embodiment, if the FPGA structure receives multiple quantum computing requests sent by the host, the storage controller 13 can send the computing data obtained from the storage mapping area to the logic timing module 18 in sequence. After the multiple computing data are frequency-converted by the logic timing module 18, they are cached in the input first-in-first-out module 20. The input first-in-first-out module 20 uses a first-in-first-out mechanism to form a first-in-first-out queue (First Input First Output, FIFO) for the computing data sent by the logic timing module 18. The logic timing module 18 first caches the computing data in the input first-in-first-out module 20 and first sends it to the logic anti-quantum computing module to execute the corresponding computing instructions to obtain the corresponding quantum computing results.

[0093] For example, the input FIFO module 20 may be a memory using a FIFO mechanism.

[0094] In one possible implementation, Figure 3 As shown, the FPGA structure may further include: an output first-in-first-out module 21; the output first-in-first-out module 21 is respectively connected to the logic timing module 18 and the logic anti-quantum cryptographic algorithm module 14, and is used to cache the quantum operation results.

[0095] In this embodiment, for the multiple operation instructions and corresponding operation data received by the logic anti-quantum cryptographic algorithm module 14, the logic anti-quantum cryptographic algorithm module 14 executes the corresponding operation instructions on the operation data, and caches the quantum operation results in the output first-in-first-out module 21. The logic timing module 18 obtains the front quantum operation result from the first-in-first-out queue according to the quantum operation results stored in the first-in-first-out queue of the output first-in-first-out module 21, performs frequency conversion, and sends it to the logic controller 13.

[0096] For example, the output FIFO module 21 may be a memory using a FIFO mechanism.

[0097] In a possible implementation, the FPGA structure may also include: a random number chip driving module 22 and a random number first-in-first-out module 23; the random number chip driving module 22 is externally connected to a random number chip, and the random number chip driving module 22 is also connected to a logic timing module 18 to send the random number obtained through the random number chip to the logic timing module 18 for time domain conversion; the random number first-in-first-out module 23 is respectively connected to the logic timing module 18 and the anti-quantum cryptographic algorithm module 14, and is used to cache the random number and then send it to the anti-quantum cryptographic algorithm module 14.

[0098] In this embodiment, a random number chip driver module 22 can also be set in the FPGA structure for an external random number chip. The logic control module 11 can send a random number generation instruction to the random number chip driver module 22 based on a key generation instruction or a packaging instruction. The random number chip driver module 22 drives the external random number chip to generate a random number. The random number chip sends the generated random number to the random number chip driver module 22. The random number chip driver module 22 sends the random number to the logic timing module 18 for frequency conversion, and then sends it to the random number first-in-first-out module 23 for caching.

[0099] The logic anti-quantum cryptographic algorithm module 14 obtains the first random number from the first-in-first-out queue of the random number first-in-first-out module 23 to execute the key generation instruction or the encapsulation instruction according to the random number.

[0100] In some embodiments, the random number chip driving module 22 and the external random number chip use a serial peripheral interface (SPI) for data transmission.

[0101] The FPGA structure of the quantum-resistant cryptographic algorithm provided in the above embodiment uses a hardware structure to implement the quantum-resistant cryptographic algorithm because FPGA has flexible programmability and high performance. Compared with software implementation, it has higher security and is not easy to be cracked, which can ensure the security and efficient computing of the quantum-resistant cryptographic algorithm. When there is sufficient FPGA resource margin, it is easy to transplant and expand to a parallel design.

[0102] In one possible implementation, Figure 4 A schematic diagram of the structure of the logic anti-quantum cryptographic algorithm module provided in the embodiment of the present application is shown in FIG. Figure 4 As shown, the logic anti-quantum cryptographic algorithm module 14 may include: a hash module 41 , a binomial distribution sampling module 42 , a number theory transformation sampling module 43 , a number theory transformation module 44 and a polynomial multiplication module 45 .

[0103] The hash module 41 is respectively connected to the binomial distribution sampling module 42 and the number theory transformation sampling module 43. The binomial distribution sampling module 42 is also connected to the number theory transformation module 44. The number theory transformation sampling module 43 is also connected to the polynomial multiplication module 45. The number theory transformation module 44 is also connected to the polynomial multiplication module 45. The polynomial multiplication module 45 is used to output the quantum operation result.

[0104] In this embodiment, the hash module 41 uses the input random number to execute a hash algorithm to generate the required hash value. The hash algorithm executed by the hash module 41 can be a hash algorithm such as SHAKE, SHA3, etc., to provide stable input for the binomial distribution sampling (Centered Binomial Distribution, CBD) module 42 and the number theoretic transform (Number Theoretic Transform, NTT) sampling module 43.

[0105] The binomial distribution sampling module 42 generates error vectors e1, e2, r, s according to the hash value, and stores them in the 32KiB block random access memory (BRAM) corresponding to the error term array. The number theory transformation sampling module 43 generates an array A of the NTT domain according to the hash value, and stores it in the BRAM corresponding to the NTT sampling.

[0106] The number theory transformation module 44 reads the error vector and the rotation factor ζ stored in the ROM from the error term array BRAM k , perform number theory transformation and inverse transformation, convert the array of polynomial ring coefficients into an NTT domain array, simplify the computational complexity of polynomial multiplication module 45, the polynomial multiplication module 45 reads array A from the NTT sampling BRAM, and reads the rotation factor ζ stored in the ROM 2k+1 , combined with the output of the number theory transformation module 44, a polynomial multiplication operation is performed to output the quantum operation result.

[0107] The FPGA structure of the quantum-resistant cryptographic algorithm provided in the above embodiment modularizes the calculation process of the quantum-resistant cryptographic algorithm, which is convenient for transplantation and expansion into a parallel design when there is sufficient FPGA resource surplus.

[0108] Based on the above-mentioned FPGA structure of the quantum-resistant cryptographic algorithm, the present application also provides a processing method of the quantum-resistant cryptographic algorithm applied to the FPGA structure. Figure 5 A flowchart of a method for processing a quantum-resistant cryptographic algorithm provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the method may include:

[0109] S501. The XDMA module receives a DMA descriptor queue and a quantum operation request sent by a host.

[0110] S502, the XDMA module obtains the quantum cryptography data packet from the memory of the host side according to the DMA descriptor queue, and stores the quantum cryptography data packet to the storage mapping area in the external memory through the storage controller.

[0111] S503: The logic control module generates a control signal corresponding to the operation instruction from the quantum operation request received by the XDMA module and the operation instruction of the quantum cryptography data packet.

[0112] S504, the logic anti-quantum cryptographic algorithm module obtains the operation data of the quantum cryptographic data packet from the storage mapping area through the storage controller, and executes the operation instruction on the operation data according to the control signal corresponding to the operation instruction to obtain the quantum operation result.

[0113] S505. The logic anti-quantum cryptographic algorithm module stores the quantum operation result to the storage mapping area through the storage controller.

[0114] S506. The XDMA module obtains the quantum operation result from the storage mapping area and sends the quantum operation result to the host end.

[0115] In this embodiment, after receiving the DMA descriptor queue, the XDMA module obtains the quantum cryptography data packet from the memory block of the host side according to the data storage address recorded in each DMA descriptor in the DMA descriptor queue, and then determines the address information of the storage mapping area of ​​the quantum cryptography data packet in the external memory connected to the FPGA structure according to the type of quantum operation request and the storage mapping relationship of the FPGA structure, and sends the quantum cryptography data packet and the address information of the storage mapping area to the storage controller. The storage controller stores the quantum cryptography data packet in the corresponding storage mapping area in the external memory according to the address information of the storage mapping area.

[0116] In addition to sending the quantum cryptography data packet to the storage mapping area of ​​the external memory through the storage controller, the XDMA module also sends the quantum operation request and the operation instruction in the quantum cryptography data packet to the logic control module. The logic control module determines the need to generate a control signal for the anti-quantum cryptography algorithm module based on the quantum operation request, and determines to generate a control signal corresponding to the operation instruction based on the type of the operation instruction.

[0117] After receiving the control signal sent by the logic control module, the logic anti-quantum cryptography algorithm module obtains the operation data in the quantum cryptography data packet from the storage mapping area through the storage controller, and executes the operation instruction on the operation data according to the PQC algorithm to obtain the quantum operation result.

[0118] After executing the operation instruction and obtaining the quantum operation result, the logical anti-quantum cryptographic algorithm module sends the quantum operation result to the storage controller, and the storage controller stores the quantum operation result to the corresponding storage mapping area in the external memory. The XDMA module accesses the storage mapping area through the storage controller to obtain the quantum operation result, and sends the quantum operation result to the memory block corresponding to the quantum cryptographic data packet corresponding to the quantum operation result in the host memory according to the address information of the memory block described in the DMA descriptor queue. The host can read the quantum operation result from the corresponding memory block.

[0119] In some embodiments, Figure 6 The interactive block diagram provided by the embodiment of the present application is as follows: Figure 6 As shown, the logic control module interacts with the logic anti-quantum cryptographic algorithm module to execute the key generation algorithm corresponding to the key generation instruction, the encapsulation algorithm corresponding to the encapsulation instruction, and the decapsulation algorithm corresponding to the decapsulation instruction.

[0120] Among them, rng_trig is the control signal corresponding to the key generation instruction, key_rdy is the key generation signal; enc_trig is the control signal corresponding to the encapsulation instruction, enc_rdy is the encapsulation completion signal, dec_trig is the control signal corresponding to the decapsulation instruction, and dec_rdy is the decapsulation completion signal.

[0121] The following describes the specific process of the logical anti-quantum cryptographic algorithm module executing the key generation algorithm, encapsulation algorithm, and decapsulation algorithm.

[0122] Specifically, in the key generation stage, the hash module processes the random number seed d to generate a hash value h, and then uses the binomial distribution sampling module to generate the private key polynomial s and the error polynomial e, and stores them in the BRAM. Subsequently, the number theory transformation module reads s and e from the BRAM, and converts them to the NTT domain through calculation to improve the calculation efficiency of the subsequent polynomial multiplication module. At the same time, the hash value h generates the polynomial array A through the number theory transformation sampling module and converts it to the NTT domain. Then, t=A·s+e is calculated through the polynomial multiplication module, and t is encoded by the encoding function to generate the public key and private key. All operations are accelerated by the parallel DSP unit. The generated public key and private key data are stored for subsequent encryption and decryption.

[0123] In the encapsulation (encryption) stage, the hash module processes the input random number stream p to generate a hash value h, and generates error terms e1, e2 and private key polynomial s through the binomial distribution sampling module. The public key data ek is input into the number theory transformation sampling module to generate a polynomial array A, which is stored in the BRAM respectively. Subsequently, the number theory transformation module converts the error terms e1, e2 and private key polynomial s to the NTT domain. The system decodes the public key through the encoding module encode to generate t, and calculates u=A·s+e1 and v=s·t+e2 by point-by-point multiplication, using the pre-stored rotation factors in the ROM and the parallel DSP unit to accelerate the operation. Finally, the polynomial multiplication module encodes the result to generate ciphertext u and v, and stores it for transmission or storage.

[0124] In the decapsulation (decryption) stage, the system sends the ciphertext u in the NTT domain to the number theory transformation module to generate u', decodes the private key s to get s', performs point multiplication on u' and s' through the polynomial multiplication module, and then performs two 128-point NTT inverse operations through the number theory transformation module. The result is subtracted from v, and then compressed and encoded to restore the original information m.

[0125] The processing method of the quantum-resistant cryptographic algorithm provided in the above embodiment is implemented based on the FPGA structure of the quantum-resistant cryptographic algorithm. Since FPGA has flexible programmability and high performance, the implementation of the quantum-resistant cryptographic algorithm using a hardware structure has higher security than software implementation and is not easy to be cracked, thereby ensuring the security and efficient calculation of the implementation of the quantum-resistant cryptographic algorithm. When there is sufficient FPGA resource margin, it is easy to transplant and expand into a parallel design.

[0126] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An FPGA structure for quantum cryptographic algorithms, characterized in that: The FPGA structure includes: a logic control module, an XDMA module, a storage controller and a logic anti-quantum cryptographic algorithm module; The XDMA module is connected to the host side through the PCIe interface, and is used to receive the DMA descriptor queue and the quantum operation request sent by the host side, so that the XDMA module obtains the quantum cryptographic data packet corresponding to the quantum operation request from the memory of the host side according to the DMA descriptor queue; The logic control module is connected to the XDMA module and the logic anti-quantum cryptographic algorithm module, and is used to receive the quantum operation request and the operation instruction of the quantum cryptographic data packet from the XDMA module, and send a control signal corresponding to the operation instruction to the logic anti-quantum cryptographic algorithm module according to the quantum operation request and the operation instruction; The XDMA module is also connected to the storage controller, and is used to store the quantum cryptography data packet into a storage mapping area in the external memory through the storage controller; The logic anti-quantum cryptographic algorithm module is also connected to the storage controller, and is used to obtain the operation data of the quantum cryptographic data packet from the storage mapping area through the storage controller according to the control signal corresponding to the operation instruction, and execute the operation instruction on the operation data to obtain the quantum operation result, and store the quantum operation result in the storage mapping area through the storage controller; The XDMA module is also used to obtain the quantum operation result from the storage mapping area through the storage controller, and send the quantum operation result to the host end.

2. The FPGA structure according to claim 1, characterized in that: The FPGA structure also includes: a logic instruction detection module and a logic instruction parsing module; The logic instruction detection module and the logic instruction parsing module are connected between the XDMA module and the logic control module, and the logic instruction detection module is used to detect the quantum cryptography data packet and obtain instruction data from the operation instruction field of the quantum cryptography data packet; The logic instruction parsing module is used to parse the instruction data to obtain the operation instruction.

3. The FPGA structure according to claim 1, characterized in that: The FPGA structure also includes: a logic arbitration module; The logic arbitration module is respectively connected to the XDMA module, the logic anti-quantum cryptographic algorithm module and the storage controller, and is used to determine the request processing order when receiving data read and write requests from the XDMA module and the logic anti-quantum cryptographic algorithm module at the same time.

4. The FPGA structure according to claim 3, characterized in that: The FPGA structure also includes: a logic timing module; The logic timing module is respectively connected to the logic arbitration module and the logic anti-quantum cryptographic algorithm module, and is used to perform time domain conversion on the operation data or the quantum operation result.

5. The FPGA structure as claimed in claim 4, characterized in that: The FPGA structure also includes: a logic protocol conversion module; The logic protocol conversion module is connected to the logic arbitration module and the logic anti-quantum cryptographic algorithm module respectively, and is used to perform data format conversion between the logic arbitration module and the logic anti-quantum cryptographic algorithm module.

6. The FPGA structure according to claim 4, characterized in that: The FPGA structure also includes: an input first-in first-out module; The input first-in-first-out module is respectively connected to the logic timing module and the logic anti-quantum cryptographic algorithm module, and is used to cache the operation data.

7. The FPGA structure according to claim 4, characterized in that: The FPGA structure also includes: an output first-in-first-out module; The output first-in-first-out module is respectively connected to the logic timing module and the logic anti-quantum cryptographic algorithm module, and is used to cache the quantum operation result.

8. The FPGA structure according to claim 4, characterized in that: The FPGA structure also includes: a random number chip driving module and a random number first-in-first-out module; The random number chip driving module is externally connected to a random number chip, and the random number chip driving module is also connected to the logic timing module to send the random number obtained by the random number chip to the logic timing module for time domain conversion; The random number first-in-first-out module is connected to the logic timing module and the anti-quantum cryptographic algorithm module respectively, and is used for caching the random number and then sending it to the anti-quantum cryptographic algorithm module.

9. The FPGA structure according to claim 1, wherein: The logic anti-quantum cryptographic algorithm module includes: a hash module, a binomial distribution sampling module, a number theory transformation sampling module, a number theory transformation module and a polynomial multiplication module; The hash module is respectively connected to the binomial distribution sampling module and the number theory transformation sampling module, the binomial distribution sampling module is also connected to the number theory transformation module, the number theory transformation sampling module is also connected to the polynomial multiplication module, the number theory transformation module is also connected to the polynomial multiplication module, and the polynomial multiplication module is used to output the quantum operation result.

10. A method for processing a quantum-resistant cryptographic algorithm, characterized in that: An FPGA structure applied to a quantum-resistant cryptographic algorithm as claimed in any one of claims 1 to 9, wherein the method comprises: The XDMA module receives the DMA descriptor queue and quantum operation request sent by the host; The XDMA module obtains a quantum cryptography data packet from the memory of the host end according to the DMA descriptor queue, and stores the quantum cryptography data packet in a storage mapping area in the external memory through a storage controller; The logic control module generates a control signal corresponding to the operation instruction according to the quantum operation request received from the XDMA module and the operation instruction of the quantum cryptography data packet; The logic anti-quantum cryptographic algorithm module obtains the operation data of the quantum cryptographic data packet from the storage mapping area through the storage controller, and executes the operation instruction on the operation data according to the control signal corresponding to the operation instruction to obtain the quantum operation result; The logic anti-quantum cryptographic algorithm module stores the quantum operation result in the storage mapping area through the storage controller; The XDMA module obtains the quantum operation result from the storage mapping area and sends the quantum operation result to the host end.

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