Bistable weak PUF (Physical Unclonable Function) circuit capable of autonomously screening stable positions

Abstract

The invention discloses a bistable weak PUF (Physical Unclonable Function) circuit capable of autonomously screening stable bits, which comprises a decoder, a sequential circuit and a PUF core circuit, the PUF core circuit realizes stable bit screening by accessing two screening levels, and when the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit is switched on to realize stable bit screening. The PUF core circuit generates W-bit original PUF response in a clock period under the control of m-bit word line level signals output to the PUF core circuit by the decoder, the m-bit word line level signals accessed by the PUF core circuit are kept unchanged, one of two screening levels accessed by the PUF core circuit is kept unchanged with an original value, and the other screening level is reduced by a certain amplitude, so that the PUF core circuit generates W-bit original PUF response in a clock period. Two W-bit screening PUF responses are obtained after the screening level is exchanged, and after XOR is carried out on the W-bit screening PUF responses, if the ith bit is 1, it is considered that the response value of the bit in the original PUF response under the excitation signal is an unstable response; the method has the advantages of high stability, low hardware overhead and low detection cost.

Description

Technical Field

[0001] The present invention relates to a weak PUF circuit, and in particular to a bistable weak PUF circuit capable of autonomously screening stable bits. Background Art

[0002] Physical Unclonable Functions (PUF) provide a new method for generating chip fingerprints, which can be used to generate characteristic keys with randomness, uniqueness and tamper-proof, and are very suitable for the field of Internet of Things. PUF captures the random process deviation in the chip manufacturing process, converts the process deviation into physical deviations such as voltage, current, and delay, and generates an output response by comparing the deviation size through an arbitrator. PUF can be roughly divided into two categories according to the ability to generate stimulus response pairs: weak PUF circuits and strong PUF circuits. For weak PUF circuits, usually a PUF unit in the PUF array generates only one PUF response. Since its hardware entropy source does not reuse, all the generated PUF responses are independent of each other. For strong PUF circuits, the PUF units in the PUF array are interrelated, and a PUF unit can generate multiple PUF responses. Since its hardware entropy source reuses, there is inevitably a correlation between the generated PUF responses. Therefore, compared with strong PUF circuits, weak PUF circuits have better resistance to model attacks and machine learning attacks, and are mainly used for key generation in information systems. However, since one PUF unit in a weak PUF circuit has only one corresponding PUF response, and the PUF response is easily affected by changes in environmental conditions such as temperature, power supply voltage and noise, and flips, the stability deteriorates, resulting in poor stability of the weak PUF circuit.

[0003] In response to the stability problem of weak PUF circuits, some researchers have proposed some detection methods to detect unstable bits of PUF responses, thereby improving the stability of weak PUF circuits. For example, in the document "An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9Key Error Probability[J], IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, vol. 67, no. 12, pp. 4855-4868", a capacitance tilt stabilization technology is proposed to detect the stability of PUF response for metastable weak PUF circuits. This capacitance tilt stabilization technology avoids the flipping of PUF response by adding a capacitor with adjustable capacitance value to the cross-coupled inverter of the PUF unit of the weak PUF circuit, thereby improving the stability of the PUF response. However, the capacitor area added by the capacitor tilt stabilization technology in the weak PUF circuit is much larger than the original weak PUF circuit area, and an additional switch must be set for each capacitor to control whether the capacitor is connected to the weak PUF circuit, which significantly increases the hardware overhead of the weak PUF circuit and the detection cost is very high.

[0004] The document "High-Density and Low-Power PUF Designs in 5nm Achieving 23×and39×BER Reduction After Unstable Bit Detection and Masking[C],2024IEEEInternational Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2024,pp.302-304." provides a technique for using a high-resolution digital-to-analog converter (DAC) to inject current offset to detect possible unstable bits (i.e., unstable PUF responses) in a weak PUF circuit, thereby filtering out unstable PUF responses. However, this technique requires an additional high-resolution digital-to-analog converter in the weak PUF circuit. The high-resolution digital-to-analog converter has a large area, resulting in a feature size of up to 3920F in the weak PUF circuit. 2 , the hardware overhead is large and the detection cost is high.

[0005] The paper “A6T-SRAM-Based Physically-Unclonable-Function With Low BER Through Automated Maximum Mismatch Detection [J], IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, vol. 71, no. 7, pp. 3493-3497.” proposes a 6T-SRAM PUF. This PUF uses maximum mismatch detection technology to detect unstable responses by identifying and selecting adjacent PUF units with the highest mismatch in four different configurations. However, additional storage space is required to store different configuration information corresponding to each PUF unit, which also increases hardware resource overhead and detection cost. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a bistable weak PUF circuit which can autonomously screen stable bits while having high stability, small hardware overhead and low detection cost.

[0007] The technical solution adopted by the present invention to solve the above technical problems is: a bistable weak PUF circuit capable of autonomously selecting stable bits, comprising a decoder, a timing circuit and a PUF core circuit; the decoder is used to access the n-bit excitation signal C1-C n , and the n-bit excitation signal C1-C n Perform decoding operation to obtain m-bit word line level signal WL1-WL m Output to the PUF core circuit, n is an integer greater than or equal to 1, m = 2 n; The timing circuit is used to access the clock signal CLK and the enable signal CEN, perform AND operation on the clock signal CLK and the enable signal CEN, obtain the clock signal AEN for controlling the working timing of the decoder and output it to the decoder, and delay the clock signal AEN and invert it and perform NAND operation on the clock signal AEN to obtain the clock signal PRE for controlling the working timing of the PUF core circuit and output it to the PUF core circuit; The PUF core circuit is used to generate a W-bit PUF response in each clock cycle of the clock signal PRE under the control of the m-bit word line level signal outputted thereto by the decoder, where W is an integer greater than or equal to 1; The PUF core circuit has the function of autonomously screening stable bits, and the PUF core circuit realizes stable bit screening by accessing two screening levels. When the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit outputs to the decoder. Under the control of the m-bit word line level signal, the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the original PUF response of the clock cycle, and then the m-bit word line level signal connected to the PUF core circuit is kept unchanged, and one of the two screening levels connected to the PUF core circuit is first kept unchanged, while the other is reduced by a certain amplitude, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the first screening PUF response, and then the two screening levels are exchanged, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the second screening PUF response, and the first screening PUF response and the second screening PUF response are XOR-operated to obtain a W-bit stability mark value, and if the value of a certain bit in the W-bit stability mark value is 1, it is considered that the response value of this bit in the original PUF response under the current excitation signal is an unstable response.

[0008] Compared with the prior art, the present invention has the advantage of performing unstable response detection by connecting two screening levels to the PUF core circuit. When the PUF core circuit generates a W-bit PUF response of a certain clock cycle, the m-bit word line level signal connected thereto is kept unchanged, and two equal screening levels are first connected to generate an original PUF response, and then two unequal screening levels are connected to generate two screened PUF responses. Since the unstable response value in the original PUF response will be flipped when the two screening levels are unequal, if there is an unstable response in the original PUF response, the unstable response will be flipped, so that the two screened PUF responses are not equal. The corresponding bit value in the W-bit stability mark value obtained after the XOR operation will be 1. At this time, if the value of a certain bit in the W-bit stability mark value is 1, it is considered that the response value of this bit in the original PUF response under the current excitation signal is an unstable response. If there is no unstable response in the original PUF response, no flipping will occur at this time, and all bits of the W-bit stability mark value will be completely 0. Therefore, the present invention can screen out unstable responses and has high stability. Moreover, by only connecting two screening levels and making the two screening levels equal or unequal, unstable screening can be achieved. No additional devices are required, the hardware overhead is small, and the detection cost is low.

[0009] Furthermore, the decoder has n excitation signal input terminals, 1 clock signal input terminal and m output terminals; the timing circuit has 2 input terminals and 2 output terminals, the 2 input terminals are respectively referred to as the first input terminal and the second input terminal, the 2 output terminals are respectively referred to as the first output terminal and the second output terminal, the PUF core circuit has a power supply terminal, a ground terminal, m word line level signal input terminals, 1 clock signal input terminal, 2 screening level input terminals and W output terminals, the n excitation signal input terminals of the decoder are used to access the n-bit excitation signals C1-C n , the m output ends of the decoder are used to output m-bit word line level signals, the m output ends of the decoder are connected one-to-one with the m word line level signal input ends of the PUF core circuit, the first input end of the timing circuit is connected to the enable signal CEN, the second input end is connected to the clock signal CLK, the first output end of the timing circuit is connected to the clock signal input end of the decoder, the first output end of the timing circuit outputs the clock signal AEN, the second output end of the timing circuit is connected to the clock signal input end of the PUF core circuit, the second output end of the timing circuit outputs the clock signal PRE, the power supply end of the PUF core circuit is used to connect to the working power supply VDD, the ground end of the PUF core circuit is used to connect to the ground voltage VSS, and the W output ends of the PUF core circuit are used to output the W-bit PUF response Z1-Z WThe two screening level input terminals of the PUF core circuit are respectively connected to the screening level V L and V R .

[0010] Furthermore, the timing circuit includes a D flip-flop, 21 inverters, a two-input AND gate and a first two-input NAND gate, the D flip-flop has an input terminal, a clock terminal and an output terminal, the two-input AND gate has a first input terminal, a second input terminal and an output terminal, the first two-input NAND gate has a first input terminal, a second input terminal and an output terminal, the input terminal of the D flip-flop is connected to the first input terminal of the timing circuit, the clock terminal of the D flip-flop and the second input terminal of the two-input AND gate, and its connection terminal is the second input terminal of the timing circuit , the output end of the D flip-flop is connected to the first input end of the two-input AND gate, the output end of the two-input AND gate, the input end of the first inverter and the second input end of the first two-input NAND gate are connected, and the connection end is the first output end of the timing circuit, the output end of the kth inverter is connected to the input end of the k+1th inverter, k=1, 2,…, 20, the output end of the 21st inverter is connected to the first input end of the first two-input NAND gate, and the output end of the first two-input NAND gate is the second output end of the timing circuit.

[0011] Further, the PUF core circuit includes W PUF unit arrays and W latches, each PUF unit array has a power supply terminal, a ground terminal, a clock signal input terminal, m word line level signal input terminals, 2 screening level input terminals and 2 output terminals, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, each latch has 2 input terminals and 1 output terminal, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the power supply terminals of the W PUF unit arrays are connected, and the connection terminal is the power supply terminal of the PUF core circuit, the ground terminals of the W PUF unit arrays are connected, and the connection terminal is the ground terminal of the PUF core circuit, the first screening level input terminals of the W PUF unit arrays are connected, And its connection end is the first screening level input end of the PUF core circuit, the second screening level input end of the W PUF unit arrays is connected, and its connection end is the second screening level input end of the PUF core circuit, the clock signal input end of the W PUF unit arrays is connected, and its connection end is the clock signal input end of the PUF core circuit, the i-th word line level signal input end of the W PUF unit arrays is connected, and its connection end is the i-th word line level signal input end of the PUF core circuit, i=1, 2, ..., m, the first output end of the b-th PUF unit array is connected to the first input end of the b-th latch, the second output end of the b-th PUF unit array is connected to the second input end of the b-th latch, b=1, 2, ..., W, the output ends of the W latches are the W output ends of the PUF core circuit;Each of the PUF unit arrays includes a decision unit and m PUF units, each PUF unit has a word line level signal input terminal, two screening level input terminals and four output terminals, the four output terminals are respectively referred to as the first output terminal, the second output terminal, the third output terminal and the fourth output terminal, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the decision unit has a power supply terminal, a ground terminal, a clock signal input terminal, two input terminals and two output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, the word line level signal input terminals of the m PUF units are the m word line level signal input terminals of the PUF unit array, the first screening level input terminals of the m PUF units are connected, and the connection terminal is the first screening level input terminal of the PUF unit array. The first input end of the decision unit is connected to the third output end of the m PUF units, the second input end of the decision unit is connected to the fourth output end of the m PUF units, the first output end of the decision unit is connected to the first output end of the m PUF units, and the connection end is the first output end of the PUF unit array, the second output end of the decision unit is connected to the second output end of the m PUF units, and the connection end is the second output end of the PUF unit array. ;

[0012] Further, the judgment unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all PMOS tubes, the fifth MOS tube and the sixth MOS tube are all NMOS tubes, the source of the first MOS tube, the source of the second MOS tube, the source of the third MOS tube and the source of the fourth MOS tube are connected, and the connection end thereof is the power supply end of the judgment unit, the source of the fifth MOS tube is connected to the source of the sixth MOS tube, and the connection end thereof is the ground end of the judgment unit, and the The gate of the third MOS tube is connected to the gate of the fourth MOS tube, and the connection end thereof is the clock signal input end of the judgment unit, the drain of the first MOS tube, the drain of the third MOS tube, the gate of the second MOS tube and the gate of the sixth MOS tube are connected, and the connection end thereof is the first output end of the judgment unit, the drain of the second MOS tube, the drain of the fourth MOS tube, the gate of the first MOS tube and the gate of the fifth MOS tube are connected, and the connection end thereof is the second output end of the judgment unit, the drain of the fifth MOS tube is the first input end of the judgment unit, and the drain of the sixth MOS tube is the second input end of the judgment unit.

[0013] Further, each PUF unit includes a seventh MOS tube, an eighth NMOS tube, a ninth MOS tube and a tenth MOS tube, the seventh MOS tube, the eighth NMOS tube, the ninth MOS tube and the tenth MOS tube are all NMOS tubes, the drain of the seventh MOS tube is the first output end of the PUF unit, the drain of the eighth MOS tube is the second output end of the PUF unit, the drain of the ninth MOS tube is the third output end of the PUF unit, the drain of the tenth MOS tube is the fourth output end of the PUF unit, the source of the seventh MOS tube is connected to the source of the ninth MOS tube, the source of the eighth MOS tube is connected to the source of the tenth MOS tube, the gate of the seventh MOS tube is connected to the gate of the eighth MOS tube, and the connection end thereof is the word line level signal input end of the PUF unit, the gate of the ninth MOS tube is the first screening level input end of the PUF unit, and the gate of the tenth MOS tube is the second screening level input end of the PUF unit.

[0014] Furthermore, each of the latches includes two NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two NAND gates are respectively referred to as a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is the first input terminal of the latch, the first input terminal of the second NAND gate is the second input terminal of the latch, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the connection terminal thereof is the output terminal of the latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The overall structure diagram of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention;

[0016] Figure 2 A circuit diagram of a sequential circuit of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0017] Figure 3 A circuit diagram of a PUF core circuit of a bistable weak PUF circuit capable of autonomously selecting stable bits according to the present invention;

[0018] Figure 4 A circuit diagram of a PUF unit array of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0019] Figure 5 A circuit diagram of a decision unit of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0020] Figure 6 A circuit diagram of a PUF unit of a bistable weak PUF circuit capable of autonomously selecting stable bits according to the present invention;

[0021] Figure 7 A circuit diagram of a latch of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0022] Figure 8 The layout of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention;

[0023] Fig. 9 A grayscale image of the PUF response of the bistable weak PUF circuit capable of autonomously selecting stable bits according to the present invention;

[0024] Fig.10 It is an average grayscale image of the PUF response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention;

[0025] Fig.11It is a simulation diagram of the normalized inter-chip Hamming distance and intra-chip Hamming distance of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention;

[0026] Fig.12 A diagram showing the ratio of unstable bits of the PUF response of the bistable weak PUF circuit capable of autonomously selecting stable bits according to the present invention;

[0027] Fig.13 This is a graph showing the unstable bit ratio of the PUF response after 5mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0028] Fig.14 It is a graph showing the unstable bit ratio of the PUF response after 10mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0029] Fig.15 This is a graph showing the unstable bit ratio of the PUF response after 15mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0030] Fig.16 It is a graph showing the unstable bit ratio of the PUF response after 20mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0031] Fig.17 This is a diagram showing the unstable bit ratio of the PUF response after composite screening of different screening levels is performed on the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below with reference to the accompanying drawings.

[0033] Embodiment 1: Figure 1 As shown, a bistable weak PUF circuit capable of autonomously selecting stable bits includes a decoder, a timing circuit and a PUF core circuit; the decoder is used to access n-bit excitation signals C1-C n , and the n-bit excitation signal C1-C n Perform decoding operation to obtain m-bit word line level signal WL1-WL m Output to the PUF core circuit, n is an integer greater than or equal to 1, m = 2 n; The timing circuit is used to access the clock signal CLK and the enable signal CEN, perform AND operation on the clock signal CLK and the enable signal CEN, obtain the clock signal AEN for controlling the working timing of the decoder and output it to the decoder, and delay the clock signal AEN and invert it and perform NAND operation on the clock signal AEN to obtain the clock signal PRE for controlling the working timing of the PUF core circuit and output it to the PUF core circuit; The PUF core circuit is used to generate a W-bit PUF response in each clock cycle of the clock signal PRE under the control of the m-bit word line level signal output by the decoder, where W is an integer greater than or equal to 1; The PUF core circuit has the function of autonomously screening stable bits. The PUF core circuit realizes stable bit screening by accessing two screening levels. When the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit is controlled by the m-bit word line level signal output by the decoder at the clock The W-bit PUF response generated within one clock cycle of the signal PRE is used as the original PUF response of the clock cycle, and then the m-bit word line level signal connected to the PUF core circuit is kept unchanged, and one of the two screening levels connected to the PUF core circuit is first kept unchanged, while the other is reduced by a certain amplitude, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the first screening PUF response, and then the two screening levels are exchanged, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the second screening PUF response, and the first screening PUF response and the second screening PUF response are XOR-operated to obtain a W-bit stability mark value, and if the value of a certain bit in the W-bit stability mark value is 1, it is considered that the response value of this bit in the original PUF response under the current excitation signal is an unstable response. In this embodiment, the decoder has n excitation signal input terminals, 1 clock signal input terminal and m output terminals; the timing circuit has 2 input terminals and 2 output terminals, the 2 input terminals are respectively referred to as the first input terminal and the second input terminal, and the 2 output terminals are respectively referred to as the first output terminal and the second output terminal, the PUF core circuit has a power supply terminal, a ground terminal, m word line level signal input terminals, 1 clock signal input terminal, 2 screening level input terminals and W output terminals, and the n excitation signal input terminals of the decoder are used to access the n-bit excitation signals C1-C n, the m output terminals of the decoder are used to output m-bit word line level signals, the m output terminals of the decoder are connected one-to-one with the m word line level signal input terminals of the PUF core circuit, the first input terminal of the timing circuit is connected to the enable signal CEN, the second input terminal is connected to the clock signal CLK, the first output terminal of the timing circuit is connected to the clock signal input terminal of the decoder, the first output terminal of the timing circuit outputs the clock signal AEN, the second output terminal of the timing circuit is connected to the clock signal input terminal of the PUF core circuit, the second output terminal of the timing circuit outputs the clock signal PRE, the power supply terminal of the PUF core circuit is used to connect to the working power supply VDD, the ground terminal of the PUF core circuit is used to connect to the ground voltage VSS, and the W output terminals of the PUF core circuit are used to output the W-bit PUF response Z1-Z W , the two screening level input terminals of the PUF core circuit are connected to the screening level V L and V R .

[0034] In this embodiment, two screening levels are connected to the PUF core circuit to perform unstable response detection. When the PUF core circuit generates a W-bit PUF response of a certain clock cycle, the m-bit word line level signal connected thereto is kept unchanged. Two equal screening levels are first connected to generate an original PUF response, and then two unequal screening levels are connected to generate two screened PUF responses. When the two screening levels are unequal, an unstable response value in the original PUF response will flip. If there is an unstable response in the original PUF response, the unstable response will flip, so that the two screened PUF responses are XORed. The corresponding bit value in the W-bit stability mark value obtained after the operation will be 1. At this time, if the value of a certain bit in the W-bit stability mark value is 1, it is considered that the response value of this bit in the original PUF response under the current excitation signal is an unstable response. If there is no unstable response in the original PUF response, no flipping will occur at this time, and all bits of the W-bit stability mark value will be completely 0. Therefore, the unstable response can be screened out, with high stability, and unstable screening can be achieved by only connecting two screening levels and making the two screening levels equal and unequal. No additional devices are required, the hardware overhead is small, and the detection cost is low. Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, if Figure 2As shown, the sequential circuit includes a D flip-flop LA1, 21 inverters INV1-INV21, a two-input AND gate AND1 and a first two-input NAND gate NAND1, the D flip-flop LA1 has an input terminal, a clock terminal and an output terminal, the two-input AND gate AND1 has a first input terminal, a second input terminal and an output terminal, the first two-input NAND gate NAND1 has a first input terminal, a second input terminal and an output terminal, the input terminal of the D flip-flop LA1 is the first input terminal of the sequential circuit, the clock terminal of the D flip-flop LA1 is connected to the second input terminal of the two-input AND gate AND1, and its connection terminal is the second input terminal of the sequential circuit. The output end of the D flip-flop LA1 is connected to the first input end of the two-input AND gate AND1, the output end of the two-input AND gate AND1, the input end of the first inverter and the second input end of the first two-input NAND gate NAND1 are connected, and the connection end is the first output end of the timing circuit, the output end of the kth inverter is connected to the input end of the k+1th inverter, k=1, 2,…, 20, the output end of the 21st inverter INV1-INV21 is connected to the first input end of the first two-input NAND gate NAND1, and the output end of the first two-input NAND gate NAND1 is the second output end of the timing circuit.

[0035] In this embodiment, when the timing circuit is working, the enable signal CEN is input into the D flip-flop LA1. Under the control of the clock signal CLK, the D flip-flop LA1 outputs the enable signal CEN through its output terminal in each cycle of the clock signal CLK. At this time, the enable signal CEN and the clock signal CLK are ANDed through the first and second input AND gates AND1 to obtain the clock signal AEN output. At the same time, the clock signal AEN and the signal obtained by inverting it in turn through 21 inverters INV1-INV21 are ANDed through the first and second input NAND gates NAND1 to obtain the clock signal PRE output, thereby realizing the overall timing control of the bistable weak PUF circuit that can autonomously screen stable bits.

[0036] Embodiment 3: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figure 3 and Figure 4As shown, the PUF core circuit includes W PUF unit arrays and W latches, each PUF unit array has a power supply terminal, a ground terminal, a clock signal input terminal, m word line level signal input terminals, 2 screening level input terminals and 2 output terminals, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, each latch has 2 input terminals and 1 output terminal, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the power supply terminals of the W PUF unit arrays are connected, and the connection terminal is the power supply terminal of the PUF core circuit, the ground terminals of the W PUF unit arrays are connected, and the connection terminal is the ground terminal of the PUF core circuit, the first screening level input terminals of the W PUF unit arrays are connected The first output terminal of the bth PUF cell array is connected to the first input terminal of the bth latch, the second output terminal of the bth PUF cell array is connected to the second input terminal of the bth latch, b=1, 2, ..., W, and the output terminals of the W latches are the W output terminals of the PUF core circuit;Each PUF unit array includes 1 decision unit and m PUF units, each PUF unit has 1 word line level signal input terminal, 2 screening level input terminals and 4 output terminals, the 4 output terminals are respectively referred to as the first output terminal, the second output terminal, the third output terminal and the fourth output terminal, the 2 screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the decision unit has a power supply terminal, a ground terminal, 1 clock signal input terminal, 2 input terminals and 2 output terminals, the 2 input terminals are respectively referred to as the first input terminal and the second input terminal, the 2 output terminals are respectively referred to as the first output terminal and the second output terminal, the word line level signal input terminals of the m PUF units are the m word line level signal input terminals of the PUF unit array, the first screening level input terminals of the m PUF units are connected, and the connection The first terminal of the decision unit is connected to the first screening level input terminal of the PUF unit array, the second screening level input terminals of the m PUF units are connected, and the connection terminal thereof is the second screening level input terminal of the PUF unit array, the power supply terminal of the decision unit is the power supply terminal of the PUF unit array, the ground terminal of the decision unit is the ground terminal of the PUF unit array, the clock signal input terminal of the decision unit is the clock signal input terminal of the PUF unit array, the first input terminal of the decision unit is connected to the third output terminals of the m PUF units, the second input terminal of the decision unit is connected to the fourth output terminals of the m PUF units, the first output terminal of the decision unit is connected to the first output terminals of the m PUF units, and the connection terminal thereof is the first output terminal of the PUF unit array, the second output terminal of the decision unit is connected to the second output terminals of the m PUF units, and the connection terminal thereof is the second output terminal of the PUF unit array. ;

[0037] In this embodiment, when the PUF core circuit is in operation, the decoder outputs the m-bit word line level signals WL1-WL m Only one of them is high level, and the remaining m-1 bits are low level. In each clock cycle of the clock signal PRE, only m-bit word line level signals WL1-WL1 are connected in each PUF unit array. mA PUF unit with a high level in the PUF array is selected and is in working state, and other PUF units are not selected and are in standby state and do not participate in work. When a PUF unit in the PUF unit array is selected, the clock signal PRE is at a low level at this time, and the decision unit in the PUF unit array enters the charging stage. The decision unit in the PUF unit array charges the selected PUF unit, so that the first output end, the second output end, the third output end and the fourth output end of the PUF unit are all pre-charged to be equal to the high level VDD, and then PRE becomes a high level, and the decision unit in the PUF unit array enters the judgment stage. In the decision evaluation stage, due to inevitable random process deviations, the discharge rates of the first output terminal and the second output terminal of the PUF unit are different, so that the discharge rates of the first output terminal and the second output terminal of the decision unit are also different. The decision unit further pulls down the signal of the output with a faster discharge rate among the first output terminal and the second output terminal of the PUF unit to VSS, and pulls up the signal of the output with a slower discharge rate to close to VDD. The latch connected to the PUF unit judges the signals output by the first output terminal and the second output terminal of the PUF unit to obtain a corresponding PUF response.

[0038] Embodiment 4: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figure 5 As shown, the judgment unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube M6. The first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are all PMOS tubes, the fifth MOS tube M5 and the sixth MOS tube M6 are all NMOS tubes, the source of the first MOS tube M1, the source of the second MOS tube M2, the source of the third MOS tube M3 and the source of the fourth MOS tube M4 are connected, and the connection end thereof is the power supply end of the judgment unit, the source of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6, and the connection end thereof is the power supply end of the judgment unit. The gate of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4, and the connection end thereof is the clock signal input end of the decision unit; the drain of the first MOS tube M1, the drain of the third MOS tube M3, the gate of the second MOS tube M2 and the gate of the sixth MOS tube M6 are connected, and the connection end thereof is the first output end of the decision unit; the drain of the second MOS tube M2, the drain of the fourth MOS tube M4, the gate of the first MOS tube M1 and the gate of the fifth MOS tube M5 are connected, and the connection end thereof is the second output end of the decision unit; the drain of the fifth MOS tube M5 is the first input end of the decision unit, and the drain of the sixth MOS tube M6 is the second input end of the decision unit.

[0039] In this embodiment, when the decision unit is working, when the clock signal PRE is at a low level, the third MOS tube M3 and the fourth MOS tube M4 of the decision unit are both turned on, and the decision unit enters the pre-charging stage, and the voltage values ​​of the first output terminal and the second output terminal thereof gradually increase to VDD, so that the first MOS tube M1 and the second MOS tube M2 are both turned off, and the fifth MOS tube M5 and the sixth MOS tube M6 are both turned on. When the clock signal PRE is at a high level, the third MOS tube M3 and the fourth MOS tube M4 of the decision unit are both turned off, and the decision unit performs the decision evaluation stage. Due to the inevitable random process deviation, the discharge rate between the first output terminal and the second output terminal of the PUF unit is different. At this time, the discharge rate between the first output terminal and the second output terminal of the decision unit is also different. The one with a faster discharge rate of the first output terminal and the second output terminal of the decision unit will be pulled down to VSS, and the one with a slower discharge rate will be pulled up to close to VD D. Specifically, there are the following two situations: if the first output end of the decision unit discharges faster, the second MOS tube M2 will be the first to be turned on, and the sixth MOS tube M6 will be the first to be turned off, so that the second output end of the decision unit is charged, and the voltage value of the second output end of the decision unit will interrupt the decline and gradually increase to approach VDD, thereby further turning off the first MOS tube M1 and turning on the fifth MOS tube M5, so that the voltage value of the first output end of the decision unit is further pulled down to VSS; if the second output end of the decision unit discharges faster, the first MOS tube M1 will be the first to be turned on, and the fifth MOS tube M5 will be the first to be turned off, so that the first output end of the decision unit is charged, and the voltage value of the first output end of the decision unit will interrupt the decline and gradually increase to approach VDD, thereby further turning off the second MOS tube M2 and turning on the sixth MOS tube M6, so that the voltage value of the second output end of the decision unit is further pulled down to VSS.

[0040] Embodiment 5: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figure 6As shown, each PUF unit includes a seventh MOS tube M7, an eighth NMOS tube, a ninth MOS tube M9 and a tenth MOS tube M10. The seventh MOS tube M7, the eighth NMOS tube, the ninth MOS tube M9 and the tenth MOS tube M10 are all NMOS tubes. The drain of the seventh MOS tube M7 is the first output end of the PUF unit, the drain of the eighth MOS tube M8 is the second output end of the PUF unit, the drain of the ninth MOS tube M9 is the third output end of the PUF unit, and the drain of the tenth MOS tube M10 is the fourth output end of the PUF unit. The source of the seventh MOS tube M7 is connected to the source of the ninth MOS tube M9, the source of the eighth MOS tube M8 is connected to the source of the tenth MOS tube M10, the gate of the seventh MOS tube M7 is connected to the gate of the eighth MOS tube M8, and the connection end thereof is the word line level signal input end of the PUF unit, the gate of the ninth MOS tube M9 is the first screening level input end of the PUF unit, and the gate of the tenth MOS tube M10 is the second screening level input end of the PUF unit.

[0041] In this embodiment, the PUF unit adopts a twin structure and is composed of only four NMOS tubes of minimum size. By comparing the subthreshold leakage currents of a group of MOS tubes of the same size and symmetrical structure, the final output response is obtained through quantization, thereby further reducing the hardware overhead of the PUF unit.

[0042] In this embodiment, the PUF unit determines whether it is selected according to the word line level signal connected to its word line level signal input terminal. When the word line level signal connected to its word line level signal input terminal is at a low level, the PUF unit is not selected and does not participate in the work. When the word line level signal connected to its word line level signal input terminal is at a high level, the PUF unit is selected to participate in the work. When the PUF unit is selected, the PUF unit first enters the charging stage, the seventh MOS tube M7 and the eighth NMOS tube are both turned on, the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the PUF unit are first pre-charged to the high level VDD, and then the PUF unit enters the evaluation stage, the seventh MOS tube M7 and the eighth NMOS tube are both turned on, and generally the screening level V connected to its first screening level input terminal is L Equal to the V connected to its second screening level input R , both equal to 325mV, the first output end of the PUF unit is discharged through the seventh MOS tube M7 and the ninth NMOS tube M9, and the second output end of the PUF unit is discharged through the eighth MOS tube M8 and the tenth NMOS tube M10. If screening is required, keep the screening level V L and V R Keep one of them unchanged and change the other one to make the screening level V L Not equal to V RAt this time, the gate voltages of the ninth NMOS tube M9 and the tenth NMOS tube M10 are different, resulting in differences in the conduction degrees of the ninth NMOS tube M9 and the tenth NMOS tube M10, so that the charge leakage speed of the first output end and the second output end of the decision unit connected to the PUF unit will be affected not only by the random process deviation of the seventh MOS tube M7 and the eighth MOS tube M8, but also by the deviation of the ninth NMOS tube M9 and the tenth NMOS tube M10 added artificially. Then the original response (only affected by the random process deviation of the seventh MOS tube M7 and the eighth MOS tube M8) is compared with the deviation added artificially, so as to screen out the stable bit and the unstable bit.

[0043] Embodiment 6: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figure 7 As shown, each latch includes two NAND gates, each NAND gate has a first input terminal, a second input terminal and an output terminal, and the two NAND gates are respectively referred to as a first NAND gate U1 and a second NAND gate U2. The first input terminal of the first NAND gate U1 is the first input terminal of the latch, the first input terminal of the second NAND gate U2 is the second input terminal of the latch, the second input terminal of the first NAND gate U1 is connected to the output terminal of the second NAND gate U2, the second input terminal of the second NAND gate U2 is connected to the output terminal of the first NAND gate U1, and the connection terminal thereof is the output terminal of the latch.

[0044] In this embodiment, when the first input terminal of the latch is connected to a high level and the second input terminal is connected to a low level, the output terminal of the first NAND gate U1 outputs a high level, and the output terminal of the second NAND gate U2 is a low level. At this time, the output terminal of the latch outputs a high level. When the second input terminal of the latch is connected to a high level and the first input terminal is connected to a low level, the output terminal of the first NAND gate U1 is reset to a low level, and the output terminal of the second NAND gate U2 outputs a high level. At this time, the output terminal of the latch outputs a low level.

[0045] X mV composite screening refers to placing the bistable weak PUF circuit that can independently screen the stable bit at the golden working point, that is, the working environment temperature is 27℃ and the working power supply voltage VDD is 1.2V; and 4 extreme working points, that is, the working environment temperature is -40℃ and the working power supply voltage VDD is 1.0V, the temperature is -40℃ and the working power supply voltage VDD is 1.4V, the temperature is 125℃ and the working power supply voltage VDD is 1.0V, and the temperature is 125℃ and the working power supply voltage VDD is 1.4V. The same screening operation is performed under the above 5 working points respectively, and X represents the screening level V L or V R The amplitude is reduced compared to 325mV. Under a certain excitation signal, the first screening level V LSet to 325mV, the second screening level V R Set to 325mV, and after obtaining the original PUF response, screening is performed. The specific screening operation is as follows: Step 1: Set the first screening level V in all PUF units in the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit L Set to 325-X mV, the second screening level V R The first screening level V in the PUF unit in the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit is set to 325mV. At this time, according to the input excitation signal, the decoder outputs an m-bit word line level signal, and the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit outputs the first W-bit PUF response value. Step 2: Set the first screening level V in the PUF unit in the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit to 325mV. L Set to 325mV, the second screening level V L Set to 325-X mV, and then give the same excitation signal as in the first step, and the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit outputs the second W-bit PUF response value. Step 3: XOR the first W-bit PUF response value with the second W-bit PUF response value to obtain a W-bit stability mark value. If the value of a certain bit of the W-bit stability mark value is 0, then the bit of the original PUF response under the excitation signal is determined to be a stable PUF response. If the value of a certain bit of the W-bit stability mark value is 1, then the bit of the original PUF response under the excitation signal is determined to be a PUF response that is prone to jump.

[0046] The bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention is implemented using TSMC 65nm technology. The chip layout is as follows: Figure 8 As shown. The layout includes 4 bistable weak PUF circuits capable of autonomously selecting stable bits of the present invention and 1 BIST test circuit. The BIST test circuit is mainly used to perform serial-to-parallel and parallel-to-serial conversion on the input and output data of the 4 bistable weak PUF circuits capable of autonomously selecting stable bits of the present invention (shared by the 4 bistable weak PUF circuits capable of autonomously selecting stable bits of the present invention). The PUF unit area is only 1.728μm 2 The characteristic size of a single PUF unit is only 204.5F 2 .

[0047] Randomness is an important property of PUF. The output responses of different PUF units are arranged according to their spatial position to form a grayscale matrix to intuitively observe the distribution of 0 and 1 of the output responses. Fig. 9 A grayscale image of the output response of a randomly selected individual bistable weak PUF circuit that can autonomously select stable bits is given, where white pixels and black pixels are used to mark responses 1 and 0, respectively. Fig. 9It can be seen that the probabilities of "1" and "0" in the response are 50.03% and 49.97% respectively, which are close to the ideal value of 50%. The average grayscale diagram of the response bit of 10 bistable weak PUF circuit individuals that can autonomously screen stable bits of the present invention is shown in Fig.10 Analysis Fig.10 It can be seen that the grayscale value is concentrated around 0.5, and no obvious spatial artifacts are observed. Therefore, it can be seen that the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention has good randomness.

[0048] Reliability is an extremely important performance indicator of PUF, which is usually measured by the intra-chip Hamming distance. The intra-chip Hamming distance is the statistical characteristic of the response change of the same PUF circuit individual under the same excitation signal in different environments. The normalized inter-chip Hamming distance and intra-chip Hamming distance of the bistable weak PUF circuit that can autonomously select stable bits of the present invention are shown in the figure below: Fig.11 Analysis Fig.11 It can be seen that the average intra-chip Hamming distance of the bistable weak PUF that can autonomously select stable bits of the present invention is 0.00379, and the reliability is 99.6%. Fig.11 It can be seen that the HD of the bistable weak PUF of the present invention that can autonomously select stable positions inter With HD intra The ratio of is more than 130, indicating that the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention has good recognition

[0049] In order to characterize the stability of the output response of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention, the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention was read repeatedly 100 times at different temperatures and voltages to obtain the statistical results of the bit error rate and unstable bit ratio of the output response at different temperatures and voltages. The original unstable bit ratio of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention in the range of -40℃~125℃, 1.0V~1.4V is shown in the figure below: Fig.12 Analysis Fig.12 It can be seen that when the voltage changes within the range of 1.0V to 1.4V and the temperature changes within the range of -40℃ to 125℃, the maximum bit error rate (unstable bit ratio) of the output response of the bistable weak PUF circuit that can autonomously screen stable bits of the present invention is 10.62% (12.17%) @1.0V / 125℃. It can be seen that the output response of the bistable weak PUF circuit that can autonomously screen stable bits of the present invention has good robustness.

[0050] The bistable weak PUF circuit capable of autonomously screening stable bits of the present invention was subjected to four X mV ​​composite screenings. In the three X mV ​​composite screenings, X mV ​​was 5 mV, 10 mV, 15 mV and 20 mV respectively. The unstable bit ratio of the PUF response after the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention was subjected to 5 mV composite screening is shown in FIG. Fig.13 As shown; the unstable bit ratio of the PUF response after 10mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is shown in FIG. Fig.14 As shown; the unstable bit ratio of the PUF response after the screening level 15mV composite screening of the bistable weak PUF circuit of the present invention that can autonomously screen the stable bit is shown as Fig.15 As shown; the unstable bit ratio of the PUF response after the screening level 20mV composite screening of the bistable weak PUF circuit of the present invention that can independently screen the stable bit is as shown Fig.16 as shown.

[0051] analyze Fig.13 It can be seen that after the 5mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is reduced to 2.21%. Fig.14 It can be seen that after the 10mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is reduced to 0.22%. Fig.15 It can be seen that after the 15mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is reduced to 0.04%. Fig.16 It can be seen that after 20mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is reduced to 0.01%. It can be seen that the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention has high stability.

[0052] In order to evaluate the screening efficiency of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention, in addition to paying attention to the proportion of unstable bits after screening, it is also necessary to pay attention to the proportion of originally stable bits marked as unstable bits, that is, the false screening rate. The unstable bit proportion of the PUF response after the composite screening of different screening levels of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is shown in the figure. Fig.17 As shown. Fig.17 As shown, the average false positive rate of the bistable weak PUF circuit capable of autonomously screening stable bits in the 20mV composite screening is 24.44%, and the maximum unstable bit accounts for 0.01%. It can be seen that the screening efficiency of the bistable weak PUF circuit capable of autonomously screening stable bits in the present invention is relatively high.

[0053] In summary, the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention can achieve unstable screening by only connecting two screening levels and making the two screening levels equal or unequal, without the need for additional devices, with low hardware overhead and low detection cost. The MPW tape-out is carried out through TSMC 65nm CMOS process, and the total area of ​​the PUF core circuit is 4455μm 2 , single bit feature size is only 204.5F 2 The chip test results show that the bistable weak PUF circuit of the present invention that can autonomously screen stable bits has good randomness (50.03%), uniqueness (48.8%), and reliability (99.6%). When the temperature is between -40℃ and 125℃ and the voltage varies between 1.0V and 1.4V, the maximum unstable bit ratio can be reduced from 12.17% to nearly 0 (less than 1×10 -4 The bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention has outstanding performance in terms of hardware overhead and stability, and is very suitable for security protection of the Internet of Things.

Claims

1. A bistable weak PUF circuit capable of autonomously selecting stable bits, characterized in that It includes a decoder, a timing circuit and a PUF core circuit; the decoder is used to access the n-bit excitation signal C1-C n , and the n-bit excitation signal C1-C n Perform decoding operation to obtain m-bit word line level signal WL1-WL m Output to the PUF core circuit, n is an integer greater than or equal to 1, m = 2 n ; The timing circuit is used to access the clock signal CLK and the enable signal CEN, perform AND operation on the clock signal CLK and the enable signal CEN, obtain the clock signal AEN for controlling the working timing of the decoder and output it to the decoder, and delay the clock signal AEN and invert it and perform NAND operation on the clock signal AEN to obtain the clock signal PRE for controlling the working timing of the PUF core circuit and output it to the PUF core circuit; The PUF core circuit is used to generate a W-bit PUF response in each clock cycle of the clock signal PRE under the control of the m-bit word line level signal outputted thereto by the decoder, where W is an integer greater than or equal to 1; The PUF core circuit has the function of autonomously screening stable bits, and the PUF core circuit realizes stable bit screening by accessing two screening levels. When the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit outputs to the decoder. Under the control of the m-bit word line level signal, the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the original PUF response of the clock cycle, and then the m-bit word line level signal connected to the PUF core circuit is kept unchanged, and one of the two screening levels connected to the PUF core circuit is first kept unchanged, while the other is reduced by a certain amplitude, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the first screening PUF response, and then the two screening levels are exchanged, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the second screening PUF response, and the first screening PUF response and the second screening PUF response are XOR-operated to obtain a W-bit stability mark value, and if the value of a certain bit in the W-bit stability mark value is 1, it is considered that the response value of this bit in the original PUF response under the current excitation signal is an unstable response.

2. A bistable weak PUF circuit capable of autonomously selecting stable bits according to claim 1, characterized in that The decoder has n excitation signal input terminals, 1 clock signal input terminal and m output terminals; the timing circuit has 2 input terminals and 2 output terminals, the 2 input terminals are respectively referred to as the first input terminal and the second input terminal, the 2 output terminals are respectively referred to as the first output terminal and the second output terminal, the PUF core circuit has a power supply terminal, a ground terminal, m word line level signal input terminals, 1 clock signal input terminal, 2 screening level input terminals and W output terminals, the n excitation signal input terminals of the decoder are used to access the n-bit excitation signals C1-C n , the m output ends of the decoder are used to output m-bit word line level signals, the m output ends of the decoder are connected one-to-one with the m word line level signal input ends of the PUF core circuit, the first input end of the timing circuit is connected to the enable signal CEN, the second input end is connected to the clock signal CLK, the first output end of the timing circuit is connected to the clock signal input end of the decoder, the first output end of the timing circuit outputs the clock signal AEN, the second output end of the timing circuit is connected to the clock signal input end of the PUF core circuit, the second output end of the timing circuit outputs the clock signal PRE, the power supply end of the PUF core circuit is used to connect to the working power supply VDD, the ground end of the PUF core circuit is used to connect to the ground voltage VSS, and the W output ends of the PUF core circuit are used to output the W-bit PUF response Z1-Z W The two screening level input terminals of the PUF core circuit are respectively connected to the screening level V L and V R .

3. A bistable weak PUF circuit capable of autonomously selecting stable bits according to claim 2, characterized in that The timing circuit includes a D flip-flop, 21 inverters, a two-input AND gate and a first two-input NAND gate, wherein the D flip-flop has an input terminal, a clock terminal and an output terminal, the two-input AND gate has a first input terminal, a second input terminal and an output terminal, the first two-input NAND gate has a first input terminal, a second input terminal and an output terminal, the input terminal of the D flip-flop is connected to the first input terminal of the timing circuit, the clock terminal of the D flip-flop and the second input terminal of the two-input AND gate, and its connection terminal is the second input terminal of the timing circuit, the The output end of the D flip-flop is connected to the first input end of the two-input AND gate, the output end of the two-input AND gate, the input end of the first inverter and the second input end of the first two-input NAND gate are connected, and the connection end is the first output end of the timing circuit, the output end of the kth inverter is connected to the input end of the k+1th inverter, k=1, 2, ..., 20, the output end of the 21st inverter is connected to the first input end of the first two-input NAND gate, and the output end of the first two-input NAND gate is the second output end of the timing circuit.

4. A bistable weak PUF circuit capable of autonomously selecting stable bits according to claim 2, characterized in that The PUF core circuit includes W PUF unit arrays and W latches, each PUF unit array has a power supply terminal, a ground terminal, a clock signal input terminal, m word line level signal input terminals, 2 screening level input terminals and 2 output terminals, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, each latch has 2 input terminals and 1 output terminal, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the power supply terminals of the W PUF unit arrays are connected, and the connection terminal is the power supply terminal of the PUF core circuit, the ground terminals of the W PUF unit arrays are connected, and the connection terminal is the ground terminal of the PUF core circuit, the first screening level input terminals of the W PUF unit arrays are connected, and the The connection end is the first screening level input end of the PUF core circuit, the second screening level input end of the W PUF unit arrays is connected, and its connection end is the second screening level input end of the PUF core circuit, the clock signal input end of the W PUF unit arrays is connected, and its connection end is the clock signal input end of the PUF core circuit, the i-th word line level signal input end of the W PUF unit arrays is connected, and its connection end is the i-th word line level signal input end of the PUF core circuit, i=1, 2, ..., m, the first output end of the b-th PUF unit array is connected to the first input end of the b-th latch, the second output end of the b-th PUF unit array is connected to the second input end of the b-th latch, b=1, 2, ..., W, and the output ends of the W latches are the W output ends of the PUF core circuit;Each of the PUF unit arrays includes a decision unit and m PUF units, each PUF unit has a word line level signal input terminal, two screening level input terminals and four output terminals, the four output terminals are respectively referred to as the first output terminal, the second output terminal, the third output terminal and the fourth output terminal, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the decision unit has a power supply terminal, a ground terminal, a clock signal input terminal, two input terminals and two output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, the word line level signal input terminals of the m PUF units are the m word line level signal input terminals of the PUF unit array, the first screening level input terminals of the m PUF units are connected, and the connection terminal is the first screening level input terminal of the PUF unit array. The first input end of the decision unit is connected to the third output end of the m PUF units, the second input end of the decision unit is connected to the fourth output end of the m PUF units, the first output end of the decision unit is connected to the first output end of the m PUF units, and the connection end is the first output end of the PUF unit array, the second output end of the decision unit is connected to the second output end of the m PUF units, and the connection end is the second output end of the PUF unit array. ; 5. A bistable weak PUF circuit capable of autonomously selecting stable bits according to claim 4, characterized in that The judgment unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, wherein the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all PMOS tubes, the fifth MOS tube and the sixth MOS tube are all NMOS tubes, the source of the first MOS tube, the source of the second MOS tube, the source of the third MOS tube and the source of the fourth MOS tube are connected, and the connection end thereof is the power supply end of the judgment unit, the source of the fifth MOS tube is connected to the source of the sixth MOS tube, and the connection end thereof is the ground end of the judgment unit, and the first MOS tube is connected to the source of the sixth MOS tube, and the connection end thereof is the ground end of the judgment unit. The gate of the third MOS tube is connected to the gate of the fourth MOS tube, and the connection end thereof is the clock signal input end of the judgment unit; the drain of the first MOS tube, the drain of the third MOS tube, the gate of the second MOS tube and the gate of the sixth MOS tube are connected, and the connection end thereof is the first output end of the judgment unit; the drain of the second MOS tube, the drain of the fourth MOS tube, the gate of the first MOS tube and the gate of the fifth MOS tube are connected, and the connection end thereof is the second output end of the judgment unit; the drain of the fifth MOS tube is the first input end of the judgment unit, and the drain of the sixth MOS tube is the second input end of the judgment unit.

6. A bistable weak PUF circuit capable of autonomously selecting stable bits according to claim 4, characterized in that Each PUF unit includes a seventh MOS tube, an eighth NMOS tube, a ninth MOS tube and a tenth MOS tube, wherein the seventh MOS tube, the eighth NMOS tube, the ninth MOS tube and the tenth MOS tube are all NMOS tubes, the drain of the seventh MOS tube is the first output end of the PUF unit, the drain of the eighth MOS tube is the second output end of the PUF unit, the drain of the ninth MOS tube is the third output end of the PUF unit, the drain of the tenth MOS tube is the fourth output end of the PUF unit, the source of the seventh MOS tube is connected to the source of the ninth MOS tube, the source of the eighth MOS tube is connected to the source of the tenth MOS tube, the gate of the seventh MOS tube is connected to the gate of the eighth MOS tube, and the connection end thereof is the word line level signal input end of the PUF unit, the gate of the ninth MOS tube is the first screening level input end of the PUF unit, and the gate of the tenth MOS tube is the second screening level input end of the PUF unit.

7. A bistable weak PUF circuit capable of autonomously selecting stable bits according to claim 4, characterized in that Each of the latches includes two NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two NAND gates are respectively referred to as a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is the first input terminal of the latch, the first input terminal of the second NAND gate is the second input terminal of the latch, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the connection terminal thereof is the output terminal of the latch.

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