Automatic time tracking method based on loop on-off keying and wireless data transmission system thereof

Abstract

The invention discloses a wireless uplink data transmission system based on a cyclic on-off keying (COOK) technology and an automatic time tracking (ATT) method thereof. The system comprises a COOK coding module, a PLL module, a dynamic comparator, a comparator, a short circuit switch and an ATT module. Wherein the ATT module generates a reference clock CLKUP aligned with a voltage signal cross point by selecting, adjusting and locking a clock phase generated by the VCO. And the clock is used as the input of the COOK coding module and is used for coding uplink data and controlling the on-off of the short-circuit switch. The ATT method comprises the specific steps of initial phase selection, frequency halving operation, voltage comparison, phase adjustment, frequency halving and comparison repeating, ATT completion judging and final selected CLKUP outputting, through the series of steps, an ATT module can automatically track and lock the cross point of a voltage signal, and it is ensured that a COOK modulation signal is accurately aligned with the cross point of the voltage signal.

Description

[Technical field]

[0001] The present invention relates to the field of wireless data transmission, and in particular to an automatic time tracking (ATT) optimization method based on cyclic on-off keying (COOK) and a wireless data transmission system thereof. [Background technology]

[0002] In recent years, with the advancement of medical and integrated circuit technology, implantable medical devices have been widely used in medical fields such as cochlear implants, retinal prostheses, and brain stimulators. These implanted devices collect internal signals and use wireless data transmission (WDT) technology to achieve data transmission from the body to the outside (uplink), providing doctors with real-time analysis and monitoring of the patient's internal conditions. In this field, wireless data transmission technology based on inductive links has become the mainstream choice due to its strong robustness and easy integration with wireless energy transmission systems.

[0003] The uplink data transmission technology based on the inductive link has a variety of modulation methods, such as load shift keying (LSK), phase shift keying (PSK), on-off keying (OOK), cyclic on-off keying (COOK), etc. Among them, the COOK modulation method (patent number US201515316835A) stands out due to its high power efficiency, simple structure, and high data transmission rate, becoming a modulation method more suitable for the needs of medical implants. Wireless data transmission systems based on COOK, such as Figure 1 As shown in the figure, the system as a whole includes a transmitter (Transmitter, TX), a receiver (Receiver, RX) and a pair of coupled coils. At the receiving end, the uplink data modulation module converts the encoded data into a COOK signal and sends the signal to the TX end through a short-circuit switch connected in parallel at both ends of the receiving coil. When the switch is disconnected, the current I L2 It circulates in the LC resonant circuit and is converted into DC through the subsequent rectifier module to provide energy for the subsequent functional modules; when the switch is closed, the capacitor is short-circuited and the current I L2 The switch is short-circuited, which means the load is short-circuited. This momentary disturbance causes the TX terminal V L The voltage amplitude at the position rises, and is thus detected by TX as uplink data. Figure 2As shown in the figure, it is necessary to ensure that the voltages VAC1 and VAC2 at both ends of the receiving coil are equal when the short-circuit switch is closed to minimize energy loss and achieve a higher modulation depth. In fact, due to various non-ideal factors (such as coil coupling, parasitic capacitance, parasitic resistance, etc.), VAC1 and VAC2 are often difficult to be completely equal. This mismatch not only increases energy loss, but also reduces the modulation depth, thereby affecting the accuracy and reliability of data transmission.

[0004] Therefore, in order to give full play to the advantages of COOK modulation and overcome its limitations, an optimization method is urgently needed to ensure that the intersection of VAC1 and VAC2 is accurately aligned when the switch is closed. This optimization method needs to comprehensively consider the influence of circuit parameters, switch action timing, and non-ideal factors to achieve more efficient and reliable wireless data transmission. [Summary of the invention]

[0005] The purpose of the present invention is to provide an ATT optimization method based on COOK, which utilizes a phase-locked loop (PLL) and dynamic comparator technology to automatically adjust and generate a clock signal (CLK_UP) for controlling the COOK switch to ensure that the switching action is accurately aligned with the intersection of the VAC1 and VAC2 voltages. It can automatically track the moment when the VAC1 and VAC2 voltages are equal, and align the COOK switch closing time with it, so as to increase the modulation depth while reducing energy loss and improving energy efficiency.

[0006] The technical solution of the present invention is as follows:

[0007] In one aspect, the present invention provides an automatic time tracking method based on cyclic on-off keying, which is characterized in that it comprises the following steps:

[0008] a) Selecting the initial phase: Among the N phases generated by the VCO in the PLL module, the most forward phase is selected as the initial phase;

[0009] b) First two-frequency division operation: the initial phase selected in step a) is divided into two frequencies to obtain a clock signal CLK_S;

[0010] c) Comparison voltage: At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the comparison result is recorded as CMP_REG, where CMP_REG is 1 when VAC1 is greater than VAC2, and CMP_REG is 0 when VAC1 is less than VAC2;

[0011] d) Adjusting the phase: selecting the next phase of the VCO clock as the new phase;

[0012] e) a second frequency division operation: performing a frequency division process on the adjacent subsequent phase selected in step d) to update and obtain a new clock signal CLK_S;

[0013] f) Repeat comparison: At the rising edge of the new CLK_S, the voltage signals VAC1 and VAC2 are compared again by the dynamic comparator, and the comparison result is recorded as CMP, where CMP is 1 when VAC1 is greater than VAC2, and CMP is 0 when VAC1 is less than VAC2;

[0014] g) Determine whether automatic time tracking is completed: compare the values ​​of CMP and CMP_REG. If they are not equal, it indicates that automatic time tracking is completed and execute step h); if they are equal, return to step d), continue to adjust the phase and repeat steps e) to f) until CMP and CMP_REG are not equal;

[0015] h) Output the final selected CLK_UP: Once the automatic time tracking is completed, the final selected CLK_S is output as CLK_UP as the clock source for subsequent circuit modules.

[0016] Furthermore, the N phases in step a) are continuous phases generated by the VCO within a preset frequency range.

[0017] Furthermore, the frequency division by two operations in steps b) and e) is implemented by a frequency divider, which is used to convert the phase generated by the VCO into the clock signal CLK_S.

[0018] Furthermore, the dynamic comparator in steps c) and f) has the characteristics of high-speed comparison and low delay to ensure accurate comparison of the voltage signals VAC1 and VAC2 at the rising edge of CLK_S.

[0019] Furthermore, the subsequent circuit module in step h) is a COOK uplink modulation module, and CLK_UP is used as the clock source of the module to achieve accurate transmission of uplink data.

[0020] Second, the present invention also provides a COOK wireless data transmission system based on ATT (automatic time tracking) optimization, which is characterized by including:

[0021] The COOK encoding module is used to receive uplink data (DATA_UP) and reference clock (CLK_UP), and use CLK_UP as the reference clock to COOK encode DATA_UP. The encoded COOK signal directly controls the on and off of the short-circuit switch to achieve wireless transmission of uplink data;

[0022] An ATT module, configured to execute the above method to generate a CLK_UP aligned with a cross point of voltage signals VAC1 and VAC2 across the receiving coil;

[0023] PLL module, used to lock the phase of the input signal;

[0024] A dynamic comparator, used for sampling and comparing voltage signals VAC1 and VAC2 at the rising edge of CLK_S, and outputting a comparison result CMP or CMP_REG;

[0025] CMP module, used to obtain the downlink carrier clock with the same frequency as the transmitter;

[0026] The short-circuit switch controls the on and off of the circuit according to the state of the COOK signal. When the COOK signal is 1, it is closed to allow current to pass. When the COOK signal is 0, it is opened to cut off the current.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1) Using technologies such as phase-locked loop (PLL) and dynamic comparator, the clock signal (CLK_UP) used to control the COOK switch is automatically adjusted to ensure that the switching action is precisely aligned with the VAC1 and VAC2 voltage crossing points, which can not only reduce energy loss but also improve the overall energy efficiency of the system and optimize the modulation depth.

[0029] 2) The ATT module accurately tracks the intersection of the voltage signals VAC1 and VAC2 at both ends of the receiving coil, and generates a COOK encoding reference clock CLK_UP aligned with it, ensuring accurate synchronization of data transmission, thereby significantly improving the accuracy and efficiency of data transmission.

[0030] 3) By dynamically adjusting the edge of the clock signal, the ATT module can ensure that the intersection points of the clock signal and the voltage signal are precisely aligned, further reducing errors and delays in data transmission.

[0031] 4) The combined use of the PLL module and the VCO component enables the system to generate an output signal that is synchronized with the input signal frequency and phase, further improving the stability and reliability of the system.

[0032] 5) The ATT module adopts a two-frequency operation and successive approximation (SAR) logic. By continuously comparing and adjusting the phase, it can automatically adapt to different voltage signal changes, thereby enhancing the robustness and stability of the system.

Brief Description of the Drawings

[0033] Figure 1 is a block diagram of an uplink wireless data transmission system based on COOK for example;

[0034] Figure 2 The working waveform of COOK and the working waveform assisted by ATT optimization method are shown;

[0035] Figure 3 It is the actual implementation circuit diagram of the COOK uplink wireless data transmission system with the ATT optimization method;

[0036] Figure 4 It is the COOK uplink encoding method used for the example;

[0037] Figure 5 is a PLL circuit structure used for example;

[0038] Figure 6 is a 20-phase VCO circuit structure used for example;

[0039] Figure 7 It is the successive approximation logic of the proposed ATT optimization method;

[0040] Figure 8 is a flow chart of the ATT optimization method provided by the present invention;

[0041] Fig. 9 It is the COOK test waveform in Example 1 without / with the assistance of the ATT optimization method. [Specific implementation method]

[0042] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present invention. But it is obvious to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, parts and algorithms without departing from the concept of the present invention. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid unnecessary ambiguity to the present invention.

[0043] Figure 3 A wireless data transmission system based on COOK optimized by AT&T, including:

[0044] COOK encoding module 1 receives uplink data (DATA_UP) and reference clock (CLK_UP), uses CLK_UP as reference clock, performs COOK encoding on uplink data DATA_UP, and the COOK signal generated after encoding directly controls the on and off of the short-circuit switch. The encoding method is as follows: Figure 4 shown.

[0045] ATT module 2: used to generate the COOK-coded reference clock CLK_UP aligned with the intersection of VAC1 and VAC2. The edges of the clock signal can be adjusted or optimized to ensure that they are precisely aligned with the intersection of VAC1 and VAC2, thereby improving the accuracy and efficiency of transmission.

[0046] PLL (Phase-Locked Loop) 3: used to generate an output signal synchronized with the input signal frequency and phase;

[0047] The internal components contain a voltage-controlled oscillator (VCO). The VCO can generate an N-phase clock, and the phase can cover a carrier cycle. The circuit diagram is as follows Figure 5 shown.

[0048] Latch CMP (dynamic comparator) 4: At the rising edge of the clock signal CLK_S, the voltage values ​​of VAC1 and VAC2 are sampled and compared.

[0049] CMP (comparator) 5: used to obtain a downlink carrier clock with the same frequency as the transmitting end.

[0050] Short-circuit switch 6: controls the on / off of the circuit according to the state of the COOK signal (1 or 0); when COOK is 1, it is closed to allow current to pass; when COOK is 0, it is opened to cut off the current.

[0051] ATT's SAR logic is as follows Figure 7 shown.

[0052] like Figure 8 As shown, the present invention provides an ATT method based on COOK, comprising the following steps:

[0053] Step 1: Select the initial phase

[0054] Among the N phases generated by the VCO in the PLL module, the first phase is selected as the initial phase. This initial phase will be used as the starting point for subsequent operations to generate clock signals and perform subsequent voltage comparisons.

[0055] Step 2: Two-way operation

[0056] The initial phase selected in step 1 is divided into two to obtain a clock signal CLK_S. This clock signal will be used in the subsequent dynamic comparator as a reference for comparing voltage signals.

[0057] Step 3: Compare Voltages

[0058] At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the comparison result is recorded as CMP_REG, where CMP_REG is 1 when VAC1 is greater than VAC2; and CMP_REG is 0 when VAC1 is less than VAC2.

[0059] Step 4: Adjust the phase

[0060] The next adjacent phase of the VCO clock is selected as the new phase, and preparation is made for the next frequency division operation and voltage comparison.

[0061] Step 5: Two-way frequency operation

[0062] The adjacent next phase selected in step 4 is divided into two and updated to obtain a new clock signal CLK_S. This new clock signal will be used for the next voltage comparison.

[0063] Step 6: Repeat the comparison

[0064] At the rising edge of the new CLK_S, the two voltage signals VAC1 and VAC2 are compared again by the dynamic comparator, and the comparison result is recorded as CMP. If VAC1 is greater than VAC2, CMP_REG is 1, and if VAC1 is less than VAC2, CMP_REG is 0.

[0065] Step 7: Determine whether automatic time tracking is completed

[0066] Compare the values ​​of CMP and CMP_REG:

[0067] If CMP and CMP_REG are not equal, it means that a point has been found by adjusting the phase to change the voltage signal relationship, that is, automatic time tracking has been completed. At this time, you can proceed to the next step to output the final selected clock signal;

[0068] If CMP is equal to CMP_REG, it means that the automatic time tracking is not completed and further phase adjustment is required. In this case, return to step 4, select the next adjacent phase of the VCO clock for binary division and comparison, and repeat the process from step 4 to step 7 until a phase point is found that makes CMP unequal to CMP_REG.

[0069] Step 8: Output the final selected CLK_UP

[0070] Once the automatic time tracking is completed, that is, the phase point that makes CMP and CMP_REG unequal is found, the finally selected CLK_S is output as CLK_UP, which is used as the clock source of the COOK switch and is used in the subsequent COOK uplink modulation module.

[0071] The number of phases of the VCO in step 1 determines the accuracy of ATT. The more phases, the higher the accuracy.

[0072] Example 1

[0073] This embodiment discloses an automatic time tracking (ATT) method based on cyclic on-off keying (COOK) technology. The method is applied to a wireless uplink data transmission system. The system adopts COOK modulation technology and uses the ATT mechanism to achieve precise alignment of the closing time of the COOK short-circuit switch with the moment when the voltages at both ends of the receiving end (RX end) coil are equal, thereby optimizing data transmission efficiency and quality.

[0074] like Figure 3 As shown, the carrier frequency is 13.56MHz, 1 is the COOK encoding module, which uses CLK_UP as the reference clock, encodes the uplink data DATA_UP and generates a COOK signal to directly control the on and off of the short-circuit switch. The encoding method is as follows Figure 4 3 is PLL, its circuit diagram is as shown Figure 5 As shown, there is a VCO inside. In this embodiment, the VCO can generate a 20-phase clock, so the accuracy of the ATT module is 4 is a dynamic comparator, which samples VAC1 and VAC2 at the rising edge of CLK_S and compares them. 5 is a comparator, which is used to obtain the downlink carrier clock with the same frequency as the transmitter. 6 is a short-circuit switch, which is closed when COOK is 1 and opened when COOK is 0. 2 is the proposed ATT module, which is used to generate a COOK-coded reference clock with its edge aligned with the intersection of VAC1 and VAC2. The SAR logic of ATT is shown in Figure 7 shown.

[0075] In order to implement the COOK modulation of the automatic time tracking described above, the automatic time tracking module of this embodiment performs the following steps:

[0076] Step 1: Select the initial phase

[0077] Among the 20 phases generated by the VCO in the PLL module, the first phase VCO[0] is selected as the initial phase. This phase will serve as the starting point for subsequent operations.

[0078] Step 2: Two-way operation

[0079] The phase selected in step 1 is divided into two to obtain a clock signal CLK_S, which will be used in the subsequent dynamic comparator.

[0080] Step 3: Compare Voltages

[0081] At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the result is recorded as CMP_REG (if VAC1 is greater than VAC2, CMP_REG is 1, and if VAC1 is less than VAC2, it is 0).

[0082] Step 4: Adjust the phase

[0083] The next next phase of the VCO clock is selected.

[0084] Step 5: Two-way frequency operation

[0085] Divide the frequency by two and update it into the clock signal CLK_S.

[0086] Step 6: Repeat the comparison

[0087] At the rising edge of the new CLK_S, the two voltage signals VAC1 and VAC2 are compared by a dynamic comparator, and the result is recorded as CMP (if VAC1 is greater than VAC2, CMP_REG is 1, and if VAC1 is less than VAC2, it is 0).

[0088] Step 7: Determine whether automatic time tracking is completed

[0089] If CMP is not equal to CMP_REG, this indicates that automatic time tracking has been completed and you can proceed to the next step.

[0090] If CMP is equal to CMP_REG, this indicates that automatic time tracking has not been completed and further phase adjustment is required. In this case, return to step 4 and select the next adjacent phase of the VCO clock for 2-division. Repeat steps 4 to 7 until the comparison result of the dynamic comparator indicates that CMP is not equal to CMP_REG, that is, automatic time tracking is completed.

[0091] Step 8: Output the final selected CLK_UP

[0092] Once the automatic time tracking is completed, the final selected CLK_S is output as CLK_UP as the clock source for the COOK switch. This clock source will be used in the subsequent COOK uplink modulation module.

[0093] like Fig. 9 As shown in Figure 1, the COOK signal without the assistance of the ATT optimization method cannot be aligned with the intersection point of VAC1 and VAC2, resulting in a lower modulation depth. The COOK signal assisted by the ATT optimization method is aligned with the intersection of VAC1 and VAC2, and the modulation depth is higher.

[0094] Those skilled in the art will appreciate that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, wherein the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0095] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the principle of the present invention. These improvements and supplements should also be regarded as the scope of protection of the present invention.

Claims

1. An automatic time tracking method based on cyclic on-off keying. It is characterized by: The following steps are involved: a) Selecting the initial phase: Among the N phases generated by the VCO in the PLL module, the most forward phase is selected as the initial phase; b) First two-frequency division operation: the initial phase selected in step a) is divided into two frequencies to obtain a clock signal CLK_S; c) Comparison voltage: At the rising edge of CLK_S, the voltage signals VAC1 and VAC2 at both ends of the receiving coil are compared by a dynamic comparator, and the comparison result is recorded as CMP_REG, where CMP_REG is 1 when VAC1 is greater than VAC2, and CMP_REG is 0 when VAC1 is less than VAC2; d) Adjusting the phase: selecting the next phase of the VCO clock as the new phase; e) a second frequency division operation: performing a frequency division process on the adjacent subsequent phase selected in step d) to update and obtain a new clock signal CLK_S; f) Repeat comparison: At the rising edge of the new CLK_S, the voltage signals VAC1 and VAC2 are compared again by the dynamic comparator, and the comparison result is recorded as CMP, where CMP is 1 when VAC1 is greater than VAC2, and CMP is 0 when VAC1 is less than VAC2; g) Determine whether automatic time tracking is completed: compare the values ​​of CMP and CMP_REG. If they are not equal, it indicates that automatic time tracking is completed and execute step h); if they are equal, return to step d), continue to adjust the phase and repeat steps e) to f) until CMP and CMP_REG are not equal; h) Output the final selected CLK_UP: Once the automatic time tracking is completed, the final selected CLK_S is output as CLK_UP as the clock source for subsequent circuit modules.

2. The ATT optimization method according to claim 1, characterized in that: The N phases in step a) are continuous phases generated by the VCO within a preset frequency range.

3. The ATT optimization method according to claim 1, characterized in that: The frequency division by two operation in steps b) and e) is implemented by a frequency divider, which is used to convert the phase generated by the VCO into a clock signal CLK_S.

4. The ATT optimization method according to claim 1, characterized in that: The dynamic comparator in steps c) and f) has the characteristics of high-speed comparison and low delay to ensure accurate comparison of the voltage signals VAC1 and VAC2 at the rising edge of CLK_S.

5. The ATT optimization method according to claim 1, characterized in that: The subsequent circuit module in step h) is a COOK uplink modulation module, and CLK_UP is used as the clock source of the module to achieve accurate transmission of uplink data.

6. A COOK wireless data transmission system based on ATT (Automatic Time Tracking) optimization, characterized in that: include: A COOK encoding module (1) is used to receive uplink data (DATA_UP) and a reference clock (CLK_UP), and use CLK_UP as a reference clock to COOK encode DATA_UP. The encoded COOK signal directly controls the on / off of a short-circuit switch (6) to achieve wireless transmission of uplink data; An ATT module (2) for executing the method according to any one of claims 1 to 5 to generate a CLK_UP aligned with a cross point of voltage signals VAC1 and VAC2 at both ends of the receiving coil; PLL module, used to lock the phase of the input signal; A dynamic comparator, used for sampling and comparing voltage signals VAC1 and VAC2 at the rising edge of CLK_S, and outputting a comparison result CMP or CMP_REG; CMP module, used to obtain the downlink carrier clock with the same frequency as the transmitter; The short-circuit switch (6) controls the on and off of the circuit according to the state of the COOK signal. When the COOK signal is 1, the short-circuit switch is closed to allow current to pass through, and when the COOK signal is 0, the short-circuit switch is opened to cut off the current.

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