A network transmission system for video data, a system-on-a-chip (SoC), and a server

Abstract

This invention discloses a video data network transmission system, a system-on-a-chip (SoC), and a server, relating to the field of chip design technology. The system, applied to an SoC, includes: a video data output control module for writing video data to be transmitted into a target area of ​​the video memory in a segmented ping-pong manner; wherein the target area includes a first segment area and a second segment area; a network module for alternately reading target video data from the first and second segment areas; and sending the corresponding video image data frames to a remote device for display. This invention, through the hardware module configuration of the video data output control module and the network module, enables the segmented ping-pong manner of writing video data to be transmitted into the on-chip cache of the network module, achieving time-division multiplexing of the target area of ​​the video memory, reducing the occupation of storage bandwidth and system bus resources by video network transmission, and improving the overall performance of the SoC chip.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a video data network transmission system, a system-on-a-chip (SoC), and a server. Background Technology

[0002] Currently, the video processing flow of traditional SoC (System on Chip) chips is as follows: First, the original RGB (red, green, blue) format data is converted to YUV (luminance, chrominance, and density) format video data through color space conversion. The YUV format data is then compressed (using video compression formats such as JPEG and AVS) or transmitted directly. The compressed data or YUV format data is then written to external video memory (such as dual data rate synchronous dynamic random access memory DDR) through the SoC chip's video data output control module. Finally, an external network driver reads the compressed YUV format data from the video memory and transmits it to a remote end for display via the SoC chip's network module.

[0003] like Figure 1 As shown, the video data output control module in the server's server management control chip (a SoC chip with video and network functions, such as a baseboard management controller, BMC) needs to write the video data (such as compressed data output by the video core compression module) to a designated DDR region B. The network driver of the CPU (Central Processing Unit) reads the video data from region B to the designated DDR region C of the network module. Then, the network driver creates a descriptor at the software level and sends it to the designated DDR region D. The network module first obtains the descriptor from region D, then parses the descriptor to obtain the address and length of the video data to be sent in DDR region C, and then initiates a DDR (Data Memory Access) DMA operation to read the video data to be sent back. The above process involves a large amount of DDR data reading and writing, which greatly consumes the system bus bandwidth and storage bandwidth of the SoC chip, reducing the overall performance of the SoC chip.

[0004] Therefore, how to reduce the network transmission of video data and its impact on storage bandwidth and system bus resources, and improve the overall performance of SoC chips, is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a video data network transmission system, a system-on-a-chip (SoC), and a server, so as to reduce the occupation of storage bandwidth and system bus resources by video data network transmission and improve the overall performance of the SoC chip.

[0006] To address the aforementioned technical problems, this invention provides a network transmission system for video data, applied to a system-on-a-chip (SoC), comprising:

[0007] A video data output control module is used to write video data to be transmitted into a target area of ​​video memory in a segmented ping-pong manner; wherein, the target area includes a first segment area and a second segment area, the video data to be transmitted includes first segment data and second segment data, the first segment area is used to store the first segment data, and the second segment area is used to store the second segment data.

[0008] A network module is used to alternately read target video data from the first segmented region and the second segmented region; and send the video image data of each frame corresponding to the target video data to a remote terminal device for display; wherein the target video data is the first segmented data or the second segmented data.

[0009] On the other hand, both the first segmented region and the second segmented region include n block regions; n is a positive integer greater than or equal to 2;

[0010] The video data output control module is specifically used to sequentially and cyclically write the segment storage data corresponding to the current first segment data into each block area of ​​the first segment area according to a preset length; wherein, the current first segment data is any first segment data, and the data length of the segment storage data is less than or equal to the preset length.

[0011] On the other hand, the step of sequentially and cyclically writing the segmented storage data corresponding to the current first segmented data into each block area of ​​the first segmented region according to a preset length includes:

[0012] Write the a-th segment data of the current first segment data into the i-th block region of the first segment region; where i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0.

[0013] On the other hand, each of the first segment data and the second segment data is a frame of video image data.

[0014] On the other hand, the alternating reading of target video data from the first segmented region and the second segmented region includes:

[0015] When the target video data is the first segment data, the segment storage data corresponding to the current first segment data is sequentially and cyclically read into the on-chip buffers of each of the n channels; wherein, the current first segment data is any first segment data, the data length of the segment storage data is less than or equal to a preset length, and n is a positive integer greater than or equal to 2; the sum of the segment storage data of the current first segment data stored in the on-chip buffers of the n channels is the current first segment data.

[0016] On the other hand, the network module includes: a scheduling submodule, a direct memory access controller, n channel submodules, and a framing submodule;

[0017] The scheduling submodule is used to control the direct memory access controller to sequentially read the segment storage data corresponding to the current target video data from the video memory, and to sequentially and cyclically store the read segment storage data corresponding to the current target video data into the on-chip cache of the n channel submodules; wherein, the current target video data is any of the target video data, the on-chip cache of the i-th channel submodule is used to store the a-th segment storage data of the current target video data, i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0;

[0018] The frame-grouping submodule is used to sequentially and cyclically read the segmented storage data corresponding to each of the target video data from the on-chip buffers of the n channel submodules and perform frame-grouping to obtain the video image data of each frame corresponding to the target video data; and sequentially send the video image data of each frame obtained by frame-grouping to the remote terminal device for display.

[0019] On the other hand, the scheduling submodule is specifically used to initiate a direct memory access read data command corresponding to the first segment storage data of the current target video data to the direct memory access controller; obtain the first segment storage data read by the direct memory access controller from the first block region of the current segment region; write the first segment storage data into the on-chip buffer of the first channel submodule, so that the frame grouping submodule reads the first segment storage data from the on-chip buffer of the first channel submodule; wherein, the current target video data is any of the target video data; the current segment region is the first segment region or the second segment region;

[0020] The scheduling submodule is further configured to, when the (b-1)th segment of the current target video data is not the last segment of the current target video data, after initiating a direct memory access read data command corresponding to the (b-1)th segment of the storage data to the direct memory access controller, initiate a direct memory access read data command corresponding to the b-th segment of the storage data to the direct memory access controller; obtain the b-th segment of the storage data read by the direct memory access controller from the j-th block region of the current segment region; write the b-th segment of the storage data into the on-chip buffer of the j-th channel submodule, so that the frame grouping submodule reads the b-th segment of the storage data from the on-chip buffer of the j-th channel submodule; wherein b is a positive integer greater than or equal to 2, j = b - (n*j), j is a positive integer less than or equal to n, and j is an integer greater than or equal to 0.

[0021] On the other hand, n is 4.

[0022] On the other hand, both the first segmented region and the second segmented region include n block regions, each of which is used to store the segmented storage data that the on-chip cache of a corresponding channel submodule needs to cache;

[0023] The direct memory access controller is controlled to sequentially read segmented storage data corresponding to the current target video data from the video memory, including:

[0024] Based on the identification information corresponding to each segment of the current target video data, the direct memory access controller is controlled to sequentially read each segment of the current target video data from the video memory; wherein, the identification information includes the segment region identifier corresponding to the first segment region or the second segment region where the segmented storage data is located, the block region identifier corresponding to the block region where the segmented storage data is located, and the block region reading order identifier corresponding to the position of the segmented storage data in the block region.

[0025] On the other hand, when the current target video data is stored in the first segmented region, the segmented region identifier in the identification information corresponding to the a-th segment of the current target video data is 0, the block region identifier is i-1, and the block region reading order identifier is j.

[0026] When the current target video data is stored in the second segment region, the segment region identifier in the identification information corresponding to the a-th segment of the current target video data is 1, the block region identifier is i-1, and the block region reading order identifier is j; where i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

[0027] On the other hand, each channel submodule includes: a channel controller and an on-chip cache;

[0028] The channel controller is used to sequentially store the segmented storage data transmitted by the scheduling submodule into the corresponding on-chip cache according to the control of the scheduling submodule.

[0029] On the other hand, the network module also includes:

[0030] The descriptor generation submodule is used to generate direct memory access read data commands corresponding to each segment of the current target video data according to the control of the scheduling submodule; and send the direct memory access read data commands to the direct memory access controller in sequence to control the direct memory access controller to read each segment of the current target video data from the video memory in sequence according to the received direct memory access read data commands.

[0031] On the other hand, the descriptor generation submodule includes: a descriptor address information generation unit, a read length generation unit, a descriptor control information generation unit, and a descriptor assembly unit;

[0032] The descriptor address information generation unit is used to generate descriptor address information for each segment of the current target video data according to the address information of the target region and the control of the scheduling submodule.

[0033] The read length generation unit is used to generate descriptor read length information corresponding to the preset length;

[0034] The descriptor control information generation unit is used to generate descriptor control information for each segment of stored data corresponding to the current target video data.

[0035] The descriptor assembly unit is used to generate direct memory access read data commands corresponding to each segment of the current target video data based on the descriptor address information, the descriptor read length information, and the descriptor control information.

[0036] On the other hand, both the first segmented region and the second segmented region include n block regions, each of which is used to store the segmented storage data that the on-chip cache of a corresponding channel submodule needs to cache;

[0037] The descriptor address information generation unit is specifically used to generate descriptor address information for each segment of the current target video data based on the address range information of the target region and the identification information corresponding to each segment of the current target video data sent by the scheduling submodule; wherein, the address range information includes the starting address and address range of the first segment region and the second segment region respectively, the descriptor address information includes the starting address of each segment of the current target video data within the target region, and the identification information includes the segment region identifier, the block region identifier, and the block region reading order identifier.

[0038] On the other hand, in the current target video data, the block region identifier in the identification information corresponding to the a-th segment of stored data is i-1 and the block region reading order identifier is j; where i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0;

[0039] The starting address of the a-th segment of stored data within the target area is BEGIN_ADDR+SIZE / n*(i-1)+j*DMA_LENGTH; where BEGIN_ADDR is the starting address of the first or second segment region corresponding to the segment region identifier in the identification information corresponding to the a-th segment of stored data, SIZE is the address range of the first or second segment region corresponding to the segment region identifier in the identification information corresponding to the a-th segment of stored data, and DMA_LENGTH is the preset length.

[0040] On the other hand, the read length generation unit is specifically used to use the length information stored in the preset length register as the preset length to generate the descriptor read length information corresponding to the preset length.

[0041] On the other hand, the network module is also used to send the length information stored in the preset length register to the video data output control module when the length information changes.

[0042] On the other hand, the system-on-a-chip is specifically a substrate management controller.

[0043] The present invention also provides a system-on-a-chip, comprising: a network transmission system for video data as described above.

[0044] In addition, the present invention also provides a server, including: a system-on-a-chip as described above.

[0045] This invention provides a video data network transmission system applied to a system-on-a-chip (SoC), comprising: a video data output control module for writing video data to be transmitted into a target area of ​​video memory in a segmented ping-pong manner; wherein the target area includes a first segment area and a second segment area, the video data to be transmitted includes first segment data and second segment data, the first segment area is used to store the first segment data, and the second segment area is used to store the second segment data; a network module for alternately reading target video data from the first segment area and the second segment area; and sending the corresponding frames of video image data to a remote terminal device for display; wherein the target video data is either the first segment data or the second segment data.

[0046] As can be seen, this invention, through a video data output control module that writes the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner, and a network module that alternately reads the target video data from the first and second segmented areas, enables the video data to be transmitted to be written into the on-chip cache of the network module in a segmented ping-pong manner. This achieves time-division multiplexing of the target area of ​​the video memory by the video data output control module and the network module, greatly reducing the occupation of storage bandwidth and system bus resources by the network transmission of video data, and improving the overall performance of the SoC chip. Furthermore, this invention also provides a system-on-a-chip and server, which also have the above-mentioned beneficial effects. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of a remote video transmission scheme for BMC in a server in related technologies;

[0049] Figure 2 This is a structural block diagram of a video data network transmission system provided in an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram illustrating time-division multiplexing of video memory space according to an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram illustrating segmented data storage in a first segmented region and a second segmented region, provided as an embodiment of the present invention.

[0052] Figure 5 This is a schematic diagram of the structure of a network module in related technologies;

[0053] Figure 6 This is a schematic diagram of the structure of a network module provided in an embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of the structure of a descriptor generation submodule provided in an embodiment of the present invention;

[0055] Figure 8 This is a schematic diagram of a 4-channel video data pipeline processing method provided in an embodiment of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] Please refer to Figure 2 , Figure 2 This is a structural block diagram of a video data network transmission system provided in an embodiment of the present invention. The system is applied to a system-on-a-chip (SoC) and may include:

[0058] The video data output control module 10 is used to write the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner; wherein, the target area includes a first segment area and a second segment area, the video data to be transmitted includes first segment data and second segment data, the first segment area is used to store the first segment data, and the second segment area is used to store the second segment data.

[0059] The network module 20 is used to alternately read target video data from the first segment region and the second segment region; and send the video image data of each frame corresponding to the target video data to the remote terminal device for display; wherein the target video data is the first segment data or the second segment data.

[0060] It is understood that the SoC chip in this embodiment can be a single chip integrating one or more of the following: a microprocessor, an analog IP (Intellectual Property) core, a digital IP core, and memory (or an off-chip memory control interface), such as a server management controller (e.g., a BMC) in a server; for example, the video data network transmission system provided in this embodiment can be applied to the server's BMC. The video memory in this embodiment can be a memory outside the SoC chip used to store the video data to be transmitted (i.e., off-chip memory), such as DDR.

[0061] Correspondingly, in this embodiment, through the hardware module settings of the video data output control module 10 (i.e., the video function module) and the network module 20 (i.e., the network function module) in the SoC chip, the video function and the network function can share the same video memory space (i.e., the target area of ​​the video memory, such as...). Figure 3 The video data output control module 10 can write the video data to be transmitted (such as compressed data or YUV format data) output by the video data output control module 10 into the on-chip buffer of the network module 20 in a segmented ping-pong manner via the target area of ​​the video memory. Figure 3 As shown, when the video data output control module 10 writes the first segment of the segmented video data to be transmitted into the B0 area (i.e., the first segment area), the network module 20 can read the second segment data already written in the B1 area (i.e., the second segment area); when the video data output control module 10 writes the second segment of the segmented video data to be transmitted into the B1 area, the network module 20 can read the first segment data already written in the B0 area, which greatly reduces the network transmission of video functions on storage bandwidth (such as DDR memory bandwidth) and system bus usage.

[0062] In other words, in this embodiment, the process of the network module 20 alternately reading target video data from the first segment region and the second segment region may include reading second segment data from the second segment region when the video data output control module 10 writes first segment data to the first segment region; and reading first segment data from the first segment region when the video data output control module 10 writes second segment data to the second segment region.

[0063] In this embodiment, the area in the video memory shared by the video data output control module 10 and the network module 20 for storing the video data to be transmitted (i.e., the target area) is divided into two areas: a first segment area and a second segment area. This allows the video data output control module 10 and the network module 20 to alternately use these two areas, enabling time-division multiplexing of the different functions (i.e., video function and network function) of the target area by the two hardware modules. This avoids the drawback of the related technology where the network transmission of video data requires moving the video data from the DDR area corresponding to the video function to the DDR area corresponding to the network function. This greatly reduces the occupation of memory bandwidth and system bus resources by the network transmission of video data, and greatly improves the overall performance of the SoC chip.

[0064] Correspondingly, the specific method by which the video data output control module 10 writes the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner in this embodiment can be set by the designer according to the practical scenario and user needs. For example, the video data output control module 10 can directly write the current part of the video data to be transmitted (such as the first segment data or the second segment data) into the first segment area or the second segment area. That is, it can directly segment the video data to be transmitted according to the length (i.e., capacity) of the first segment area and the second segment area or the pre-set length of the first segment data and the second segment data, so that the segmented video data to be transmitted (i.e., the first segment data and the second segment data) can be written into their respective first segment area or second segment area.

[0065] Correspondingly, in order to facilitate the network module 20 to read video data in the target area using multiple channels (i.e., n channels), in this embodiment, the first segment area and the second segment area can be divided into n block areas respectively, and each first segment data and each second segment data can be further segmented according to a preset length (such as the agreed length or the length configured by the register), so that the segmented data (i.e., the segmented storage data) corresponding to each first segment data and each second segment data can be sequentially written into each block area in the first segment area, so that each channel can read the corresponding segmented storage data from one block area corresponding to each of the first segment area and the second segment area respectively.

[0066] For example, in some embodiments, both the first segment region and the second segment region may include n block regions; n is a positive integer greater than or equal to 2; the video data output control module 10 can be specifically used to sequentially and cyclically write the segment storage data corresponding to the current first segment data into each block region of the first segment region according to a preset length; wherein, the current first segment data is any first segment data, and the data length of the segment storage data is less than or equal to the preset length. That is to say, when the video data output control module 10 writes the current first segment data into the first segment region, it can divide the first segment data into each segment storage data according to a preset length and sequentially and cyclically write it into each block region of the first segment region.

[0067] Correspondingly, the video data output control module 10 can also be specifically used to sequentially and cyclically write the segmented storage data corresponding to the current second segmented data into each block area of ​​the second segmented region according to a preset length; wherein, the current second segmented data is any second segmented data. That is to say, when the video data output control module 10 writes the current second segmented data into the second segmented region, it can divide the second segmented data into segmented storage data according to a preset length and sequentially and cyclically write it into each block area of ​​the second segmented region.

[0068] The specific method for sequentially writing the segmented storage data corresponding to the current first segment data into the respective block areas of the first segment region according to a preset length can be customized by the designer based on the usage scenario and user needs. For example, the video data output control module 10 can write the a-th segment storage data of the current first segment data into the i-th block area of ​​the first segment region; where i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0. For instance, when n is 4, such as... Figure 3 and Figure 4 As shown, the starting address of region B0 (i.e., the first segment region) can be B0_BEGIN_ADDR, and the total address range of region B0 is B0_SIZE. Region B0 is divided into 4 equal parts. The first block (i.e., the first segment region) is denoted as B0_0, with a starting address of B0_BEGIN_ADDR and an address range of B0_SIZE / 4. The second block (i.e., the second segment region) is denoted as B0_1, with a starting address of B0_BEGIN_ADDR + B0_SIZE / 4 and an address range of B0_SIZE / 4. The third block (i.e., the third segment region)... The first block region is denoted as region B0_2, with a starting address of B0_BEGIN_ADDR+B0_SIZE / 2 and an address range of B0_SIZE / 4; the fourth block region is denoted as region B0_3, with a starting address of B0_BEGIN_ADDR+B0_SIZE*3 / 4 and an address range of B0_SIZE / 4; the video data to be transmitted (i.e., the current first segment data) is written to regions B0_0, B0_1, B0_2, and B0_3 respectively according to a preset length (DMA_LENGTH), and written cyclically in sequence, as shown below. Figure 7 As shown, the 1st / 5th / 9th / 13th... segment data is written to B0_0, the 2nd / 6th / 10th / 14th... segment data is written to B0_1, the 3rd / 7th / 11th / 15th... segment data is written to B0_2, and the 4th / 8th / 12th / 16th... segment data is written to B0_3.

[0069] Correspondingly, the implementation method of sequentially writing the segment storage data corresponding to the current second segment data into the block area of ​​the second segment region according to the preset length is similar to the above process. The video data output control module 10 can write the a-th segment storage data of the current second segment data into the i-th block area of ​​the second segment region; where i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0. For example, when n is 4, such as Figure 3 and Figure 4As shown, the starting address of region B1 (i.e., the second segment region) can be B1_BEGIN_ADDR, and the total address range of region B1 is B1_SIZE. Region B1 is divided into 4 equal parts. The first block (i.e., the first segment region) is denoted as B1_0, with a starting address of B1_BEGIN_ADDR and an address range of B1_SIZE / 4. The second block (i.e., the second segment region) is denoted as B1_1, with a starting address of B1_BEGIN_ADDR + B0_SIZE / 4 and an address range of B1_SIZE / 4. The third block (i.e., the third segment region)... The first block region is denoted as B1_2, with a starting address of B1_BEGIN_ADDR+B0_SIZE / 2 and an address range of B1_SIZE / 4; the fourth block region is denoted as B1_3, with a starting address of B1_BEGIN_ADDR+B0_SIZE*3 / 4 and an address range of B1_SIZE / 4; the video data to be transmitted (i.e., the current second segment data) is written to regions B1_0, B1_1, B1_2, and B1_3 respectively in units of a preset length (DMA_LENGTH), and written cyclically in this manner, as follows: Figure 7 As shown, the 1st / 5th / 9th / 13th... segment data is written to B1_0, the 2nd / 6th / 10th / 14th... segment data is written to B1_1, the 3rd / 7th / 11th / 15th... segment data is written to B1_2, and the 4th / 8th / 12th / 16th... segment data is written to B1_3.

[0070] Correspondingly, in some embodiments, the n block regions in the first segmented region can be of the same size, such as the n block regions in the first segmented region can be obtained by dividing the first segmented region into n equal parts; correspondingly, the n block regions in the second segmented region can be of the same size, such as the n block regions in the second segmented region can be obtained by dividing the first segmented region into n equal parts.

[0071] In this embodiment, the specific data lengths of each first segment and second segment corresponding to the video data to be transmitted can be set by the designer according to the usage scenario and user needs. For example, since the first segment area can completely store one first segment data and the second segment area can completely store one second segment data in this embodiment, the first segment area and the second segment area can be used alternately to realize the alternation of the first segment area and the second segment area. In this embodiment, the data lengths (i.e., data sizes) of the first segment data and the second segment data are set according to the capacity of the first segment area and the second segment area. To facilitate subsequent frame assembly operations, in some embodiments, each first segment data and the second segment data can be a frame of video image data, that is, the capacity of the first segment area and the second segment area can be greater than or equal to the data length of a frame of video image data. Correspondingly, when the first segment data and the second segment data are segmented according to a preset length, the data length of the segmented storage data is less than or equal to the preset length. For example, the data length of the segmented storage data before the last segmented storage data of the first segment data can be equal to the preset length, and the last segmented storage data can be less than or equal to the preset length.

[0072] Correspondingly, when the video data to be transmitted is segmented directly according to the preset length, the data length of the segmented storage data of the first segment and the second segment can both be equal to the preset length.

[0073] It is understood that the network module 20 in this embodiment can alternately read the currently stored target video data (i.e., the first segment data or the second segment data) from the first segment region and the second segment region. For example, when the video data output control module 10 writes the first segment data to the first segment region, the network module 20 can read the second segment data from the second segment region; when the video data output control module 10 writes the second segment data to the second segment region, the network module 20 can read the first segment data from the first segment region.

[0074] Correspondingly, the specific method by which network module 20 alternately reads the currently stored target video data from the first segment region and the second segment region can be set by the designer according to the practical scenario and user needs. For example, network module 20 can alternately read the currently stored target video data from the first segment region and the second segment region into the on-chip cache, as is the case in related technologies. In order to improve the processing efficiency of network module 20, this embodiment can realize parallel processing of video data by setting up a video data reading mechanism of n channels in n-stage pipeline processing. For example, when network module 20 reads the current first segment data (i.e., the target video data is the first segment data) in the first segment data, it can sequentially read the segment storage data corresponding to the current first segment data into the on-chip cache of each of the n channels. Here, the current first segment data is any first segment data, the data length of the segment storage data is less than or equal to a preset length, and n is a positive integer greater than or equal to 2. The sum of the segment storage data of the current first segment data stored in the on-chip cache of the n channels is the current first segment data.

[0075] Accordingly, when the target video data is the second segment data, the network module 20 can sequentially read the segment storage data corresponding to the current second segment data into the on-chip buffers of each of the n channels. That is to say, as... Figure 5 In the related technologies shown, the network module 20 needs to wait for the framing submodule (such as the Ethernet framing submodule) to read the on-chip buffer before initiating the DMA read operation. This is to ensure that the data returned by the DMA read has sufficient space in the TX_FIFO (Transmit First-In-First-Out queue). Otherwise, data will be lost due to untimely buffering, leading to transmission errors. Therefore, the related technologies can only achieve serial processing between the DMA controller, the on-chip buffer controller, and the subsequent framing submodule, resulting in low processing efficiency. This causes excessive buffering time for video data in DDR, leading to large network transmission delays and affecting the video display quality of the remote device. In this embodiment, the setting of an n-channel video data reading mechanism through n-stage pipeline processing enables parallel processing of video data, improving the video display quality of the remote device.

[0076] For example, network module 20 may include: a scheduling submodule, a direct memory access controller (DMA controller), n channel submodules, and a framing submodule;

[0077] The scheduling submodule controls the direct memory access controller to sequentially read the segmented storage data corresponding to the current target video data from the video memory, and then sequentially and cyclically stores the read segmented storage data corresponding to the current target video data into the on-chip cache of the n channel submodules. Here, the current target video data can be any target video data, and the on-chip cache of the i-th channel submodule is used to store the a-th segment of the current target video data, where i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0.

[0078] The frame assembly submodule is used to sequentially read the segmented storage data corresponding to each of the n channel submodules from their on-chip buffers and assemble them into frames to obtain the video image data of each frame corresponding to the target video data; and then send the video image data of each frame obtained by framing to the remote terminal device for display.

[0079] In other words, the scheduling submodule can control the DMA controller to sequentially store the segmented storage data corresponding to the current target video data into the on-chip buffers of the n channel submodules through DMA read operations. This enables the frame assembly submodule to sequentially read the segmented storage data from the on-chip buffers of the n channel submodules and assemble the frames to obtain the video image data of each frame corresponding to the target video data, thereby improving the processing efficiency of the video data to be transmitted.

[0080] The process of network module 20 processing data to be transmitted can include the following four steps: 1. Initiating a DMA read operation; 2. Waiting for the DMA read data to return; 3. Writing the returned data into the on-chip buffer (such as TX_FIFO or random access memory RAM); 4. The framing submodule reads the on-chip buffer, adds the video data to the Ethernet frame, and sends it. In this embodiment, four channels can be set for these four processes, i.e., n can be 4, so that each channel can complete the above four processes, and these four channels can perform different processes at the same time, thereby realizing a four-channel video data reading mechanism based on four-stage pipeline processing; correspondingly, two or three channels can also be set, and this embodiment does not impose any restrictions on this.

[0081] For example, in some embodiments, the scheduling submodule is specifically used to initiate a direct memory access read data command corresponding to the first segment storage data of the current target video data to the direct memory access controller (as described in process 1 above); obtain the first segment storage data read by the direct memory access controller from the first block region of the current segment region (as described in process 1 above); and write the first segment storage data into the on-chip buffer of the first channel submodule (as described in process 3 above), so that the framing submodule reads the first segment storage data from the on-chip buffer of the first channel submodule (as described in process 4 above). Here, the current target video data is any target video data; the current segment region is either the first segment region or the second segment region.

[0082] The scheduling submodule is further configured to, when the (b-1)th segment of the current target video data is not the last segment of the current target video data, after initiating a direct memory access read command corresponding to the (b-1)th segment of the direct memory access controller, initiate a direct memory access read command corresponding to the bth segment of the direct memory access controller; obtain the bth segment of the direct memory access controller from the jth block region of the current segment region; and write the bth segment of the direct memory access controller into the on-chip buffer of the jth channel submodule so that the frame grouping submodule can read the bth segment of the direct memory access controller from the on-chip buffer of the jth channel submodule; where b is a positive integer greater than or equal to 2, j = b - (n * j), j is a positive integer less than or equal to n, and j is an integer greater than or equal to 0.

[0083] Correspondingly, the specific method by which the scheduling submodule controls the direct memory access controller to sequentially read the segmented storage data corresponding to the current target video data from the video memory can be set by the designer according to the usage scenario and user needs. For example, if both the first segment region and the second segment region include n block regions, and each block region is used to store the segmented storage data that the on-chip cache of the corresponding channel submodule needs to cache, the scheduling submodule can control the direct memory access controller to sequentially read the segmented storage data corresponding to the current target video data from the video memory according to the identification information corresponding to each segmented storage data of the current target video data. Among them, the identification information includes the segment region identifier corresponding to the first segment region or the second segment region where the segmented storage data is located, the block region identifier corresponding to the block region where the segmented storage data is located, and the block region reading order identifier corresponding to the position of the segmented storage data in the block region.

[0084] In other words, the segment region identifier can be used to indicate whether the segmented storage data to be read by the DMA controller is stored in the first segment region or the second segment region. The segmented storage data can be used to indicate which block region within the first or second segment region the segmented storage data to be read by the DMA controller is stored in. The block region read order identifier can be used to indicate the order in which the segmented storage data to be read by the DMA controller is stored in the block region. When the data length of the segmented storage data is a preset length, the position of the segmented storage data in the block region can be determined by the block region read order identifier.

[0085] For example, in some embodiments, when the current target video data is stored in the first segment region, the segment region identifier in the identification information corresponding to the a-th segment of the current target video data is 0, the block region identifier is i-1, and the block region reading order identifier is j; when the current target video data is stored in the second segment region, the segment region identifier in the identification information corresponding to the a-th segment of the current target video data is 1, the block region identifier is i-1, and the block region reading order identifier is j; where i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0.

[0086] Correspondingly, in some other embodiments, when the current target video data is stored in the first segment region, the segment region identifier in the identification information corresponding to the a-th segment of the current target video data is 1, the block region identifier is i, and the block region reading order identifier is j+1; when the current target video data is stored in the second segment region, the segment region identifier in the identification information corresponding to the a-th segment of the current target video data is 2, the block region identifier is i, and the block region reading order identifier is j+1; where i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

[0087] Furthermore, in the related technology, the creation of the descriptor used to control the DMA controller in the network module 20 is performed by the network driver software running on the CPU. After creation, the descriptor is first written to the specified DDR area (e.g., Figure 1 The network module 20 reads and parses the descriptor from the first segmented region (D region) to reduce CPU resource consumption and improve the overall performance of the SoC chip. In this embodiment, the process of creating the descriptor can be offloaded from the CPU, and the network module 20 in the SoC chip hardware is responsible for creating the descriptor and executing the function. That is, the process of the network module 20 alternately reading target video data from the first segmented region and the second segmented region can be used to create a descriptor (i.e., a DMA read data command) for the network module 20, controlling its internal DMA controller to alternately read target video data from the first segmented region and the second segmented region. For example... Figure 6 As shown, network module 20 may further include: a descriptor generation submodule, used to generate direct memory access read data commands (i.e., descriptors) corresponding to each segment of the current target video data according to the control of the scheduling submodule; and to send the direct memory access read data commands sequentially to the direct memory access controller (DMA controller) to control the DMA controller to read each segment of the current target video data from the video memory according to the received direct memory access read data commands. That is, during the process of the scheduling submodule initiating the direct memory access read data command corresponding to the first segment of the current target video data (or the (b-1)th segment of the current target video data) to the DMA controller, the scheduling submodule can control the descriptor generation submodule to generate and send the DMA read data command corresponding to the first segment of the current target video data to the DMA controller.

[0088] For example, such as Figure 7 As shown, the descriptor generation submodule may include: a descriptor address information generation unit, a read length generation unit, a descriptor control information generation unit, and a descriptor assembly unit; the descriptor address information generation unit is used to generate descriptor address information for each segment of the current target video data based on the address information of the target area and the control of the scheduling submodule; the read length generation unit is used to generate descriptor read length information corresponding to a preset length; the descriptor control information generation unit is used to generate descriptor control information for each segment of the current target video data; and the descriptor assembly unit is used to generate direct memory access read data commands for each segment of the current target video data based on the descriptor address information, descriptor read length information, and descriptor control information.

[0089] The descriptor address information generation unit is responsible for generating the address information in the descriptor, such as... Figure 3The mid-video data output control module 10 can transmit the area address range division (i.e., the target area address information) of the first segment area (B0 area) and the second segment area (B1 area) to the network module 20, so that the descriptor address information generation unit can determine the starting address information of the block area of ​​each of the first segment area and the second segment area. Then, the descriptor address information generation unit generates the descriptor address information of each segment storage data corresponding to the current target video data according to the identification information of each segment storage data corresponding to the current target video data transmitted by the scheduling submodule (such as the segment area identifier, block area identifier and block area reading order identifier mentioned above). In other words, both the first and second segment regions include n block regions. Each block region is used to store the segmented storage data that the on-chip cache of a corresponding channel submodule needs to cache. The descriptor address information generation unit can specifically generate descriptor address information for each segmented storage data corresponding to the current target video data based on the address range information of the target region and the identification information corresponding to each segmented storage data of the current target video data sent by the scheduling submodule. The address range information includes the starting address and address range of the first and second segment regions, the descriptor address information includes the starting address of each segmented storage data in the target region, and the identification information includes the segment region identifier, the block region identifier, and the block region reading order identifier.

[0090] Accordingly, if the block region identifier in the identification information corresponding to the a-th segment of the current target video data is i-1 and the block region reading order identifier is j, the starting address of the a-th segment of the stored data in the target region in the descriptor address information generated by the descriptor address information generation unit can be BEGIN_ADDR+SIZE / n*(i-1)+j*DMA_LENGTH; where i is a positive integer less than or equal to n, a=i+(n*j), j is an integer greater than or equal to 0, BEGIN_ADDR is the starting address of the first segment region or the second segment region corresponding to the segment region identifier in the identification information corresponding to the a-th segment of the stored data, SIZE is the address range of the first segment region or the second segment region corresponding to the segment region identifier in the identification information corresponding to the a-th segment of the stored data, and DMA_LENGTH is the preset length.

[0091] For example, when n is 4, if the segment region identifier and block region identifier in the identification information of a certain segment of storage data sent by the scheduling submodule are 0 (i.e., i-1=0) and the block region read order identifier is 0 (i.e., j=0), it means that the first block region of region B0 (i.e., the first segment region) is to be read, and the read order is the first read. The DMA read data command corresponding to the segment of storage data generated by the descriptor address information generation unit can be B0_BEGIN_ADDR+B0_SIZE / 4*(i-1)+j*DMA_LENGTH; if the segment region identifier and block region identifier in the identification information of a certain segment of storage data sent by the scheduling submodule are 1, ... (i.e., i-1=0) and the block region read order identifier is 0 (i.e., j=0), which means that the first block region of region B1 (i.e., the second segment region) is to be read. The read order is the first read. The DMA read data command corresponding to the segment storage data generated by the descriptor address information generation unit can be B1_BEGIN_ADDR+B1_SIZE / 4*(i-1)+j*DMA_LENGTH; where B0_BEGIN_ADDR and B1_BEGIN_ADDR represent the starting addresses of the first segment region and the second segment region, respectively; B0_SIZE and B1_SIZE represent the address ranges of the first segment region and the second segment region, respectively.

[0092] Correspondingly, the read length generation unit can be responsible for generating the length of the DMA read data command (i.e., DMA read operation), namely DMA_LENGTH. The read length generation unit can receive the configuration of a register (such as a preset length register), allowing the user to change DMA_LENGTH. After the change, the network module 20 can synchronously transmit this information to the video data output control module 10. In other words, the read length generation unit can specifically be used to generate the descriptor read length information corresponding to the preset length, using the length information stored in the preset length register as the preset length. The network module 20 can also be used to send the length information to the video data output control module 10 when the length information stored in the preset length register changes.

[0093] Correspondingly, the descriptor control information generation unit can be responsible for generating the descriptor control information (i.e., descriptor control information). For example, the descriptor control information may include control information for indicating whether the current descriptor (i.e., DMA read data command) is the first or last descriptor of the current network packet, and control information for indicating whether to insert SA / DA (source address or destination address) into the current network packet. Some of this control information can be generated by the descriptor control information generation unit itself, and some can be directly sent to the internal register of the descriptor control information generation unit by the network driver.

[0094] The descriptor assembly unit is responsible for packaging the information output by the above three units into a corresponding descriptor structure (i.e., DMA read data command), and passing it to the DMA controller to initiate a DMA read operation (i.e., read the B0 / B1 region).

[0095] For example, when n is 4, by Figure 8 The four-stage pipeline mechanism shown maximizes the utilization of the internal functions of network module 20, enabling parallel processing of the video data to be transmitted. For example... Figure 6 and Figure 8 As shown, the scheduling submodule can first respond to the read request of channel 0 (i.e., channel 1), generate corresponding identification information (such as segment region identifier, block region identifier, and block region read order identifier), and pass it to the descriptor generation submodule. After the descriptor generation submodule generates the corresponding descriptor (i.e., DMA read data command), it passes it to the DMA controller, which then initiates a read operation on the specified address space of region B0 / B1 (i.e., the first segment region or the second segment region). While waiting for the DMA controller to return the read data, the scheduling submodule can respond to the read request of channel 1 (i.e., channel 2), generate the identification information of the next segment of stored data, and pass it to the descriptor generation submodule. After the descriptor generation submodule generates the corresponding descriptor, it passes it to the DMA controller, which then initiates another read operation on the specified address space of region B0 / B1. The scheduling submodule receives the read return data from the DMA controller and forwards the data to the DMA controller. The data is written to on-chip buffer 0 via the channel 0 controller, while simultaneously waiting for the DMA data return initiated by channel 1. At the same time, the scheduling submodule responds to the read request from channel 2, generates the identifier information for the next segment of stored data, and passes it to the descriptor generation submodule. The descriptor generation submodule generates the corresponding descriptor and passes it to the DMA, which then initiates a read operation on the specified address space of the B0 / B1 region. The subsequent frame assembly module reads the video data from the on-chip buffer of channel 0. Simultaneously, the scheduling submodule writes the read return data corresponding to channel 1 into the on-chip buffer corresponding to channel 1, waits for the read data return from channel 2, and responds to the read request from channel 3, generating the identifier information for the next segment of stored data and passing it to the descriptor generation submodule. The descriptor generation submodule generates the corresponding descriptor and passes it to the DMA, which then initiates a read operation on the specified address space of the B0 / B1 region. This achieves data parallel processing via a 4-stage pipeline mechanism.

[0096] Correspondingly, from the perspective of the descriptor generation module, the received identification information (segment region identifier, block region identifier, and block region read order identifier) ​​can be as follows if the current requirement is to read region B0 (i.e., the first segment region): (0,0,0), (0,1,0), (0,2,0), (0,3,0), (0,0,1), (0,1,1), (0,2,1), (0,3,1), (0,0,2), (0,1,2), (0,2,2), (0,3) ,2), (0,0,3), (0,1,3), (0,2,3), (0,3,3)……; If we need to read region B1 (i.e., the second segment region), then the received identifier information can be as follows: (1,0,0), (1,1,0), (1,2,0), (1,3,0), (1,0,1), (1,1,1), (1,2,1), (1,3,1), (1,0,2), (1,1,2), (1,2,2), (1,3,2), (1,0,3), (1,1,3), (1,2,3), (1,3,3)……. The four-stage pipeline reading mechanism described above can be combined with the segmented ping-pong operation writing mechanism of the video data to be transmitted to the video memory (such as DDR). This enables the video data to be transmitted to be read back to the network module 20 in parallel through a four-channel, four-stage pipeline and to be processed into frames before being sent to the remote device. This greatly reduces the buffering time of the video data to be transmitted in the video memory and greatly reduces the network latency of the video data to be transmitted. At the same time, it improves the parallelism and utilization of the internal functions of the network module 20 and greatly improves the display quality of the remote device.

[0097] It should be noted that this embodiment does not limit the specific application scenario of the System-on-a-Chip (SoC) chip. For example, the SoC chip can be the BMC of a server; correspondingly, the SoC chip may also include, Figure 1 The diagram shows the VGA (Video Graphics Array) module, video data capture module, color space conversion module, and video core compression module. For example, when KVM (Keyboard, Video, and Mouse) functionality is activated, the server host transmits the raw video data (i.e., images displayed remotely by the operating system, such as the operating system's real-time interface) to the BMC's VGA module via PCIe (a high-speed serial computer expansion bus standard). The VGA module generates raw video data in RGB format. This process requires interaction with external DDR (video memory), such as... Figure 1The DDR A region in the video data capture module obtains the raw RGB video data from the VGA module and transmits it to the color space conversion module. The color space conversion module can convert the raw RGB video data to YUV format data. The conversion process can use the following formulas: Y=(0.257*R)+(0.504*G)+(0.098*B)+16, U=0.148*R–0.291*G+0.439*B+128 and V=0.439*R-0.368*G-0.071*B+128.

[0098] Correspondingly, the video core compression module can compress the received YUV format data using the corresponding video compression format (such as H.264, JPEG, and AVS video compression formats) to obtain compressed video data; the compressed video output control module can receive compressed video data or uncompressed YUV format data as video data to be transmitted.

[0099] In this embodiment, the video data output control module 10 writes the video data to be transmitted into the target area of ​​the video memory in a segmented ping-pong manner, and the network module 20 alternately reads the target video data from the first segmented area and the second segmented area. This allows the video data to be transmitted to be written into the on-chip cache of the network module 20 in a segmented ping-pong manner, realizing time-division multiplexing of the target area of ​​the video memory by the two hardware modules, the video data output control module 10 and the network module 20. This greatly reduces the occupation of storage bandwidth and system bus resources by the network transmission of video data, and improves the overall performance of the SoC chip.

[0100] Corresponding to the above system embodiments, this invention also provides a system-on-a-chip (SoC). The SoC described below and the video data network transmission system described above can be referred to in correspondence.

[0101] A system-on-a-chip includes a network transmission system for video data as provided in the above embodiments.

[0102] Specifically, the system-on-a-chip (SoC) provided in this embodiment can be a BMC.

[0103] Corresponding to the system embodiments above, this invention also provides a server. The server described below and the system-on-a-chip described above can be referred to in correspondence.

[0104] A server includes a system-on-a-chip as provided in the embodiments described above.

[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the system-on-a-chip (SoC) and server disclosed in the embodiments, since they correspond to the systems disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be found in the system section description.

[0106] The foregoing has provided a detailed description of the video data network transmission system, system-on-a-chip (SoC), and server provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A network transmission system for video data, characterized in that, Applications in system-on-a-chip (SoC) include: A video data output control module is used to write video data to be transmitted into a target area of ​​video memory in a segmented ping-pong manner; wherein, the target area includes a first segment area and a second segment area, the video data to be transmitted includes first segment data and second segment data, the first segment area is used to store the first segment data, and the second segment area is used to store the second segment data. The network module is used to alternately read target video data from the first segmented region and the second segmented region; and send the video image data of each frame corresponding to the target video data to a remote terminal device for display; wherein, the target video data is the first segmented data or the second segmented data; both the video data output control module and the network module are hardware modules; The alternating reading of target video data from the first segmented region and the second segmented region includes: When the target video data is the first segment data, the segment storage data corresponding to the current first segment data is sequentially and cyclically read into the on-chip buffers of each of the n channels; wherein, the current first segment data is any first segment data, the data length of the segment storage data is less than or equal to a preset length, and n is a positive integer greater than or equal to 2; the sum of the segment storage data of the current first segment data stored in the on-chip buffers of the n channels is the current first segment data; The network module includes: a scheduling submodule, a direct memory access controller, n channel submodules, and a framing submodule; The scheduling submodule is used to control the direct memory access controller to sequentially read the segment storage data corresponding to the current target video data from the video memory, and to sequentially and cyclically store the read segment storage data corresponding to the current target video data into the on-chip cache of the n channel submodules; wherein, the current target video data is any of the target video data, the on-chip cache of the i-th channel submodule is used to store the a-th segment storage data of the current target video data, i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0; The frame-building submodule is used to sequentially and cyclically read the segmented storage data corresponding to each of the target video data from the on-chip buffer of each of the n channel submodules and assemble them into frames to obtain the video image data of each frame corresponding to the target video data; and sequentially send the video image data of each frame obtained by framing to the remote terminal device for display. The network module also includes: The descriptor generation submodule is used to generate direct memory access read data commands corresponding to each segment of the current target video data according to the control of the scheduling submodule; and send the direct memory access read data commands to the direct memory access controller in sequence to control the direct memory access controller to read each segment of the current target video data from the video memory in sequence according to the received direct memory access read data commands.

2. The video data network transmission system according to claim 1, characterized in that, The first segmented region and the second segmented region each include n block regions; n is a positive integer greater than or equal to 2; The video data output control module is specifically used to sequentially and cyclically write the segment storage data corresponding to the current first segment data into each block area of ​​the first segment area according to a preset length; wherein, the current first segment data is any first segment data, and the data length of the segment storage data is less than or equal to the preset length.

3. The video data network transmission system according to claim 2, characterized in that, The step of sequentially and cyclically writing the segmented storage data corresponding to the current first segmented data into each block area of ​​the first segmented region according to a preset length includes: Write the a-th segment data of the current first segment data into the i-th block region of the first segment region; where i is a positive integer less than or equal to n, a = i + (n * j), and j is an integer greater than or equal to 0.

4. The network transmission system for video data according to claim 1, characterized in that, Each of the first segment data and the second segment data is a single frame of video image data.

5. The network transmission system for video data according to claim 1, characterized in that, The scheduling submodule is specifically used to initiate a direct memory access read data command corresponding to the first segment of the current target video data to the direct memory access controller; obtain the first segment of the stored data read by the direct memory access controller from the first block region of the current segment region; write the first segment of the stored data into the on-chip buffer of the first channel submodule, so that the frame grouping submodule reads the first segment of the stored data from the on-chip buffer of the first channel submodule; wherein, the current target video data is any of the target video data; the current segment region is the first segment region or the second segment region; The scheduling submodule is further configured to, when the (b-1)th segment of the current target video data is not the last segment of the current target video data, after initiating a direct memory access read data command corresponding to the (b-1)th segment of the storage data to the direct memory access controller, initiate a direct memory access read data command corresponding to the b-th segment of the storage data to the direct memory access controller; obtain the b-th segment of the storage data read by the direct memory access controller from the j-th block region of the current segment region; write the b-th segment of the storage data into the on-chip buffer of the j-th channel submodule, so that the frame grouping submodule reads the b-th segment of the storage data from the on-chip buffer of the j-th channel submodule; wherein b is a positive integer greater than or equal to 2, j = b - (n*j), j is a positive integer less than or equal to n, and j is an integer greater than or equal to 0.

6. The video data network transmission system according to claim 5, characterized in that, n is 4.

7. The network transmission system for video data according to claim 1, characterized in that, Both the first segmented region and the second segmented region include n block regions, and each block region is used to store the segmented storage data that the on-chip cache of a corresponding channel submodule needs to cache; The direct memory access controller is controlled to sequentially read segmented storage data corresponding to the current target video data from the video memory, including: Based on the identification information corresponding to each segment of the current target video data, the direct memory access controller is controlled to sequentially read each segment of the current target video data from the video memory; wherein, the identification information includes the segment region identifier corresponding to the first segment region or the second segment region where the segmented storage data is located, the block region identifier corresponding to the block region where the segmented storage data is located, and the block region reading order identifier corresponding to the position of the segmented storage data in the block region.

8. The network transmission system for video data according to claim 7, characterized in that, When the current target video data is stored in the first segment region, the segment region identifier in the identification information corresponding to the a-th segment of the current target video data is 0, the block region identifier is i-1, and the block region reading order identifier is j. When the current target video data is stored in the second segment region, the segment region identifier in the identification information corresponding to the a-th segment of the current target video data is 1, the block region identifier is i-1, and the block region reading order identifier is j; where i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0.

9. The network transmission system for video data according to claim 1, characterized in that, Each channel submodule includes: a channel controller and an on-chip cache; The channel controller is used to sequentially store the segmented storage data transmitted by the scheduling submodule into the corresponding on-chip cache according to the control of the scheduling submodule.

10. The network transmission system for video data according to claim 1, characterized in that, The descriptor generation submodule includes: a descriptor address information generation unit, a read length generation unit, a descriptor control information generation unit, and a descriptor assembly unit; The descriptor address information generation unit is used to generate descriptor address information for each segment of the current target video data according to the address information of the target region and the control of the scheduling submodule. The read length generation unit is used to generate descriptor read length information corresponding to the preset length; The descriptor control information generation unit is used to generate descriptor control information for each segment of stored data corresponding to the current target video data. The descriptor assembly unit is used to generate direct memory access read data commands corresponding to each segment of the current target video data based on the descriptor address information, the descriptor read length information, and the descriptor control information.

11. The network transmission system for video data according to claim 10, characterized in that, Both the first segmented region and the second segmented region include n block regions, and each block region is used to store the segmented storage data that the on-chip cache of a corresponding channel submodule needs to cache; The descriptor address information generation unit is specifically used to generate descriptor address information for each segment of the current target video data based on the address range information of the target region and the identification information corresponding to each segment of the current target video data sent by the scheduling submodule; wherein, the address range information includes the starting address and address range of the first segment region and the second segment region respectively, the descriptor address information includes the starting address of each segment of the current target video data within the target region, and the identification information includes the segment region identifier, the block region identifier, and the block region reading order identifier.

12. The network transmission system for video data according to claim 11, characterized in that, In the current target video data, the block region identifier in the identification information corresponding to the a-th segment of stored data is i-1 and the block region reading order identifier is j; where i is a positive integer less than or equal to n, a=i+(n*j), and j is an integer greater than or equal to 0; The starting address of the a-th segment of stored data within the target area is BEGIN_ADDR+SIZE / n*(i-1)+j*DMA_LENGTH; where BEGIN_ADDR is the starting address of the first or second segment region corresponding to the segment region identifier in the identification information corresponding to the a-th segment of stored data, SIZE is the address range of the first or second segment region corresponding to the segment region identifier in the identification information corresponding to the a-th segment of stored data, and DMA_LENGTH is the preset length.

13. The network transmission system for video data according to claim 10, characterized in that, The read length generation unit is specifically used to take the length information stored in the preset length register as the preset length and generate the descriptor read length information corresponding to the preset length.

14. The network transmission system for video data according to claim 13, characterized in that, The network module is also used to send the length information stored in the preset length register to the video data output control module when the length information changes.

15. The network transmission system for video data according to claim 1, characterized in that, The system-on-a-chip is specifically a baseboard management controller.

16. A system-on-a-chip (SoC), characterized in that, include: The network transmission system for video data as described in any one of claims 1 to 15.

17. A server, characterized in that, include: The system-on-a-chip as described in claim 16.

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