A 2T1C global shutter pixel structure and working mode based on a floating gate

Abstract

The present invention discloses a floating-gate-based 2T1C global shutter pixel structure and its working method, belonging to the field of image sensors. The method includes: by arranging the global shutter switch transistor above the signal collection area without additionally occupying the proportion of the photoelectric signal collection area, it ensures that the function of the global shutter is increased without sacrificing the proportion of the photoelectric signal collection area; moreover, the pixel structure proposed by the present invention is simple and has a high shutter efficiency; under the premise of reducing the pixel size and not sacrificing pixel performance in high-resolution application scenarios, the global shutter function on small-size pixel units is realized.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and more particularly to a floating-gate-based 2T1C global shutter pixel structure and its working mode. Background Art

[0002] Charge-coupled device (CCD) and complementary metal oxide semiconductor (CMOS) are the two main technical routes of current image sensors. Their working principles are to convert optical signals into electrical signals, and obtain images by processing and reading the electrical signals. Compared with CCD, complementary metal oxide semiconductor image sensor (CIS) has more flexible functions, higher frame rate, lower power consumption, lower price, and no loss during signal transfer. Currently, it has occupied a larger market share. However, since the realization of functions such as photosensitivity, reading, and reset of CIS pixel units depends on individual transistors, the increase in the number of transistors will compress the area ratio of the photosensitive area of the device. And as the pixel size shrinks, the area ratio of the photosensitive area will be smaller, resulting in a significant decrease in the full well capacity of the pixel, affecting the pixel peak signal-to-noise ratio, thus restricting the requirements of high-resolution application scenarios.

[0003] In addition, the operation of an image sensor chip often involves two exposure methods: rolling shutter and global shutter. Compared with rolling shutter, global shutter requires a shorter exposure time, is suitable for applications that require high dynamic range and low noise, and can avoid image deformation and motion blur when imaging high-speed moving objects. Therefore, in fields such as surveillance and reconnaissance, industrial inspection, and intelligent vehicles, when affected by platform vibration or imaging high-speed moving objects, global shutter is usually required to avoid image distortion. Compared with the solution of adding a mechanical shutter outside the detector to achieve global shutter, the pixel-level global shutter solution has become the main solution for image sensor chips to achieve global shutter due to advantages such as high mechanical stability and high global shutter efficiency. Usually, the simplest global shutter pixel is a 5T structure, as Figure 6 shown. It adds a field effect transistor (SH) on the basis of the structure of a standard 4T CIS pixel, which is used to timely conduct away the subsequent photoelectric signals entering the PD node after all pixels have transferred the collected photoelectric signals from the PD node to the FD node, so as to prevent interference signals from entering the FD node. In addition, its FD node also needs to be shaded to ensure the global shutter efficiency. Since the newly added structure further compresses the area ratio of the photosensitive area in the pixel under the same size, therefore, to ensure sufficient photosensitive area to guarantee the imaging quality, currently, for image sensor chips with device-level global shutter function, the pixel size is usually larger than 2 µm × 2 µm, and the number of pixels integrated on a single chip is difficult to meet the requirements of some high-resolution application scenarios.

[0004] Chinese Patent No. CN102938409A discloses a dual - transistor photosensitive detector based on a composite dielectric - gate MOSFET and its signal reading method. This detector realizes the photosensitive and reading functions of the photosensitive detector by using a photosensitive transistor and a reading transistor respectively, and still ensures good imaging quality at the sub - micron pixel size. However, this detector lacks a device - level global shutter structure, resulting in serious restrictions on its application in scenarios such as capturing high - speed moving objects and imaging on a vibrating platform.

[0005] Generally speaking, in application scenarios that require high resolution, the reduction of pixel size becomes an inevitable trend; while in application scenarios such as reconnaissance and vehicle - mounted applications that require the recognition of high - speed moving objects, global - shutter pixels are essential. The realization of the global - shutter function and small - size pixels restrict each other. Therefore, how to implement the global - shutter function on small - size pixel units without sacrificing pixel performance has become a current research difficulty. Summary of the Invention

[0006] The object of the present invention is: aiming at the problems encountered in the reduction of pixel size of the current global - shutter image sensor, to propose a floating - gate - based 2T1C global - shutter pixel structure and its working mode, and to realize the function of a global - exposure - type image sensor through a simplified structure of two transistors (2T) and a capacitor (1C) in the vertical direction.

[0007] The first object of the present invention is to provide a floating - gate - based 2T1C global - shutter pixel structure. This global - shutter pixel structure specifically includes a floating - gate capacitor, a signal collection region, a floating - gate transistor, a shallow - trench isolation structure, and a global - shutter switch transistor formed on the same semiconductor substrate. The floating - gate capacitor is used for collecting optoelectronic signals, including a capacitor dielectric layer and a capacitor gate electrode sequentially arranged above the semiconductor substrate, and the semiconductor substrate region below the capacitor dielectric layer is the signal collection region. The floating - gate transistor is used for reading optoelectronic signals, including a transistor source, a transistor drain, and a transistor bottom dielectric layer, a transistor floating gate, a transistor top dielectric layer, and a transistor top gate sequentially arranged above the semiconductor substrate between the transistor source and the transistor drain. The shallow - trench isolation structure is located in the lower - substrate range between the floating - gate capacitor and the floating - gate transistor, separating the region near the upper surface of the substrate to prevent the optoelectronic signals collected below the floating - gate capacitor from leaking through the source or drain of the floating - gate transistor. The global - shutter switch transistor is used to realize the function of device - level global shutter. The global - shutter switch transistor includes a switch - transistor bottom dielectric layer, a switch - transistor body region, a switch - transistor top dielectric layer, and a switch - transistor gate electrode sequentially arranged above the semiconductor substrate between the floating - gate capacitor and the floating - gate transistor.

[0008] One end of the switch body region is connected to the capacitor gate, and the other end is connected to the transistor floating gate. All three are in an electrically floating state and are not connected to external voltage interfaces; the capacitor gate and the transistor floating gate are not directly connected; the switch gate and the transistor top gate are not connected to each other; the switch bottom dielectric layer is connected to the capacitor dielectric layer and the transistor bottom dielectric layer respectively, and the switch top dielectric layer is connected to the transistor top dielectric layer; the transistor source, the transistor drain, the transistor top gate, the switch gate, and the semiconductor substrate are connected to different external voltage interfaces respectively.

[0009] Further, the shallow trench isolation structure is located in the substrate surface region below the global shutter switch transistor, and the inside of the shallow trench isolation structure is filled with an insulating dielectric.

[0010] Further, the transistor source and drain have the same doping type, which is opposite to the doping type of the semiconductor substrate; the capacitor gate and the transistor floating gate have the same doping type, which is opposite to the doping type of the switch body region.

[0011] Further, the switch bottom dielectric layer is connected to the capacitor dielectric layer and the transistor bottom dielectric layer respectively, and the three form an integral structure; the switch top dielectric layer is connected to the transistor top dielectric layer, and the two form an integral structure.

[0012] Further, the semiconductor substrate is composed of single crystal silicon, and the materials of the transistor floating gate, the switch body region, and the capacitor gate are composed of polysilicon or single crystal silicon. The materials of the transistor top gate and the switch gate are composed of one of low-resistance polysilicon, aluminum, tantalum, tungsten, hafnium, titanium, or platinum.

[0013] Further, when multiple floating-gate-based 2T1C global shutter pixel structures are arranged in an array, an isolation structure is provided between adjacent pixel structures to reduce the crosstalk of optoelectronic signals between pixels. The isolation structure includes an annular front isolation structure and an annular back isolation structure. The annular front isolation structure separates the region of the substrate near the upper surface between adjacent floating-gate-based 2T1C global shutter pixel structures, and the annular back isolation structure separates the region of the substrate near the bottom between adjacent floating-gate-based 2T1C global shutter pixel structures, and the top of the annular back isolation structure does not contact the bottom of the annular front isolation structure; and, the inside of the isolation structure is filled with an insulating dielectric or a high-concentration doped semiconductor material having the same doping type as the semiconductor substrate.

[0014] The second object of the present invention is to provide a working method for a floating-gate-based 2T1C global shutter pixel structure, and the method includes the following steps:

[0015] Step 1: Initial power-on; 0V voltages are applied to the external voltage interfaces connected to the transistor source, the transistor drain, the transistor top gate, the switch gate, and the semiconductor substrate.

[0016] Step 2: Reset of the signal collection region; By adjusting the voltage of the gate of the switching transistor, an inversion layer channel appears on the upper surface of the body region of the switching transistor, electrically connecting the gate of the capacitor to the floating gate of the transistor, so that the gate of the capacitor and the floating gate of the transistor achieve equipotential; At this time, by applying a voltage difference between the top gate of the transistor and the semiconductor substrate, majority carrier accumulation can occur on the lower side of the dielectric gate capacitor. Part of the minority carriers originally located here recombine with the majority carriers, and the other part flows away from the source and drain of the transistor through diffusion, realizing the reset of the signal collection region;

[0017] Step 3: Generation and collection of photo-generated charges; Maintaining the equipotential state between the gate of the capacitor and the floating gate of the transistor, by changing the voltage difference between the top gate of the transistor and the semiconductor substrate, the majority carriers in the signal collection region are drained, so that a photo-generated charge collection well in a depleted state is formed in the signal collection region. Under the action of light, photo-generated charges are excited in the semiconductor substrate. The photo-generated charges enter the collection well through diffusion and are collected on the lower surface of the dielectric layer of the capacitor under the action of the vertical electric field. The collection of photo-generated charges will change the surface potential on the lower side of the dielectric layer of the capacitor, thereby changing the distribution of carriers in the gate of the capacitor and the floating gate of the transistor, and affecting the potential of the floating gate of the transistor, thus realizing the mapping of the collected photo-generated charge signal to the number of carriers in the floating gate of the transistor;

[0018] Step 4: Closing of the global shutter; When multiple 2T1C global shutter pixel structures based on floating gates are arranged in an array, "Step 3: Generation and collection of photo-generated charges" of all pixel units are carried out simultaneously. By simultaneously changing the voltage of the gate of the switching transistor in all pixel units, the electrical connection between the gate of the capacitor and the floating gate of the transistor in all pixel units is no longer established. At this time, the number of carriers and the potential in the floating gate of the transistor no longer change following the subsequent collection of photo-generated charges, thereby realizing the closing of the global shutter;

[0019] Step 5: Reading of the optoelectronic signal; Controlling the voltage of the gate of the switching transistor of all 2T1C global shutter pixel structure units in the pixel array, maintaining the non-electrical conduction state between the gate of the capacitor and the floating gate of all pixel units. At this time, the threshold voltage of the floating gate transistor depends on the number of carriers in the floating gate of the transistor. The pixel array is read row by row. A voltage difference of 0.1V - 1V is applied between the source and drain of the transistor of the pixel unit to be read. By scanning the voltage of the top gate of the transistor, the threshold voltage of the floating gate transistor is quantized and read according to the current of the drain of the transistor extracted by the subsequent circuit, thereby realizing the reading of the optoelectronic signal collected by each pixel unit.

[0020] The beneficial effects of the present invention are:

[0021] The present invention provides a floating-gate-based 2T1C global shutter pixel structure. By arranging the global shutter switch transistor above the signal collection area, it does not additionally occupy the duty cycle of the optoelectronic signal collection area, ensuring the addition of the global shutter function without sacrificing the proportion of the optoelectronic signal collection area. At the same time, a part of the transistor floating gate has the function of storing optoelectronic signals. The pixel structure proposed by the present invention is simple. Compared with the prior art, when the global shutter pixel size is less than 5×5 µm 2 the duty cycle of the optoelectronic signal collection area is usually less than 50%. The pixel structure proposed by the present invention can still ensure a duty cycle of more than 60% for the optoelectronic signal collection area even when the pixel is reduced to sub-micron size. On the premise of reducing the pixel size and not sacrificing pixel performance in high-resolution application scenarios, the global shutter function on small-size pixel units is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 is the circuit schematic diagram of an image sensor with a floating-gate 2T1C global shutter pixel structure proposed in an embodiment of the present invention;

[0024] Figure 2 is the three-dimensional structure schematic diagram of an image sensor with a floating-gate 2T1C global shutter pixel structure provided in an embodiment of the present invention;

[0025] Figure 3 is the schematic diagram of the X-section of the three-dimensional structure of an image sensor with a floating-gate 2T1C global shutter pixel structure provided in an embodiment of the present invention;

[0026] Figure 4 is the schematic diagram of the Y-section of the three-dimensional structure of an image sensor with a floating-gate 2T1C global shutter pixel structure provided in an embodiment of the present invention;

[0027] Figure 5 is the schematic diagram of the working timing of a device with a floating-gate 2T1C global shutter pixel structure provided in an embodiment of the present invention;

[0028] Figure 6 is the circuit schematic diagram of a 5T global shutter image sensor in the prior art;

[0029] Among them, 101 - floating - gate capacitor; 101a - capacitor dielectric layer; 101b - capacitor gate; 102 - signal collection area; 103 - floating - gate transistor; 103a - transistor source; 103b - transistor drain; 103c - transistor bottom dielectric layer; 103d - transistor floating gate; 103e - transistor top dielectric layer; 103f - transistor top gate; 104 - global shutter switch transistor; 202a - switch transistor bottom dielectric layer; 202b - switch transistor body region; 202c - switch transistor top dielectric layer; 202d - switch transistor gate; 105 - semiconductor substrate voltage port; 201 - semiconductor substrate; 203 - shallow trench isolation structure; 301 - annular front - side isolation structure; 302 - annular back - side isolation structure. Detailed implementation manners

[0030] To make the content of the present invention clearer and easier to understand, the following further explains the content of the present invention in conjunction with the accompanying drawings of the specification. Of course, the present invention is not limited to this specific embodiment, and general substitutions well - known to those skilled in the art are also covered by the protection scope of the present invention.

[0031] Embodiment 1

[0032] The purpose of this embodiment is to provide a floating - gate - based 2T1C global - shutter pixel structure, and its circuit schematic diagram is as Figure 1 shown, including a floating - gate capacitor 101, a signal collection area 102, a floating - gate transistor 103, a global - shutter switch transistor 104, and a semiconductor substrate voltage port 105; wherein the floating - gate capacitor 101 includes a capacitor dielectric layer 101a and a capacitor gate 101b; the floating - gate transistor 103 includes a transistor source 103a, a transistor drain 103b, a transistor bottom dielectric layer 103c, a transistor floating gate 103d, a transistor top dielectric layer 103e, and a transistor top gate 103f.

[0033] The semiconductor substrate voltage port 105 is connected to the signal collection area 102 and provides a substrate voltage for the floating - gate transistor 103. There is a capacitor dielectric layer 101a in series between the signal collection area 102 and the capacitor gate 101b; there is a transistor bottom dielectric layer 103c in series between the semiconductor substrate voltage port 105 and the transistor floating gate 103d; there is a transistor top dielectric layer 103e in series between the transistor floating gate 103d and the transistor top gate 103f; the capacitor gate 101b is connected to one end of the global - shutter switch transistor 104, and the transistor floating gate 103d is connected to the other end of the global - shutter switch transistor 104.

[0034] The three - dimensional structure schematic diagram of an image sensor with a floating - gate - based 2T1C global - shutter pixel structure provided in this embodiment is as Figure 2 shown. The pixel structure is formed on the same semiconductor substrate 201. Except Figure 1In addition to the structure described in the schematic diagram, the pixel structure of the present invention also includes a shallow trench isolation structure 203, which is filled with insulating material to prevent the photoelectric signal collected in the signal collection area 102 from flowing away from the transistor source 103a and the transistor drain 103b during the collection process. The bottom dielectric layer 202a of the switch tube, the switch tube body area 202b, the top dielectric layer 202c of the switch tube and the switch tube gate 202d are the specific structures of the global shutter switch tube 104. Among them, the bottom dielectric layer 202a of the switch tube is respectively connected to the capacitor dielectric layer 101a and the bottom dielectric layer 103c of the transistor, and the three are an integral structure; the top dielectric layer 202c of the switch tube is connected to the top dielectric layer 103e of the transistor, and the two are an integral structure; one end of the switch tube body area 202b is connected to the capacitor gate 101b, and the other end is connected to the transistor floating gate 103d. The three are electrically floating structures, and the material is polysilicon.

[0035] In this embodiment, the transistor source 103a and the transistor drain 103b are ≥10 19 / cm 3 The semiconductor substrate 201 is 10 15 / cm 3 The P-type doped epi layer has a value of ≥10 17 / cm 3 The switch body region 202b is ≤10 16 / cm 3 A low concentration P-type doped region.

[0036] Figure 3 and Figure 4 Embodiments of the present invention Figure 2 The pixel cross-sectional structure along the X direction and along the Y direction, in addition to the structures mentioned above, also involves the isolation structure between adjacent pixels when the pixel structure of the present invention is arranged in an array form, mainly including an annular front isolation structure 301 and an annular back isolation structure 302, both of which are filled with insulating materials or the same doping type as the semiconductor substrate 201 with a doping concentration of ≥10 18 / cm 3 Highly doped semiconductor materials are used to reduce crosstalk between photoelectric signals collected by different pixels.

[0037] Embodiment 2

[0038] The purpose of this embodiment is to provide an image sensor working method based on a floating gate 2T1C global shutter pixel structure. The working method is implemented based on the structure provided in the first embodiment. The timing diagram is as follows: Figure 5As shown; this working mode includes the following 5 steps: initial pressurization, reset of the signal collection area, generation and collection of photo-generated charges, closing of the global shutter, and reading of the optoelectronic signal.

[0039] Step 1: Initial pressurization; apply a voltage of 0V to all voltage ports of the device: transistor source 103a, transistor drain 103b, transistor top gate 103f, switch transistor gate 202d, and semiconductor substrate voltage port 105.

[0040] Step 2: Reset of the signal collection area; raise the voltage of the switch transistor gate 202d, generally 2V - 3V, to form an inversion layer channel on the upper surface of the switch transistor body region 202b, electrically connect the capacitor gate 101b and the transistor floating gate 103d to make them at the same potential; lower the potential of the semiconductor substrate voltage port 105 to -3V - -2V to provide the pressurization condition for the formation of the photo-generated electron collection trap in the subsequent steps; then, by lowering the potential of the transistor top gate 103f, make the potential of the capacitor gate 101b lower than that of the semiconductor substrate voltage port 105, and hole accumulation appears on the lower side (signal collection area 102) of the capacitor dielectric layer 101a. Part of the electrons originally located here recombine with the accumulated holes, and the other part flows away through diffusion from the transistor source 103a and the transistor drain 103b, thus realizing the reset of the signal collection area.

[0041] Step 3: Generation and collection of photo-generated charges; maintain the electrical connection state between the capacitor gate 101b and the transistor floating gate 103d, raise the potential of the transistor top gate 103f to ≥0V, drain the holes in the signal collection area 102, and form a depleted photo-generated electron collection trap in the signal collection area 102. Under the action of external light illumination, photo-generated charge pairs are excited in the semiconductor substrate 201. Among them, the photo-generated electrons enter the electron collection trap through diffusion and are collected at the lower surface of the capacitor dielectric layer 101a under the action of the vertical electric field. As the electrons are collected, the surface potential on the lower side of the capacitor dielectric layer 101a will change accordingly, thereby changing the distribution of carriers in the capacitor gate 101b and the transistor floating gate 103d, and the potential of the transistor floating gate 103d will also become lower accordingly, so as to realize the mapping of the number of collected photo-generated electrons to the number of carriers in the transistor floating gate 103d.

[0042] Step 4: Closing of the global shutter; When multiple floating-gate-based 2T1C global shutter pixel structures of the present invention are arranged in an array, the "third step" of all pixels is carried out simultaneously, and the voltage of the gate 202d of the switching transistor of all pixel units is reduced to ≤ -2V at the same time, so that the capacitor gate 101b and the transistor floating gate 103d in all pixel units are no longer electrically connected. At this time, the number of charges in the transistor floating gate 103d no longer changes following the collection of subsequent photo-generated charges, and the potential of the transistor floating gate 103d no longer changes with external light illumination, thus realizing the closing of the global shutter;

[0043] Step 5: Reading of the optoelectronic signal; Keeping the negative voltage state of the gate 202d of the switching transistor of all pixel units, at this time, the capacitor gate 101b and the transistor floating gate 103d in each pixel unit maintain a non-electrically conductive state. Since the threshold voltage of the floating-gate transistor 103 depends on the number of carriers in the transistor floating gate 103d, its threshold voltage remains unchanged. Then, the pixel array is read out row by row, that is, the potential of the drain 103b of the transistor of the pixel unit to be read out is raised (0.1V - 1V), and the voltage of the top gate 103f of the transistor of the pixels in the row to be read is scanned (from 0V to 5V). According to the current of the drain 103b of the transistor extracted by the subsequent circuit, the threshold voltage of the floating-gate transistor 103 is quantized and read out, that is, the reading of the optoelectronic signals collected by all pixel units is completed.

[0044] In this embodiment, the switching transistor body region 202b adopts a thin layer structure with a thickness of several nanometers to dozens of nanometers to ensure a small volume, which is used to reduce the parasitic photo-response of the transistor floating gate 103d caused by the external light directly irradiating on the switching transistor body region 202b during the "closing of the global shutter" and "reading of the optoelectronic signal" stages, so as to increase the global shutter efficiency.

[0045] This embodiment provides a solution for implementing a global shutter function on sub-micron ultra-small size pixels. By adding only one global shutter switch transistor 104 on the floating gate in the vertical direction, the floating gate not only functions to transfer the voltage signal of the signal collection region 102, but also a part of the floating gate, namely the transistor floating gate 103d, simultaneously has the function of storing optoelectronic signals. Compared with the current conventional solution of adding multiple transistors and storage regions in the horizontal direction to implement the global shutter function, the present invention does not lose the duty cycle of the pixel signal collection region 102, and avoids the degradation of performance indicators such as the pixel full well capacity while implementing the global shutter function, ensuring the imaging quality of sub-micron ultra-small size pixels. In addition, since the global shutter switch transistor 104 of the present invention is a SOI transistor, it effectively shields the influence of the parasitic optoelectronic signal of the semiconductor substrate 201 on the stored signal in the transistor floating gate 103d during the "closing of the global shutter" stage, so that only the part where the external light directly irradiates the body region 202b of the switch transistor will introduce parasitic light response. By adopting back-illuminated imaging, setting up a metal light-shielding structure, reducing the thickness and area of the switch transistor body region 202b, etc., the parasitic light response can be greatly reduced, and the global shutter efficiency of the pixel can be improved. Currently, based on a 10nm switch transistor body region thickness, a high visible light global shutter efficiency (signal collection region quantum efficiency / parasitic light response) greater than 10 4 can be achieved.

[0046] Although the present invention has been disclosed above with preferred embodiments, the above-mentioned embodiments are only for the convenience of illustration and are not intended to limit the present invention. Those skilled in the art can make several modifications and refinements without departing from the spirit and scope of the present invention. The scope of protection claimed by the present invention shall be subject to what is described in the claims.

Claims

1. A 2T1C global shutter pixel structure based on a floating gate, characterized in that: The floating gate-based 2T1C global shutter pixel structure comprises a floating gate capacitor (101), a signal collection region (102), a floating gate transistor (103), a global shutter switch tube (104) and a shallow trench isolation structure (203) formed on the same semiconductor substrate (201); The floating gate capacitor (101), the global shutter switch tube (104) and the floating gate transistor (103) are sequentially arranged on the semiconductor substrate (201); the signal collection area (102) is located below the floating gate capacitor (101) and the global shutter switch tube (104); and the shallow trench isolation structure (203) is also located below the global shutter switch tube (104); The floating gate capacitor (101) is used for collecting photoelectric signals, and comprises a capacitor dielectric layer (101a) and a capacitor gate (101b) sequentially arranged above the semiconductor substrate (201), and the semiconductor substrate (201) region below the capacitor dielectric layer (101a) is a signal collection region (102); The floating gate transistor (103) is used for reading out a photoelectric signal, and comprises a transistor source (103a), a transistor drain (103b), and a transistor bottom dielectric layer (103c), a transistor floating gate (103d), a transistor top dielectric layer (103e), and a transistor top gate (103f) sequentially arranged above the semiconductor substrate (201); The shallow trench isolation structure (203) is located within the lower substrate between the floating gate capacitor (101) and the floating gate transistor (103), separating the area of ​​the substrate close to the upper surface, and is used to prevent the photoelectric signal collected below the floating gate capacitor (101) from being lost through the floating gate transistor source (103a) or transistor drain (103b); The global shutter switch tube (104) is used to realize the function of a device-level global shutter, and the global shutter switch tube (104) comprises a switch tube bottom dielectric layer (202a), a switch tube body region (202b), a switch tube top dielectric layer (202c), and a switch tube gate (202d) which are sequentially arranged above the semiconductor substrate (201); One end of the switch tube body region (202b) is connected to the capacitor gate (101b), and the other end is connected to the transistor floating gate (103d), and all three are in an electrically floating state and are not connected to an external voltage interface; the capacitor gate (101b) is not directly connected to the transistor floating gate (103d); the capacitor gate (101b) and the transistor top gate (103f) are not connected to each other; the transistor source (103a), transistor drain (103b), transistor top gate (103f), switch tube gate (202d), and semiconductor substrate (201) are respectively connected to different external voltage interfaces.

2. The floating gate-based 2T1C global shutter pixel structure according to claim 1, characterized in that: The shallow trench isolation structure (203) is located in a substrate surface area below the global shutter switch tube (104), and an insulating medium is filled inside the shallow trench isolation structure (203).

3. The floating gate-based 2T1C global shutter pixel structure according to claim 2, characterized in that: The transistor source (103a) and the transistor drain (103b) have the same doping type, which is opposite to the doping type of the semiconductor substrate (201); the capacitor gate (101b) and the transistor floating gate (103d) have the same doping type, which is opposite to the doping type of the switch body region (202b).

4. The floating gate-based 2T1C global shutter pixel structure according to claim 3, characterized in that: The bottom dielectric layer (202a) of the switch tube is respectively connected to the capacitor dielectric layer (101a) and the bottom dielectric layer (103c) of the transistor, and the three form an integral structure; the top dielectric layer (202c) of the switch tube is connected to the top dielectric layer (103e) of the transistor, and the two form an integral structure.

5. The floating gate-based 2T1C global shutter pixel structure according to claim 4, characterized in that: The semiconductor substrate (201) is made of single crystal silicon, the transistor floating gate (103d), the switch tube body region (202b), and the capacitor gate (101b) are made of polycrystalline silicon or single crystal silicon, and the transistor top gate (103f) and the switch tube gate (202d) are made of one of polycrystalline silicon, aluminum, tantalum, tungsten, hafnium, titanium, or platinum.

6. A 2T1C global shutter pixel structure array based on floating gate, characterized in that: The array is composed of the floating gate-based 2T1C global shutter pixel structure according to any one of claims 1 to 5 above; an isolation structure is provided between adjacent pixel structures in the array to reduce crosstalk of photoelectric signals between pixels, the isolation structure comprising an annular front isolation structure (301) and an annular back isolation structure (302), the annular front isolation structure (301) separates the substrate regions close to the upper surface between adjacent 2T1C global shutter pixel structures based on the floating gate, the annular back isolation structure (302) separates the substrate regions close to the bottom between adjacent 2T1C global shutter pixel structures based on the floating gate, and the top of the annular back isolation structure (302) and the bottom of the annular front isolation structure (301) do not contact each other; and the material composition of the annular front isolation structure (301) and the annular back isolation structure (302) comprises an insulating medium or a semiconductor material of the same doping type as the semiconductor substrate (201).

7. A working mode of a 2T1C global shutter pixel structure based on a floating gate, characterized in that: The working method is implemented based on the floating gate-based 2T1C global shutter pixel structure according to any one of claims 1 to 5 or the floating gate-based 2T1C global shutter pixel structure array according to claim 6; the working method comprises the steps of: Step 1: Initial power-on; 0V voltage is applied to the external voltage interfaces connected to the transistor source (103a), the transistor drain (103b), the transistor top gate (103f), the switch gate (202d), and the semiconductor substrate (201); Step 2: resetting the signal collection area (102); by adjusting the voltage of the switch tube gate (202d), an inversion layer channel appears on the upper surface of the switch tube body area (202b), the capacitor gate (101b) and the transistor floating gate (103d) are electrically connected, so that the capacitor gate (101b) and the transistor floating gate (103d) achieve the same potential; at this time, by applying a voltage difference between the top gate (103f) of the transistor and the semiconductor substrate (201), majority carriers accumulate on the lower side of the capacitor dielectric layer, part of the minority carriers originally located there are recombined with the majority carriers, and the other part flows away from the transistor source (103a) and the transistor drain (103b) through diffusion, thereby resetting the signal collection area (102); Step 3: Generation and collection of photogenerated charges; maintaining an equipotential state between the capacitor gate (101b) and the transistor floating gate (103d), and displacing the majority of carriers in the signal collection area (102) by changing the voltage difference between the transistor top gate (103f) and the semiconductor substrate (201), so that the signal collection area (102) forms a depleted photogenerated charge collection well. Under the action of light, photogenerated charges are stimulated in the semiconductor substrate (201), and the photogenerated charges enter the collection well through diffusion, and are collected on the lower surface of the capacitor dielectric layer (101a) under the action of a vertical electric field. The collection of photogenerated charges changes the surface potential on the lower side of the capacitor dielectric layer (101a), thereby changing the distribution of carriers in the capacitor gate (101b) and the transistor floating gate (103d), and affecting the potential of the transistor floating gate (103d), thereby realizing the mapping of the collected photogenerated charge signal to the number of carriers in the transistor floating gate (103d); Step 4: closing of the global shutter; when a plurality of floating gate-based 2T1C global shutter pixel structures are arranged in an array, "step 3: generation and collection of photogenerated charges" of all pixel units are performed simultaneously, and by simultaneously changing the voltage of the switch gate (202d) in all pixel units, the capacitor gate (101b) and the transistor floating gate (103d) in all pixel units are no longer electrically conductive, and at this time, the number of carriers and the potential in the transistor floating gate (103d) no longer change with the subsequent collection of photogenerated charges, thereby achieving the closing of the global shutter; Step 5: photoelectric signal reading; controlling the voltage of the switch tube gate (202d) of all the 2T1C global shutter pixel structure units based on floating gate in the 2T1C global shutter pixel structure array based on floating gate, maintaining the non-electrical conduction state of the capacitor gate (101b) and the transistor floating gate (103d) in all pixel units, at which time the threshold voltage of the floating gate transistor (103) depends on the number of carriers in the floating gate (103d) of the transistor, and performing row-by-row reading of the 2T1C global shutter pixel structure array based on floating gate, applying a fixed voltage difference between the transistor source (103a) and the transistor drain (103b) of the pixel unit to be read out, scanning the voltage of the top gate (103f) of the transistor, and quantizing the threshold voltage of the floating gate transistor (103) according to the current of the transistor drain (103b) extracted by the subsequent circuit, thereby realizing the reading of the photoelectric signal collected by each pixel unit.

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