Single-photon detector high-speed turn-off gating circuit, device and system

Abstract

The present invention discloses a high-speed turn-off gating circuit, device and system for a single-photon detector, belonging to the field of optical time domain reflectometers. A quenching broadening circuit is used to delay and broaden the signal output of a discrimination circuit to generate a quenching pulse signal; an FPGA module generates a turn-off gating pulse signal, and the two are combined to form a first mixed signal. The first mixed signal is amplified by a driving circuit and then applied to the negative high-voltage bias terminal of an avalanche diode; a noise removal broadening circuit is used to generate a pulse signal that is synchronous with the quenching pulse but has a phase delay, and the FPGA module generates a noise removal gating signal that is synchronous with the turn-off gating pulse but has a phase delay. The two signals are combined and superimposed on the discrimination reference signal of the discrimination circuit; the FPGA module is used to control the noise removal pulse superimposed on the discrimination reference signal to be higher than the amplitude of the overshoot signal coupled into the load signal. The present invention can eliminate the false signals coupled by the gating to the load, the gating method does not affect the photon response signal, and the response speed is fast.

Description

Technical Field

[0001] The present invention relates to the field of single optical time domain reflectometers, and more specifically, to a high-speed turn-off gating circuit, device, and system for single-photon detectors. Background Art

[0002] The single-photon detector operates in the Geiger mode with a bias voltage higher than the breakdown voltage V br . Once a photon generates an electron-hole pair, an avalanche effect generates a large number of electron-hole pairs, and the current flows through the die and the load resistor R L . The load voltage signals under different conditions of no quenching, large-resistance passive quenching, and pulse active quenching are as Figure 1 shown. Without quenching, the current rises to a certain magnitude and then remains relatively stable. The continuous flow of a large current through the die will ultimately cause the device to burn out. Therefore, a quenching circuit must be added to the single-photon detection receiving circuit. Passive quenching is to connect a large resistor in series at the bias end. By the voltage drop across the large resistor, the bias voltage of the diode is reduced below V br to play a protective role. The time constant of the large resistor is large, and the time to restore the normal bias voltage is very long, which is not suitable for high-speed detection applications. Active quenching is to generate a quenching pulse after receiving the photo-generated pulse and add it to the bias end, so that the voltage quickly drops below V br . After the pulse ends, the bias is immediately restored, and then the normal receiving state is restored.

[0003] Currently, high-precision optical time domain reflectometers (OTDRs) based on single-photon detection technology adopt the active quenching method, and the signal time is in the ns order of magnitude. How to ensure the time efficiency of OTDR is a technical problem that needs to be solved urgently by those skilled in the art. In the existing solutions, the common gating signal is a periodic sine wave or square wave. Since the gating signal will be partially coupled to the load through the diode to form a false signal, subsequent circuits are required to eliminate this influence, mainly including filtering and signal cancellation methods.

[0004] The periodic gating method has the following disadvantages: on the one hand, the detection time efficiency is only 50%, and on the other hand, adding subsequent circuits to the signal link will introduce various adverse factors such as noise, reduction of high-frequency characteristics, and reduction of signal amplitude, which affect the characteristics of the detection signal. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a high-speed turn-off gating circuit, device, and system for single-photon detectors, which can eliminate the false signal coupled to the load by the gating without substantially reducing the OTDR test time efficiency, and the gating method does not affect the photon response signal and has a fast response speed.

[0006] The purpose of the present invention is achieved through the following solutions:

[0007] A high-speed turn-off gating circuit for a single-photon detector, comprising: a discrimination circuit, a driving circuit, a quenching and broadening circuit, a noise-removing and broadening circuit, and an FPGA module; using the quenching and broadening circuit to delay and broaden the signal output of the discrimination circuit to generate a quenching pulse signal; generating a turn-off gating pulse signal through the FPGA module; combining the two to form a first mixed signal, and amplifying the first mixed signal through the driving circuit and applying it to the negative high-voltage bias terminal of the avalanche diode; using the noise-removing and broadening circuit to generate a pulse signal that is synchronized with the quenching pulse but has a phase delay, and the FPGA module generates a noise-removing gating signal that is synchronized with the turn-off gating pulse but has a phase delay, and the two signals are combined and superimposed on the discrimination reference signal of the discrimination circuit; controlling through the FPGA module so that the noise-removing pulse superimposed on the discrimination reference signal is higher than the amplitude of the overshoot signal coupled into the load signal.

[0008] Further, the noise-removing and broadening circuit uses RC delay.

[0009] Further, the delay accuracy of the noise-removing gating signal is 0.1 ns.

[0010] Further, the FPGA module further includes a photon counting unit for performing pulse shaping on the output of the discrimination circuit and then performing photon counting.

[0011] Further, a high-voltage DC-blocking coupling capacitor is provided between the driving circuit and the negative high-voltage bias terminal of the diode.

[0012] Further, a load R is also connected to the negative high-voltage bias terminal of the diode D .

[0013] A high-speed turn-off gating device for a single-photon detector, comprising the high-speed turn-off gating circuit for a single-photon detector as described in any one of the above.

[0014] A high-speed turn-off gating system for a single-photon detector, comprising the high-speed turn-off gating device for a single-photon detector as described above.

[0015] The beneficial effects of the present invention include:

[0016] The solution of the present invention proposes a more effective turn-off gating and related processing circuit, which only applies gating to saturated optical pulses, and no other circuits are added to the signal link. Instead, a synchronous noise-removing signal is added to the discrimination comparison reference signal, realizing the elimination of false signals coupled by the gating to the load under the condition of basically not reducing the OTDR test time efficiency, and the gating method does not affect the photon response signal, and the response speed is fast. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is a load response signal diagram;

[0019] Figure 2 It is a principle block diagram of the turn-off gating circuit in the embodiment of the present invention; wherein, SPD represents a single-photon detector;

[0020] Figure 3 is Figure 2 the waveform diagram of the circuit node in Specific embodiments

[0021] All the features disclosed in all the embodiments in this specification, or all the steps in the methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended, replaced in any way.

[0022] The present invention aims to eliminate the false signals coupled by the gating to the load under the condition of basically not reducing the OTDR test time efficiency. In the specific implementation solution, a more effective turn-off gating and related processing circuit is proposed. The gating is only applied to the saturated optical pulses, and no other circuits are added to the signal link. Instead, a synchronous noise removal signal is added to the discrimination comparison reference signal to eliminate the false signals coupled by the gating to the load. And in the solution of the present invention, the gating method does not affect the photon response signal, has a fast response speed, and basically does not reduce the detection time efficiency.

[0023] More specifically, the working principle of the turn-off gating conceived in the present invention is to turn off the saturated pulse response when receiving strong light, receive the pulse in the non-saturated state when receiving weak light, and add the pulse in the weak light curve to the corresponding position in the strong light curve to synthesize a complete optical signal detection curve, thereby reducing the overall system test time. For further design, the block diagram of the single-photon detector turn-off gating circuit of the present invention is as Figure 2As shown, it includes a discrimination circuit, a drive circuit, a quenching and broadening circuit, a noise removal and broadening circuit, and an FPGA module. A quenching pulse signal is generated through the output of the discrimination circuit and the delay broadening of the quenching and broadening circuit. Specifically, the quenching and broadening circuit is used to perform delay broadening on the signal output of the discrimination circuit to generate a quenching pulse signal; and a turn-off gating pulse signal is generated through the FPGA module. The two are combined to form a mixed signal 1, and the mixed signal 1 is amplified by the drive circuit and then applied to the high-voltage bias terminal of the negative electrode of the avalanche diode. The noise removal and broadening circuit is used to generate a pulse signal that is synchronized with the quenching pulse but has a phase delay, and the FPGA module generates a noise removal gating signal that is synchronized with the turn-off gating pulse but has a phase delay. The two signals are combined and superimposed on the discrimination reference signal of the discrimination circuit. The noise removal pulse superimposed on the discrimination reference signal is higher than the amplitude of the overshoot signal coupled into the load signal. This signal is the standard level amplitude, and the signal terminal for discrimination comparison is a weak level signal. The signal levels of the quenching and noise removal pulses and the gating and noise removal pulses are higher than the overshoot signal, and the signal time width covers the overshoot signal, so that there is no overshoot signal in the discrimination output signal, thereby eliminating the influence of quenching and gating overshoot of the photon detection signal.

[0024] In an embodiment of the present invention, based on Figure 2 the principle block diagram of the turn-off gating circuit therein, the waveform of its circuit nodes is as Figure 3 shown. A load R D is connected between the high-voltage bias terminal of the negative electrode of the diode and the Vh terminal. Further, the gating pulse is a 0.1 ns precision pulse generated by a 10G rate FPGA, and the active quenching is generated by the delay broadening of the discrimination output. The two are combined to form a mixed signal, which is amplified by the drive and then applied to the high-voltage bias terminal of the negative electrode of the diode. The waveform is as Figure 3 the curve ① in. When a pulse appears, the bias voltage drops below the breakdown voltage V br to turn off the avalanche effect. The pulse signal of the bias waveform will be partially coupled to the load R L at the positive electrode of the diode, such as the coupling overshoot shown by the curve ③ in Figure 3 . The overshoot size is related to the amplitude of the bias pulse and the distribution parameters of the diode. Some overshoot signal amplitudes are higher than the photon response signal amplitude. If not processed, the overshoot will form an output pulse through the discrimination circuit, resulting in extra counts, and more serious consequences will cause the circuit system to collapse. The overshoot effect must be eliminated.

[0025] Further, as shown in the principle block Figure 2 diagram, once an avalanche effect caused by photon input or thermal noise generates a pulse signal on R L , the discrimination circuit outputs an electrical pulse P1, and the quenching and broadening circuit generates an active quenching pulse M1, which is applied to the bias terminal. The overshoot of the quenching pulse M1 is coupled to R LAbove, without desiccation, the discrimination circuit generates an output pulse P2 due to overshoot. Similarly, the quenching and broadening circuit will also generate M2 based on P2, and this cycle continues. At the signal output end, continuous outputs P1, P2, P3... are obtained, forming quenching cycle pulses. Similarly, once a gating pulse is applied to the bias terminal, gating cycle pulses are formed in the same way. Additionally, even without optical input and gating input, there is constantly thermal noise in the single-photon detector on R L generating dark count signals, and as a result, various cycles are superimposed, causing the circuit to fail. Therefore, a coupling overshoot noise elimination circuit must be further added to eliminate the invalid cycles.

[0026] The noise elimination processing circuit is shown in Figure 2 . The noise elimination and broadening generate pulses that are synchronized with the quenching pulses but have a phase delay. The FPGA module generates a noise elimination gating that is synchronized with the turn-off gating but has a phase delay. The two signals are combined and superimposed on the discrimination reference signal, as shown in Figure 3 . In the discrimination comparison of the discrimination circuit, since the noise elimination pulses superimposed on the discrimination reference signal are higher than the overshoot signal amplitude coupled into the R L load signal, only the effective photon signals form output pulses in the discrimination output, and the invalid overshoots do not form outputs, such as the photon response output pulses in curve ④. Therefore, the circuit can avoid invalid cycles.

[0027] Regarding the synchronous delay noise elimination and broadening relative to the quenching pulses, if the time delay is too much, it is only equivalent to an increase in the dead time caused by quenching, and has little impact on the system. Therefore, in the concept of this invention, the noise elimination and broadening circuit uses RC delay. The high-precision OTDR gating function is to turn off the optoelectronic response of strong reflected light pulses, and at the same time requires a quick recovery to normal reception after gating. During the overshoot elimination period after gating, signal output is prohibited. If the gating time and the overshoot elimination time are within the attenuation blind area of the optical reflection pulse, the gating will not affect the attenuation blind area. If the gating time and the overshoot elimination time exceed the attenuation blind area of the optical reflection pulse, it will be manifested as an increase in the attenuation blind area and a reduction in the system resolution accuracy. The high-precision OTDR attenuation blind area is less than 40 cm, corresponding to a time of 4 ns. Therefore, it is necessary to minimize the influence time span of gating as much as possible. The concept of this invention reduces it from two aspects. On the one hand, it is the control of delay accuracy. Both the turn-off gating and the noise elimination gating are generated by the FPGA, controlling the delay accuracy to 0.1 ns, which can accurately control the delay accuracy to reduce the delay error. On the other hand, in the circuit link, the overshoot delay at the discrimination comparison node is minimized. Therefore, noise elimination pulses are added to the discrimination comparison reference signal to prohibit overshoot output, and the time used to eliminate the overshoot is the least.

[0028] The specific implementation manners of the present invention are not limited to the above manners. The above description is only the preferred embodiments of the present invention and the technical principles applied. Those skilled in the art can understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the principles and concepts of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

[0029] The units involved in the embodiments of the present invention are implemented based on hardware. Some functions can be implemented in software, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases. Embodiments of the present invention can provide corresponding computer program products or computer programs. The computer program products or computer programs include computer instructions, and the computer instructions are stored in corresponding hardware devices. The corresponding hardware devices read and execute the computer instructions, so that the hardware devices execute the methods provided in the above various alternative implementation manners.

Claims

1. A single-photon detector high-speed shut-off gating circuit, characterized in that: include: Identification circuit, driving circuit, quenching and widening circuit, noise elimination and widening circuit and FPGA module; The signal output of the discrimination circuit is delayed and widened by using the quenching and widening circuit to generate a quenching pulse signal; a shut-off gate pulse signal is generated by using the FPGA module; The two are combined to form a mixed signal 1, which is amplified by the driving circuit and then added to the negative high voltage bias terminal of the avalanche diode; A quenching and noise reduction pulse signal which is synchronized with the quenching pulse but with a phase delay is generated by a noise reduction and widening circuit, and a gated noise reduction pulse signal which is synchronized with the shut-down gated pulse but with a phase delay is generated by an FPGA module. The two signals are combined and superimposed on the discrimination reference signal of the discrimination circuit. The quenching and noise reduction pulse signal and the gated noise reduction pulse signal superimposed on the discrimination reference signal are controlled to be higher than the amplitude of the overshoot signal coupled into the load signal, and the time width of the quenching and noise reduction pulse signal and the gated noise reduction pulse signal covers the overshoot signal.

2. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: The noise removal and widening circuit adopts RC delay.

3. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: The delay accuracy of the gated noise removal pulse signal is 0.1ns.

4. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: The FPGA module also includes a photon counting unit, which is used to perform photon counting after pulse shaping on the output of the discrimination circuit.

5. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: A high-voltage DC-isolating coupling capacitor is arranged between the driving circuit and the cathode high-voltage bias terminal of the diode.

6. The single-photon detector high-speed shut-off gating circuit according to claim 5, characterized in that: A load R is also connected to the negative high voltage bias end of the diode. D .

7. A high-speed shut-off gating device for a single-photon detector, characterized in that: A single-photon detector high-speed shutdown gating circuit comprising any one of claims 1 to 6.

8. A single photon detector high-speed shut-off gating system, characterized in that: It includes the single-photon detector high-speed shutoff gating device as described in claim 7.

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