Vehicle controller, chip awakening method and vehicle

Abstract

The invention relates to the field of vehicle control, and provides a vehicle controller, a chip awakening method and a vehicle, the vehicle controller comprises a first chip and a second chip which are connected through a hard wire, the first chip is configured to receive an awakening instruction, execute a first awakening program to awaken the first chip, and control the level of the hard wire to jump; and the second chip is configured to execute a second wake-up program to wake up the second chip when detecting that the level of the hard wire jumps. The first chip and the second chip are connected through the hard wire, sending and receiving of network messages are not needed, the wakeup time is shortened, and the requirements of network management specifications are met. When the first chip is awakened, the level of the hard wire is controlled to jump, the second chip can be awakened as long as the second chip detects the level jump of the hard wire, then the first chip and the second chip are awakened basically synchronously, real-time execution of functions is guaranteed, and the use experience of a vehicle is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of vehicle control, and in particular to a vehicle controller, a chip wake-up method and a vehicle. Background Art

[0002] With the development of vehicle technology, in order to achieve higher performance of the vehicle, there are two or more chips inside the vehicle controller, and the chips communicate with each other through a bus.

[0003] When the chip in the current vehicle controller is awakened, after one of the chips is awakened, the awakened chip needs to send a network management message through the bus to wake up other chips. Other chips can only be awakened after receiving the network management message, which causes the overall chip wake-up time to be too long and does not meet the requirements of network management specifications. Summary of the invention

[0004] In view of this, the purpose of the present disclosure is to propose a vehicle controller, a chip wake-up method and a vehicle, so as to solve or partially solve the problem that after waking up one of the chips, the awakened chip needs to send a network management message through the bus to wake up other chips, and other chips can only be awakened after receiving the network management message, resulting in the overall chip wake-up time being too long.

[0005] Based on the above purpose, a first aspect of the present disclosure provides a vehicle controller, wherein the vehicle controller includes a first chip and a second chip connected by a hard line.

[0006] The first chip is configured to receive a wake-up instruction, execute a first wake-up program to wake up the first chip, and control the hard line level to jump;

[0007] The second chip is configured to detect a jump in the hard line level and execute a second wake-up program to wake up the second chip.

[0008] Based on the same inventive concept, the second aspect of the present disclosure proposes a chip wake-up method, comprising:

[0009] The first chip receives the wake-up instruction, executes the first wake-up program to wake up the first chip, and controls the hard line level to jump;

[0010] In response to detecting that the hard line level has changed, the second chip executes a second wake-up procedure to wake up the second chip.

[0011] Based on the same inventive concept, the third aspect of the present disclosure proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method as described above when executing the computer program.

[0012] Based on the same inventive concept, a fourth aspect of the present disclosure proposes a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method as described above.

[0013] Based on the same inventive concept, the fifth aspect of the present disclosure provides a vehicle, including the vehicle controller described in the first aspect or the electronic device described in the third aspect or the storage medium described in the fourth aspect.

[0014] From the above, it can be seen that the present disclosure provides a vehicle controller, a chip wake-up method and a vehicle. The vehicle controller includes a first chip and a second chip connected by a hard wire. When the first chip receives the wake-up instruction, it executes the first wake-up program to wake up the first chip and controls the hard wire level to jump. When the second chip detects that the hard wire level jumps, it executes the second wake-up program to wake up the second chip. The first chip and the second chip are connected by a hard wire, and there is no need to send and receive network messages, which shortens the wake-up time and meets the requirements of network management specifications. When the first chip is awakened, the hard wire level jump is controlled. The second chip can be awakened as long as the hard wire level jump is detected, so that the first chip and the second chip can be awakened basically synchronously. Since the time required for hard wire awakening is short, the real-time execution of the function is guaranteed, and the vehicle use experience is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of a vehicle controller provided by an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of a vehicle controller including two chips provided by an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of a vehicle controller including three chips provided by an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of a vehicle controller including three chips provided by another embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of a vehicle controller including three chips provided in yet another embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a vehicle controller including a current limiting resistor provided by an embodiment of the present disclosure;

[0022] Figure 7 A schematic diagram of a vehicle controller including a voltage regulator diode provided by an embodiment of the present disclosure;

[0023] Figure 8 A schematic diagram of a vehicle controller including a current limiting resistor and a voltage stabilizing diode provided by an embodiment of the present disclosure;

[0024] Fig. 9 A schematic diagram of a vehicle controller including four hard wires provided for an embodiment of the present disclosure;

[0025] Fig.10 A schematic diagram of a vehicle controller including four hard wires provided for another embodiment of the present disclosure;

[0026] Fig.11 A flowchart of an exemplary method provided by an embodiment of the present disclosure;

[0027] Fig.12 A schematic diagram of the structure of an exemplary electronic device provided in an embodiment of the present disclosure.

[0028] The reference numerals in the embodiments of the present disclosure are as follows:

[0029] Vehicle controller 100, first chip 101, second chip 102, third chip 103;

[0030] Current limiting resistor 104 and voltage stabilizing diode 105 . DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0032] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] The terms used in this disclosure are explained as follows:

[0034] GPIO: General Purpose Input / Output (GPIO) is a digital interface used to connect and control various external devices.

[0035] With the development of vehicle technology, in order to achieve higher performance of the vehicle, there are two or more chips inside the vehicle controller, and the chips communicate with each other through the private local area network CAN.

[0036] When the chip in the current vehicle controller is awakened, after one of the chips is awakened, the awakened chip needs to send a network management message through the private local area network CAN to wake up other chips. Other chips can only be awakened after receiving the network management message, which causes the overall chip wake-up time to be too long and does not meet the requirements of network management specifications.

[0037] Under normal circumstances, after chip A is awakened, it sends a network management message through the private CAN to wake up chip B. After receiving the network management message, B is initialized. In this case, the wake-up time of the entire body domain controller is basically the wake-up time of chip A + chip B, which is about 250 to 300ms. However, the network management specification requires that the wake-up time of the body domain controller must be guaranteed to be within 100 to 150ms. Therefore, this design does not meet the wake-up requirements of the network management specification for the body domain controller.

[0038] Based on the above description, an embodiment of the present disclosure provides a vehicle controller, characterized in that the vehicle controller includes a first chip and a second chip connected by a hard line. The embodiments of the present application are described below in conjunction with the accompanying drawings.

[0039] Figure 1A schematic diagram of a vehicle controller 100 provided in an embodiment of the present disclosure is shown.

[0040] The vehicle controller 100 includes a plurality of chips, wherein the chips are connected to each other by hard wires. For example, the vehicle controller 100 includes two chips and is a vehicle body domain controller. Figure 1 As shown, the vehicle controller 100 includes a first chip 101 and a second chip 102 connected by hard wires, wherein the number of the hard wires is at least two.

[0041] After receiving the wake-up instruction, the first chip 101 executes its own first wake-up program to wake up the first chip 101 and controls the hard line level to jump. After the second chip 102 detects that the hard line level connected to the first chip 101 jumps, it executes its own second wake-up program to wake up the second chip 102.

[0042] In this embodiment, the type of the wake-up instruction includes at least one of the following: a radio frequency wake-up instruction, a hard-line wake-up instruction, or a bus wake-up instruction. Exemplarily, the hard-line wake-up signal is a switch signal, and the bus signal is a network wake-up signal.

[0043] When there are multiple chips in the body controller, the type of wake-up instruction corresponding to each chip may be the same or different, and each chip corresponds to a different vehicle control function. For example, the vehicle controller 100 includes chip A, chip B and chip C. The vehicle control function corresponding to chip A is the function corresponding to the front area of ​​the vehicle, the vehicle control function corresponding to chip B is the function corresponding to the rear area of ​​the vehicle, and the vehicle control function corresponding to chip C is the function corresponding to the trunk area of ​​the vehicle.

[0044] Through the above scheme, the vehicle controller 100 includes a first chip 101 and a second chip 102 connected by a hard wire. When the first chip 101 receives the wake-up instruction, the first wake-up program is executed to wake up the first chip 101, and the hard wire level is controlled to jump. When the second chip 102 detects that the hard wire level jumps, the second wake-up program is executed to wake up the second chip 102. The first chip 101 and the second chip 102 are connected by a hard wire, and there is no need to send and receive network messages, which shortens the wake-up time and meets the requirements of network management specifications. When the first chip 101 is awakened and controls the hard wire level jump, the second chip 102 can be awakened as long as the hard wire level jump is detected, so that the first chip 101 and the second chip 102 can be awakened basically synchronously, ensuring the real-time execution of functions and improving the vehicle use experience.

[0045] In some embodiments, controlling the hard-line level to jump includes pulling up the hard-line level and pulling down the hard-line level. In this embodiment, pulling down the hard-line level is preferred.

[0046] In some embodiments, the first chip 101 and the second chip 102 are connected via two hard wires, that is, the first chip 101 and the second chip 102 are connected via a first hard wire and a second hard wire. The first hard wire connects the output of the first chip 101 with the input of the second chip 102, that is, one end of the first hard wire is connected to the output of the first chip 101, and the other end is connected to the input of the second chip 102. The second hard wire connects the input of the first chip 101 with the output of the second chip 102, that is, one end of the second hard wire is connected to the input of the first chip 101, and the other end is connected to the output of the second chip 102.

[0047] In this embodiment, the input and output of the first chip 101 and the input and output of the second chip 102 are in the form of pins. In this embodiment, the pins are specifically GPIO pins, and each chip includes at least one input pin and at least one output pin.

[0048] For example, Figure 2 As shown, Figure 2 A schematic diagram of a vehicle controller 100 provided in accordance with another embodiment of the present disclosure is shown.

[0049] The vehicle body domain controller includes two chips, and the two chips are connected by two hard wires. The first chip 101 is chip A, the second chip 102 is chip B, the output pin of the first chip 101 is GPIO_A1, the input pin of the first chip 101 is GPIO_A2, the input pin of the second chip 102 is GPIO_B1, the output pin of the second chip 102 is GPIO_B2, the first hard wire is hard wire C, and the second hard wire is hard wire D. One end of the hard wire C is connected to the output pin of the first chip 101, which is GPIO_A1, and the other end of the hard wire C is connected to the input pin of the second chip 102, which is GPIO_B1. One end of the hard wire D is connected to the input pin of the first chip 101, which is GPIO_A2, and the other end of the hard wire D is connected to the output pin of the second chip 102, which is GPIO_B2.

[0050] Furthermore, if the first chip 101 is chip A, after receiving the wake-up instruction, chip A executes its own first wake-up program to wake up chip A, and at the same time, controls the level of hard line C to jump. After chip B detects that the level of hard line C connected to chip A jumps, it executes its own second wake-up program to wake up chip B.

[0051] Furthermore, if the first chip 101 is chip B, after receiving the wake-up instruction, chip B executes its own second wake-up program to wake up chip B, and at the same time, controls the level of hard line D to jump. After chip A detects that the level of hard line D connected to chip B jumps, it executes its own first wake-up program to wake up chip A.

[0052] Another example, such as Figure 3 As shown, Figure 3 A schematic diagram of a vehicle controller 100 provided in accordance with another embodiment of the present disclosure is shown.

[0053] The vehicle body domain controller includes three chips, namely, the first chip 101 chip A, the second chip 102 chip B and the third chip 103 chip C. Chip A and chip B are connected by two hard wires, namely hard wire C and hard wire D. Chip B and chip C are connected by two hard wires, namely hard wire E and hard wire F.

[0054] The output pin of the first chip 101 is GPIO_A1, the input pin of the first chip 101 is GPIO_A2, the input pins of the second chip 102 are GPIO_B1 and GPIO_B4, the output pins of the second chip 102 are GPIO_B2 and GPIO_B3, the input pin of the third chip 103 is GPIO_C1, and the output pin of the third chip 103 is GPIO_C2. One end of the hard wire C is connected to the output pin GPIO_A1 of the first chip 101, and the other end of the hard wire C is connected to the input pin GPIO_B1 of the second chip 102. One end of the hard wire D is connected to the input pin GPIO_A2 of the first chip 101, and the other end of the hard wire D is connected to the output pin GPIO_B2 of the second chip 102. One end of the hard wire E is connected to the output pin GPIO_B3 of the second chip 102, and the other end of the hard wire E is connected to the input pin GPIO_C1 of the third chip 103. One end of the hard wire F is connected to the input pin GPIO_B4 of the second chip 102 , and the other end of the hard wire F is connected to the output pin GPIO_C2 of the third chip 103 .

[0055] Further, if the first chip 101 is chip A, after receiving the wake-up instruction, chip A executes its own first wake-up program to wake up chip A, and at the same time, controls the level of hard wire C to jump. After chip B detects that the level of hard wire C connected to chip A jumps, it executes its own second wake-up program to wake up chip B. While chip B executes its own second wake-up program to wake up chip B, it controls hard wire E to jump. After chip C detects that the level of hard wire E connected to chip B jumps, it executes its own third wake-up program to wake up chip C.

[0056] Another example, such as Figure 4 As shown, Figure 4 A schematic diagram of a vehicle controller 100 provided in accordance with another embodiment of the present disclosure is shown.

[0057] The vehicle body domain controller includes three chips, namely, the first chip 101 chip A, the second chip 102 chip B and the third chip 103 chip C. Chip A and chip B are connected by two hard wires, namely hard wire C and hard wire D. Chip A and chip C are connected by two hard wires, namely hard wire G and hard wire H.

[0058] The output pins of the first chip 101 are GPIO_A1 and GPIO_A3, the input pins of the first chip 101 are GPIO_A2 and GPIO_A4, the input pin of the second chip 102 is GPIO_B1, the output pin of the second chip 102 is GPIO_B2, the input pin of the third chip 103 is GPIO_C1, and the output pin of the third chip 103 is GPIO_C2. One end of the hard wire C is connected to the output pin GPIO_A1 of the first chip 101, and the other end of the hard wire C is connected to the input pin GPIO_B1 of the second chip 102. One end of the hard wire D is connected to the input pin GPIO_A2 of the first chip 101, and the other end of the hard wire D is connected to the output pin GPIO_B2 of the second chip 102. One end of the hard wire G is connected to the output pin GPIO_A3 of the first chip 101, and the other end of the hard wire G is connected to the input pin GPIO_C1 of the third chip 103. One end of the hard wire H is connected to the input pin GPIO_A4 of the first chip 101 , and the other end of the hard wire H is connected to the output pin GPIO_C2 of the third chip 103 .

[0059] Further, if the first chip 101 is chip A, after receiving the wake-up instruction, chip A executes its own first wake-up program to wake up chip A, and at the same time, controls the levels of hard wire C and hard wire G to jump. After chip B detects that the level of hard wire C connected to chip A jumps, it executes its own second wake-up program to wake up chip B. After chip C detects that the level of hard wire G connected to chip A jumps, it executes its own third wake-up program to wake up chip C.

[0060] Another example, such as Figure 5 As shown, Figure 5 A schematic diagram of a vehicle controller 100 provided in accordance with another embodiment of the present disclosure is shown.

[0061] The vehicle body domain controller includes three chips, namely, the first chip 101 chip A, the second chip 102 chip B and the third chip 103 chip C. Chip A and chip B are connected by two hard wires, namely hard wire C and hard wire D. Chip B and chip C are connected by two hard wires, namely hard wire E and hard wire F. Chip A and chip C are connected by two hard wires, namely hard wire G and hard wire H.

[0062] The output pins of the first chip 101 are GPIO_A1 and GPIO_A3, the input pins of the first chip 101 are GPIO_A2 and GPIO_A4, the input pins of the second chip 102 are GPIO_B1 and GPIO_B4, the output pins of the second chip 102 are GPIO_B2 and GPIO_B3, the input pins of the third chip 103 are GPIO_C1 and GPIO_C3, and the output pins of the third chip 103 are GPIO_C2 and GPIO_C4. One end of the hard wire C is connected to the output pin GPIO_A1 of the first chip 101, and the other end of the hard wire C is connected to the input pin GPIO_B1 of the second chip 102. One end of the hard wire D is connected to the input pin GPIO_A2 of the first chip 101, and the other end of the hard wire D is connected to the output pin GPIO_B2 of the second chip 102. One end of the hard wire E is connected to the output pin GPIO_B3 of the second chip 102, and the other end of the hard wire E is connected to the input pin GPIO_C1 of the third chip 103. One end of the hard wire F is connected to the input pin GPIO_B4 of the second chip 102, and the other end of the hard wire F is connected to the output pin GPIO_C2 of the third chip 103. One end of the hard wire G is connected to the output pin GPIO_A3 of the first chip 101, and the other end of the hard wire G is connected to the input pin GPIO_C3 of the third chip 103. One end of the hard wire H is connected to the input pin GPIO_A4 of the first chip 101, and the other end of the hard wire H is connected to the output pin GPIO_C4 of the third chip 103.

[0063] Further, if the first chip 101 is chip A, after receiving the wake-up instruction, chip A executes its own first wake-up program to wake up chip A, and at the same time, controls the levels of hard wire C and hard wire G to jump. After chip B detects that the level of hard wire C connected to chip A jumps, it executes its own second wake-up program to wake up chip B. After chip C detects that the level of hard wire G connected to chip A jumps, it executes its own third wake-up program to wake up chip C.

[0064] Further, if the first chip 101 is chip B, after receiving the wake-up instruction, chip B executes its own first wake-up program to wake up chip B, and at the same time, controls the levels of hard wire D and hard wire E to jump. After chip A detects that the level of hard wire D connected to chip B jumps, it executes its own second wake-up program to wake up chip A. After chip C detects that the level of hard wire E connected to chip B jumps, it executes its own third wake-up program to wake up chip C.

[0065] In some embodiments, Figure 6 As shown, Figure 6FIG. 1 is a schematic diagram of a vehicle controller 100 provided in another embodiment of the present disclosure. The vehicle controller 100 further includes a current limiting resistor 105, wherein the current limiting resistor 105 is arranged on the hard wire to limit the current in the hard wire and improve the reliability and safety of the circuit.

[0066] In some embodiments, Figure 7 As shown, Figure 7 FIG. 1 is a schematic diagram of a vehicle controller 100 provided in another embodiment of the present disclosure. The vehicle controller 100 further includes a voltage regulator diode 106, wherein the voltage regulator diode 106 is arranged on the hard line to limit the voltage in the hard line and improve the reliability and safety of the circuit.

[0067] In some embodiments, Figure 8 As shown, Figure 8 FIG. 1 is a schematic diagram of a vehicle controller 100 provided by another embodiment of the present disclosure. The vehicle controller 100 may include a current limiting resistor 105 and a voltage zener diode 106 at the same time, wherein the current limiting resistor and the voltage zener diode are arranged in series on the hard line to simultaneously limit the current and voltage in the hard line, further improving the reliability and safety of the circuit.

[0068] In some embodiments, the first chip 101 and the second chip 102 are connected via two first hard wires, and there are four hard wires between the first chip 101 and the second chip 102, including two first hard wires and two second hard wires. The first chip 101 receives the wake-up instruction, executes the first wake-up program to wake up the first chip 101, and simultaneously controls the levels of the two first hard wires to jump. When the second chip 102 detects that the level of at least one first hard wire jumps, it can be considered that the first chip 101 is awakened, and the second chip 102 executes the second wake-up program to wake up the second chip 102.

[0069] For example, Fig. 9 As shown, Fig. 9 A schematic diagram of a vehicle controller 100 provided by another embodiment of the present disclosure is shown. The vehicle body domain controller includes two chips, and the two chips are connected by four hard wires, including two first hard wires C1 and C2, and two second hard wires D1 and D2. The first chip 101 is chip A, and the second chip 102 is chip B.

[0070] The output pins of the first chip 101 are GPIO_A1 and GPIO_A2, the input pins of the first chip 101 are GPIO_A3 and GPIO_A4, the input pins of the second chip 102 are GPIO_B1 and GPIO_B2, the output pins of the second chip 102 are GPIO_B3 and GPIO_B4, the first hard wires are hard wires C1 and C2, and the second hard wires are hard wires D1 and D2. One end of the hard wire C1 is connected to the output pin GPIO_A1 of the first chip 101, and the other end of the hard wire C1 is connected to the input pin GPIO_B1 of the second chip 102. One end of the hard wire C2 is connected to the output pin GPIO_A2 of the first chip 101, and the other end of the hard wire C2 is connected to the input pin GPIO_B2 of the second chip 102. One end of the hard wire D1 is connected to the input pin GPIO_A3 of the first chip 101, and the other end of the hard wire D1 is connected to the output pin GPIO_B3 of the second chip 102. One end of the hard wire D2 is connected to the input pin GPIO_A4 of the first chip 101 , and the other end of the hard wire D2 is connected to the output pin GPIO_B4 of the second chip 102 .

[0071] Furthermore, if the first chip 101 is chip A, after receiving the wake-up instruction, chip A executes its own first wake-up program to wake up chip A, and at the same time, controls the level of hard wire C1 and hard wire C2 to jump. After chip B detects that the level of hard wire C1 and / or hard wire C2 connected to chip A jumps, it executes its own second wake-up program to wake up chip B.

[0072] Through the above solution, two first hard wires are included between the first chip 101 and the second chip 102. When the first chip 101 wakes up, the levels of the two first hard wires are controlled to jump. When the second chip 102 detects that at least one of the two first hard wires jumps, it can be considered that the first chip 101 is awakened. This avoids the problem that the second chip 102 cannot be normally awakened when there is only one first hard wire and the first hard wire is abnormal, and ensures the normal awakening of the two chips.

[0073] Based on the above example, further, if the first chip 101 is chip B, after receiving the wake-up instruction, chip B executes its own second wake-up program to wake up chip B, and at the same time, controls the level of hard wire D1 and hard wire D2 to jump. After chip A detects that the level of hard wire D1 and / or hard wire D2 connected to chip B jumps, it executes its own first wake-up program to wake up chip A.

[0074] In some embodiments, the first chip 101 and the second chip 102 are connected via two first hard wires, and there are four hard wires between the first chip 101 and the second chip 102, including two first hard wires and two second hard wires. The first chip 101 receives the wake-up instruction, executes the first wake-up program to wake up the first chip 101, and simultaneously controls the levels of the two first hard wires to jump. When the second chip 102 detects that the levels of the two first hard wires jump, it can be considered that the first chip 101 is awakened, and the second chip 102 executes the second wake-up program to wake up the second chip 102.

[0075] For example, Fig.10 As shown, Fig.10 A schematic diagram of a vehicle controller 100 provided by another embodiment of the present disclosure is shown. The vehicle body domain controller includes two chips, and the two chips are connected by four hard wires, including two first hard wires C1 and C2, and two second hard wires D1 and D2. The first chip 101 is chip A, and the second chip 102 is chip B.

[0076] The output pins of the first chip 101 are GPIO_A1 and GPIO_A2, the input pins of the first chip 101 are GPIO_A3 and GPIO_A4, the input pins of the second chip 102 are GPIO_B1 and GPIO_B2, the output pins of the second chip 102 are GPIO_B3 and GPIO_B4, the first hard wires are hard wires C1 and C2, and the second hard wires are hard wires D1 and D2. One end of the hard wire C1 is connected to the output pin GPIO_A1 of the first chip 101, and the other end of the hard wire C1 is connected to the input pin GPIO_B1 of the second chip 102. One end of the hard wire C2 is connected to the output pin GPIO_A2 of the first chip 101, and the other end of the hard wire C2 is connected to the input pin GPIO_B2 of the second chip 102. One end of the hard wire D1 is connected to the input pin GPIO_A3 of the first chip 101, and the other end of the hard wire D1 is connected to the output pin GPIO_B3 of the second chip 102. One end of the hard wire D2 is connected to the input pin GPIO_A4 of the first chip 101 , and the other end of the hard wire D2 is connected to the output pin GPIO_B4 of the second chip 102 .

[0077] Furthermore, if the first chip 101 is chip A, after receiving the wake-up instruction, chip A executes its own first wake-up program to wake up chip A, and at the same time, controls the levels of hard wire C1 and hard wire C2 to jump. After chip B detects that the levels of hard wire C1 and hard wire C2 connected to chip A have jumped, it executes its own second wake-up program to wake up chip B.

[0078] Through the above scheme, two first hard wires are included between the first chip 101 and the second chip 102. When the first chip 101 wakes up, the levels of the two first hard wires are controlled to jump. When the second chip 102 detects that both of the two first hard wires jump, it can be considered that the first chip 101 is awakened. The conditions for the second chip 102 to be awakened are improved, and when there is only one first hard wire, the first hard wire erroneously jumps, thereby preventing the second chip 102 from being awakened by mistake, thereby improving the accuracy of chip awakening.

[0079] Based on the above example, further, if the first chip 101 is chip B, after receiving the wake-up instruction, chip B executes its own second wake-up program to wake up chip B, and at the same time, controls the levels of hard wire D1 and hard wire D2 to jump. After chip A detects that the levels of hard wire D1 and hard wire D2 connected to chip B have jumped, it executes its own first wake-up program to wake up chip A.

[0080] Another embodiment of the present disclosure further provides a chip wake-up method, which is applied to the vehicle controller described in the above embodiment. Fig.11 FIG. 1 is a flow chart of an exemplary method provided by an embodiment of the present disclosure. The method may be implemented by the vehicle controller 100. Fig.11 As shown, the method may further include the following steps.

[0081] Step 201: The first chip receives a wake-up instruction, executes a first wake-up program to wake up the first chip, and controls the hard line level to jump.

[0082] Step 202 : In response to detecting that the hard line level has changed, the second chip executes a second wake-up procedure to wake up the second chip.

[0083] In a specific implementation, the vehicle controller includes a first chip and a second chip connected by a hard line. After receiving the wake-up instruction, the first chip executes its own first wake-up program to wake up the first chip, and at the same time, controls the hard line level to jump. After the second chip detects that the hard line level connected to the first chip jumps, it executes its own second wake-up program to wake up the second chip.

[0084] In this embodiment, the type of the wake-up instruction includes at least one of the following: a radio frequency wake-up instruction, a hard-line wake-up instruction, or a bus wake-up instruction. Exemplarily, the hard-line wake-up signal is a switch signal, and the bus signal is a network wake-up signal.

[0085] When there are multiple chips in the body controller, the type of wake-up instruction corresponding to each chip may be the same or different, and each chip corresponds to a different vehicle control function. For example, the vehicle controller includes chip A, chip B and chip C. The vehicle control function corresponding to chip A is the function corresponding to the front area of ​​the vehicle, the vehicle control function corresponding to chip B is the function corresponding to the rear area of ​​the vehicle, and the vehicle control function corresponding to chip C is the function corresponding to the trunk area of ​​the vehicle.

[0086] Through the above scheme, the vehicle controller includes a first chip and a second chip connected by a hard wire. When the first chip receives the wake-up instruction, it executes the first wake-up program to wake up the first chip and controls the hard wire level to jump. When the second chip detects that the hard wire level jumps, it executes the second wake-up program to wake up the second chip. The first chip and the second chip are connected by a hard wire, and there is no need to send and receive network messages, which shortens the wake-up time and meets the requirements of network management specifications. When the first chip is awakened, the hard wire level jump is controlled. The second chip can be awakened as long as the hard wire level jump is detected, so that the first chip and the second chip can be awakened basically synchronously, ensuring the real-time execution of functions and improving the vehicle use experience.

[0087] In some embodiments, step 201 specifically includes:

[0088] Step 2011, the first chip controls the hard line level to jump and starts timing.

[0089] Step 2012: In response to the timing duration being greater than or equal to a preset time threshold, the first chip controls the hard line to recover from the current level to the level before the transition.

[0090] In specific implementation, the first chip starts timing while controlling the hard line level to jump, and continues timing until the timing duration is greater than or equal to a preset time threshold, at which time the first chip controls the hard line to recover from the current level to the level before the jump.

[0091] Exemplarily, the control hard line level is changed to the first chip pulling down the hard line level, and the preset time threshold is 200ms, that is, the first chip pulls down the level and starts timing, and stops pulling down the hard line level after continuously pulling down for 200ms.

[0092] Through the above scheme, since the time it takes for the second chip to detect a jump in the hard-line level is basically around 10ms, after the timing duration is greater than or equal to the preset time threshold, it is considered that the second chip can detect the hard-line level jump. Therefore, after the timing duration is greater than or equal to the preset time threshold, the hard-line level is stopped from being lowered to reduce unnecessary resource loss.

[0093] In some embodiments, step 2011 further includes:

[0094] In response to receiving a wake-up success instruction fed back by the second chip through the hard line, and the timing duration is less than the preset time threshold, the first chip controls the hard line to recover from the current level to the level before the jump.

[0095] In specific implementation, when the first chip receives the wake-up success instruction fed back by the second chip through the hard line, and the timing duration is less than the preset time threshold, it means that the second chip has been awakened and there is no need to continue to control the hard line level jump. Then the first chip controls the hard line to recover from the current level to the level before the jump.

[0096] It should be noted that the method of the embodiment of the present disclosure can be performed by a single device, such as a computer or a server. The method of the present embodiment can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0097] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0098] The vehicle controller 100 of the aforementioned embodiment can be used to implement the corresponding method in any of the aforementioned embodiments. Therefore, the method embodiment has the beneficial effects of the corresponding device embodiment, which will not be repeated here.

[0099] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the chip wake-up method described in any of the above embodiments is implemented.

[0100] Fig.12 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0101] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0102] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0103] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0104] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0105] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0106] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0107] The electronic device of the above embodiment is used to implement the corresponding chip wake-up method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0108] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the chip wake-up method described in any of the above embodiments.

[0109] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0110] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the chip wake-up method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0111] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides a vehicle, including the in-vehicle voice interaction device in the above-mentioned embodiments, the electronic device in the above-mentioned embodiments, and the computer-readable storage medium in the above-mentioned embodiments, and the vehicle equipment implements the chip wake-up method described in any of the above embodiments.

[0112] The vehicle of the above-mentioned embodiment is used to implement the chip wake-up method described in any of the above-mentioned embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0113] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0114] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present disclosure difficult to understand, the known power / ground connections to the integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present disclosure will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it is apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0115] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0116] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A vehicle controller, characterized in that: The vehicle controller includes a first chip and a second chip connected by hard wires, The first chip is configured to receive a wake-up instruction, execute a first wake-up program to wake up the first chip, and control the hard line level to jump; The second chip is configured to detect a jump in the hard line level and execute a second wake-up program to wake up the second chip.

2. The vehicle controller according to claim 1, characterized in that: The first chip and the second chip are connected via a first hard wire and a second hard wire, The first hard wire connects the output of the first chip to the input of the second chip; The second hard wire connects an input of the first chip with an output of the second chip.

3. The vehicle controller according to claim 1, characterized in that: The vehicle controller further includes a current limiting resistor disposed on the hard line.

4. The vehicle controller according to claim 1, characterized in that: The vehicle controller further includes a zener diode disposed on the hard line.

5. The vehicle controller according to claim 2, characterized in that: The first chip and the second chip are connected via two first hard wires; The first chip is configured to receive a wake-up instruction, execute a first wake-up program to wake up the first chip, and control the levels of the two first hard lines to jump; The second chip is configured to detect a level jump of at least one of the first hard lines and execute a second wake-up program to wake up the second chip.

6. The vehicle controller according to claim 2, characterized in that: The first chip and the second chip are connected via two first hard wires; The first chip is configured to receive a wake-up instruction, execute a first wake-up program to wake up the first chip, and control the levels of the two first hard lines to jump; The second chip is configured to detect that the levels of the two first hard wires both change, and execute a second wake-up procedure to wake up the second chip.

7. A chip wake-up method, characterized in that: The vehicle controller according to any one of claims 1 to 6 comprises: The first chip receives the wake-up instruction, executes the first wake-up program to wake up the first chip, and controls the hard line level to jump; In response to detecting that the hard line level has changed, the second chip executes a second wake-up procedure to wake up the second chip.

8. The method according to claim 7, characterized in that The control of the hard line level to jump includes: The first chip controls the hard line level to jump and start timing; In response to the timing duration being greater than or equal to a preset time threshold, the first chip controls the hard line to recover from the current level to the level before the transition.

9. The method according to claim 8, characterized in that After the start of the timer, it also includes: In response to receiving a wake-up success instruction fed back by the second chip through the hard line, and the timing duration is less than the preset time threshold, the first chip controls the hard line to recover from the current level to the level before the jump.

10. A vehicle, characterized in that: A vehicle controller comprising any one of claims 1 to 6.

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