Memory space allocation method, device, computer equipment and storage medium

Abstract

The present application relates to a memory space allocation method, apparatus, computer equipment, computer-readable storage medium and computer program product. The method comprises: obtaining the execution information of the work group and the allocatable space data of the target memory; wherein the execution information at least includes the number of thread bundles of the work group and the space data of the target memory that each thread bundle needs to access; determining the number of target memory slots according to the execution information and the allocatable space data; allocating a target memory slot label to each thread bundle according to the number of target memory slots; executing the target task of the thread bundle accessing the target memory according to the target memory slot label, and releasing the storage space corresponding to the target memory according to the target memory slot label after the execution of the target task is completed. The use of this method can reduce the waste of video memory.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a memory space allocation method, apparatus, computer equipment, storage medium and computer program product. Background Art

[0002] Each work group in the graphics processor includes one or more thread bundles. A thread bundle (Wave) is packaged by 32 processing units (Lane) or 64 processing units. Such a thread bundle is called a SIMD32 (Single Instruction Multiple Data) thread bundle or a SIMD64 thread bundle.

[0003] The thread warps of each work group run in the computing unit. Each processing unit has a copy of the private storage space, and the processing units cannot access each other. Generally, when there are too many register files used by a processing unit and there is no register file to store the result after the operation, the data in some register files will be temporarily saved in the private memory. When the used register files are released or the data is needed, the data will be taken out of the private memory and written to the register files.

[0004] Currently, in related solutions, when allocating private storage space, private space is applied for according to the maximum number of thread warps that can be run simultaneously by a computing unit. However, the more register files a single thread warp uses, the fewer thread warps that can be run simultaneously by the computing unit. Applying for private space according to the maximum number of thread warps that can be run simultaneously by a computing unit will lead to a waste of video memory. Summary of the invention

[0005] Based on this, it is necessary to provide a memory space allocation method, apparatus, computer equipment, computer-readable storage medium and computer program product that can reduce video memory waste in response to the above technical problems.

[0006] In a first aspect, the present application provides a memory space allocation method, comprising:

[0007] Acquire execution information of the work group and data on the allocatable space of the target memory; wherein the execution information includes at least the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access;

[0008] Determining the target memory slot quantity according to the execution information and the allocatable space data;

[0009] Allocating a target memory slot label to each of the thread warps according to the number of the target memory slots;

[0010] According to the target memory slot tag, a target task for the thread warp to access the target memory is executed, and after the execution of the target task is completed, a storage space corresponding to the target memory is released according to the target memory slot tag.

[0011] In one embodiment, determining the target number of memory slots according to the execution information and the allocatable space data includes:

[0012] Calculating the maximum number of thread warps in the work group that are allowed to access the target memory according to the space data of the target memory that each thread warp needs to access and the allocatable storage space data;

[0013] When the maximum number of warps is greater than or equal to the number of warps in the work group, the target number of memory slots is determined according to the maximum number of warps.

[0014] In one embodiment, the execution information further includes the number of register files required to be used by each of the thread warps; and determining the target number of memory slots according to the maximum number of thread warps includes:

[0015] Calculate the maximum number of threads of the thread warp that are allowed to run simultaneously according to the number of register files;

[0016] The target number of memory slots is determined according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads.

[0017] In one embodiment, determining the target number of memory slots according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads includes:

[0018] When the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running threads, assigning the maximum number of simultaneously running threads to the target number of memory slots;

[0019] When the maximum number of thread warps is less than the maximum number of simultaneously running threads, the maximum number of thread warps is assigned to the target number of memory slots.

[0020] In one embodiment, the target memory slot tag is stored in a buffer space; and the step of allocating the target memory slot tag to each of the thread warps according to the number of the target memory slots includes:

[0021] Determine an allocatable range of target memory slot labels according to the number of target memory slots;

[0022] Traversing the current state of each data bit in the buffer space according to the allocatable range;

[0023] When the current state is an unallocatable state, continue to traverse the next data bit;

[0024] When the current state is an allocatable state, the target memory slot tag corresponding to the data bit is allocated to the thread warp, and the current state is updated to an unallocatable state.

[0025] In one of the embodiments, before allocating a target memory slot label to each of the thread warps according to the number of the target memory slots, the method includes:

[0026] Checking whether the target task corresponding to each of the thread warps needs to access the target memory;

[0027] In the case that the target task needs to access the target memory, a step of allocating a target memory slot tag to each of the thread warps according to the number of the target memory slots is performed.

[0028] In a second aspect, the present application further provides a memory space allocation device, comprising:

[0029] A data acquisition module, used to acquire execution information of the work group and data on the allocatable space of the target memory; wherein the execution information at least includes the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access;

[0030] A quantity determination module, used to determine the number of target memory slots according to the execution information and the allocatable space data;

[0031] a label allocation module, configured to allocate a target memory slot label to each of the thread warps according to the number of the target memory slots;

[0032] The space allocation module is used to execute the target task of the thread warp accessing the target memory according to the target memory slot tag, and release the storage space corresponding to the target memory according to the target memory slot tag after the execution of the target task is completed.

[0033] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0034] Acquire execution information of the work group and data on the allocatable space of the target memory; wherein the execution information includes at least the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access;

[0035] Determining the target memory slot quantity according to the execution information and the allocatable space data;

[0036] Allocating a target memory slot label to each of the thread warps according to the number of the target memory slots;

[0037] According to the target memory slot tag, a target task for the thread warp to access the target memory is executed, and after the execution of the target task is completed, a storage space corresponding to the target memory is released according to the target memory slot tag.

[0038] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0039] Acquire execution information of the work group and data on the allocatable space of the target memory; wherein the execution information includes at least the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access;

[0040] Determining the target memory slot quantity according to the execution information and the allocatable space data;

[0041] Allocating a target memory slot label to each of the thread warps according to the number of the target memory slots;

[0042] According to the target memory slot tag, a target task for the thread warp to access the target memory is executed, and after the execution of the target task is completed, a storage space corresponding to the target memory is released according to the target memory slot tag.

[0043] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0044] Acquire execution information of the work group and data on the allocatable space of the target memory; wherein the execution information includes at least the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access;

[0045] Determining the target memory slot quantity according to the execution information and the allocatable space data;

[0046] Allocating a target memory slot label to each of the thread warps according to the number of the target memory slots;

[0047] According to the target memory slot tag, a target task for the thread warp to access the target memory is executed, and after the execution of the target task is completed, a storage space corresponding to the target memory is released according to the target memory slot tag.

[0048] The above-mentioned memory space allocation method, device, computer equipment, storage medium and computer program product obtain the execution information of the work group and the allocatable space data of the target memory to obtain the number of thread bundles of the work group and the space data of the target memory that each thread bundle needs to access, determine the number of target memory slots according to the execution information and the allocatable space data, and then allocate target memory slot labels to each thread bundle according to the number of target memory slots, determine the number of thread bundles that are currently allowed to access the target memory according to the execution information and the allocatable space data, execute the target task of the thread bundle accessing the target memory according to the target memory slot labels, ensure that the thread bundles are allocated within the allowable range, and release the storage space corresponding to the target memory according to the target memory slot labels after the execution of the target task is completed, so that the storage space of the target memory can be dynamically applied for and released within the allowable range, thereby reducing the waste of video memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 An application environment diagram of a memory space allocation method in one embodiment;

[0051] Figure 2 A schematic diagram of a flow chart of a memory space allocation method in an embodiment;

[0052] Figure 3 A schematic diagram of a system workflow in one embodiment;

[0053] Figure 4 A schematic diagram of the relationship between target memory slot tag allocation and release in one embodiment;

[0054] Figure 5 A schematic diagram of a target memory slot tag storage mapping relationship in one embodiment;

[0055] Figure 6 It is a flowchart of step S204 of a memory space allocation method in one embodiment;

[0056] Figure 7 is a structural block diagram of a memory space allocation device in one embodiment;

[0057] Figure 8 is an internal structure diagram of a computer device in one embodiment;

[0058] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in another embodiment. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0060] The memory space allocation method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, the terminal 102 communicates with the server 104 through the network, the terminal 102 can be used to obtain data that the work group needs to process, and send the data to the server 104, the server 104 can be used to distribute the data obtained by the terminal 102 to each computing unit for processing, the server 104 can store the data in the data storage system, and store and retrieve the data to be processed during the data processing process.

[0061] Among them, the server 104 can be implemented by an independent server or a server cluster composed of multiple servers. The server 104 may include a graphics processing unit (GPU, Graphics Processing Unit), which is usually composed of multiple graphics processing clusters (GPC, Graphics Processing Cluster), and each GPC contains multiple slices (SLICE, Slice). Slices are the smallest unit of GPU operation, and the performance of the chip can be controlled by adjusting the number of slices. There are multiple computing units (Computer Unit) in each slice, and the computing unit includes an ALU unit (Arithmetic Logic Unit, Arithmetic Logic Unit), a memory access unit, a register file (RF, Register File), etc. The thread bundle (Wave) is packaged by 32 processing units (Lane) or 64 processing units. Such a thread bundle is called a SIMD32 (Single Instruction Multiple Data) thread bundle or a SIMD64 thread bundle. The server 104 may also include a thread bundle scheduler and a thread bundle builder, wherein the thread bundle scheduler is used to assign thread bundle numbers to thread bundles, and the thread bundle builder requests register file resources and thread bundle numbers from the thread bundle scheduler.

[0062] The terminal 102 may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, IoT devices, and portable wearable devices. IoT devices may be smart speakers, smart TVs, smart air conditioners, smart car devices, etc. Portable wearable devices may be smart watches, smart bracelets, head-mounted devices, etc.

[0063] The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104, or may be placed on a cloud or other network server. The data storage system may be used to store information such as execution information of a work group and data on allocatable space of a target memory. The data storage system may include a register module (REG), a private register, and a load store module (LS).

[0064] In an exemplary embodiment, Figure 2 As shown, a memory space allocation method is provided, which is applied to Figure 1 The server 104 in the example is used as an example to illustrate the method, which includes the following steps S202 to S208. Among them:

[0065] Step S202, obtaining the execution information of the work group and the allocatable space data of the target memory.

[0066] The execution information includes at least the number of thread warps of the work group and the spatial data of the target memory that each thread warp needs to access. The execution information may also include the number of register files that each thread warp needs to use. The target memory may be a private memory, and the execution module of the server 104 may be a shader of a GPU.

[0067] Exemplarily, the server 104 can write configuration information into registers in other modules through the REG register module, thereby configuring the target memory slot number register and the storage space register in the thread warp scheduler, wherein the target memory slot number register is used to record the maximum number of thread warps that each computing unit uses the storage space of the private memory, and this value can be less than or equal to the maximum number of thread warps that the computing unit can run simultaneously; the value of the storage space register is used to indicate whether the shader uses private storage space, and a value of 0 indicates that the shader does not use private storage space, and a value of 1 indicates that private storage space needs to be used.

[0068] Step S204, determining the target memory slot quantity according to the execution information and the allocatable space data.

[0069] Exemplarily, the server 104 may calculate the number of target memory slots allowed to be used according to the number of warps in the execution information and the space data of the target memory that each warp needs to access. The warp builder of the server 104 may request the warp scheduler for register file resources and warp numbers. After receiving the request from the warp builder, the warp scheduler may check the register file resources and whether there are idle warp numbers. If the resources are sufficient, the register file and warp number may be allocated to the current warp.

[0070] Furthermore, before step S206, the server 104 may also check whether the target tasks corresponding to each thread warp need to access the target memory. If the target tasks need to access the target memory, the server 104 executes the step of allocating target memory slot labels to each thread warp according to the number of target memory slots, that is, when the storage space register value is 1, the target memory slot label is allocated to the current thread warp, and the corresponding position of the newly added Buffer space in the thread warp scheduler is modified to 1.

[0071] Step S206: assigning a target memory slot label to each warp according to the number of target memory slots.

[0072] The target memory slot tag is stored in the buffer space.

[0073] Exemplarily, the server 104 may add a buffer in the warp scheduler to record which warps use private storage space, and add a buffer in the LS unit to record the target memory slot tags of the warps. Only warps that use private storage space will be allocated target memory slot tags.

[0074] like Figure 3 As shown in the figure, PM_SLOT_MASK represents the newly added buffer space in the warp scheduler. Each computing unit occupies one layer in the buffer. The buffer depth given in the figure is 2 layers, indicating that there are two computing units in each slice. The unit of the newly added buffer space in the warp scheduler is bit, because each warp may use private storage space.

[0075] Exemplarily, the server 104 can determine the allocatable range of the target memory slot tag based on the number of target memory slots; traverse the current state of each data bit in the buffer space according to the allocatable range; when the current state is an unallocatable state, continue to traverse the next data bit; when the current state is an allocatable state, allocate the target memory slot tag corresponding to the data bit to the thread warp, and update the current state to an unallocatable state.

[0076] Exemplarily, each bit in the newly added buffer space in the warp scheduler is 0 initially. When the warp needs private storage space, that is, the value of the storage space register is 1, the server 104 can traverse the newly added buffer space in the warp scheduler from the position pointed to by the target memory slot tag until the first position with a value of 0 is found and modified to 1, and the current target memory slot tag is sent to the memory access unit, and then the target memory slot tag is increased by 1. When the warp execution ends, the corresponding position of the newly added buffer space in the warp scheduler is set to 0 according to the value of the target memory slot tag. Furthermore, the server 104 can also add a private memory slot number register in the warp scheduler to store the target memory slot number, indicating the number of warps that can use the private storage space.

[0077] like Figure 4 As shown in the figure, the newly added buffer space in the warp scheduler is 64 bits, the value of the private memory slot number register is 58, the newly added buffer space (PM_SLOT_MASK) in the warp scheduler can use the first 58 bits, and the value range of the target memory slot tag (PSID) is 0~57. Initially, no warp uses private storage space, and the newly added buffer space in the warp scheduler is 0, as shown in row a, and the value of the target memory slot tag is 0. If a warp arrives at this time, the 0 bit position of the newly added buffer space in the warp scheduler will be modified to 1, and the target memory slot tag with a value of 0 will be sent back to the warp scheduler, and then the target memory slot tag will be modified to 1, as shown in row b. In row c, if the warp with a target memory slot tag of 1 ends at this time, the memory access unit returns the target memory slot tag to the warp scheduler, and the warp scheduler modifies the first bit of the newly added buffer space in the warp scheduler to 0 according to the value of the target memory slot tag, indicating that the private space of the warp is released, as shown in row d.

[0078] Step S208 , executing the target task of the thread warp to access the target memory according to the target memory slot tag, and releasing the storage space corresponding to the target memory according to the target memory slot tag after the target task is executed.

[0079] Exemplarily, the warp scheduler in the server 104 may send the register file and the warp number back to the warp builder, and the warp scheduler sends the target memory slot tag back to the LS module. The instruction execution data flow (EUDP, Execution Unit Data Path) in the figure is used to execute ALU (arithmetic logic unit) instructions, bypassing PM (private memory) instructions to the LS module, and the LS module can calculate the address of the data in the private memory according to the target memory slot tag after receiving it.

[0080] After the thread warp finishes executing the target task, the LS module sends the target memory slot label to the thread warp scheduler. The thread warp scheduler can modify the corresponding position of the newly added Buffer space in the thread warp scheduler to 0 according to the value of the target memory slot label, thereby releasing the private storage space of the thread warp.

[0081] Exemplarily, the server 104 may also include a memory access unit, which is used to process the memory access instruction bypassed by the instruction execution data stream EUDP and calculate the address of each processing unit in the instruction. If the memory access instruction is a Load instruction, the address is sent to the memory management unit, and the memory management unit reads the data from the video memory; if the memory access instruction is a Store instruction, the address and data are sent to the memory management unit, and the memory management unit writes the data into the video memory of the corresponding address.

[0082] Furthermore, the server 104 may add a 2 m+n The buffer of each layer is m+1 bits in size, 1 bit PmAlloc indicates whether to use PM space, and m bits target memory slot tag.

[0083] like Figure 5 As shown, the row with PmAlloc being 0 indicates that the current thread warp does not use private storage space. m+n The reason for the layer is that there are 2n computing units in SLICE, and the maximum number of thread warps allowed for each computing unit is 2m. For example, n is 1, indicating that each SLICE has 2 computing units, and m is 6, indicating that each computing unit has 64 layers. The layer number corresponds to the thread warp number one by one, that is, the second layer stores the information of thread warp number 2. In order to facilitate the calculation of private memory addresses, a PM address management module is added to the memory access unit. The memory access unit receives the data sent by the thread warp scheduler and transmits the data to the PM address management module for processing. The PM address management module calculates which layer of the Buffer the target memory slot tag should be stored in based on the thread warp number and computing unit ID in the data, and then writes the PmAlloc and target memory slot tag in the data into the corresponding layer position.

[0084] Among them, the value range of the warp ID can be 0 to 2 m -1, and the value range of the compute unit ID can be 0 to 2 n -1. Shifting the compute unit ID (CUID) left by n bits or the upper warp ID, that is, ((CUID << n) | warp number), can obtain the layer number of the warp ID in the Buffer

[0085] Next, when the memory access unit receives the PM instruction sent down by the instruction execution data stream, it sends the CUID and the warp number to the PM address management module, and retrieves the target memory slot label from the ((CUID << n) | warp number) layer of the Buffer, so as to be able to calculate the address of the private memory of each Lane. The private space address calculation formula is:

[0086]

[0087] Among them, the range of the target memory slot label in a single compute unit is 0 to (the number of target memory slots) - 1. In the entire GPU, the value of the target memory slot label is (m * (n * GID + SID) + CUID) * (the number of target memory slots) + the target memory slot label. Where GID is the GPC ID, that is, which GPC in the GPU, SID is the SLICE ID, that is, which SLICE in the GPC. Here, n represents that there are n Slices in each GPC, and m represents that there are m CUs in the SLICE

[0088] In the above memory space allocation method, by obtaining the execution information of the workgroup and the allocable space data of the target memory, the number of warps in the workgroup and the space data of the target memory that each warp needs to access are obtained. According to the execution information and the allocable space data, the number of target memory slots is determined. Then, according to the number of target memory slots, target memory slot labels are allocated to each warp. According to the execution information and the allocable space data, the number of warps that can be allowed to access the target memory currently can be determined. According to the target memory slot label, the target task of the warp accessing the target memory is executed, which can ensure that the warps are allocated within the allowable range, and after the execution of the target task ends, the storage space corresponding to the target memory is released according to the target memory slot label, so as to be able to dynamically apply for and release the storage space of the target memory within the allowable range, thereby reducing video memory waste

[0089] In an exemplary embodiment, as Figure 6 shown, step S204 includes steps S302 to S304. Among them:

[0090] Step S302 : calculating the maximum number of warps in the work group that are allowed to access the target memory according to the space data of the target memory that each warp needs to access and the data of the allocatable storage space.

[0091] Exemplarily, server 104 may preset a tolerable space for the private memory as the allocatable storage space, and calculate the size of the private storage space that can be allocated to each computing unit based on the current total number of computing units, where the value is allocatable storage space data / current total number of computing units.

[0092] Next, the server 104 may calculate the maximum number of thread warps allowed to access the target memory according to the size of the private storage space that can be allocated to each computing unit and the space data of the target memory that each thread warp needs to access, wherein the space data of the target memory that each thread warp needs to access is calculated by the compiler and notified to the driver.

[0093] Step S304: when the maximum number of warps is greater than or equal to the number of warps in the work group, determine the target number of memory slots according to the maximum number of warps.

[0094] The execution information also includes the number of register files that each thread warp needs to use.

[0095] Exemplarily, when the maximum number of thread bundles is greater than or equal to the number of thread bundles in the work group, the server 104 can determine the target number of memory slots based on the maximum number of thread bundles; when the maximum number of thread bundles is less than the number of thread bundles in the work group, the driver cannot apply for a larger private storage space due to video memory limitations, and the server 104 needs to meet the above conditions by reducing the number of GPCs running in the GPU. Since the thread bundles in the work group can only run in the same computing unit, in order to ensure that the thread bundle execution will not deadlock, the target number of memory slots should be greater than or equal to the number of thread bundles in each work group in the compute shader, that is, to ensure that the thread bundles in the same work group can be assigned to the target memory slot tags. The maximum number of thread bundles running in the computing unit is also limited by the number of register files used by the thread bundles. When the number of register files used by the thread bundles exceeds a certain number, the more register files used by the thread bundles, the fewer thread bundles that can run simultaneously.

[0096] Exemplarily, the server 104 may calculate the maximum number of simultaneously running threads of the thread warps allowed to be simultaneously run according to the number of register files, and determine the target number of memory slots according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads.

[0097] Furthermore, the server 104 may assign the maximum number of simultaneously running threads to the target number of memory slots when the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running threads; and assign the maximum number of thread warps to the target number of memory slots when the maximum number of thread warps is less than the maximum number of simultaneously running threads.

[0098] For example, the preset allocatable storage space is 256MB, the total number of CUs in the GPU is 16, and each thread warp uses 1MB of private storage space, then the target number of memory slots is 16, the number of thread warps in the work group is 8, and the maximum number of thread warps that can be run by the computing unit determined by the register file used by the thread warp is 12, then 12 is the final result; if the maximum number of thread warps that can be run by the computing unit determined by the register file used by the thread warp is 20, then the final result is 16 bits; if the number of thread warps in the work group is greater than 16, the driver needs to increase the preset allocatable storage space until the value of the target number of memory slots is greater than or equal to the number of thread warps in each work group in the compute shader. When it is increased to the point where more space cannot be allocated from the video memory, the number of GPCs needs to be reduced.

[0099] In another exemplary embodiment, the server 104 obtains the execution information of the work group and the allocatable space data of the target memory, obtains the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access, and then calculates the maximum number of thread warps in the work group that are allowed to access the target memory based on the space data of the target memory that each thread warp needs to access and the allocatable storage space data.

[0100] When the maximum number of thread warps is greater than or equal to the number of thread warps in the work group, the server 104 calculates the maximum number of simultaneously running threads of the thread warps that are allowed to run simultaneously according to the number of register files; when the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running threads, the server 104 assigns the maximum number of simultaneously running threads to the target number of memory slots; when the maximum number of thread warps is less than the maximum number of simultaneously running threads, the server 104 assigns the maximum number of thread warps to the target number of memory slots.

[0101] Next, check whether the target task corresponding to each thread bundle needs to access the target memory. If the target task needs to access the target memory, determine the allocatable range of the target memory slot label according to the number of target memory slots, and traverse the current state of each data bit in the buffer space according to the allocatable range; if the current state is an unallocatable state, continue to traverse the next data bit; if the current state is an allocatable state, allocate the target memory slot label corresponding to the data bit to the thread bundle, and update the current state to an unallocatable state.

[0102] Finally, the server 104 executes the target task of the thread warp to access the target memory according to the target memory slot tag, and releases the storage space corresponding to the target memory according to the target memory slot tag after the target task is executed.

[0103] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0104] Based on the same inventive concept, the embodiment of the present application also provides a memory space allocation device for implementing the memory space allocation method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more memory space allocation device embodiments provided below can refer to the limitations of the memory space allocation method above, and will not be repeated here.

[0105] In an exemplary embodiment, Figure 7 As shown, a memory space allocation device is provided, including: a data acquisition module 702, a quantity determination module 704, a label allocation module 706 and a space allocation module 708, wherein:

[0106] The data acquisition module 702 is used to acquire the execution information of the work group and the allocatable space data of the target memory; wherein the execution information at least includes the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access;

[0107] A quantity determination module 704 is used to determine the number of target memory slots according to the execution information and the allocatable space data;

[0108] The label allocation module 706 is used to allocate a target memory slot label to each thread warp according to the number of target memory slots;

[0109] The space allocation module 708 is used to execute the target task of the thread warp to access the target memory according to the target memory slot tag, and release the storage space corresponding to the target memory according to the target memory slot tag after the target task is executed.

[0110] In one embodiment, the quantity determination module 704 includes:

[0111] A data processing unit, configured to calculate a maximum number of thread warps in the work group that are allowed to access the target memory according to the space data of the target memory that each thread warp needs to access and the allocatable storage space data;

[0112] The data calculation unit is used to determine the target memory slot quantity according to the maximum number of thread warps when the maximum number of thread warps is greater than or equal to the number of thread warps of the work group.

[0113] In one of the embodiments, the execution information also includes the number of register files required to be used by each thread warp; the data calculation unit is specifically used to: calculate the maximum number of simultaneously running threads of the thread warp that are allowed to run simultaneously according to the number of register files; determine the target number of memory slots according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads.

[0114] In one of the embodiments, the data calculation unit is specifically used to: when the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running threads, assign the maximum number of simultaneously running threads to the target number of memory slots; when the maximum number of thread warps is less than the maximum number of simultaneously running threads, assign the maximum number of thread warps to the target number of memory slots.

[0115] In one of the embodiments, the target memory slot tag is stored in the buffer space; the space allocation module 708 is specifically used to: determine the allocatable range of the target memory slot tag according to the number of target memory slots; traverse the current state of each data bit in the buffer space according to the allocatable range; when the current state is an unallocatable state, continue to traverse the next data bit; when the current state is an allocatable state, allocate the target memory slot tag corresponding to the data bit to the thread warp, and update the current state to an unallocatable state.

[0116] In one of the embodiments, the device further includes: a data checking unit, configured to check whether a target task corresponding to each thread bundle needs to access a target memory; if the target task needs to access the target memory, executing a step of allocating a target memory slot label to each thread bundle according to the number of target memory slots.

[0117] Each module in the above-mentioned memory space allocation device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0118] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 8 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store information such as the execution information of the work group and the allocatable space data of the target memory. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a memory space allocation method is implemented.

[0119] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Fig. 9 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a memory space allocation method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0120] Those skilled in the art will understand that Fig. 9The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0121] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the following steps when executing the computer program: obtaining execution information of a work group and allocatable space data of a target memory; wherein the execution information includes at least the number of thread bundles of the work group and space data of the target memory that each thread bundle needs to access; determining the number of target memory slots according to the execution information and the allocatable space data; allocating a target memory slot tag to each thread bundle according to the number of target memory slots; executing a target task of the thread bundle to access the target memory according to the target memory slot tag, and releasing the storage space corresponding to the target memory according to the target memory slot tag after the execution of the target task is completed.

[0122] In one embodiment, when the processor executes the computer program, the following steps are further implemented: according to the space data of the target memory that each thread warp needs to access and the allocatable storage space data, the maximum number of thread warps in the work group that are allowed to access the target memory is calculated; when the maximum number of thread warps is greater than or equal to the number of thread warps in the work group, the number of target memory slots is determined according to the maximum number of thread warps.

[0123] In one embodiment, when executing the computer program, the processor further implements the following steps: calculating the maximum number of simultaneously running threads of the thread warps that are allowed to run simultaneously according to the number of register files; and determining the target number of memory slots according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads.

[0124] In one embodiment, when the processor executes the computer program, the following steps are further implemented: when the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running threads, the maximum number of simultaneously running threads is assigned to the target number of memory slots; when the maximum number of thread warps is less than the maximum number of simultaneously running threads, the maximum number of thread warps is assigned to the target number of memory slots.

[0125] In one embodiment, the processor further implements the following steps when executing the computer program: determining an allocatable range of the target memory slot tag according to the number of target memory slots; traversing the current state of each data bit in the buffer space according to the allocatable range; when the current state is an unallocatable state, continuing to traverse the next data bit; when the current state is an allocatable state, allocating the target memory slot tag corresponding to the data bit to the thread warp, and updating the current state to an unallocatable state.

[0126] In one embodiment, when the processor executes the computer program, the following steps are further implemented: checking whether the target task corresponding to each thread warp needs to access the target memory; if the target task needs to access the target memory, executing the step of allocating a target memory slot label to each thread warp according to the number of target memory slots.

[0127] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: obtaining execution information of a work group and allocatable space data of a target memory; wherein the execution information includes at least the number of thread bundles of the work group and the space data of the target memory that each thread bundle needs to access; determining the number of target memory slots according to the execution information and the allocatable space data; allocating a target memory slot tag to each thread bundle according to the number of target memory slots; executing a target task of the thread bundle to access the target memory according to the target memory slot tag, and releasing the storage space corresponding to the target memory according to the target memory slot tag after the execution of the target task is completed.

[0128] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: based on the space data of the target memory that each thread warp needs to access and the allocatable storage space data, the maximum number of thread warps in the work group that are allowed to access the target memory is calculated; when the maximum number of thread warps is greater than or equal to the number of thread warps in the work group, the number of target memory slots is determined based on the maximum number of thread warps.

[0129] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: calculating the maximum number of simultaneously running threads of the thread warps that are allowed to run simultaneously according to the number of register files; and determining the target number of memory slots according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running thread warps.

[0130] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running thread warps, the maximum number of simultaneously running threads is assigned to the target number of memory slots; when the maximum number of thread warps is less than the maximum number of simultaneously running threads, the maximum number of thread warps is assigned to the target number of memory slots.

[0131] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: determining the allocatable range of the target memory slot tag according to the number of target memory slots; traversing the current state of each data bit in the buffer space according to the allocatable range; when the current state is an unallocatable state, continuing to traverse the next data bit; when the current state is an allocatable state, allocating the target memory slot tag corresponding to the data bit to the thread warp, and updating the current state to an unallocatable state.

[0132] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: checking whether the target task corresponding to each thread warp needs to access the target memory; if the target task needs to access the target memory, executing the step of allocating a target memory slot label to each thread warp according to the number of target memory slots.

[0133] In one embodiment, a computer program product is provided, including a computer program, which implements the following steps when executed by a processor: obtaining execution information of a work group and allocatable space data of a target memory; wherein the execution information includes at least the number of thread bundles of the work group and space data of the target memory that each thread bundle needs to access; determining the number of target memory slots according to the execution information and the allocatable space data; allocating a target memory slot tag to each thread bundle according to the number of target memory slots; executing a target task of the thread bundle accessing the target memory according to the target memory slot tag, and releasing the storage space corresponding to the target memory according to the target memory slot tag after the execution of the target task is completed.

[0134] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: based on the space data of the target memory that each thread warp needs to access and the allocatable storage space data, the maximum number of thread warps in the work group that are allowed to access the target memory is calculated; when the maximum number of thread warps is greater than or equal to the number of thread warps in the work group, the number of target memory slots is determined based on the maximum number of thread warps.

[0135] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: calculating the maximum number of simultaneously running threads of the thread warps that are allowed to run simultaneously according to the number of register files; and determining the target number of memory slots according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads.

[0136] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running threads, the maximum number of simultaneously running threads is assigned to the target number of memory slots; when the maximum number of thread warps is less than the maximum number of simultaneously running threads, the maximum number of thread warps is assigned to the target number of memory slots.

[0137] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: determining the allocatable range of the target memory slot tag according to the number of target memory slots; traversing the current state of each data bit in the buffer space according to the allocatable range; when the current state is an unallocatable state, continuing to traverse the next data bit; when the current state is an allocatable state, allocating the target memory slot tag corresponding to the data bit to the thread warp, and updating the current state to an unallocatable state.

[0138] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: checking whether the target task corresponding to each thread warp needs to access the target memory; if the target task needs to access the target memory, executing the step of allocating a target memory slot label to each thread warp according to the number of target memory slots.

[0139] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0140] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0141] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A memory space allocation method, characterized in that: The method comprises: Acquire execution information of the work group and data on the allocatable space of the target memory; wherein the execution information includes at least the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access; Determining the target memory slot quantity according to the execution information and the allocatable space data; Allocating a target memory slot label to each of the thread warps according to the number of the target memory slots; According to the target memory slot tag, a target task for the thread warp to access the target memory is executed, and after the target task is executed, a storage space corresponding to the target memory is released according to the target memory slot tag.

2. The method according to claim 1, characterized in that The step of determining the target number of memory slots according to the execution information and the allocatable space data comprises: Calculating the maximum number of thread warps in the work group that are allowed to access the target memory according to the space data of the target memory that each thread warp needs to access and the allocatable storage space data; When the maximum number of warps is greater than or equal to the number of warps in the work group, the target number of memory slots is determined according to the maximum number of warps.

3. The method according to claim 2, characterized in that The execution information also includes the number of register files required to be used by each of the thread warps; and determining the target number of memory slots according to the maximum number of thread warps includes: Calculate the maximum number of threads of the thread warp that are allowed to run simultaneously according to the number of register files; The target number of memory slots is determined according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads.

4. The method according to claim 3, characterized in that The determining the target number of memory slots according to the relationship between the maximum number of thread warps and the maximum number of simultaneously running threads includes: When the maximum number of thread warps is greater than or equal to the maximum number of simultaneously running threads, assigning the maximum number of simultaneously running threads to the target number of memory slots; When the maximum number of thread warps is less than the maximum number of simultaneously running threads, the maximum number of thread warps is assigned to the target number of memory slots.

5. The method according to any one of claims 1 to 4, characterized in that: The target memory slot tag is stored in a buffer space; The allocating a target memory slot label to each of the thread warps according to the number of the target memory slots includes: Determine an allocatable range of target memory slot labels according to the number of target memory slots; Traversing the current state of each data bit in the buffer space according to the allocatable range; When the current state is an unallocatable state, continue to traverse the next data bit; When the current state is an allocatable state, the target memory slot tag corresponding to the data bit is allocated to the thread warp, and the current state is updated to an unallocatable state.

6. The method according to claim 1, characterized in that Before allocating a target memory slot label to each of the thread warps according to the number of the target memory slots, the method includes: Checking whether the target task corresponding to each of the thread warps needs to access the target memory; In the case that the target task needs to access the target memory, a step of allocating a target memory slot tag to each of the thread warps according to the number of the target memory slots is performed.

7. A memory space allocation device, characterized in that: The device comprises: A data acquisition module, used to acquire execution information of the work group and data on the allocatable space of the target memory; wherein the execution information at least includes the number of thread warps of the work group and the space data of the target memory that each thread warp needs to access; A quantity determination module, used to determine the number of target memory slots according to the execution information and the allocatable space data; a label allocation module, configured to allocate a target memory slot label to each of the thread warps according to the number of the target memory slots; The space allocation module is used to execute the target task of the thread warp accessing the target memory according to the target memory slot tag, and release the storage space corresponding to the target memory according to the target memory slot tag after the execution of the target task is completed.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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