Massive chip code coverage acquisition method, electronic equipment and medium

Abstract

This invention relates to the field of chip technology, and more particularly to a method, electronic device, and medium for obtaining large-scale chip code coverage. The method includes step S1: constructing different test clusters; step S2: for G... i q Set the verification configuration information, test parameters, and set of interfaces to be verified; Step S3, Parallel verification based on each A i q Generate the corresponding file list and compile to produce the corresponding executable file F. i q Step S4: Parallel processing of B i q Transmitted to G i q The test cases in the F i q Perform the corresponding verification operation to obtain G. i q The set of interfaces to be verified, E, has been flipped. i q Step S5, when G q After all operations are completed, obtain G. q All corresponding E i q Union of GE i q Step S6: When all G q After all operations are completed, retrieve all GE data. i q The union of GE and GD is used to determine the code coverage of large-scale chips. This invention can accurately and quickly obtain the code coverage of large-scale chips.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method, electronic device, and medium for obtaining large-scale chip code coverage. Background Technology

[0002] As the demands on chip computing power continue to increase, chip scale is also constantly expanding. This expansion places extremely high demands on chip verification platforms. Current technologies often employ full-chip, full-area verification methods to verify large-scale chips. However, this approach is slow, time-consuming, has poor operational stability, consumes significant resources, and is susceptible to uncertainties. To address these shortcomings, existing technologies have proposed modular verification methods, building separate verification platforms for different modules. This results in high verification costs and prevents cross-module verification. Furthermore, both of these methods struggle to collect code coverage data for large-scale chips, making it difficult to accurately and quickly obtain such coverage. Therefore, accurately and quickly obtaining code coverage data for large-scale chips has become a pressing technical problem that needs to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a method, electronic device, and medium for obtaining large-scale chip code coverage, which can accurately and quickly obtain large-scale chip code coverage.

[0004] According to a first aspect of the present invention, a method for obtaining large-scale chip code coverage is provided, comprising:

[0005] Step S1: Construct different test clusters {G1, G2, ..., G...} q ,...,G Q}, G q For the g-th test cluster, q ranges from 1 to Q, where Q is the total number of test clusters, and G... q ={G1 q G2 q ,....,G i q ,...,G f(q) q},G i q For G q The i-th test case group, where i ranges from 1 to f(q), and f(q) is G. q The corresponding number of test case groups, different G i q Corresponding to different verification configuration information;

[0006] Step S2, for each G iq Set the corresponding verification configuration information A i q The corresponding test parameter B i q and the corresponding set of interfaces to be verified, D i q , the same G q China G i q The corresponding A i q They are all different, different G q China G i q The corresponding A i q Possibly the same, all D i q The union of these is the set of all unverified interfaces of a large-scale chip, GD.

[0007] Step S3, Parallel based on each G i q Corresponding A i q Generate G i q The corresponding file list is generated, and the corresponding executable file F is compiled. i q Each F i q Located in a separate file directory;

[0008] Step S4: Parallelize B i q Transmitted to the corresponding G i q The test cases in G are then processed in parallel. i q The test cases in the F are based on the corresponding F i q Perform the corresponding verification operation to obtain G. i q The corresponding set of flipped and unverified interfaces E i q ;

[0009] Step S5, when G q Corresponding G i q After all operations are completed, obtain G. q All corresponding E i q Union of GE i q ;

[0010] Step S6, when all Gq After all operations are completed, retrieve all GE data. i q The union of GE and GD is used to determine large-scale chip code coverage.

[0011] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0012] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0013] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the large-scale chip code coverage acquisition method, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects:

[0014] The method described in this invention constructs different test clusters and sets corresponding verification configuration information for test case groups in each test cluster. Based on the verification results of each test case group, it obtains the corresponding set of flipped and unverified interfaces. Then, based on the verification results of a test cluster, it obtains the corresponding set of flipped and unverified interfaces. Finally, based on the verification results of all clusters, it obtains the corresponding set of flipped and unverified interfaces, thereby accurately and quickly obtaining large-scale chip code coverage. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart of a method for obtaining large-scale chip code coverage provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This invention provides a method for obtaining large-scale chip code coverage, such as... Figure 1 As shown, it includes:

[0019] Step S1: Construct different test clusters {G1, G2, ..., G...} q ,...,G Q}, G q For the g-th test cluster, q ranges from 1 to Q, where Q is the total number of test clusters, and G... q ={G1 q G2 q ,....,G i q ,...,G f(q) q},G i q For G q The i-th test case group, where i ranges from 1 to f(q), and f(q) is G. q The corresponding number of test case groups, different G i q Different verification configuration information is required.

[0020] It should be noted that the value of f(q) can also differ depending on the value of q. This means that different test clusters may correspond to different numbers of test case groups, and the number of test cases in each test case group may also differ. The test clusters are specifically divided based on chip functional attributes, with each test cluster corresponding to one chip functional attribute. These chip functional attributes include power consumption, chip interconnect, virtual implementation, and chip reset, etc. Different G... i q Different verification configurations correspond to different verification objectives. Each test cluster is used to execute one test regression.

[0021] Step S2, for each G i q Set the corresponding verification configuration information A i q The corresponding test parameter B i q and the corresponding set of interfaces to be verified, D i q , the same Gq China G i q The corresponding A i q They are all different, different G q China G i q The corresponding A i q Possibly the same, all D i q The union of these is the set of all unverified interfaces of a large-scale chip, GD.

[0022] It should be noted that the same G q China G i q The corresponding A i q "All different" means that the verification configuration information corresponding to the test case groups in the same test cluster is all different, i.e., the same G... q China G i q Running on different verification configurations, the corresponding verification objectives differ. During verification, if the interface to be verified flips, it indicates that the interface has passed verification. If all interfaces to be verified on a large-scale chip flip, it indicates that the code coverage of the large-scale chip has reached 100%. To ensure that all interfaces to be verified participate in verification, all D... i q The union of these is the set of all unverified interfaces of a large-scale chip, GD.

[0023] Step S3, Parallel based on each G i q Corresponding A i q Generate G i q The corresponding file list is generated, and the corresponding executable file F is compiled. i q Each F i q It is located in a separate file directory.

[0024] It should be noted that each verification configuration information contains the module type corresponding to each component module in the large-scale chip verification system. Different file lists are generated based on different verification configuration information. The file lists corresponding to each verification configuration information are compiled in parallel to produce different compilation environments. The file lists corresponding to each verification configuration information are isolated in different file directories and run in parallel, thereby running the verification of different verification targets in parallel.

[0025] Step S4: Parallelize B i q Transmitted to the corresponding Gi q The test cases in G are then processed in parallel. i q The test cases in the F are based on the corresponding F i q Perform the corresponding verification operation to obtain G. i q The corresponding set of flipped and unverified interfaces E i q .

[0026] It should be noted that, due to F i q Located in a separate file directory, therefore different from G i q Test cases can be run in parallel. During the verification process, interfaces that pass verification will be redirected to those awaiting verification.

[0027] Step S5, when G q Corresponding G i q After all operations are completed, obtain G. q All corresponding E i q Union of GE i q .

[0028] It should be noted that a test cluster G q For each test regression, after each test regression is completed, all the flipped and unverified interfaces corresponding to the test cluster are merged.

[0029] Step S6, when all G q After all operations are completed, retrieve all GE data. i q The union of GE and GD is used to determine large-scale chip code coverage.

[0030] It should be noted that when all G q After all executions are completed, merge all the flipped interfaces to be verified corresponding to all test clusters, and then combine the number of interfaces in the set of all interfaces to be verified for large-scale chips to determine the code coverage of large-scale chips.

[0031] As one embodiment, in step S1, different test clusters {G1, G2, ..., G...} are constructed according to the chip's functional attributes. q ,...,G Q}, each G q A corresponding chip functional attribute is defined, which includes power consumption, chip interconnection, virtual implementation, and chip reset.

[0032] As one embodiment, each verification configuration defines the model type of each component module in the large-scale chip verification system. The large-scale chip verification system includes multiple engine modules, data path buses, configuration path buses, storage modules, and PCIe modules. Each engine module implements a chip function, such as image processing, encryption / decryption, or computation. The PCIe modules conform to the Peripheral Component Interconnect Express (PCIe) standard. Each engine module is connected to both the data path bus and the configuration path bus. The storage modules are also connected to both the data path bus and the configuration path bus. All engine modules, storage modules, and PCIe modules are configurable modules. The configurable module type is used to set either a hardware module or a behavioral function model. The data path bus and configuration path bus are always set as hardware modules and are not configurable. Hardware modules include complete internal logic and interfaces. Behavioral function models include module functional logic and interfaces. The functional logic is one type of logic from the complete internal logic. The interface functions of hardware modules and behavioral function models are consistent. The data path subsystem of a large-scale chip consists of the engine module, the data path bus, and the storage module. The PCIe module communicates with the CPU (Central Processing Unit) outside the large-scale chip via its PCIe slot. The configuration path subsystem of the large-scale chip consists of the PCIe module, the configuration path bus, and the engine module. The verification target is a subsystem or system composed of one or more modules; that is, based on the system, verification of any one of its components can be achieved, such as any engine module, storage module, or PCIe module. It can also be a subsystem composed of the engine module, storage module, or both, or the entire system composed of all its components.

[0033] As one embodiment, if the verification target is the interaction between one or more target engine modules, the verification configuration information sets the target engine module as a hardware module, and sets the non-target engine modules, storage modules, and PCIe modules as behavioral-level functional models. The target engine inputs the corresponding test stimulus to the system to verify the verification target.

[0034] As one embodiment, if the verification target is a storage module, the verification configuration information sets all engine modules and PCIE modules to behavioral-level functional models, sets the storage module as a hardware module, and verifies the storage module by inputting external test stimuli to the storage module through the data path bus.

[0035] As one embodiment, if the verification target is a PCIE module, the verification configuration information sets all engine modules and storage modules to behavioral-level functional models, sets the PCIE module as a hardware module, and the PCIE module receives test stimuli from an external CPU to verify the PCIE module.

[0036] As one embodiment, if the verification target is a data path subsystem, the verification configuration information selects at least one target engine module, sets both the target engine module and the storage module as hardware modules, and sets the non-target engine module and the PCIE module as behavioral-level functional models. The target engine module transmits test stimuli to the data path bus, and performs corresponding read or write operations in the storage module based on the transmitted test stimuli through the data path bus to verify the data path.

[0037] As one embodiment, if the verification target is a configuration path subsystem, the verification configuration information selects at least one target engine module, sets both the target engine module and the PCIE module as hardware modules, sets the non-target engine module and the storage module as behavioral-level functional models, the external CPU inputs test stimuli to the PCIE module, and the PCIE module performs the corresponding configuration operation in the target engine module through the configuration path bus to verify the configuration path.

[0038] As one embodiment, the data path bus is pre-configured with a corresponding hardware file list, the configuration path bus is pre-configured with a corresponding hardware file list, and each configurable module is pre-configured with a first file list and a second file list. The first file list is the file list corresponding to the hardware module of the configurable module, and the second file list is the file list corresponding to the behavioral-level functional model of the configurable module. It should be noted that the size of the first file list of the same configurable module is larger than the size of the second file list. Step S3 includes:

[0039] Step S31: Parallel parsing of each G i q Corresponding A i q Determine each G i q The module type identifier corresponding to each configurable module.

[0040] Step S32: If the module type identifier corresponding to the configurable module is the first identifier, then add the first file list corresponding to the configurable module to G. i q If the module type identifier corresponding to a configurable module in the corresponding file list is the second identifier, then add the second file list corresponding to the configurable module to G. i q The corresponding file list.

[0041] Step S33: Generate G by pre-setting the corresponding hardware file list for the data path bus and the corresponding hardware file list for the configuration path bus. i q The corresponding file list.

[0042] Step S34, Compile G i q The corresponding file list generates the corresponding executable file F. i q .

[0043] It should be noted that, through steps S31-S34, the configurable modules involved in the verification target are set as hardware modules, while the configurable modules not involved in the verification target are set as behavioral-level functional models. The data path bus and configuration path bus are always set as hardware modules. Each verification configuration information corresponds to a different file list, resulting in a different list of compiled files and therefore a different compilation environment, isolated in different file directories. Therefore, different verification target processes can be executed in parallel without affecting each other.

[0044] As one embodiment, step S4 includes:

[0045] Step S41, parallelize B i q Transmitted to the corresponding G i q The test cases in the database.

[0046] Step S42, Parallel based on the corresponding F i q Build a corresponding large-scale chip verification system.

[0047] Step S43, Parallel based on G i q The test cases in the system input test stimuli into the corresponding large-scale chip verification system to execute the corresponding verification operations.

[0048] Step S43, Parallel G i q Construct a corresponding set E of all flipped and unverified interfaces. iq .

[0049] It should be noted that G i q After the corresponding large-scale chip verification system is generated, the G-series test cases with transmitted test parameters will be used. i q The test cases in G are transmitted to G i q The corresponding large-scale chip verification system can realize the transmission of test cases with transmitted test parameters in G i q The corresponding large-scale chip verification system is used to achieve G i q Verification of the corresponding verification target.

[0050] As one embodiment, step S6 includes:

[0051] Step S61, when all G q After all operations are completed, retrieve all GE data. i q The union of GE.

[0052] Step S62: Obtain the number of flipped and unverified interfaces NE in GE and the number of unverified interfaces ND in GD.

[0053] Step S63: Determine the large-scale chip code coverage CV based on NE and ND:

[0054] CV = NE / ND.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0056] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0057] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0058] The method described in this embodiment of the invention constructs different test clusters and sets corresponding verification configuration information for test case groups in each test cluster. Based on the verification results of each test case group, the corresponding set of flipped and unverified interfaces is obtained. Then, based on the verification results of a test cluster, the corresponding set of flipped and unverified interfaces is obtained. Finally, based on the verification results of all clusters, the corresponding set of flipped and unverified interfaces is obtained, thereby accurately and quickly obtaining large-scale chip code coverage.

[0059] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for obtaining large-scale chip code coverage, characterized in that, include: Step S1: Construct different test clusters {G1, G2, ..., G...} q ,...,G Q }, G q Let G be the q-th test cluster, where q ranges from 1 to Q, Q is the total number of test clusters, and G is the number of test clusters. q ={G1 q G2 q ,....,G i q ,...,G f(q) q },G i q For G q The i-th test case group, where i ranges from 1 to f(q), and f(q) is G. q The corresponding number of test case groups, different G i q Corresponding to different verification configuration information; Step S2, for each G i q Set the corresponding verification configuration information A i q The corresponding test parameter B i q and the corresponding set of interfaces to be verified, D i q , the same G q China G i q The corresponding A i q All are different, all D i q The union of these is the set of all unverified interfaces of a large-scale chip, GD. Step S3, Parallel based on each G i q Corresponding A i q Generate G i q The corresponding file list is generated, and the corresponding executable file F is compiled. i q Each F i q Located in a separate file directory; Step S4: Parallelize B i q Transmitted to the corresponding G i q The test cases in G are then processed in parallel. i q The test cases in the F are based on the corresponding F i q Perform the corresponding verification operation to obtain G. i q The corresponding set of flipped and unverified interfaces E i q If the interface to be verified flips, it means that the interface to be verified has passed verification. Step S5, when G q Corresponding G i q After all operations are completed, obtain G. q All corresponding E i q Union of GE i q ; Step S6, when all G q After all operations are completed, retrieve all GE data. i q The union of GE and GD is used to determine large-scale chip code coverage.

2. The method according to claim 1, characterized in that, In step S1, different test clusters {G1,G2,...,G...} are constructed based on the chip's functional attributes. q ,...,G Q }, each G q A corresponding chip functional attribute is defined, which includes power consumption, chip interconnection, virtual implementation, and chip reset.

3. The method according to claim 1, characterized in that, Each verification configuration information defines the module type of each component module in the large-scale chip verification system. The large-scale chip verification system includes multiple engine modules, data path buses, configuration path buses, storage modules, and PCIe modules. Each engine module is used to implement a chip function. Each engine module is connected to the data path bus and the configuration path bus respectively. The storage module is connected to the data path bus and the configuration path bus respectively. The PCIe module is connected to the data path bus and the configuration path bus respectively. The engine module, storage module, and PCIe module are all configurable modules. The configurable module can be set as a hardware module or a behavioral-level functional model by configuring the module type. The data path bus and configuration path bus are always set as hardware modules. The hardware module includes the complete internal logic and interface of the module, and the behavioral-level functional model includes the module's functional logic and interface. The functional logic is one of the logics in the complete internal logic. The interface functions of the hardware module and the behavioral-level functional model are consistent.

4. The method according to claim 3, characterized in that, The data path bus is pre-set with a corresponding hardware file list, the configuration path bus is pre-set with a corresponding hardware file list, and each configurable module is pre-set with a first file list and a second file list. The first file list is the file list corresponding to the hardware module of the configurable module, and the second file list is the file list corresponding to the behavioral-level functional model of the configurable module. Step S3 includes: Step S31: Parallel parsing of each G i q Corresponding A i q Determine each G i q The module type identifier corresponding to each configurable module; Step S32: If the module type identifier corresponding to the configurable module is the first identifier, then add the first file list corresponding to the configurable module to G. i q If the module type identifier corresponding to a configurable module in the corresponding file list is the second identifier, then add the second file list corresponding to the configurable module to G. i q The corresponding file list; Step S33: Generate G by pre-setting the corresponding hardware file list for the data path bus and the corresponding hardware file list for the configuration path bus. i q The corresponding file list; Step S34, Compile G i q The corresponding file list generates the corresponding executable file F. i q .

5. The method according to claim 1, characterized in that, Step S4 includes: Step S41, parallelize B i q Transmitted to the corresponding G i q Test cases in; Step S42, Parallel based on the corresponding F i q Build a corresponding large-scale chip verification system; Step S43, Parallel based on G i q The test cases in the system input test stimuli into the corresponding large-scale chip verification system to execute the corresponding verification operations. Step S43, Parallel G i q Construct a corresponding set E of all flipped and unverified interfaces. i q .

6. The method according to claim 1, characterized in that, Step S6 includes: Step S61, when all G q After all operations are completed, retrieve all GE data. i q The union of GE; Step S62: Obtain the number of flipped and unverified interfaces NE in GE and the number of unverified interfaces ND in GD; Step S63: Determine the large-scale chip code coverage CV based on NE and ND: CV = NE / ND.

7. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, the instructions being configured to perform the method of any one of claims 1-6.

8. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-6.

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