Quantum circuit optimization design methods, devices, storage media and computer equipment

Abstract

The quantum circuit optimization design method, apparatus, storage medium, and computer equipment provided in this application, when designing quantum circuits, can first obtain an initial quantum circuit structure pool composed of multiple initial quantum circuits and a first candidate queue composed of blank circuits. Then, based on each initial quantum circuit, the circuits in the first candidate queue are expanded, and the size of the expanded first candidate queue is adjusted according to the performance index values ​​of each circuit in the expanded first candidate queue. Circuits whose performance index values ​​meet preset scores are then selected from the adjusted first candidate queue as circuits to be optimized. Next, this application can randomly select multiple quantum gates from the circuits to be optimized to form a second candidate queue, and then optimize the circuits to be optimized based on each quantum gate in the second candidate queue to obtain the final target circuit. This process can quickly find the circuits to be optimized that can meet the specific training requirements of a QNN.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum circuit optimization design, and particularly relates to a quantum circuit optimization design method and device, a storage medium and a computer device. BACKGROUND

[0002] Quantum machine learning, as an intersection of quantum computing and artificial intelligence, has attracted extensive attention from academia and industry in recent years. By utilizing the unique properties of quantum mechanics, such as quantum superposition and entanglement, quantum machine learning algorithms are expected to break through the limitations of classical machine learning algorithms and achieve significant performance improvement in high-dimensional data processing and complex pattern recognition tasks.

[0003] Quantum neural networks (QNNs) are an important class of quantum machine learning models that construct parameterized quantum circuits and train parameters using classical optimization algorithms. QNNs have shown advantages over classical neural networks in quantum phase recognition, ground state preparation, energy solving, and Gibbs state preparation, and most of them have been preliminarily experimentally verified on noisy intermediate-scale quantum (NISQ) devices.

[0004] Currently, although NISQ devices can provide hundreds of physical qubits, due to the influence of training ability, the current quantum neural network scale is still limited to more than ten qubits, far from the potential of NISQ. Moreover, QNNs often face various challenges during training, such as insufficient expressiveness, barren plateau, and local minimum, which seriously affect the training efficiency and model performance of quantum neural networks. When the number of qubits and circuit depth increases, the performance of QNNs will decrease significantly.

[0005] Therefore, how to accurately design a quantum circuit suitable for the training needs of a specific QNN has become a technical problem to be solved. SUMMARY

[0006] The present application aims to at least solve one of the above technical defects, particularly the technical defect that the prior art cannot accurately design a quantum circuit suitable for the training needs of a specific QNN.

[0007] The present application provides a quantum circuit optimization design method, which comprises:

[0008] An initial quantum circuit structure pool composed of a plurality of initial quantum circuits and a first candidate queue composed of blank circuits are obtained;

[0009] According to each initial quantum circuit, the circuits in the first candidate queue are expanded, and according to the performance index values of each circuit in the expanded first candidate queue, the size of the expanded first candidate queue is adjusted;

[0010] From the adjusted first candidate queue, a circuit with a performance index value meeting a preset score is selected as a to-be-optimized circuit, and a plurality of quantum gates are randomly selected from the to-be-optimized circuit to form a second candidate queue;

[0011] According to each quantum gate in the second candidate queue, the to-be-optimized circuit is optimized to obtain a final target circuit.

[0012] Optionally, the expanding the circuits in the first candidate queue according to each initial quantum circuit to obtain an expanded first candidate queue comprises:

[0013] Ranking each circuit in the first candidate queue, and selecting a circuit ranked first and randomly selecting other circuits from the remaining circuits;

[0014] According to each initial quantum circuit, the circuit ranked first and the other circuits are respectively expanded to obtain a third candidate queue composed of a plurality of expanded circuits;

[0015] According to the performance index values of each expanded circuit in the third candidate queue, the first candidate queue is expanded to obtain an expanded first candidate queue.

[0016] Optionally, the expanding the first candidate queue according to the performance index values of each expanded circuit in the third candidate queue to obtain an expanded first candidate queue comprises:

[0017] Calculating the performance index values of each expanded circuit in the third candidate queue;

[0018] According to the performance index values of each expanded circuit, a plurality of expanded circuits are selected from the third candidate queue and added to the first candidate queue to obtain an expanded first candidate queue.

[0019] Optionally, the calculating the performance index values of each expanded circuit in the third candidate queue comprises:

[0020] Determining a to-be-calculated performance index value, and a Hamiltonian corresponding to the performance index value and a sampling number;

[0021] By combining Clifford gates, the continuous-time evolution described by the Hamiltonian is discretized to obtain a combination of discretized parameter values;

[0022] For each rotating gate in each expansion circuit in the third candidate queue, at each sampling time, randomly select any one parameter value in the parameter value combination as the parameter value of the rotating gate, and after modifying the expansion circuit according to the selected parameter value, calculate the performance index value of the modified expansion circuit until the sampling times are reached.

[0023] Obtain the performance index values calculated after each sampling in each expansion circuit, and calculate the performance index values of each expansion circuit according to the variances corresponding to the performance index values.

[0024] Optionally, the adjusting the size of the expanded first candidate queue according to the performance index values of the circuits in the expanded first candidate queue comprises:

[0025] Calculating the performance index values of the circuits in the expanded first candidate queue to obtain a calculation result.

[0026] According to the calculation result, the circuits in the expanded first candidate queue are sorted in descending order, and the size of the expanded first candidate queue is adjusted according to the sorting result and a preset size threshold.

[0027] Optionally, the selecting circuits whose performance index values meet a preset score from the adjusted first candidate queue as the to-be-optimized circuits, and randomly selecting a plurality of quantum gates from the to-be-optimized circuits to form a second candidate queue comprises:

[0028] Determining whether the circuit with the highest performance index value in the adjusted first candidate queue meets a preset score.

[0029] If yes, the circuit meeting the preset score is selected as the to-be-optimized circuit, and a plurality of quantum gates are randomly selected from the to-be-optimized circuit to form a second candidate queue.

[0030] If not, the first candidate queue is updated according to the adjusted first candidate queue, and the step of expanding the circuits in the first candidate queue according to the initial quantum circuits and adjusting the size of the expanded first candidate queue according to the performance index values of the circuits in the expanded first candidate queue is performed.

[0031] Optionally, the optimizing the to-be-optimized circuit according to the quantum gates in the second candidate queue to obtain a final target circuit comprises:

[0032] Selecting any one quantum gate in the second candidate queue as a current quantum gate.

[0033] After removing the current quantum gate from the to-be-optimized circuit, it is determined whether a performance index value of the to-be-optimized circuit after removing the quantum gate is greater than a preset index threshold value;

[0034] If yes, the to-be-optimized circuit after removing the quantum gate is taken as a final target circuit;

[0035] Otherwise, after removing the current quantum gate from the second candidate queue, the step of selecting an arbitrary quantum gate from the second candidate queue as the current quantum gate and the subsequent steps are continuously performed until the performance index value of the to-be-optimized circuit after removing the quantum gate is greater than the preset index threshold value, or there is no quantum gate in the second candidate queue;

[0036] When there is no quantum gate in the second candidate queue, the to-be-optimized circuit is taken as the final target circuit.

[0037] The application further provides a quantum circuit optimization design device, comprising:

[0038] A quantum circuit acquisition module is configured to acquire an initial quantum circuit structure pool composed of a plurality of initial quantum circuits and a first candidate queue composed of blank circuits;

[0039] A candidate queue adjustment module is configured to expand the circuits in the first candidate queue according to each initial quantum circuit, and adjust the size of the expanded first candidate queue according to the performance index values of each circuit in the expanded first candidate queue;

[0040] A to-be-optimized circuit determination module is configured to select a circuit with a performance index value satisfying a preset score from the adjusted first candidate queue as a to-be-optimized circuit, and randomly select a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue;

[0041] A quantum circuit optimization module is configured to optimize the to-be-optimized circuit according to each quantum gate in the second candidate queue to obtain a final target circuit.

[0042] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores computer readable instructions, and the computer readable instructions are executed by one or more processors to make the one or more processors execute the steps of the quantum circuit optimization design method in any one of the above embodiments.

[0043] The application further provides a computer device, comprising one or more processors and a memory.

[0044] The memory stores computer readable instructions which, when executed by the one or more processors, perform the steps of the quantum circuit optimization design method of any of the above embodiments.

[0045] From the above technical solutions, the embodiments of the present application have the following advantages:

[0046] The quantum circuit optimization design method, device, storage medium and computer equipment provided by the present application can first obtain an initial quantum circuit structure pool composed of a plurality of initial quantum circuits and a first candidate queue composed of blank circuits when designing a quantum circuit. Then, each initial quantum circuit is expanded to the circuits in the first candidate queue, and the size of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue. Then, the circuit with a performance index value meeting a preset score is selected from the adjusted first candidate queue as a to-be-optimized circuit. Next, the present application can randomly select a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue, and then optimize the to-be-optimized circuit according to each quantum gate in the second candidate queue to obtain a final target circuit. In this process, a two-round search framework is designed. The first round of the search framework first performs a round of coarse search, so as to effectively evaluate and optimize the expression ability and training gradient stability of the quantum circuit according to the performance index value, and quickly find a to-be-optimized circuit that can meet the specific QNN training requirements. Then, on the basis of the to-be-optimized circuit, the present application attempts to reduce the redundant quantum gates in the to-be-optimized circuit, thereby reducing the circuit overhead and improving the operation efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0048] Figure 1 A flowchart of a quantum circuit optimization design method provided by an embodiment of the present application;

[0049] Figure 2 A flowchart of selecting a circuit with a performance index value meeting a preset score from the adjusted first candidate queue as a to-be-optimized circuit provided by an embodiment of the present application;

[0050] Figure 3 A flowchart of optimizing the to-be-optimized circuit provided by an embodiment of the present application;

[0051] Figure 4A structural schematic diagram of a quantum circuit optimization design device provided by an embodiment of the present application is provided.

[0052] Figure 5 An internal structural schematic diagram of a computer device provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0054] In one embodiment, as shown in Figure 1 , Figure 1 A flowchart of a quantum circuit optimization design method provided by an embodiment of the present application is provided. The present application provides a quantum circuit optimization design method, which can include:

[0055] S110: Obtain an initial quantum circuit structure pool composed of a plurality of initial quantum circuits, and a first candidate queue composed of blank circuits.

[0056] In this step, when optimizing the quantum circuit, the initial quantum circuit structure pool composed of a plurality of initial quantum circuits and the first candidate queue composed of a plurality of blank circuits can be obtained first, and then the blank circuits are expanded based on each initial quantum circuit, so as to find the to-be-optimized circuit that can meet the training requirements.

[0057] Specifically, in order to design an effective method to dynamically control the expressiveness and trainability of QNN to achieve good performance, the present application can use quantum architecture search (QAS) to find the target circuit that can meet the specific QNN training requirements. It can be understood that quantum architecture search (QAS) is a key task in the field of quantum computing, which directly affects the performance and practicality of quantum neural network (QNN). By intelligently searching for the optimal quantum circuit design, QAS can not only maximize the performance of quantum algorithms on specific hardware, but also ensure the scalability and robustness of the algorithms.

[0058] Among them, quantum architecture search is not only an important driving force for the innovation of quantum computing technology, but also a key factor in promoting the practical application of quantum algorithms. In addition, as quantum technology expands to more complex commercial and scientific applications, the importance of QAS will further emerge. In advanced applications such as quantum machine learning and quantum chemical simulation, optimized quantum circuits can greatly improve the efficiency and accuracy of problem solving, accelerating the application process of quantum computing in various industries. Therefore, QAS is not only an important branch of quantum computing technology development, but also one of the key technologies to promote the practicality and commercialization of quantum computing.

[0059] The current QAS scheme generally faces the problems of high training cost and insufficient consideration of quantum neural network training. To solve these challenges, the present application designs a two-round search framework based on existing quantum architecture search. The first search framework first performs a round of coarse search to effectively evaluate and optimize the expression ability and training gradient stability of the quantum circuit according to the performance index value, and quickly find the to-be-optimized circuit that can meet the specific QNN training requirements. Then, based on the to-be-optimized circuit, the present application attempts to reduce the redundant quantum gates in the to-be-optimized circuit, thereby reducing the circuit overhead and improving the operation efficiency.

[0060] Based on this, the present application can select a plurality of initial quantum circuits of single-bit gates or two-bit gates that can be implemented in hardware according to the type of hardware device, and form an initial quantum circuit structure pool , wherein, is the lth initial quantum circuit, then the present application can initialize the first candidate queue , wherein represents a blank circuit.

[0061] It can be understood that the blank circuit here refers to a printed circuit board (PCB) without electronic components or without wiring. It is only a physical carrier with circuit path planning (such as pre-designed copper foil line layer line layout), but without actual electronic components soldered, or internal integrated circuits and other chips have not been packaged and other operations.

[0062] S120: According to each initial quantum circuit, the circuit in the first candidate queue is expanded, and the size of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue.

[0063] In this step, after obtaining the plurality of initial quantum circuits in the initial quantum circuit structure pool and the plurality of blank circuits in the first candidate queue through S110, since the blank circuit does not have electronic elements or the printed circuit board has not been wired, the application can expand the circuits in the first candidate queue according to the initial quantum circuits, which can increase the number of circuits in the first candidate queue, and further more accurately screen the to-be-optimized circuit that meets the training requirements.

[0064] After the application expands the circuits in the first candidate queue, the application can also calculate the performance index value of each circuit in the expanded first candidate queue, so that the size of the expanded first candidate queue can be adjusted according to the performance index value of each circuit, which can not only reduce the calculation amount of the subsequent optimized circuit, but also improve the optimization quality of the circuit.

[0065] The performance index value includes but is not limited to one or more of the RF index value in the quantum network, the quantum state fidelity, the operation complexity, the quantum Fisher matrix, etc., which can form a multi-dimensional evaluation system, and further evaluate the performance of the quantum neural network from a more comprehensive perspective, and provide more accurate decision support for quantum architecture search.

[0066] S130: Selecting a circuit with a performance index value meeting a preset score from the adjusted first candidate queue as a to-be-optimized circuit, and randomly selecting a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue.

[0067] S140: Optimizing the to-be-optimized circuit according to each quantum gate in the second candidate queue to obtain a final target circuit.

[0068] In the above steps, after adjusting the size of the expanded first candidate queue through S120, the application can select a circuit with a performance index value meeting a preset score from the adjusted first candidate queue as a to-be-optimized circuit, and then randomly select a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue, which can optimize the to-be-optimized circuit through the second candidate queue, and thus obtain a final target circuit.

[0069] It can be understood that after the application calculates the performance index value corresponding to each circuit in the adjusted first candidate queue, since the performance index value is evaluated from a more comprehensive perspective of the performance of the quantum neural network, the to-be-optimized circuit selected by the performance index value of each circuit meeting the preset score can better meet the training requirements of the specific quantum neural network.

[0070] In addition, in order to reduce circuit overhead and improve operation efficiency, the application can also select a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue, so as to optimize the to-be-optimized circuit through the second candidate queue, thereby reducing the redundant quantum gates in the to-be-optimized circuit.

[0071] In the above embodiment, when designing a quantum circuit, an initial quantum circuit structure pool composed of a plurality of initial quantum circuits and a first candidate queue composed of blank circuits can be obtained first. Then, each initial quantum circuit is used to expand the circuits in the first candidate queue, and the size of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue. Then, a circuit with a performance index value meeting a preset score is selected from the adjusted first candidate queue as a to-be-optimized circuit. Then, a plurality of quantum gates are randomly selected from the to-be-optimized circuit to form a second candidate queue, and the to-be-optimized circuit is optimized according to each quantum gate in the second candidate queue to obtain a final target circuit. In this process, a two-round search framework is designed. The first round of search framework first performs a round of coarse search, so as to effectively evaluate and optimize the expression ability and training gradient stability of the quantum circuit according to the performance index value, and quickly find a to-be-optimized circuit that can meet the specific QNN training requirements. Then, on the basis of the to-be-optimized circuit, the redundant quantum gates in the to-be-optimized circuit are tried to be reduced, thereby reducing the circuit overhead and improving the operation efficiency.

[0072] In one embodiment, the expansion of the first candidate queue in S120 according to each initial quantum circuit can include:

[0073] S121: ranking each circuit in the first candidate queue and selecting a circuit ranked first, and then randomly selecting other circuits from the remaining circuits.

[0074] S122: expanding the circuit ranked first and the other circuits respectively according to each initial quantum circuit, to obtain a third candidate queue composed of a plurality of expanded circuits.

[0075] S123: expanding the first candidate queue according to the performance index value of each expanded circuit in the third candidate queue, to obtain an expanded first candidate queue.

[0076] In this embodiment, when the circuits in the first candidate queue are expanded, the circuits in the first candidate queue can be ranked first, and then the circuit ranked first is selected, and other circuits are randomly selected from the remaining circuits. Then, the ranked first circuit and the other circuits are respectively expanded according to the initial quantum circuits, and a third candidate queue composed of a plurality of expanded circuits is obtained. Finally, the first candidate queue is expanded according to the performance index value of each expanded circuit, and the expanded first candidate queue is obtained.

[0077] In a specific implementation, the first candidate queue can be initialized by the application , wherein represents a blank circuit, and then the circuit ranked first in is selected for expansion, and a candidate queue is obtained. Then, the circuits ranked first in other than the circuit ranked first are randomly selected for expansion, and the candidate queue is expanded, wherein The smaller the value is, the greater the probability of selection is. Finally, the two queues are combined to obtain a third candidate queue composed of a plurality of expanded circuits.

[0078] In this embodiment, when the circuits in the first candidate queue are ranked, they can be ranked from the performance index, or from the adaptability to hardware, or from the ease of use and design flexibility. When they are ranked from the performance index, they can be ranked from the scalability, error rate, stability, running speed and frequency response. The specific selection can be selected according to the actual situation, and is not limited here.

[0079] Further, when the other circuits are randomly selected from the remaining circuits, a common selection function can be used for selection, such as the softmax function used by the application to complete the selection work, and then the other circuits selected are expanded. Of course, the application can also use other ways to randomly select, and the specific selection can be selected according to the actual situation, and is not limited here.

[0080] In one embodiment, S123, expanding the first candidate queue according to the performance index value of each expanded circuit in the third candidate queue to obtain the expanded first candidate queue, can include:

[0081] S1231: Calculate the performance index value of each expanded circuit in the third candidate queue.

[0082] S1232: selecting a plurality of expansion circuits from the third candidate queue according to the performance index values of the expansion circuits, and adding the plurality of expansion circuits to the first candidate queue to obtain an expanded first candidate queue.

[0083] In the embodiment, when expanding the first candidate queue, the performance index values of the expansion circuits in the third candidate queue are calculated first, and then a plurality of expansion circuits are selected from the third candidate queue according to the performance index values of the expansion circuits and added to the first candidate queue, so as to obtain an expanded first candidate queue.

[0084] In the embodiment, when expanding the first candidate queue, the performance index values of the expansion circuits in the third candidate queue are calculated first, and then a plurality of expansion circuits are selected from the third candidate queue according to the performance index values of the expansion circuits and added to the first candidate queue, so as to obtain an expanded first candidate queue.

[0085] In one embodiment, the calculation of the performance index values of the expansion circuits in the third candidate queue in S1231 can include:

[0086] S2311: determining a performance index value to be calculated, and a Hamiltonian corresponding to the performance index value and a sampling number.

[0087] S2312: discretizing continuous-time evolution described by the Hamiltonian by combining Clifford gates to obtain a combination of discretized parameter values.

[0088] S2313: for each rotation gate in each expansion circuit in the third candidate queue, randomly selecting any one of the parameter values in the combination of parameter values as the parameter value of the rotation gate at each sampling, and calculating the performance index value of the modified expansion circuit after modifying the expansion circuit according to the selected parameter value until the sampling number is reached.

[0089] S2314: obtaining the performance index values calculated after each sampling in each expansion circuit, and calculating the performance index values of the expansion circuits according to the variances corresponding to the performance index values.

[0090] In this embodiment, when calculating the performance indicator value of each extension circuit in the third candidate queue, the application can adopt an architecture search strategy based on the performance indicator value. This strategy does not need to implement actual quantum circuit training, thereby significantly reducing the operation overhead of the quantum computer and effectively optimizing the use of quantum resources, such as quantum chemical simulation, material design, etc., and significantly enhancing the commercial appeal and competitiveness of quantum computing. Moreover, this strategy can also help quantum algorithms maintain good performance under different quantum hardware and task conditions, and by dynamically adjusting the circuit structure, the quantum algorithm can adapt to changing environments and complex task requirements.

[0091] It can be understood that due to the high training cost and insufficient consideration of quantum neural network training of the current QAS scheme. To solve these challenges, the application proposes an automatic variational circuit search scheme based on loss function fluctuation. This scheme uses the indicators of loss function fluctuation to effectively evaluate and optimize the expression ability and training gradient stability of quantum circuits, thereby more accurately designing quantum circuits suitable for specific QNN training requirements.

[0092] In a specific implementation, the application can first determine the performance indicator value to be calculated, and the Hamiltonian and the number of samplings corresponding to the performance indicator value, then discretize the continuous-time evolution described by the Hamiltonian by combining Clifford gates, and then obtain the discretized parameter value combination. Next, for each rotation gate in each extension circuit in the third candidate queue, at each sampling, the application can randomly select any one of the parameter value combinations as the parameter value of the rotation gate, and after modifying the extension circuit according to the selected parameter value, calculate the performance indicator value of the modified extension circuit, until the number of samplings is reached. Finally, the application can obtain the performance indicator value calculated after each sampling in each extension circuit, and calculate the performance indicator value of each extension circuit according to the variance corresponding to each performance indicator value.

[0093] For example, the application can input a Hamiltonian and a number of samplings, the Hamiltonian is represented as a series of Pauli strings and corresponding coefficients, in the form of where j is an index that marks different Pauli strings, is a Pauli string, is a corresponding coefficient. In quantum mechanics, the Hamiltonian is an operator that describes the total energy of a system, which determines the time evolution of the quantum system. The Hamiltonian contains various interactions and energy information of the system, such as the kinetic energy, potential energy, and interaction energy of particles, etc. The number of samplings input by the application can be used for discretization simulation using Clifford gates.

[0094] It can be appreciated that the state space of a quantum system is continuous, which makes it very difficult to simulate accurately. Clifford sampling takes advantage of the special properties of Clifford circuits to discretize the quantum state space. Since Clifford circuits have certain regularity in their operations on quantum states, they can map quantum states onto a finite, discrete set of states. In some cases, Clifford gates can be used to discretize the simulation of continuous-time evolution described by a Hamiltonian. Although the evolution driven by a Hamiltonian is continuous, it can be approximated by appropriately combining Clifford gates.

[0095] For example, for a simple single-qubit system, its Hamiltonian can be According to the Schrödinger equation, the quantum state will continuously rotate around the z-axis at a certain frequency. Therefore, a series of Clifford gates can be used to approximate this rotation. For example, the present application can combine Hadamard gates and phase gates to simulate the effect of this continuous rotation in discrete steps. Specifically, when calculating the RF value, the RF indicator can be defined as where , is the uniform ensemble of parameter points, is the 1-norm of the Hamiltonian coefficient vector, is the loss function. The present application can discretize into values in These angles correspond to operations that can be achieved by combining basic Clifford gates, such as and The H gate can also be converted to an S gate by adding a pre- and post-Hadamard gate.

[0096] Next, for a given extended circuit C, randomly select any one parameter in for each rotation gate of the extended circuit, then modify the extended circuit according to the selected parameter, and perform efficient calculations on a classical computer. Since such calculations take advantage of the efficient properties of Clifford gates, they can be tracked by stable classical data structures, and there is no exponential growth of computational complexity. Repeat the above simulation steps until the pre-set number of samples is reached, then collect all the output of the simulation results, calculate the variance of the output results, and calculate the performance indicator value of the extended circuit according to the variance.

[0097] To demonstrate the effectiveness of the present application, the following numerical experiment was performed: a one-dimensional cluster model (1D-Cluster Model) was selected as the simulated quantum system. Specifically, the mathematical expression of the cluster model is: where j is the size of the quantum system. The above scheme is adopted in this application, and its effect is compared with the ideal scheme and other known schemes.

[0098] The following table shows the training results of each scheme. The percentage of the final training loss reaching the theoretical minimum value is used as an evaluation indicator, and the number of iterations required to reach this result is compared. Because the initialization parameters of the circuit can cause fluctuations in the results, this application will run the searched circuit 100 times. The results after running are as follows:

[0099]

[0100] Table 1 shows the training results of each scheme provided by the embodiments of this application

[0101] The ideal scheme mentioned above usually refers to the construction of a quantum circuit using two layers of Cartan layers. This structure can achieve excellent training results due to its excellent expression ability. However, since the current quantum hardware devices cannot directly support this complex circuit design, it is defined as an ideal scheme. As can be seen from the above table, the technical scheme of this application is superior in performance compared to other schemes.

[0102] Further, after obtaining the optimized quantum circuit through the above method, this application can apply it to the training process of a quantum neural network. The application can be applied through the following embodiments.

[0103] Embodiment 1: Basic implementation

[0104] Objective: To describe the basic application of this application, such as using RF-based automated variational circuit search to optimize simple quantum algorithms.

[0105] System configuration: Detailed description of the hardware and software configuration used, including the type of quantum computer, the number of qubits used, and the basic software tools.

[0106] Operation steps:

[0107] 1. Initialize the quantum circuit and the RF calculation module.

[0108] 2. Set search parameters such as the number of iterations and the learning rate.

[0109] 3. Perform circuit search and record the RF value and related performance indicators at each step.

[0110] 4. Select the optimal circuit and perform performance testing.

[0111] Result evaluation: Provide test results and performance analysis of this implementation to prove its effectiveness.

[0112] Example 2: Advanced Implementation

[0113] Objective: Demonstrate the application of the invention in handling more complex quantum computing tasks, such as VQE or quantum machine learning models.

[0114] System Configuration: Includes high-performance quantum computers and advanced algorithm configurations.

[0115] Operation Steps:

[0116] 1. Configure advanced RF evaluation tools and dynamic optimization algorithms.

[0117] 2. Use complex quantum circuit templates for searching.

[0118] 3. Implement multi-parameter optimization, fine-tuning circuit parameters with machine learning techniques.

[0119] 4. Conduct extensive testing, including cross-validation and performance benchmarking.

[0120] Result Evaluation: Demonstrate the performance improvement and resource optimization of the advanced implementation in more challenging tasks.

[0121] Example 3: Specific Application Scenarios

[0122] Objective: Illustrate the specific use of the invention in certain industries or applications, such as quantum simulation in drug discovery or materials science research.

[0123] Operation Steps:

[0124] 1. Describe the optimization process of quantum circuit design for specific chemical reactions.

[0125] 2. Introduce collaboration with industry experts and integration of industry knowledge for circuit design.

[0126] 3. Detail the comparison of experimental results with existing industry solutions.

[0127] Result Evaluation: Analyze the economic and technical benefits of this example in actual industry applications, such as cost savings, shortened research and development time, etc.

[0128] Furthermore, during the quantum architecture search process, the present application can also use cross-validation methods to evaluate the generalization ability of quantum neural networks. By testing algorithm performance on different tasks, the practicality and stability of quantum neural networks can be more accurately evaluated. The present application can also introduce a feedback-based adaptive adjustment mechanism to automatically adjust search strategies and parameter settings based on current algorithm performance. For example, when the algorithm performs poorly under a certain parameter configuration, the system can automatically adjust the search direction.

[0129] Of course, the application can also design a dynamic learning system (reinforcement learning or machine learning strategy) that can continuously learn and optimize according to the performance of the quantum network in practical applications. This method not only can adjust the configuration of the quantum neural network in real time, but also can optimize the algorithm strategy according to the application feedback to realize continuous performance improvement.

[0130] In one embodiment, the adjusting the size of the expanded first candidate queue according to the performance indicator values of the circuits in the expanded first candidate queue in S120 can include:

[0131] S124: Calculate the performance indicator values of the circuits in the expanded first candidate queue to obtain a calculation result.

[0132] S125: Sort the circuits in the expanded first candidate queue in descending order according to the calculation result, and adjust the size of the expanded first candidate queue according to the sorting result and a preset size threshold.

[0133] In this embodiment, when adjusting the size of the expanded first candidate queue, the application can first calculate the performance indicator values of the circuits in the expanded first candidate queue. The calculation process can refer to the calculation process of the performance indicator values of the expanded circuits described above. When the calculation result is obtained, the application can sort the circuits in the expanded first candidate queue in descending order according to the calculation result. In this way, the size of the expanded first candidate queue can be adjusted according to the sorting result and a preset size threshold.

[0134] For example, after obtaining the sorting result, the application can discard the circuits ranked at the back of the sorting result according to the preset size threshold, so that the size of the adjusted first candidate queue does not exceed the preset size threshold, thereby effectively reducing the circuit overhead and improving the operation efficiency.

[0135] In one embodiment, as shown in Figure 2 , a flowchart for selecting a circuit with a performance indicator value satisfying a preset score from the adjusted first candidate queue as a to-be-optimized circuit is provided for the embodiment of the application; and S130 can include: Figure 2 S131: Determine whether the circuit with the highest performance indicator value in the adjusted first candidate queue satisfies the preset score; if yes, execute S132; if no, execute S133.

[0136]

[0137] ​S132: Select circuits that meet the preset scores as circuits to be optimized, and randomly select multiple quantum gates from the circuits to be optimized to form a second candidate queue.

[0138] S133: After updating the first candidate queue according to the adjusted first candidate queue, return to execute the steps of expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the size of the expanded first candidate queue according to the performance index values ​​of each circuit in the expanded first candidate queue.

[0139] In this embodiment, when selecting a circuit whose performance index value meets a preset score from the adjusted first candidate queue as the circuit to be optimized, it can first determine whether the circuit with the highest performance index value in the adjusted first candidate queue meets the preset score. For example, when the performance index value is RF value, it can be determined whether the RF value score corresponding to the circuit with the highest RF value is greater than 1. If it is greater, it is selected as the circuit to be optimized, and multiple quantum gates are randomly selected from the circuit to be optimized to form a second candidate queue. If it is not greater, the circuits in the adjusted first candidate queue are expanded according to each initial quantum circuit, and the size of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue. Then, it is determined whether the circuit with the highest performance index value in the adjusted first candidate queue meets the preset score, until it is determined that there is a circuit whose performance index value meets the preset score. At this time, the circuit can be selected as the circuit to be optimized, and multiple quantum gates are randomly selected from the circuit to be optimized to form a second candidate queue.

[0140] In one embodiment, such as Figure 3 As shown, Figure 3 This is a schematic flowchart illustrating the optimization process of the circuit to be optimized according to an embodiment of this application; S140 optimizes the circuit to be optimized based on each quantum gate in the second candidate queue to obtain the final target circuit, which may include:

[0141] S141: Select any quantum gate from the second candidate queue as the current quantum gate.

[0142] S142: After removing the current quantum gate from the circuit to be optimized, determine whether the performance index value of the circuit to be optimized after removing the quantum gate is greater than the preset index threshold. If yes, execute S143; otherwise, execute S144.

[0143] S143: The circuit to be optimized after removing the quantum gate is taken as the final target circuit.

[0144] S144: After removing the current quantum gate from the second candidate queue, continue to execute the step of selecting any quantum gate from the second candidate queue as the current quantum gate and the subsequent steps until the performance index value of the to-be-optimized circuit after removing the quantum gate is greater than the preset index threshold or there is no quantum gate in the second candidate queue.

[0145] S145: When there is no quantum gate in the second candidate queue, the to-be-optimized circuit is taken as the final target circuit.

[0146] In this embodiment, when optimizing the to-be-optimized circuit, any quantum gate can be first selected from the second candidate queue as the current quantum gate, and then the current quantum gate is removed from the to-be-optimized circuit, the performance index value of the to-be-optimized circuit after removing the quantum gate is calculated, and it is determined whether the calculated performance index value is greater than the preset index threshold. If yes, the to-be-optimized circuit after removing the quantum gate is taken as the final target circuit; if no, the current quantum gate is removed from the second candidate queue, and then any quantum gate is selected from the second candidate queue as the current quantum gate, and the current quantum gate is removed from the to-be-optimized circuit, the performance index value of the to-be-optimized circuit after removing the quantum gate is calculated, and it is determined whether the calculated performance index value is greater than the preset index threshold. If yes, the to-be-optimized circuit after removing the quantum gate is taken as the final target circuit; if no, the current quantum gate is removed from the second candidate queue, until the performance index value of the to-be-optimized circuit after removing the quantum gate is greater than the preset index threshold or there is no quantum gate in the second candidate queue. Further, when there is no quantum gate in the second candidate queue, the to-be-optimized circuit can be taken as the final target circuit.

[0147] For example, the present application can realize micro search through the following process:

[0148] 1. Input: to-be-optimized circuit satisfying RF score greater than 1 , candidate number ;

[0149] 2. Select quantum gates in the to-be-optimized circuit , randomly select quantum gates to form a candidate queue ;

[0150] 3. Calculate the RF value after removing from the to-be-optimized circuit , if the RF value is less than 1, check . Repeat this step until the RF value is still greater than 1, then update the to-be-optimized circuit ;

[0151] 4. If all the second candidate queues If none of the above conditions are met, the to-be-optimized circuit is output as the final target circuit, otherwise, the step 2 is returned.

[0152] The quantum circuit optimization design device provided in the embodiments of the present application is described below. The quantum circuit optimization design device described below can be referred to in correspondence with the quantum circuit optimization design method described above.

[0153] In one embodiment, as shown in Figure 4 Figure 4 A structure diagram of a quantum circuit optimization design device provided in the embodiments of the present application; the present application also provides a quantum circuit optimization design device, which can include a quantum circuit acquisition module 210, a candidate queue adjustment module 220, a to-be-optimized circuit determination module 230, and a quantum circuit optimization module 240, and specifically includes the following:

[0154] The quantum circuit acquisition module 210 is configured to acquire an initial quantum circuit structure pool composed of a plurality of initial quantum circuits and a first candidate queue composed of blank circuits.

[0155] The candidate queue adjustment module 220 is configured to expand the circuits in the first candidate queue according to each initial quantum circuit, and adjust the size of the expanded first candidate queue according to the performance index value of each circuit in the expanded first candidate queue.

[0156] The to-be-optimized circuit determination module 230 is configured to select a circuit with a performance index value satisfying a preset score from the adjusted first candidate queue as a to-be-optimized circuit, and randomly select a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue.

[0157] The quantum circuit optimization module 240 is configured to optimize the to-be-optimized circuit according to each quantum gate in the second candidate queue to obtain a final target circuit.

[0158] ​In the above embodiments, in the design of the quantum circuit, the initial quantum circuit structure pool composed of a plurality of initial quantum circuits and the first candidate queue composed of blank circuits can be obtained first; then the circuits in the first candidate queue are expanded according to each initial quantum circuit, and the size of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue, and then a circuit with a performance index value meeting a preset score is selected from the adjusted first candidate queue as a to-be-optimized circuit; then, a plurality of quantum gates are randomly selected from the to-be-optimized circuit to form a second candidate queue, and the to-be-optimized circuit is optimized according to each quantum gate in the second candidate queue to obtain a final target circuit. In this process, a two-round search framework is designed. The first round of the search framework first performs a round of coarse search, so as to effectively evaluate and optimize the expression ability and training gradient stability of the quantum circuit according to the performance index value, and quickly find a to-be-optimized circuit that can meet the specific QNN training requirements. Then, on the basis of the to-be-optimized circuit, the redundant quantum gates in the to-be-optimized circuit are tried to be reduced, so as to reduce the circuit overhead and improve the operation efficiency.

[0159] In one embodiment, the present application further provides a computer readable storage medium, wherein computer readable instructions are stored in the computer readable storage medium, and the computer readable instructions are executed by one or more processors to make the one or more processors perform the steps of the quantum circuit optimization design method according to any one of the above embodiments.

[0160] In one embodiment, the present application further provides a computer device, comprising one or more processors and a memory.

[0161] The memory stores computer readable instructions, and the computer readable instructions are executed by the one or more processors to perform the steps of the quantum circuit optimization design method according to any one of the above embodiments.

[0162] As shown in Figure 5 , Figure 5 Fig. 1 shows an internal structure schematic diagram of a computer device provided by an embodiment of the present application. The computer device 300 can be provided as a server. As shown in Figure 5 , the computer device 300 comprises a processing assembly 302, which further comprises one or more processors and a memory resource represented by a memory 301 for storing instructions executable by the processing assembly 302, such as an application program. The application program stored in the memory 301 can include one or more than one module each corresponding to a set of instructions. In addition, the processing assembly 302 is configured to execute the instructions to perform the quantum circuit optimization design method according to any one of the above embodiments.

[0163] The computer device 300 can further include a power supply component 303 configured to perform power management of the computer device 300, a wired or wireless network interface 304 configured to connect the computer device 300 to a network, and an input / output (I / O) interface 305. The computer device 300 can operate based on an operating system stored in the memory 301, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, Free BSD TM, or the like.

[0164] Those skilled in the art can understand that Figure 5 The structure shown in FIG. 3 is merely a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. A specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0165] Finally, it should be noted that the terms such as first and second, etc., are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Also, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the phrase "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0166] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The various embodiments can be combined as needed, and the same or similar parts refer to each other.

[0167] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of quantum circuit optimization design, characterized by, The method comprises: obtaining an initial quantum circuit structure pool composed of a plurality of initial quantum circuits, and a first candidate queue composed of blank circuits; expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the size of the expanded first candidate queue according to the performance index values of each circuit in the expanded first candidate queue; selecting a circuit with a performance index value meeting a preset score from the adjusted first candidate queue as a to-be-optimized circuit, and selecting a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue; optimizing the to-be-optimized circuit according to each quantum gate in the second candidate queue to obtain a final target circuit.

2. The method of claim 1, wherein, The method comprises: ranking each circuit in the first candidate queue, and selecting a first-ranked circuit and other circuits from the remaining circuits; expanding the first-ranked circuit and the other circuits according to each initial quantum circuit to obtain a third candidate queue composed of a plurality of expanded circuits; expanding the first candidate queue according to the performance index values of each expanded circuit in the third candidate queue to obtain an expanded first candidate queue.

3. The method of claim 2, wherein, The method comprises: calculating the performance index values of each expanded circuit in the third candidate queue; selecting a plurality of expanded circuits from the third candidate queue according to the performance index values of each expanded circuit to obtain an expanded first candidate queue.

4. The method of claim 3, wherein, The method comprises: determining a to-be-calculated performance index value, a Hamiltonian corresponding to the performance index value, and a sampling number; discretizing the continuous-time evolution described by the Hamiltonian by combining Clifford gates to obtain a discretized parameter value combination; for each rotation gate in each expanded circuit in the third candidate queue, randomly selecting any one of the parameter value combinations as the parameter value of the rotation gate at each sampling, and calculating the performance index value of the modified expanded circuit according to the selected parameter value until the sampling number is reached; obtaining the performance index value calculated after each sampling of each expanded circuit, and calculating the performance index value of each expanded circuit according to the variance corresponding to each performance index value.

5. The method of claim 1-4, wherein, The method comprises: calculating the performance index values of each circuit in the expanded first candidate queue to obtain a calculation result; According to the calculation result, each circuit in the expanded first candidate queue is sorted in descending order, and the size of the expanded first candidate queue is adjusted according to the sorting result and a preset size threshold.

6. The method of claim 1-4, wherein, The circuit with a performance index value satisfying a preset score is selected from the adjusted first candidate queue as a to-be-optimized circuit, and a second candidate queue is formed by randomly selecting multiple quantum gates from the to-be-optimized circuit. It is determined whether the circuit with the highest performance index value in the adjusted first candidate queue satisfies the preset score. If yes, the circuit satisfying the preset score is taken as the to-be-optimized circuit, and a second candidate queue is formed by randomly selecting multiple quantum gates from the to-be-optimized circuit. If no, the first candidate queue is updated according to the adjusted first candidate queue, and the step of expanding the first candidate queue according to each initial quantum circuit and adjusting the size of the expanded first candidate queue according to the performance index value of each circuit in the expanded first candidate queue is performed again.

7. The method of claim 1-4, wherein, The to-be-optimized circuit is optimized according to each quantum gate in the second candidate queue to obtain a final target circuit. An arbitrary quantum gate in the second candidate queue is selected as a current quantum gate. It is determined whether the performance index value of the to-be-optimized circuit after removing the current quantum gate is greater than a preset index threshold. If yes, the to-be-optimized circuit after removing the quantum gate is taken as the final target circuit. Otherwise, the current quantum gate is deleted from the second candidate queue, and the step of selecting an arbitrary quantum gate in the second candidate queue as a current quantum gate and the subsequent steps are continued until the performance index value of the to-be-optimized circuit after removing the quantum gate is greater than the preset index threshold or there is no quantum gate in the second candidate queue. When there is no quantum gate in the second candidate queue, the to-be-optimized circuit is taken as the final target circuit.

8. A quantum circuit optimization design apparatus, characterized by comprising: The quantum circuit obtaining module is configured to obtain an initial quantum circuit structure pool composed of multiple initial quantum circuits and a first candidate queue composed of blank circuits. The candidate queue adjusting module is configured to expand the first candidate queue according to each initial quantum circuit and adjust the size of the expanded first candidate queue according to the performance index value of each circuit in the expanded first candidate queue. The to-be-optimized circuit determining module is configured to select a circuit with a performance index value satisfying a preset score from the adjusted first candidate queue as a to-be-optimized circuit, and form a second candidate queue by randomly selecting multiple quantum gates from the to-be-optimized circuit. The quantum circuit optimization module is configured to optimize the to-be-optimized circuit according to each quantum gate in the second candidate queue to obtain a final target circuit. ​ 9. A computer-readable storage medium, characterized in that: The computer readable storage medium stores computer readable instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of the quantum circuit optimization design method of any one of claims 1 to 7.

10. A computer device, comprising: comprising: one or more processors, and a memory; The memory stores computer readable instructions which, when executed by the one or more processors, perform the steps of the quantum circuit optimization design method of any one of claims 1 to 7.

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