Signal receiver, data receiver and data latch thereof

Abstract

The invention provides a signal receiver, a data receiver and a data latch thereof. The signal receiver comprises a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. The first-stage current mode logic circuit receives a data signal, and the final-stage current mode logic circuit outputs an amplified data signal. A plurality of data latches receive the amplified data signal, where each of the data latches sums the amplified data signal and a plurality of feedback data to obtain summed data, and latches the summed data to output output data in accordance with one of the plurality of amplified data strobe signals. The data strobe signal receiver receives a data strobe signal and generates a plurality of amplified data strobe signals by dividing a frequency of the data strobe signal.

Description

Technical Field

[0001] The present invention relates to a signal receiver, a data receiver and a data latch thereof, and more particularly to a signal receiver, a data receiver and a data latch thereof that can comply with JEDEC (Solid State Technology Association) standards. Background Art

[0002] Since the decision feedback equalization (DFE) structure has been added to the circuit structure of the double data rate fifth-generation synchronous dynamic random-access memory (DDR5 DRAM), in order to solve the problem of the reflection effect of the system, according to the JEDEC specification, the DFE structure should be applied to the selection signal generator of the signal receiver. In this way, the propagation delay between the data receiver and the data selection signal receiver is large, and the data signal received by the data receiver should be a smaller signal. In this way, the conventional circuit structure of the signal receiver of the DRAM cannot match the requirements of the JEDEC specification of DDR5. A new circuit structure for the signal receiver should be provided. Summary of the invention

[0003] The present invention provides a signal receiver applicable to a dynamic random access memory (DRAM) device. The signal receiver includes a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. The plurality of current mode logic circuits are coupled in series, wherein the first-stage current mode logic circuit receives a data signal, and the final-stage current mode logic circuit outputs an amplified data signal. The plurality of data latches are coupled to the final-stage current mode logic circuit to receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain summed data, and latches the summed data to output output data according to one of the plurality of amplified data strobe signals. The data strobe signal receiver receives the data strobe signal, and generates a plurality of amplified data strobe signals by dividing the frequency of the data strobe signal.

[0004] The data latch can be applied to a data receiver of a DRAM device. The data latch includes a first latch circuit, a differential pair, a current source, a plurality of first DFE summers, a plurality of second DFE summers, and a second latch circuit. The differential pair has a first differential end and a second differential end respectively coupled to two ends of the first latch circuit, wherein the differential pair receives a first signal and a second signal, and the first signal and the second signal are a differential signal pair. The current source is coupled to a common end of the differential pair, and draws a common current from the common end according to a first bias voltage. The first DFE summer is coupled to the first differential end, and draws a first bias current from the first differential end according to a plurality of feedback data. The second DFE summer is coupled to the second differential end, and draws a second bias current from the second differential end according to a plurality of feedback data. The second latch circuit is coupled to two inverting ends of the first latch circuit, and obtains corresponding output data according to two inverting output signals on the two inverting ends.

[0005] The data receiver can be applied to a DRAM device. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches, as mentioned above. The current mode logic circuits are coupled in series, wherein the first stage current mode logic circuit receives a data signal, and the final stage current mode logic circuit outputs an amplified data signal. The data latch is coupled to the final stage current mode logic circuit to receive the amplified data signal. Each of the data latches sums the amplified data signal and a plurality of feedback data to obtain summed data, and latches the summed data to output output data according to one of a plurality of amplified data selection signals.

[0006] In summary, the data receiver of the present disclosure includes multiple current mode logic (CML) circuits to amplify the data signal to comply with the JEDEC data input swing request. In addition, the data receiver can improve the maximum time difference between the data request signal and the data signal (tRX_DQS2DQ) by increasing the propagation delay of the data signal.

[0007] In order to make the foregoing content more easily understood, several embodiments with accompanying drawings are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0009] Figure 1 A schematic diagram showing a signal receiver according to an embodiment of the present disclosure;

[0010] Figure 2 A circuit diagram showing a DQS receiver according to an embodiment of the present disclosure;

[0011] Figure 3 A circuit diagram showing a portion of a signal latch according to an embodiment of the present disclosure;

[0012] Figure 4A and Figure 4B A schematic diagram illustrating a data latch of a signal receiver in a DRAM device according to an embodiment of the present disclosure.

[0013] Description of Figure Numbers

[0014] 100: signal receiver;

[0015] 110: data receiver;

[0016] 111-1, 111-2, 111-3: current mode logic circuit;

[0017] 113: Decision Feedback Equalization Controller;

[0018] 120, 200: DQS receiver;

[0019] 130: signal tree;

[0020] 211-1, 211-N: CML circuit;

[0021] 212: analog / digital amplifier;

[0022] 213: frequency divider;

[0023] 300: signal latch;

[0024] 310, 400, 401, 402, 403, 1121, 1122, 1123, 1124: data latch;

[0025] 311, 312, 442: latch circuit;

[0026] 313, 413: differential pair;

[0027] 314, 414: current source;

[0028] 315, 415: first DFE summer;

[0029] 316, 416: second DFE summer;

[0030] 320: bias voltage generator;

[0031] 321: Subcircuit;

[0032] 411, 412: latch;

[0033] 3151, 3161: logic gates;

[0034] ADOS1, ADOS2: amplified data request signals;

[0035] C1, C2, C3, C4: latch signal;

[0036] CLK: clock signal;

[0037] CME: Common End;

[0038] com-, com+: differential end;

[0039] Dfb1, Dfb2-, Dfb3-, DfbN+, DfbN-, Dfb1+, Dfb1-, Dfb2+, Df2-, Dfb3+, Df3-, Dfb4+, Dfb4-: feedback data;

[0040] DO+, DO-, DO0+, DO0-, DO1+, DO1-, DO2+, DO2-, DO3+, DO3-: output signal;

[0041] DO0, DO1, DO2, DO3, ODATA: output data;

[0042] DOA1, DOA2: amplified data signals;

[0043] DQ: data signal;

[0044] DQS_0, DQS_90, DQS_180, DQS_270: data strobe signal;

[0045] DQS_c, DQS_t: data request signal;

[0046] DS1, DS2, DS3, DS4: amplified data selection signals;

[0047] GND: reference ground voltage;

[0048] GTS: gain tuning signal;

[0049] M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M14, M15, M16, M18, Mb1, Mb2, Mb3, Mb4, MC1, MC2: transistors;

[0050] MCS: Set code;

[0051] OE1, OE2: output signal;

[0052] PB, Vb1, Vb2: bias voltage;

[0053] SGN1, SGN+, SGN-: positive and negative sign information;

[0054] Vin+, Vin-: input signal;

[0055] VP: power supply voltage;

[0056] VREFDQ: Reference data signal. DETAILED DESCRIPTION

[0057] Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0058] Please refer to Figure 1 , Figure 1 A schematic diagram of a signal receiver according to an embodiment of the present disclosure is shown. The signal receiver 100 includes a data (DQ) receiver 110, a data strobe signal (DQS) receiver, and a signal tree 130. The DQ receiver 110 includes a plurality of current mode logic (CML) circuits 111-1 to 111-3, a plurality of data latches 1121 to 1124, and a decision feedback equalization (DFE) controller 113. The CML circuits 111-1 to 111-3 are coupled in series. The first stage CML circuit 111-1 receives a data signal DQ through a first input terminal and receives a reference data signal VREFDQ through a second input terminal. The CML circuits 111-1 to 111-3 amplify the data signal DQ step by step, and the last stage CML circuit 111-3 can generate an amplified data signal DOA1 and an amplified data signal DOA2, wherein the amplified data signal DOA1 is inverted from the amplified data signal DOA2. The data latches 1121 to 1124 are coupled in parallel and usually receive the amplified data signal DOA1 and the amplified data signal DOA2. The data latches 1121 to 1124 receive the latch signals C1 to C4, respectively, and each of the data latches sums the amplified data signal DOA1 and the amplified data signal DOA2 and a plurality of feedback data to obtain summed data. Each of the data latches 1121 to 1124 further latches the corresponding summed data to output each of the output data DO0 to the output data DO3 according to each of the latch signals C1 to C4. In this embodiment, the phases of the latch signals C1 to C4 are different, the latch signal C1 and the latch signal C2 have a phase difference of 90 degrees; the latch signal C2 and the latch signal C3 have a phase difference of 90 degrees; and the latch signal C3 and the latch signal C4 have a phase difference of 90 degrees.

[0059] Each of the feedback data is generated by each of the output data DO0 to the output data DO3. In detail, taking the data latch 1121 as an example, the output data DO0 of the data latch 1121 can be fed back to the data latches 1121 to the data latches 1124 as feedback data of the data latches 1121 to the data latches 1124. The data latch 1121 also receives the output data DO0 to the output data DO3 as its feedback data.

[0060] In the present disclosure, each of the CML circuits 111-1 to 111-3 may be formed by a differential pair, a resistor, and at least one current source. The first-stage CML circuit 111-1 may be a continuous time linear equalizer (CTLE) for compensating for low-pass channel effects. The intermediate-stage CML circuit 111-2 may be coupled to the DFE controller 113, and the amplification gain of the intermediate-stage CML circuit 111-2 may be adjusted by a gain tuning signal GTS provided by the DFE controller 113. In this embodiment, the DFE controller 113 may receive a setting code MCS and generate a gain tuning signal GTS according to the setting code MCS. The setting code MCS may be provided by an external electronic device and may be pre-stored in a storage device in advance. In addition, the setting code MCS may be dynamically adjusted as needed. In addition, the amplification gain of the final-stage CML circuit 111-3 may be fixed.

[0061] It should be noted here that the CML circuits 111-1 to 111-3 form an amplification string to amplify the data signal DQ for generating the amplified data signal DOA1 and the amplified data signal DOA2. In this way, the voltage swing of the data signal DQ can be minimized and can meet the JEDEC specification for the minimum swing requirement of the input data signal. On the other hand, the amplification string also provides a propagation delay for transmitting the data signal DQ and can improve the maximum time difference between the data selection signal DQS and the data signal DQ.

[0062] In another embodiment, the number of stages of CML circuits in the amplification string can be adjusted and is not limited to three. Figure 1 The three CML circuits 111 - 1 to 111 - 3 in FIG. 1 are merely examples for illustration and are not intended to limit the scope of the present disclosure.

[0063] The latch signals C1 to C4 are generated by the signal tree 130. The signal tree 130 receives the amplified data strobe signals DS1 to DS4 from the DQS receiver 120, and generates the latch signals C1 to C4 by buffering the amplified data strobe signals DS1 to DS4, respectively. The DQS receiver 120 is coupled to the signal tree 130, receives the data strobe signal DQS, and generates the amplified data strobe signals DS1 to DS4 by amplifying the data strobe signal DQS, wherein the amplified data strobe signals DS1 to DS4 are 4-phase quadrature signals.

[0064] Please refer to Figure 2 , Figure 2 A circuit diagram of a DQS receiver according to an embodiment of the present disclosure is shown. The DQS receiver 200 includes a plurality of CML circuits 211-1 to 211-N, an analog / digital amplifier 212, and a frequency divider 213. The CML circuits 211-1 to 211-N are coupled in series. The first-stage CML circuit 211-1 receives a data request signal including a data request signal DQS_t and a data request signal DQS_c that are complementary to each other. The first-stage CML circuit 211-1 may be a CTLE circuit. The CML circuits 211-1 to 211-N form an amplification string to amplify the data request signal DQS_t and the data request signal DQS_c, and generate an amplified data request signal ADOS1 and an amplified data request signal ADOS2.

[0065] The analog / digital amplifier 212 is coupled to the final-stage CML circuit 211-N, and converts the amplified data request signal ADOS1 and the amplified data request signal ADOS2 from an analog format to a digital format. The frequency divider 213 is coupled to the analog / digital amplifier 212, and generates the amplified data strobe signal DS1 to the amplified data strobe signal DS4 by dividing the frequency of at least one of the amplified data request signal ADOS1 and the amplified data request signal ADOS2 in a digital format. The frequency divider 213 can divide the frequency of the amplified data request signal ADOS1 and the amplified data request signal ADOS2 by 2. In this embodiment, the amplified data strobe signal DS1 to the amplified data strobe signal DS4 can have four different phases, respectively, and the amplified data strobe signal DS1 to the amplified data strobe signal DS4 are half-frequency signals.

[0066] Please refer to Figure 3 , Figure 3A circuit diagram of a portion of a signal latch according to an embodiment of the present disclosure is shown. The signal latch 300 includes a data latch 310 and a bias voltage generator 320. The data latch 310 includes latch circuits 311 and 312, a differential pair 313, a current source 314, a plurality of first DFE summers 315, and a plurality of second DFE summers 316. The latch circuit 311 includes transistors M3 to M10. The transistor M3 and the transistor M4 are coupled in series between the power supply voltage VP and the reference ground voltage GND to form a first inverter. The transistor M5 and the transistor M6 are coupled in series between the power supply voltage VP and the reference ground voltage GND to form a second inverter. The input terminal of the first inverter (the control terminal of the transistor M3 and the transistor M4) is coupled to the output terminal of the second inverter (the second terminal of the transistor M5 and the first terminal of the transistor M6). The input end of the second inverter (the control end of the transistor M5 and the transistor M6) is coupled to the output end of the first inverter (the second end of the transistor M3 and the first end of the transistor M4). The second end of the transistor M4 and the second end of the transistor M6 are respectively coupled to the differential end com- and the differential end com+ of the differential pair 313. In addition, the transistor M7 and the transistor M8 are coupled to the transistor M3 in parallel and are controlled by the clock signal CLK. The transistor M9 and the transistor M10 are coupled to the transistor M5 in parallel and are controlled by the clock signal CLK. The transistors M7 to M10 are pull-up transistors, and when the clock signal CLK is in a logic low, the pull-up transistors are used to pull the output of the latch circuit 311 to the power supply voltage VP. When the clock signal CLK is in a logic high, the two output signals OE1 and the output signal OE2 of the latch circuit 311 are differential signals, and the latch circuit 311 can latch the signals on the two differential ends com- and the differential end com+ to generate output signals OE1 and OE2 on the two inverted output ends and the output end.

[0067] The output terminals OE1 and OE2 of the latch circuit 311 are coupled to the latch circuit 312. The latch circuit 312 latches the output signal of the latch circuit 311 to generate output data ODATA.

[0068] The differential pair 313 includes a transistor M1 and a transistor M2. A first end of the transistor M1 is coupled to the differential end com-, a second end of the transistor M1 is coupled to the common end CME of the differential pair 313, and a control end of the transistor M1 receives an input signal Vin+. A first end of the transistor M2 is coupled to the differential end com+, a second end of the transistor M2 is coupled to the common end CME of the differential pair 313, and a control end of the transistor M2 receives an input signal Vin-. The input signal Vin+ and the input signal Vin- may be amplified data signals provided by a plurality of CML circuits in a data receiver of the DRAM.

[0069] The current source 314 includes a transistor MC1 and a transistor MC2, and the transistor MC1 and the transistor MC2 are coupled in series between a common terminal CME and a reference ground voltage GND. The transistor MC2 is controlled by a clock signal CLK. The transistor MC1 is controlled by a bias voltage Vb1.

[0070] The first DFE summer 315 is coupled to the first differential terminal com-, and the second DFE summer 316 is coupled to the second differential terminal com+. The number of the first DFE summers 315 may be determined by the number of taps. In this embodiment, the number of the first DFE summers 315 may be equal to M, where M is a positive integer. In addition, the number of the second DFE summers 316 is equal to the number of the first DFE summers 315. The M first DFE summers 315 correspond to a plurality of feedback data (e.g., first feedback data to Mth feedback data), respectively, and the M second DFE summers 316 also correspond to a plurality of feedback data (e.g., first feedback data to Mth feedback data), respectively.

[0071] Each of the first DFE summers 315 includes transistors M11 to M14. The transistors M11 to M14 are coupled in series between the first differential terminal com- and the reference ground voltage GND. In the first stage of the first DFE summer 315, the transistor M11 is controlled by the bias voltage Vb2. The transistor M12 is controlled by the output signal of the logic gate 3151, and the transistor M14 is controlled by the clock signal CLK. The logic gate 3151 receives the feedback data Dfb1 and the positive and negative sign information SGN1 of the feedback data Dfb1, and the logic gate 3151 can be an exclusive NOR gate. The first DFE summer 315 is used to draw a bias current from the first differential terminal com- according to a plurality of feedback data Dfb1. Each of the second DFE summers 316 includes transistors M15 to M18. In the first stage of the second DFE summer 316, the transistors M15 to M18 are coupled in series between the second differential terminal com+ and the reference ground voltage GND. The transistor M15 is controlled by the bias voltage Vb2. The transistor M16 is controlled by the output signal of the logic gate 3161, and the transistor M18 is controlled by the clock signal CLK. The logic gate 3161 receives the feedback data Dfb1 and the positive and negative sign information SGN1 of the feedback data Dfb1, and the logic gate 3161 can be an XOR gate. The second DFE summer 316 is used to draw a bias current from the second differential terminal com+ according to the plurality of feedback data Dfb1.

[0072] On the other hand, the bias voltage generator 320 is coupled to the data latch 310, and the bias voltage generator 320 is used to provide the bias voltage Vb1 and the bias voltage Vb2 to the data latch 310. The bias voltage generator 320 includes transistors Mb1 to Mb4. Transistor Mb1 and transistor Mb3 are coupled in series between the power supply voltage VP and the reference ground voltage GND. Transistor Mb1 is controlled by the bias voltage PB. The control terminal and the first terminal of transistor Mb3 are coupled together to generate the bias voltage Vb1. Transistor Mb2 and transistor Mb4 are coupled in series between the power supply voltage VP and the reference ground voltage GND. Transistor Mb2 is controlled by the bias voltage PB. The control terminal and the first terminal of transistor Mb4 are coupled together to generate the bias voltage Vb2. It should be noted here that the current of transistor Mb2 can be adjusted according to the setting code. The setting code can be recorded in the mode register of the memory device. The current of transistor Mb2 flows through transistor Mb4 to establish the bias voltage Vb2. That is, the bias voltage Vb2 can be programmed according to the setting code.

[0073] It should be noted here that the number of sub-circuits 321 formed by transistors Mb2 and Mb4 may be equal to M. That is, the number of sub-circuits 321 is the same as the number of first DFE summers 315 , and is also the same as the number of second DFE summers 316 .

[0074] It should be noted here that during operation, both transistor M11 and transistor M15 may be turned on at the same time.

[0075] In addition, in the present disclosure, one bias voltage generator 320 can be shared by multiple signal latches as the signal latch 300 to save circuit size. For example, one bias voltage generator 320 can be shared by four signal latches.

[0076] Please refer to Figure 4A and Figure 4B , Figure 4A and Figure 4B A schematic diagram showing a data latch of a signal receiver in a DRAM device according to an embodiment of the present disclosure. Figure 4A In FIG. 4 , the data latch 400 includes latches 411 and 412, a differential pair 413, a current source 414, a plurality of first DFE summers 415, and a plurality of second DFE summers 416. Figure 3 Detailed circuits of latches 411 and 412, differential pair 413, current source 414, multiple first DFE summers 415, and multiple second DFE summers 416 are described in the embodiment of FIG. 1 and will not be repeated here.

[0077] It should be noted here that the output signal DO+ and the output signal DO- generated by the latch circuit 412 can be fed back to generate feedback data Dfb4+ and feedback data Dfb4-, respectively. In addition, the data latch 400 can receive other output signals from other data latches to obtain feedback data Dfb1+ to feedback data Dfb3+ and feedback data Dfb1- to feedback data Dfb3-. The output signal DO+ and the output signal DO- are differential signal pairs, and the feedback data Dfb1+ and feedback data Dfb1-, feedback data Dfb2+ and feedback data Dfb2-, and feedback data Dfb3+ and feedback data Dfb3- are all differential signal pairs.

[0078] Feedback data Dfb1+ to feedback data Dfb4+ and feedback data Dfb1- to feedback data Dfb4- and corresponding positive and negative sign information may be input to the first DFE summer 415 and the second DFE summer 416, respectively. In this embodiment, the number of first summers 415 may be four, and the number of second summers 416 may also be four. The four first summers 415 and the four second summers 416 correspond to the feedback data Dfb1+ to feedback data Dfb4+ and the feedback data Dfb1- to feedback data Dfb4-, respectively. Figure 4B In the embodiment, the transistors of one of the first summers 415 receive the feedback data DfbN+, the feedback data DfbN- and the corresponding sign information SGN+ and SGN-, respectively. The transistors of one of the second summers 416 receive the feedback data DfbN+, the feedback data DfbN- and the corresponding sign information SGN+ and SGN-, respectively. Wherein, N can be 1 to 4. In this way, the first summer 415 and the second summer 416 can share a bias voltage generator as Figure 3 The bias voltage generator 320 in the embodiment of the present invention can be used to save circuit size.

[0079] exist Figure 4B , a plurality of data latches 400 to 403 are shown. The circuit structure of each of the data latches 401 to 403 is similar to the circuit structure of the data latch 400, and has been described in detail. Figure 4A The details of the circuit structure of the data latch 400 are described in the embodiment of FIG. 4 and will not be described here. Figure 4B, data latches 400 to 403 receive data strobe signals DQS_0, DQS_90, DQS_180, and DQS270, respectively. There is a 90-degree phase difference between data strobe signal DQS_0 and data strobe signal DQS_90; there is a 90-degree phase difference between data strobe signal DQS_90 and data strobe signal DQS_180; there is a 90-degree phase difference between data strobe signal DQS_180 and data strobe signal DQS_270; and there is a 90-degree phase difference between data strobe signal DQS_270 and data strobe signal DQS_0.

[0080] On the other hand, data latch 400 provides output signal DO0+ and output signal DO0-; data latch 401 provides output signal DO1+ and output signal DO1-; data latch 402 provides output signal DO2+ and output signal DO2-; data latch 403 provides output signal DO3+ and output signal DO3-. Output signal DO0+ to output signal DO3+ respectively form a plurality of output signal pairs with output signal DO0- to output signal DO3-, wherein each of the output signal pairs is a differential signal pair. There is a 90-degree phase difference between output signal DO0+ and output signal DO1+; there is a 90-degree phase difference between output signal DO1+ and output signal DO2+; there is a 90-degree phase difference between output signal DO2+ and output signal DO3+; and there is a 90-degree phase difference between output signal DO3+ and output signal DO0+0. In addition, in the disclosure presented, in the disclosure presented, the data latch 400 may feed back the output signal DO0+ and the output signal DO0- to itself to form the feedback data Dfb4+ and the feedback data Dfb4-; the data latch 401 may feed back the output signal DO1+ and the output signal DO1- to the data latch 400 to form the feedback data Dfb3+ and the feedback data Df3-; the data latch 402 may feed back the output signal DO2+ and the output signal DO2- to the data latch 400 to form the feedback data Dfb2+ and the feedback data Df2-. It should be noted here that the data latch 403 may not feed back the output signal DO3+ and the output signal DO3- to the data latch 400 to the data latch 402 to directly form the feedback data Dfb1+ and the feedback data Dfb1-. In this embodiment, the data latch 403 is the last stage data latch, and the data latch 403 can feedback the signal input to the latch circuit 442 for generating the output signal DO3+ and the output signal DO3- to form the feedback data Dfb1+ and the feedback data Dfb1-. The signal input to the latch circuit 442 is the two inverted output signals generated by the latch circuit of the data latch 403.

[0081] The feedback data Dfb1+ to Dfb4+ and the feedback data Dfb1 − to Dfb4 − may be transmitted to the summer of the data latch 400 .

[0082] It should be noted here that data latches 400 to 403 are also connected by Figure 4B Feedback data Dfb1+ to Dfb4+ and feedback data Dfb1 − to Dfb4 − are provided to each of data latches 401 to 403 in the same manner as shown in FIG.

[0083] In summary, in the disclosed embodiment, a plurality of CML circuits are arranged in a data receiver of a signal receiver to amplify a data signal. In addition, the CML circuit in the data receiver provides a propagation delay for transmitting the amplified data signal. In this way, the specification of the JEDEC standard for DDR5 DRAM can be met.

[0084] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure encompass modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A signal receiver, comprising: A data receiver, comprising: a plurality of current mode logic circuits coupled in series, wherein a first stage current mode logic circuit receives a data signal and a final stage current mode logic circuit outputs an amplified data signal; and a plurality of data latches coupled to the final-stage current mode logic circuit to receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain summed data, and latches the summed data to output output data according to one of a plurality of frequency-divided data strobe signals; and The data strobe signal receiver receives a data strobe signal and generates the plurality of divided frequency data strobe signals by dividing the frequency of the data strobe signal.

2. The signal receiver according to claim 1, wherein the current mode logic circuit comprises a plurality of first current mode logic circuits and second current mode logic circuits, At least one of the first current mode logic circuits adjusts the amplification gain according to a gain tuning signal, the amplification gain of the second current mode logic circuit is fixed, and the second current mode logic circuit is the final stage current mode logic circuit.

3. The signal receiver according to claim 2, wherein the data receiver further comprises: The decision feedback equalization controller generates the gain tuning signal according to the setting code. 4 . The signal receiver according to claim 1 , wherein the plurality of frequency-divided data strobe signals respectively have a plurality of different phases.

5. The signal receiver of claim 1 , wherein each of the data latches comprises: a first latch circuit; a differential pair having a first differential end and a second differential end respectively coupled to two ends of the first latch circuit, wherein the differential pair receives the amplified data signal and an inverted amplified data signal; a current source coupled to a common terminal of the differential pair and drawing a common current from the common terminal according to a first bias voltage; A plurality of first decision feedback equalization summers, coupled to the first differential end, and drawing a first bias current from the first differential end according to the plurality of feedback data; A plurality of second decision feedback equalization summers, coupled to the second differential terminal, and drawing a second bias current from the second differential terminal according to the plurality of feedback data; as well as The second latch circuit is coupled to the first latch circuit and obtains corresponding output data according to the output from the first latch circuit.

6. The signal receiver according to claim 5, wherein one of the first decision feedback equalization summer and the second decision feedback equalization summer comprises: A first transistor having a first terminal coupled to the first differential terminal or the second differential terminal, a control terminal of the first transistor receiving a second bias voltage; A logic gate, receiving one of the plurality of feedback data and corresponding positive and negative sign information; a second transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal of the second transistor coupled to the output terminal of the logic gate; as well as The third transistor is coupled between the second terminal of the second transistor and the reference ground terminal and is controlled by a clock signal.

7. The signal receiver of claim 5, wherein each of the first decision feedback equalization summers comprises: A first transistor having a first terminal coupled to the first differential terminal or the second differential terminal, a control terminal of the first transistor receiving a second bias voltage; A second transistor and a third transistor coupled in series, wherein the second transistor has a first end coupled to the second end of the first transistor, a control end of the second transistor receives first feedback data, and a control end of the third transistor receives first positive and negative sign information corresponding to the first feedback data; a fourth transistor and a fifth transistor coupled in series, wherein the fourth transistor has a first end coupled to the second end of the first transistor, a control end of the fourth transistor receives second feedback data, and a control end of the fifth transistor receives second positive and negative sign information corresponding to the second feedback data, wherein the second feedback data is inverted with respect to the first feedback data; as well as The sixth transistor is coupled between the second terminal of the third transistor and the reference ground terminal and is controlled by a clock signal.

8. The signal receiver of claim 5, wherein each of the second decision feedback equalization summers comprises: A first transistor having a first terminal coupled to the first differential terminal or the second differential terminal, a control terminal of the first transistor receiving a second bias voltage; A second transistor and a third transistor coupled in series, wherein the second transistor has a first end coupled to the second end of the first transistor, a control end of the second transistor receives first feedback data, and a control end of the third transistor receives second positive and negative sign information corresponding to the second feedback data; a fourth transistor and a fifth transistor coupled in series, wherein the fourth transistor has a first end coupled to the second end of the first transistor, a control end of the fourth transistor receives the second feedback data, and a control end of the fifth transistor receives first sign information corresponding to the first feedback data, wherein the second feedback data is inverted with respect to the first feedback data; as well as The sixth transistor is coupled between the second terminal of the third transistor and the reference ground terminal and is controlled by a clock signal.

9. The signal receiver according to claim 7, further comprising: The bias voltage generator generates the first bias voltage and the second bias voltage.

10. The signal receiver according to claim 8, wherein the bias voltage generator comprises: a seventh transistor having a first terminal for receiving a power supply voltage, and a control terminal of the seventh transistor for receiving a third bias voltage; at least one eighth transistor coupled in parallel with the seventh transistor; a ninth transistor, coupled between the second terminal of the eighth transistor and the reference ground terminal, wherein the control terminal of the ninth transistor is coupled to the second terminal of the eighth transistor to output the second bias voltage; as well as at least one tenth transistor coupled between the second terminal of the seventh transistor and the reference ground terminal, wherein the control terminal of the tenth transistor is coupled to the second terminal of the seventh transistor to output the first bias voltage, The current of the eighth transistor is controlled according to a setting code. 11 . The signal receiver of claim 1 , wherein one of the data latches provides one of the feedback data to all of the data latches according to corresponding output data.

12. The signal receiver of claim 11, wherein each of the data latches comprises: a first latch circuit; as well as a second latch circuit coupled to the first latch circuit and obtaining the corresponding output data according to the output from the first latch circuit; The last stage of the data latch provides the output data from the first latch circuit as the corresponding feedback data, and the other stages of the data latch provide the corresponding output data from the second latch circuit as the corresponding feedback data.

13. A data latch, applied to a data receiver, wherein the data latch comprises: a first latch circuit; a differential pair having a first differential end and a second differential end respectively coupled to two ends of the first latch circuit, wherein the differential pair receives a first signal and a second signal, and the first signal and the second signal are a differential signal pair; a current source coupled to a common terminal of the differential pair and drawing a common current from the common terminal according to a first bias voltage; A plurality of first decision feedback equalization summers, coupled to the first differential end, and drawing a first bias current from the first differential end according to a plurality of feedback data; A plurality of second decision feedback equalization summers, coupled to the second differential terminal, and drawing a second bias current from the second differential terminal according to the plurality of feedback data; as well as The second latch circuit is coupled to the first latch circuit and obtains corresponding output data according to the output from the first latch circuit.

14. The data latch of claim 13, wherein one of the first decision feedback equalization summer and the second decision feedback equalization summer comprises: A first transistor having a first terminal coupled to the first differential terminal or the second differential terminal, a control terminal of the first transistor receiving a second bias voltage; A logic gate, receiving one of the plurality of feedback data and corresponding positive and negative sign information; a second transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal of the second transistor coupled to the output terminal of the logic gate; as well as The third transistor is coupled between the second terminal of the second transistor and the reference ground terminal and is controlled by a clock signal.

15. The data latch of claim 14, wherein the logic gate in each of the first decision feedback equalization summers is an XNOR gate.

16. The data latch of claim 14, wherein the logic gate in each of the second decision feedback equalization summers is an XOR gate.

17. The data latch of claim 13, wherein each of the first decision feedback equalization summers comprises: A first transistor having a first terminal coupled to the first differential terminal or the second differential terminal, a control terminal of the first transistor receiving a second bias voltage; A second transistor and a third transistor coupled in series, wherein the second transistor has a first end coupled to the second end of the first transistor, a control end of the second transistor receives first feedback data, and a control end of the third transistor receives first positive and negative sign information corresponding to the first feedback data; a fourth transistor and a fifth transistor coupled in series, wherein the fourth transistor has a first end coupled to the second end of the first transistor, a control end of the fourth transistor receives second feedback data, and a control end of the fifth transistor receives second positive and negative sign information corresponding to the second feedback data, wherein the second feedback data is inverted with respect to the first feedback data; as well as The sixth transistor is coupled between the second terminal of the third transistor and the reference ground terminal and is controlled by a clock signal.

18. The data latch of claim 13, wherein each of the second decision feedback equalization summers comprises: A first transistor having a first terminal coupled to the first differential terminal or the second differential terminal, a control terminal of the first transistor receiving a second bias voltage; A second transistor and a third transistor coupled in series, wherein the second transistor has a first end coupled to the second end of the first transistor, a control end of the second transistor receives first feedback data, and a control end of the third transistor receives second positive and negative sign information corresponding to the second feedback data; a fourth transistor and a fifth transistor coupled in series, wherein the fourth transistor has a first end coupled to the second end of the first transistor, a control end of the fourth transistor receives the second feedback data, and a control end of the fifth transistor receives first sign information corresponding to the first feedback data, wherein the second feedback data is inverted with respect to the first feedback data; as well as The sixth transistor is coupled between the second terminal of the third transistor and the reference ground terminal and is controlled by a clock signal.

19. The data latch according to claim 17, further comprising: The bias voltage generator generates the first bias voltage and the second bias voltage.

20. The data latch according to claim 19, wherein the bias voltage generator comprises: a seventh transistor having a first terminal for receiving a power supply voltage, and a control terminal of the seventh transistor for receiving a third bias voltage; at least one eighth transistor coupled in parallel with the seventh transistor; a ninth transistor, coupled between the second terminal of the eighth transistor and the reference ground terminal, wherein the control terminal of the ninth transistor is coupled to the second terminal of the eighth transistor to output the second bias voltage; as well as at least one tenth transistor coupled between the second terminal of the seventh transistor and the reference ground terminal, wherein the control terminal of the tenth transistor is coupled to the second terminal of the seventh transistor to output the first bias voltage, The current of the eighth transistor is controlled according to a setting code.

21. A data receiver, wherein the data receiver comprises: a plurality of current mode logic circuits coupled in series, wherein a first stage current mode logic circuit receives a data signal and a final stage current mode logic circuit outputs an amplified data signal; as well as A plurality of data latches are coupled to the final-stage current mode logic circuit to receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain summed data, and latches the summed data to output output data according to one of a plurality of data selection signals.

22. The data receiver of claim 21 , wherein the current mode logic circuit comprises a plurality of first current mode logic circuits and second current mode logic circuits, At least one of the first current mode logic circuits adjusts the amplification gain according to a gain tuning signal, the amplification gain of the second current mode logic circuit is fixed, and the second current mode logic circuit is the final stage current mode logic circuit.

23. The data receiver according to claim 22, wherein the data receiver further comprises: The decision feedback equalization controller generates the gain tuning signal according to the setting code.

24. The data receiver of claim 21, wherein each of the data latches comprises: a first latch circuit; a differential pair having a first differential end and a second differential end respectively coupled to two ends of the first latch circuit, wherein the differential pair receives the amplified data signal and an inverted amplified data signal; a current source coupled to a common terminal of the differential pair and drawing a common current from the common terminal according to a first bias voltage; A plurality of first decision feedback equalization summers, coupled to the first differential end, and drawing a first bias current from the first differential end according to the plurality of feedback data; A plurality of second decision feedback equalization summers, coupled to the second differential terminal, and drawing a second bias current from the second differential terminal according to the plurality of feedback data; as well as The second latch circuit is coupled to the first latch circuit and obtains corresponding output data according to the output from the first latch circuit.

25. The data receiver of claim 21, wherein one of the data latches provides one of the feedback data to all of the data latches according to the output data.

26. The data receiver of claim 25, wherein each of the data latches comprises: a first latch circuit; as well as a second latch circuit coupled to the first latch circuit and obtaining the output data according to the output from the first latch circuit; The last stage of the data latch provides the output data from the first latch circuit as the feedback data, and the other stages of the data latch provide the output data from the second latch circuit as the feedback data.

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