Memory device

Abstract

A memory device includes a first memory cell, a second memory cell, a word line, a bit line, a first source line, and a second source line. The first memory unit comprises a control terminal, a data terminal and a source terminal. The second memory unit includes a control terminal, a data terminal and a source terminal. The word line is coupled to the control terminal of the first memory unit and the control terminal of the second memory unit. The bit line is coupled to the data terminal of the first memory unit and the data terminal of the second memory unit. The first source line is coupled to a source terminal of the first memory cell for receiving a first source voltage. The second source line is coupled to a source terminal of the second memory cell for receiving a second source voltage. The second source voltage is different from the first source voltage.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and in particular to a memory device. Background Art

[0002] Magnetoresistive random access memory (MRAM) is a non-volatile memory with many advantages such as high read and write speed, high density, high durability, low power consumption and radiation resistance. MRAM changes the magnetization direction and resistance value by controlling the signals on the word line, bit line and source line, and then writes data into the memory cell. However, since each memory cell in each column of memory cells needs to be controlled individually during read and write operations, many bit lines need to be set in the MRAM to control the memory cells in the MRAM, so the circuit area cannot be reduced. Summary of the invention

[0003] An embodiment of the present invention provides a memory device, comprising a first memory cell, a second memory cell, a word line, a bit line, a first source line and a second source line. The first memory cell comprises a control terminal, a data terminal and a second terminal. The second memory cell comprises a control terminal, a data terminal and a second terminal. The word line is coupled to the control terminal of the first memory cell and the control terminal of the second memory cell. The bit line is coupled to the data terminal of the first memory cell and the data terminal of the second memory cell. The first source line is coupled to the source terminal of the first memory cell to receive a first source voltage. The second source line is coupled to the source terminal of the second memory cell to receive a second source voltage, and the second source voltage is different from the first source voltage.

[0004] The embodiment of the present invention further proposes a memory device, comprising a first source line, a second source line, a first bit line, a second bit line, a first memory unit, a second memory unit, a first bit line connection layer and a second bit line connection layer. The first source line and the second source line are formed along a first direction, and the second source line and the first source line are separated from each other. The first bit line and the second bit line are formed along a first direction. The first memory unit comprises a first diffusion layer and a third diffusion layer, the first diffusion layer at least partially overlaps the first bit line, and the third diffusion layer at least partially overlaps the first bit line. The second memory unit comprises a second diffusion layer and a fourth diffusion layer, the second diffusion layer at least partially overlaps the second bit line, and the fourth diffusion layer at least partially overlaps the second bit line. The first bit line connection layer is formed along a second direction, at least partially overlaps the first diffusion layer and the second diffusion layer. The second bit line connection layer is formed along a second direction, at least partially overlaps the third diffusion layer and the fourth diffusion layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1is a circuit diagram of a memory device according to an embodiment of the present invention;

[0006] Figure 2A is a circuit diagram of another memory unit in an embodiment of the present invention;

[0007] Figure 2B is a circuit diagram of another memory device in an embodiment of the present invention;

[0008] Figure 3A is a circuit diagram of another memory unit in an embodiment of the present invention;

[0009] Figure 3B is a circuit diagram of another memory device in an embodiment of the present invention;

[0010] Figure 4 for Figure 1 A schematic diagram of a layout of a memory device in;

[0011] Figure 5 for Figure 1 Another schematic diagram of the layout of the memory device in;

[0012] Figure 6 for Figure 4 6 ′ is a cross-sectional view of the memory device 1 .

[0013] Explanation of symbols

[0014] 1 to 3: Memory device

[0015] 11 and 12, 21 and 22, 31 and 32: memory cells

[0016] ALD OX: Atomic Layer Deposition Oxide Layer

[0017] BL1, BL2: bit lines

[0018] C1 to C4: Contact

[0019] D: First end

[0020] D1 to D8: Diffusion layer

[0021] G: Control terminal

[0022] M1,M2,M: memory elements

[0023] MTJ1 to MTJ4: Magnetic Tunnel Junction

[0024] N1c, N2c: Control terminal

[0025] N11, N21: First data terminal

[0026] N13, N23: Second data terminal

[0027] N12, N22: Second end

[0028] P1 to P6: Polysilicon layer

[0029] S: Second end

[0030] SL1, SL2: Source lines

[0031] M,M1,M3,M4: Conductive layer

[0032] M31, M32: bit line connection layer

[0033] SiCN: Silicon Carbon Nitride Layer

[0034] T1 to T3, T: transistor

[0035] TEOS:Tetraethyl orthosilicate layer

[0036] TiN: Titanium Nitride Layer

[0037] ULK: Ultra-low dielectric constant layer

[0038] VIA1, VIA2: Perforation

[0039] V3: Perforated layer

[0040] WL: Word Line

[0041] W: Tungsten layer DETAILED DESCRIPTION

[0042] Herein, the control terminal of the transistor may be a gate terminal, the first terminal of the transistor may be one of the drain terminal and the source terminal, and the second terminal of the transistor may be the other of the drain terminal and the source terminal. For example, the first terminal of the transistor may be a drain terminal, and the second terminal of the transistor may be a source terminal. In addition, for example, the first terminal of the transistor may be a source terminal, and the second terminal of the transistor may be a drain terminal. In the figures of this article, the drain terminal, source terminal and gate terminal of the transistor may be marked with D, S and G respectively, and the drain terminal (D), source terminal (S) and gate terminal (G) of the transistor are only examples and are not used to limit the present invention. If reasonable design changes are made according to the characteristics of the transistor, it still falls within the scope of the embodiment. The memory device described herein may be a magnetoresistive random access memory (MRAM), using a magnetic tunnel junction (MTJ) as a memory cell. The magnetic tunnel junction includes two layers of magnetic material and an insulating layer between the two layers of magnetic material. When the magnetization directions of the two magnetic material layers are the same, the magnetic tunnel junction has a low resistance value, representing data "1"; when the magnetization directions of the two magnetic material layers are opposite, the magnetic tunnel junction has a high resistance value, representing data "0". The magnetic tunnel junction can be set to a predetermined resistance state to store data.

[0043] Figure 1 Schematic diagram of a circuit of a memory device 1 in an embodiment of the present invention. The memory device 1 may include a memory cell array, at least two memory cells share the same bit line and use at least two separate source lines to complete the read and write operations of at least two memory cells, saving the number of bit lines, simplifying the circuit layout and reducing the circuit area.

[0044] The memory device 1 may include a first memory cell 11, a second memory cell 12, a word line WL, a first bit line BL1, a first source line SL1, and a second source line SL2. The first memory cell 11 and the second memory cell 12 may be adjacent to each other. The first memory cell 11 may include a control terminal N1c, a first data terminal N11, and a source terminal N12. The second memory cell 12 includes a control terminal N2c, a first data terminal N21, and a source terminal N22. The word line WL may be coupled to the control terminal N1c of the first memory cell 11 and the control terminal N2c of the second memory cell 12. The first bit line BL1 is coupled to the first data terminal N11 of the first memory cell 11 and the first data terminal N21 of the second memory cell 12. The first source line SL1 is coupled to the source terminal N12 of the first memory cell 11 to receive a first source voltage. The second source line SL2 is coupled to the source terminal N22 of the second memory cell 12 to receive a second source voltage. The first memory unit 11 and the second memory unit 12 may share the first bit line BL1 and use a separate first source line SL1 and a separate second source line SL2, respectively. The first bit line BL1, the first source line SL1, and the second source line SL2 may be further coupled to a controller. The controller may control the first memory unit 11 and the second memory unit 12 to perform read and write operations via the first bit line BL1 by providing a first source voltage to the first source line SL1 and providing a second source voltage to the second source line SL2. Since the first memory unit 11 and the second memory unit 12 share the first bit line BL1, only one of the first memory unit 11 and the second memory unit 12 can be enabled to perform read and write operations at a time, and the other is disabled and cannot perform read and write operations.

[0045] The controller can control the first memory unit 11 and the second memory unit 12 respectively through the first source voltage and the second source voltage. The second source voltage may be different from the first source voltage. The first source voltage may be one of an enable voltage and a disable voltage, and the second source voltage may be the other of the enable voltage and the disable voltage. In some embodiments, the enable voltage may be 0V, and the disable voltage may be a floating voltage. For example, if the first source voltage is the enable voltage and the second source voltage is the disable voltage, the first memory unit 11 may be enabled to perform read and write operations via the first bit line BL1, and the second memory unit 12 may be disabled and cannot perform read and write operations. In another example, if the first source voltage is the disable voltage and the second source voltage is the enable voltage, the first memory unit 11 may be disabled and cannot perform read and write operations, and the first memory unit 12 may be enabled to perform read and write operations via the first bit line BL1.

[0046] The first memory unit 11 and the second memory unit 12 may each have 3 transistors and 2 memory elements (referred to as a 3T2M architecture). For the 3T2M architecture, the first memory unit 11 may further include a second data terminal N13. And the second memory unit 12 may further include a second data terminal N23. The memory device 1 may further include a second bit line BL2 coupled to the second data terminal N13 of the first memory unit 11 and the second data terminal N23 of the second memory unit 12. Therefore, the first memory unit 11 and the second memory unit 12 also share a second bit line BL2, and the second bit line BL2 may be further coupled to the controller.

[0047] The first memory unit 11 may include a first memory element M1, a second memory element M2, a first transistor T1, a second transistor T2, and a third transistor T3. The first memory element M1 includes a first terminal coupled to the first data terminal N11 of the first memory unit 11; and a second terminal. The second memory element M2 includes a first terminal coupled to the second data terminal N13 of the first memory unit 11; and a second terminal. The first transistor T1 includes a control terminal G coupled to the control terminal N1c of the first memory unit 11; a first terminal D coupled to the second terminal S of the first memory element M1 of the first memory unit 11; and a second terminal S coupled to the source terminal N12 of the first memory unit 11. The second transistor T2 includes a control terminal G coupled to the control terminal N1c of the first memory unit 11; a first terminal D coupled to the second terminal of the second memory element M2 of the first memory unit 11; and a second terminal S coupled to the source terminal N12 of the first memory unit 11. The third transistor T3 includes a control terminal G coupled to the control terminal N1c of the first memory unit 11; a first terminal D coupled to the first terminal D of the first transistor T1 of the first memory unit 11; and a second terminal S coupled to the first terminal D of the second transistor T2 of the first memory unit 11.

[0048] The second memory unit 12 may include a first memory element M1, a second memory element M2, a first transistor T1, a second transistor T2, and a third transistor T3. The first memory element M1 includes a first terminal coupled to the first data terminal N21 of the second memory unit 12; and a second terminal. The second memory element M2 includes a first terminal coupled to the second data terminal N23 of the second memory unit 12; and a second terminal. The first transistor T1 includes a control terminal G coupled to the control terminal N2c of the second memory unit 12; a first terminal D coupled to the second terminal of the first memory element M1 of the second memory unit 12; and a second terminal S coupled to the source terminal N22 of the second memory unit 12. The second transistor T2 includes a control terminal G coupled to the control terminal N2c of the second memory unit 12; a first terminal D coupled to the second terminal of the second memory element M2 of the second memory unit 12; and a second terminal S coupled to the source terminal N22 of the second memory unit 12. The third transistor T3 includes a control terminal G coupled to the control terminal N2c of the second memory unit 12; a first terminal D coupled to the first terminal D of the first transistor T1 of the second memory unit 12; and a second terminal S coupled to the first terminal D of the second transistor T2 of the second memory unit 12.

[0049] The first memory element M1 and the second memory element M2 of the first memory unit 11 and the first memory element M1 and the second memory element M2 of the second memory unit 12 are magnetic tunnel junctions, and the first transistor M1, the second transistor M2 and the third transistor M3 of the first memory unit 11 and the first transistor M1, the second transistor M2 and the third transistor M3 of the second memory unit 12 may be transistors of the same type. In the present embodiment, the first transistor M1, the second transistor M2 and the third transistor M3 of the first memory unit 11 and the first transistor M1, the second transistor M2 and the third transistor M3 of the second memory unit 12 may be, but are not limited to, N-type metal-oxide-semiconductor field-effect transistors (MOSFET). In some embodiments, the first transistor M1, the second transistor M2 and the third transistor M3 of the first memory unit 11 and the first transistor M1, the second transistor M2 and the third transistor M3 of the second memory unit 12 may also be P-type MOSFETs or other types of transistors.

[0050] The controller will only perform read and write operations on one memory element in the first memory unit 11 or the second memory unit 12 via one of the first bit line BL1 and the second bit line BL2 at a time. For example, if the first memory element M1 of the first memory unit 11 is to be written, the controller may set the first source voltage on the first source line SL1 to an enable voltage, set the second source voltage on the second source line SL2 to a disable voltage, set the control voltage on the word line WL to a conduction voltage (e.g., 1.8V), load the data into the first bit line BL1, and float the second bit line BL2, so as to set the first memory element M1 of the first memory unit 11 to a corresponding resistance according to the data. Since the control voltage on the word line WL is a conduction voltage and the first source voltage on the first source line SL1 is an enable voltage, the first transistor T1, the second transistor T2 and the third transistor T3 of the first memory unit 11 are all turned on, and the first memory unit 11 can write data into the first memory element M1 of the first memory unit 11 according to the total conduction current of the two paths (the first transistor T1 and the stacked third transistor T3 and the second transistor T2), so as to increase the write current and thus accelerate the write operation. Since the second source voltage on the second source line SL2 is a disable voltage, even if the control voltage on the word line WL is a conduction voltage, the first transistor T1, the second transistor T2 and the third transistor T3 of the second memory unit 12 are still turned off, so as to disable the second memory unit 12.

[0051] In another example, if the second memory element M2 of the second memory unit 12 is to be read, the controller may set the first source voltage on the first source line SL1 to a disable voltage, set the second source voltage on the second source line SL2 to an enable voltage, set the control voltage on the word line WL to a turn-on voltage, float the first bit line BL1, and read the data stored in the second memory element M2 of the second memory unit 12 through the second bit line BL2. Since the control voltage on the word line WL is a turn-on voltage and the second source voltage on the second source line SL2 is an enable voltage, the first transistor T1, the second transistor T2, and the third transistor T3 of the second memory unit 12 are all turned on, and the first memory unit 11 can read the second memory element M2 of the second memory unit 12 according to the total turn-on current of the two paths (the second transistor T2 and the stacked third transistor T3 and the first transistor T1), so as to increase the read current and thus accelerate the read operation. Since the first source voltage on the first source line SL1 is a disabling voltage, even if the control voltage on the word line WL is a turn-on voltage, the first transistor T1 , the second transistor T2 and the third transistor T3 of the first memory unit 11 are still turned off to disable the first memory unit 11 .

[0052] For the 3T2M architecture, the related art uses 4 bit lines and 1 source line to read and write 4 memory elements, while the present embodiment shares the first bit line BL1 and the second bit line BL2 and uses the separated first source line SL1 and the second source line SL2 to read and write 4 memory elements. Therefore, the related art uses 5 lines (4+1) to control the read and write of 4 memory elements, while the present embodiment uses 4 lines (2+2) to control the read and write of 4 memory elements. Therefore, compared with the related art, the present embodiment uses a smaller number of bus lines to achieve the read and write operation of 4 memory elements, thereby reducing the number of bit lines of the memory elements, simplifying the circuit layout and reducing the circuit area. If the remaining memory cells in the memory device 1 are also set and operated in a manner similar to the first memory cell 11 and the second memory cell 12, the number of bus lines of the related art (=N bit lines+1 source line) will greatly exceed the number of bus lines of the present embodiment (=N / 2 bit lines+2 source lines). Therefore, compared with the related art, the present embodiment will reduce the total number of bit lines of the memory device 1, simplify the circuit layout and reduce the circuit area.

[0053] Figure 2A FIG. 2 is a circuit diagram of another memory unit 21 / 22 in an embodiment of the present invention. The memory unit 21 / 22 can replace the first memory unit 11 and the second memory unit 12 in the memory device 1 to form the memory device 2. Figure 2B As shown, it will be explained in detail in the subsequent paragraphs.

[0054] The memory cell 21 / 22 may include a memory element M and a transistor T (referred to as a 1T1M architecture). The memory element M includes a first terminal coupled to the bit line BL1 via the first data terminal N11 / N21 of the memory cell 21 / 22; and a second terminal. The transistor T includes a control terminal G coupled to the word line WL via the control terminal N1c / N2c of the memory cell 21 / 22; a first terminal D coupled to the second terminal of the memory element M; and a second terminal S coupled to the source line SL1 / SL2 via the source terminal N12 / N22 of the memory cell 21 / 22.

[0055] If the memory element M is to be read / written, the source voltage on the source line SL1 / SL2 can be set to an enable voltage and the control voltage on the word line WL can be set to a conduction voltage, so as to read the data of the memory element M through the bit line BL1 / set the memory element M of the memory cell 21 / 22 to a corresponding resistance according to the data on the bit line BL1. Since the control voltage on the word line WL is a conduction voltage and the source voltage on the source line SL1 / SL2 is an enable voltage, the transistor T is turned on, and the first memory cell 11 can read the data of the memory element M / write the data into the memory element M according to the conduction current flowing through the first end D and the second end S of the transistor T. Compared with the first memory cell 11 / the second memory cell 12, the memory cell 21 / 22 is read / written through only one conduction path (the first end D and the second end S of the transistor T), so the read / write current is smaller and the read / write operation speed is slower.

[0056] refer to Figure 2B The difference between the memory device 2 and the memory device 1 lies in the memory cell and the bit line. The other elements of the memory device 2 are similar to those of the memory device 1, and their description is not repeated here. The difference between the memory device 2 and the memory device 1 is described below. The first memory cell 21 and the second memory cell 22 in the memory device 2 may be adjacent to each other, and may only share the bit line BL1 and use separate first source lines SL1 and second source lines SL2.

[0057] The first memory unit 21 includes a memory element M and a transistor T. The memory element M includes a first terminal coupled to the first data terminal N11 of the first memory unit 21; and a second terminal. The transistor T includes a control terminal G coupled to the control terminal N1c of the first memory unit 21; a first terminal D coupled to the second terminal of the memory element M of the first memory unit 21; and a second terminal S coupled to the source terminal N12 of the first memory unit 21. The second memory unit 22 includes a memory element M and a transistor T. The memory element M includes a first terminal coupled to the first data terminal N21 of the second memory unit 22; and a second terminal. The transistor T includes a control terminal G coupled to the control terminal N2c of the second memory unit 22; a first terminal D coupled to the second terminal of the memory element M of the second memory unit 22; and a second terminal S coupled to the source terminal N22 of the second memory unit 22.

[0058] The memory element M of the first memory unit 21 and the memory element M of the second memory unit 22 are magnetic tunnel junctions, and the transistor T of the first memory unit 21 and the transistor T of the second memory unit 22 may be transistors of the same type. In the present embodiment, the transistor T of the first memory unit 21 and the transistor T of the second memory unit 22 may be, but not limited to, N-type MOSFETs. In some embodiments, the transistor T of the first memory unit 21 and the transistor T of the second memory unit 22 may also be P-type MOSFETs or other types of transistors.

[0059] The controller can enable one of the first memory unit 21 and the second memory unit 22 at a time to perform read and write operations, and disable the other to prohibit read and write operations. For example, if the memory element M of the first memory unit 21 is to be written, the controller can set the first source voltage on the first source line SL1 to the enable voltage, set the second source voltage on the second source line SL2 to the disable voltage, set the control voltage on the word line WL to the on voltage (e.g., 1.8V), and load data into the bit line BL1 for setting the memory element M of the first memory unit 21 to the corresponding resistance according to the data. Since the control voltage on the word line WL is the on voltage and the first source voltage on the first source line SL1 is the enable voltage, the transistor T of the first memory unit 21 is turned on, and the first memory unit 21 can write data into the memory element M of the first memory unit 21 according to the on current flowing through the first end D and the second end S of the transistor T. Since the second source voltage on the second source line SL2 is a disabling voltage, even if the control voltage on the word line WL is a turn-on voltage, the transistor T of the second memory unit 22 will still be turned off to disable the second memory unit 22 .

[0060] In another example, if the memory element M of the second memory unit 22 is to be read, the controller may set the first source voltage on the first source line SL1 to a disabling voltage, set the second source voltage on the second source line SL2 to an enabling voltage, set the control voltage on the word line WL to an on voltage, and read the data stored in the memory element M of the second memory unit 22 through the bit line BL1. Since the control voltage on the word line WL is an on voltage and the second source voltage on the second source line SL2 is an enabling voltage, the transistor T of the second memory unit 22 is turned on, and the second memory unit 22 can read the memory element M of the second memory unit 22 according to the on current flowing through the first end D and the second end S of the transistor T. Since the first source voltage on the first source line SL1 is a disabling voltage, even if the control voltage on the word line WL is an on voltage, the transistor T of the first memory unit 21 will still be turned off to disable the first memory unit 21.

[0061] For the 1T1M architecture, the related art uses 2 bit lines and 1 source line to read and write 2 memory elements, while the present embodiment uses a common bit line BL1 and uses a separate first source line SL1 and a second source line SL2 to read and write 2 memory elements. Therefore, the related art uses 3 lines (2+1) to control the reading and writing of 2 memory elements, while the present embodiment also uses 3 lines (1+2) to control the reading and writing of 2 memory elements. If the remaining memory cells in the memory device 1 are also set and operated in a manner similar to the first memory cell 21 and the second memory cell 22, the number of bus lines of the related art (=N bit lines+1 source line) will greatly exceed the number of bus lines of the present embodiment (=N / 2 bit lines+2 source lines). Therefore, compared with the related art, the present embodiment will reduce the total number of bit lines of the memory device 2, simplify the circuit layout and reduce the circuit area.

[0062] Figure 3A FIG. 3 is a circuit diagram of another memory unit 31 / 32 in an embodiment of the present invention. The memory unit 31 / 32 can replace the first memory unit 21 and the second memory unit 22 in the memory device 2 to form the memory device 3. Figure 3B As shown, it will be explained in detail in the subsequent paragraphs.

[0063] The memory cell 31 / 32 may include a memory element M, a first transistor T1, and a second transistor T2 (referred to as a 2T1M architecture). The memory element M includes a first terminal coupled to the bit line BL1 via the first data terminal N11 / N21 of the memory cell 31 / 32; and a second terminal. The first transistor T1 includes a control terminal G coupled to the word line WL via the control terminal N1c / N2c of the memory cell 31 / 32; a first terminal D coupled to the second terminal of the memory element M of the memory cell 31 / 32; and a second terminal S coupled to the source line SL1 / SL2 via the source terminal N12 / N22 of the memory cell 31 / 32. The second transistor T2 includes a control terminal G coupled to the word line WL via the control terminal N1c / N2c of the memory unit 31 / 32; a first terminal D coupled to the second terminal of the memory element M of the memory unit 31 / 32; and a second terminal S coupled to the source line SL1 / SL2 via the source terminal N12 / N22 of the memory unit 31 / 32.

[0064] If the memory element M is to be read / written, the source voltage on the source line SL1 / SL2 can be set to an enable voltage and the control voltage on the word line WL can be set to a conduction voltage, so as to read the data of the memory element M through the bit line BL1 / set the memory element M of the memory cell 31 / 32 to a corresponding resistance according to the data on the bit line BL1. Since the control voltage on the word line WL is a conduction voltage and the source voltage on the source line SL1 / SL2 is an enable voltage, the first transistor T1 and the second transistor T2 are both turned on, and the first memory cell 11 can read the data of the memory element M / write the data to the memory element M according to the total conduction current flowing through the first transistor T1 and the second transistor T2, so as to increase the read / write current and thus accelerate the read / write operation. Compared with the first memory cell 11 / the second memory cell 12, the memory cell 31 / 32 is also read / written through two conduction paths (the first transistor T1 and the second transistor T2), so the read / write current is the same and the read / write operation speed is the same. Compared with the first memory cell 21 / the second memory cell 22 , the memory cell 31 / 32 is read / written via two conduction paths (the first transistor T1 and the second transistor T2 ), so the read / write current is larger and the read / write operation speed is faster.

[0065] refer to Figure 3B The difference between the memory device 3 and the memory device 2 lies in the memory cell. The other elements of the memory device 3 are similar to those of the memory device 2, and their description is not repeated here. The difference between the memory device 3 and the memory device 2 is described below. The first memory cell 31 and the second memory cell 32 in the memory device 3 may be adjacent to each other, and may only share the bit line BL1 and use separate first source lines SL1 and second source lines SL2.

[0066] The first memory unit 31 includes a memory element M, a first transistor T1, and a second transistor T2. The memory element M includes a first terminal coupled to the first data terminal N11 of the first memory unit 31; and a second terminal. The first transistor T1 includes a control terminal G coupled to the control terminal N1c of the first memory unit 31; a first terminal D coupled to the second terminal of the memory element M of the first memory unit 31; and a second terminal S coupled to the source terminal N12 of the first memory unit 31. The second transistor T2 includes a control terminal G coupled to the control terminal N1c of the first memory unit 31; a first terminal D coupled to the second terminal of the memory element M of the first memory unit 31; and a second terminal S coupled to the source terminal N12 of the first memory unit 31. The second memory unit 32 includes a memory element M, a first transistor T1, and a second transistor T2. The memory element M includes a first terminal coupled to the first data terminal N21 of the second memory unit 32; and a second terminal. The first transistor T1 includes a control terminal G coupled to the control terminal N2c of the second memory unit 32, a first terminal D coupled to the second terminal of the memory element M of the second memory unit 32, and a second terminal S coupled to the source terminal N22 of the second memory unit 32. The second transistor T2 includes a control terminal G coupled to the control terminal N2c of the second memory unit 32, a first terminal D coupled to the second terminal of the memory element M of the second memory unit 32, and a second terminal S coupled to the source terminal N22 of the second memory unit 32.

[0067] The memory element M of the first memory unit 31 and the memory element M of the second memory unit 32 are magnetic tunnel junctions, and the first transistor T1 and the second transistor T2 of the first memory unit 31 and the first transistor T1 and the second transistor T2 of the second memory unit 32 may be transistors of the same type. In the present embodiment, the first transistor T1 and the second transistor T2 of the first memory unit 31 and the first transistor T1 and the second transistor T2 of the second memory unit 32 may be, but are not limited to, N-type MOSFETs. In some embodiments, the first transistor T1 and the second transistor T2 of the first memory unit 31 and the first transistor T1 and the second transistor T2 of the second memory unit 32 may also be P-type MOSFETs or other types of transistors.

[0068] The controller can enable one of the first memory unit 31 and the second memory unit 32 to perform read and write operations, and disable the other to prohibit read and write operations. The controllable manner of the first memory unit 31 and the second memory unit 32 can be similar to the first memory unit 21 and the second memory unit 22, and the description thereof is not repeated here.

[0069] For the 2T1M architecture, the related art uses 2 bit lines and 1 source line to read and write 2 memory elements, while the present embodiment uses a common bit line BL1 and uses a separate first source line SL1 and a second source line SL2 to read and write 2 memory elements. Therefore, the related art uses 3 lines (2+1) to control the reading and writing of 2 memory elements, while the present embodiment also uses 3 lines (1+2) to control the reading and writing of 2 memory elements. If the remaining memory cells in the memory device 1 are also set and operated in a manner similar to the first memory cell 31 and the second memory cell 32, the number of bus lines of the related art (=N bit lines+1 source line) will greatly exceed the number of bus lines of the present embodiment (=N / 2 bit lines+2 source lines). Therefore, compared with the related art, the present embodiment will reduce the total number of bit lines of the memory device 3, simplify the circuit layout and reduce the circuit area.

[0070] Figure 4 Schematic diagram of the layout of the memory device 1. The memory device 1 includes a first conductive layer SL1, a second conductive layer SL2, a first bit line BL1, a second bit line BL2, a first bit line connection layer M31, a second bit line connection layer M32, first to sixth polysilicon layers P1 to P6, first to eighth diffusion layers D1 to D8, and first to fourth magnetic tunnel junctions MTJ1 to MTJ4. The first diffusion layer D1, the third diffusion layer D3, the fifth diffusion layer D5, the sixth diffusion layer D6, the first polysilicon layer P1, the third polysilicon layer P3, the fifth polysilicon layer P5, the first magnetic tunnel junction MTJ1, and the third magnetic tunnel junction MTJ3 can form a first memory cell 11. The second diffusion layer D2, the fourth diffusion layer D4, the seventh diffusion layer D7, the eighth diffusion layer D8, the second polysilicon layer P2, the fourth polysilicon layer P4, the sixth polysilicon layer P6, the second magnetic tunnel junction MTJ2, and the fourth magnetic tunnel junction MTJ4 can form a second memory cell 12.

[0071] The first conductive layer SL1 and the second conductive layer SL2 may be formed along the first direction d1. The second conductive layer SL2 and the first conductive layer SL1 may be formed Figure 1 The first source line SL1 and the second source line SL2 are formed in the first direction d1. The second conductive layer SL2 and the first conductive layer SL1 can be separated from each other. The first conductive layer SL1 and the second conductive layer SL2 are formed from the same conductive layer M1. The first bit line BL1 and the second bit line BL2 can be formed along the first direction d1. The first bit line BL1 and the second bit line BL2 can be formed respectively. Figure 1 The first bit line BL1 and the second bit line BL2 are separated from each other. The first bit line BL1 and the second bit line BL2 are formed from the same conductive layer M4.

[0072] The first polysilicon layer P1 may be formed along the second direction d2 and may at least partially overlap the first conductive layer SL1 and the first bit line BL1. The first direction d1 may be perpendicular to the second direction d2. The first polysilicon layer P1 may be formed Figure 1 The second polysilicon layer P2 may be formed along the second direction d2 and may at least partially overlap the second conductive layer SL2 and the second bit line BL2. Figure 1 The third polysilicon layer P3 may be formed along the second direction d2 and may at least partially overlap the first conductive layer SL1 and the first bit line BL1. Figure 1 The fourth polysilicon layer P4 may be formed along the second direction d2 and may at least partially overlap the second conductive layer SL2 and the second bit line BL2. Figure 1 The fifth polysilicon layer P5 may be formed along the second direction d2 and may at least partially overlap the first conductive layer SL1 and the first bit line BL1. Figure 1 The sixth polysilicon layer P6 may be formed along the second direction d2 and may at least partially overlap the second conductive layer SL2 and the second bit line BL2. Figure 1 The control terminal G of the second transistor T2 of the second memory unit 12 in the first embodiment is connected to the control terminal G of the second transistor T2 of the second memory unit 12. The first polysilicon layer P1, the second polysilicon layer P2, the third polysilicon layer P3, the fourth polysilicon layer P4, the fifth polysilicon layer P5 and the sixth polysilicon layer P6 are formed from the same polysilicon layer. The first polysilicon layer P1, the second polysilicon layer P2, the third polysilicon layer P3, the fourth polysilicon layer P4, the fifth polysilicon layer P5 and the sixth polysilicon layer P6 can be separated from each other. In some embodiments, the first polysilicon layer P1 and the second polysilicon layer P2 can also be coupled to each other, the third polysilicon layer P3 and the fourth polysilicon layer P4 can also be coupled to each other, and the fifth polysilicon layer P5 and the sixth polysilicon layer P6 can also be coupled to each other.

[0073] The first diffusion layer D1 may at least partially overlap the first bit line BL1 and be located between the first polysilicon layer P1 and the third polysilicon layer P3. The first diffusion layer D1 may be formed Figure 1 The first end D of the first transistor T1 of the first memory unit 11 and the first end D of the third transistor T3 of the first memory unit 11. The second diffusion layer D2 may at least partially overlap the second bit line BL2 and be located between the second polysilicon layer P2 and the fourth polysilicon layer P4. The second diffusion layer D2 may be formed Figure 1The first end D of the first transistor T1 of the second memory unit 12 and the first end D of the third transistor T3 of the first memory unit 11. The third diffusion layer D3 may at least partially overlap the first bit line BL1 and be located between the third polysilicon layer P3 and the fifth polysilicon layer P5. The third diffusion layer D3 may be formed Figure 1 The fourth diffusion layer D4 may at least partially overlap the second bit line BL2 and be located between the fourth polysilicon layer P4 and the sixth polysilicon layer P6. The fourth diffusion layer D4 may be formed Figure 1 The first end D of the second transistor T2 of the second memory unit 12 and the second end S of the third transistor T3 of the first memory unit 11 are connected.

[0074] The fifth diffusion layer D5 may at least partially overlap the first conductive layer SL1 and may form Figure 1 The sixth diffusion layer D6 may at least partially overlap the first conductive layer SL1 and may form a second end S of the first transistor T1 of the first memory cell 11. Figure 1 The seventh diffusion layer D7 may at least partially overlap the second conductive layer SL2 and may form a second end S of the second transistor T2 of the first memory cell 11. Figure 1 The eighth diffusion layer D8 may at least partially overlap the second conductive layer SL2 and may form a second end S of the first transistor T1 of the second memory cell 12. Figure 1 The first diffusion layer D1, the second diffusion layer D2, the third diffusion layer D3, the fourth diffusion layer D4, the fifth diffusion layer D5, the sixth diffusion layer D6, the seventh diffusion layer D7 and the eighth diffusion layer D8 are formed from the same diffusion layer.

[0075] The first magnetic tunnel junction MTJ1 may overlap the first diffusion layer D1 and the first bit line BL1, and may form Figure 1 The first memory element M1 of the first memory cell 11. The second magnetic tunnel junction MTJ2 may overlap the second diffusion layer D2 and the second bit line BL2, and may form Figure 1 The third magnetic tunnel junction MTJ3 may overlap the third diffusion layer D3 and the first bit line BL1, and may form a first memory element M1 of the second memory cell 12. Figure 1 The fourth magnetic tunnel junction MTJ4 may overlap the fourth diffusion layer D4 and the second bit line BL2, and may form a second memory element M2 of the first memory cell 11. Figure 1 The second memory element M2 of the second memory unit 12 in FIG.

[0076] The first bit line connection layer M31 may be formed along the second direction d2 and at least partially overlap the first diffusion layer D1 and the second diffusion layer D2 for coupling. Figure 1 The first end D of the first transistor T1 of the first memory unit 11 and the first end D of the first transistor T1 of the second memory unit 12. The second bit line connection layer M32 can be formed along the second direction d2, at least partially overlapping the third diffusion layer D3 and the fourth diffusion layer D4, for coupling Figure 1 The first end D of the second transistor T2 of the first memory unit 11 and the first end D of the second transistor T2 of the second memory unit 12. The first bit line connection layer M31 and the second bit line connection layer M32 are formed from the same conductive layer M3.

[0077] The memory device 1 may further include first to fourth contacts C1 to C4. The first contact C1 may overlap the fifth diffusion layer D5. The second contact C2 may overlap the sixth diffusion layer D6. The third contact C3 may overlap the seventh diffusion layer D7. The fourth contact C4 may overlap the eighth diffusion layer D8.

[0078] Figure 5 is another layout diagram of the memory device 1. The memory device 1 may further include a first through-hole VIA1 and a second through-hole VIA2. The first through-hole VIA1 may overlap the third diffusion layer D3 and the third magnetic tunnel junction MTJ3 to couple the third diffusion layer D3 and the third magnetic tunnel junction MTJ3. The second through-hole VIA2 may overlap the second diffusion layer D2 and the second magnetic tunnel junction MTJ2 to couple the second diffusion layer D2 and the second magnetic tunnel junction MTJ2. The first through-hole VIA1 and the second through-hole VIA2 are formed from the same through-hole layer V3.

[0079] Figure 6 for Figure 4 The cross-sectional view of the memory device 1 along the cutting line 6-6' includes a silicon carbon nitride (SiCN) layer, a conductive layer M4, a perforated layer V3, a conductive layer M3, an ultra low-k dielectric constant (ultra low-k) layer ULK, a titanium nitride (TiN) layer, an atomic layer deposition oxide (ALD OX) layer, a tungsten (W) layer, a tetraethyl orthosilicate (TEOS) layer, and a conductive layer M. Figure 6 The conductive layer M4 is coupled to the second bit line connection layer M32 of the conductive layer M3 through the first via VIA1 of the via layer V3, and the second bit line connection layer M32 of the conductive layer M3 is separated from the first bit line connection layer M31 of the conductive layer M3. The first bit line connection layer M31 and the second bit line connection layer M32 are disposed on their respective magnetic tunneling junctions.

[0080] At least two memory cells in the memory device of the embodiment of the present invention share the same bit line and use at least two separate source lines to complete the read and write operations of at least two memory cells, saving the number of bit lines, simplifying the circuit layout and reducing the circuit area.

[0081] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A memory device, comprising: A first memory unit comprises a control terminal, a first data terminal and a source terminal; A second memory unit includes a control terminal, a first data terminal and a source terminal; A word line coupled to the control terminal of the first memory unit and the control terminal of the second memory unit; A first bit line coupled to the first data terminal of the first memory unit and the first data terminal of the second memory unit; A first source line, coupled to the source terminal of the first memory unit, for receiving a first source voltage; and The second source line is coupled to the source terminal of the second memory unit and is used to receive a second source voltage, which is different from the first source voltage. 2 . The memory device of claim 1 , wherein the first source voltage is one of an enable voltage and a disable voltage, and the second source voltage is the other of the enable voltage and the disable voltage.

3. The memory device of claim 1, wherein: The first memory unit comprises: A memory element comprises a first terminal coupled to the first data terminal of the first memory unit; and a second terminal; and a transistor comprising a control terminal coupled to the control terminal of the first memory cell; a first terminal coupled to the second terminal of the memory element of the first memory cell; and a second terminal coupled to the source terminal of the first memory cell; and The second memory unit comprises: A memory element comprising a first terminal coupled to the first data terminal of the second memory unit; and a second terminal; and The transistor comprises a control terminal coupled to the control terminal of the second memory unit; a first terminal coupled to the second terminal of the memory element of the second memory unit; and a second terminal coupled to the source terminal of the second memory unit.

4. The memory device of claim 3, wherein the memory element of the first memory cell and the memory element of the second memory cell are magnetic tunnel junctions, and the transistor of the first memory cell and the transistor of the second memory cell are N-type transistors.

5. The memory device of claim 1, wherein: The first memory unit comprises: A memory element comprising a first terminal coupled to the first data terminal of the first memory unit; and a second terminal; A first transistor comprising a control terminal coupled to the control terminal of the first memory cell; a first terminal coupled to the second terminal of the memory element of the first memory cell; and a second terminal coupled to the source terminal of the first memory cell; and A second transistor comprising a control terminal coupled to the control terminal of the first memory cell; a first terminal coupled to the second terminal of the memory element of the first memory cell; and a second terminal coupled to the source terminal of the first memory cell; and The second memory unit comprises: A memory element comprising a first terminal coupled to the first data terminal of the second memory unit; and a second terminal; A first transistor including a control terminal coupled to the control terminal of the second memory unit; a first terminal coupled to the second terminal of the memory element of the second memory unit; and a second terminal coupled to the source terminal of the second memory unit; and The second transistor comprises a control terminal coupled to the control terminal of the second memory unit, a first terminal coupled to the second terminal of the memory element of the second memory unit, and a second terminal coupled to the source terminal of the second memory unit.

6. The memory device of claim 5, wherein the memory element of the first memory cell and the memory element of the second memory cell are magnetic tunnel junctions, and the first transistor and the second transistor of the first memory cell and the first transistor and the second transistor of the second memory cell are N-type transistors.

7. The memory device of claim 1, wherein: The first memory unit further comprises a second data terminal; The second memory unit further comprises a second data terminal; and The memory device further includes a second bit line coupled to the second data terminal of the first memory unit and the second data terminal of the second memory unit.

8. The memory device of claim 7, wherein: The first memory unit comprises: A first memory element comprising a first terminal coupled to the first data terminal of the first memory unit; and a second terminal; A second memory element comprises a first terminal coupled to the second data terminal of the first memory unit; and a second terminal; A first transistor comprising a control terminal coupled to the control terminal of the first memory cell; a first terminal coupled to the second terminal of the first memory element of the first memory cell; and a second terminal coupled to the source terminal of the first memory cell; A second transistor comprising a control terminal coupled to the control terminal of the first memory unit; a first terminal coupled to the second terminal of the second memory element of the first memory unit; and a second terminal coupled to the source terminal of the first memory unit; and a third transistor comprising a control terminal coupled to the control terminal of the first memory unit; a first terminal coupled to the first terminal of the first transistor of the first memory unit; and a second terminal coupled to the first terminal of the second transistor of the first memory unit; and The second memory unit comprises: A first memory element comprising a first terminal coupled to the first data terminal of the second memory unit; and a second terminal; A second memory element comprises a first terminal coupled to the second data terminal of the second memory unit; and a second terminal; A first transistor comprising a control terminal coupled to the control terminal of the second memory unit; a first terminal coupled to the second terminal of the first memory element of the second memory unit; and a second terminal coupled to the source terminal of the second memory unit; A second transistor comprising a control terminal coupled to the control terminal of the second memory unit; a first terminal coupled to the second terminal of the second memory element of the second memory unit; and a second terminal coupled to the source terminal of the second memory unit; and The third transistor comprises a control end coupled to the control end of the second memory unit; a first end coupled to the first end of the first transistor of the second memory unit; and a second end coupled to the first end of the second transistor of the second memory unit.

9. The memory device of claim 8, wherein the first memory element of the first memory cell and the second memory element of the second memory cell are magnetic tunnel junctions, and the first transistor, the second transistor and the third transistor of the first memory cell and the first transistor, the second transistor and the third transistor of the second memory cell are N-type transistors.

10. A memory device comprising: A first source line formed along a first direction; A second source line is formed along the first direction, and the second source line and the first source line are separated from each other; a first bit line formed along the first direction; a second bit line formed along the first direction; A first memory unit comprises: A first diffusion layer at least partially overlaps the first bit line; and a third diffusion layer at least partially overlapping the first bit line; A second memory unit comprises: a second diffusion layer at least partially overlapping the second bit line; and a fourth diffusion layer at least partially overlapping the second bit line; A first bit line connection layer is formed along the second direction and at least partially overlaps the first diffusion layer and the second diffusion layer; and The second bit line connection layer is formed along the second direction and at least partially overlaps the third diffusion layer and the fourth diffusion layer.

11. The memory device of claim 10, wherein: The first memory unit further comprises: A first polysilicon layer is formed along the second direction and at least partially overlaps the first source line and the first bit line; a third polysilicon layer formed along the second direction and at least partially overlapping the first source line and the first bit line, wherein the first diffusion layer is located between the first polysilicon layer and the third polysilicon layer; a fifth polysilicon layer formed along the second direction and at least partially overlapping the first source line and the first bit line, wherein the third diffusion layer is located between the third polysilicon layer and the fifth polysilicon layer; A first magnetic tunnel junction overlaps the first diffusion layer and the first bit line; A third magnetic tunnel junction overlaps the third diffusion layer and the first bit line; a fifth diffusion layer at least partially overlapping the first source line; and a sixth diffusion layer at least partially overlapping the first source line; The second memory unit further comprises: A second polysilicon layer is formed along the second direction and at least partially overlaps the second source line and the second bit line; a fourth polysilicon layer formed along the second direction and at least partially overlapping the second source line and the second bit line, wherein the second diffusion layer is located between the second polysilicon layer and the fourth polysilicon layer; a sixth polysilicon layer formed along the second direction and at least partially overlapping the second source line and the second bit line, wherein the fourth diffusion layer is located between the fourth polysilicon layer and the sixth polysilicon layer; A second magnetic tunnel junction overlaps the second diffusion layer and the second bit line; a fourth magnetic tunnel junction overlapping the fourth diffusion layer and the second bit line; a seventh diffusion layer at least partially overlapping the second source line; and The eighth diffusion layer at least partially overlaps the second source line.

12. The memory device of claim 11, wherein: The first source line and the second source line are formed from the same conductive layer; The first bit line and the second bit line are formed from the same conductive layer; The first bit line connection layer and the second bit line connection layer are formed from the same conductive layer; The first polysilicon layer, the second polysilicon layer, the third polysilicon layer, the fourth polysilicon layer, the fifth polysilicon layer, and the sixth polysilicon layer are formed from the same polysilicon layer; and The first diffusion layer, the second diffusion layer, the third diffusion layer, the fourth diffusion layer, the fifth diffusion layer, the sixth diffusion layer, the seventh diffusion layer, and the eighth diffusion layer are formed from the same diffusion layer. 13 . The memory device of claim 11 , wherein the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, the fourth polysilicon layer, the fifth polysilicon layer, and the sixth polysilicon layer are separated from each other.

14. The memory device of claim 11, further comprising: A first contact point overlaps the fifth diffusion layer; a second contact overlapping the sixth diffusion layer; A third contact overlaps the seventh diffusion layer; and The fourth contact overlaps the eighth diffusion layer.

15. The memory device of claim 11, wherein: The first memory cell further includes a first through hole overlapping the third diffusion layer and the third magnetic tunnel junction; and The second memory cell further includes a second through hole overlapping the second diffusion layer and the second magnetic tunnel junction.

16. The memory device of claim 10, wherein the first bit line and the second bit line are separated from each other.

17. The memory device of claim 10, wherein the first direction is perpendicular to the second direction.

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