A flexibly configurable and expandable channel simulation system

Abstract

The present application discloses a channel simulation system that can be flexibly configured and expanded, relating to the technical field of signal transceiver and processing. The system includes a multi-element extended interconnected computing matrix. By means of the connection relationships between the upper and lower levels of the extended interconnected computing matrix, between the extended interconnected computing matrix and the interconnected computing matrix, and between the internal computing units of the interconnected computing matrix, computing arrays with different topological structures and different scales can be constructed. Moreover, the more the number of array elements of the interconnected computing matrix and the more the number of extended interconnected levels, the larger the scale of the computing matrix, the greater the total computing power and storage space, which can meet the channel simulation requirements of larger scales, achieve the goal of adapting to different channel scales and instantaneous bandwidths. Furthermore, users can easily customize the channel simulation system according to their own needs, and can gradually expand the product functions and channel scales through phased construction, reducing costs and improving the product utilization rate.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal transceiver and processing, and particularly relates to a channel simulation system that can be flexibly configured and expanded to meet the channel simulation requirements of different channel scales and different instantaneous bandwidths. Background Art

[0002] A channel simulator is a device used to simulate the characteristics of an electromagnetic wave propagation channel. It can reproduce the propagation characteristics of electromagnetic signals in a real environment, including path loss, multipath effect, Doppler frequency shift, fading, and interference, etc. Channel simulators are very important in fields such as wireless communication, radar systems, and electronic countermeasures, because they allow engineers and researchers to test and evaluate the performance of radio frequency systems under controlled laboratory conditions.

[0003] Currently, there are already mature commercial channel simulators on the existing market, which are mainly used to simulate the propagation channels of wireless communication systems, and generally have an instantaneous bandwidth of several hundred MHz. However, if it is needed to simulate the radio frequency signal propagation channels in the fields of radar and electronic countermeasures, the instantaneous bandwidth of the channel simulator needs to reach 1 GHz or 2 GHz. At this time, the amount of data that the channel simulator needs to calculate and transmit will increase greatly, resulting in a significant increase in the construction cost of the system and a significant increase in the difficulty.

[0004] Taking a typical channel simulation system with 32 receivers and 32 transmitters and an instantaneous bandwidth of 2 GHz as an example: (1) The total system bandwidth is 64 GHz, and the total external data throughput is 320 GB / s; (2) The number of system channels is 32 2 , that is, 1024, the calculation data throughput of each channel is 10 GB / s, and the total internal data throughput is 10 TB / s; (3) The number of calculations for each channel is generally dozens of complex multiplication and addition operations. Calculated with 20 operations and 2 bytes each time, 1024 channels need to complete a total of 20×10÷2 = 100 TOps in total. Among them, TOps refers to one trillion operations per second (the full name is Tera Operations Per Second), which is a unit of the computing power of a processor.

[0005] In order to cope with such a large amount of data transmission and calculation, the related products on the market are all in the form of customized medium and large-sized instrument devices. At the same time, they have the disadvantages of relatively single functions and extremely high prices, and it is difficult to change the product characteristics, expand the product functions, and adjust the channel scale according to the different needs of users. Summary of the Invention

[0006] The object of the present invention is to provide a channel simulation system that can be flexibly configured and expanded, so as to solve the problems existing in existing medium and large-sized channel simulation instruments and equipment, such as fixed form, relatively single function, extremely high price, and difficulty in changing product characteristics, expanding product functions, and adjusting channel scale according to different user requirements.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] The present invention provides a channel simulation system that can be flexibly configured and expanded, including an N-element extended interconnected computing matrix, wherein, the N-element extended interconnected computing matrix includes M N-element extended interconnected computing matrices, the M N-element extended interconnected computing matrices include P N-element extended interconnected computing matrices, and so on, the n N-element extended interconnected computing matrices include Q N-element extended interconnected computing matrices, until the n N-element extended interconnected computing matrices include R N-element interconnected computing matrices, the N-element interconnected computing matrices include K computing units, wherein N is the abbreviation of , and the computing units are used to perform signal propagation simulation calculations on the input digital signals obtained by converting the input radio frequency signals to obtain output digital signals for converting into output radio frequency signals, , , , , and respectively represent integers greater than or equal to 2, represents an integer greater than or equal to 2, wherein exists when it is greater than or equal to 3, and represents an integer greater than or equal to 0 and less than ;

[0009] Any two of the K computing units in the

[0010] are communicatively connected; For each of the computing units in any one N-element interconnected computing matrix, the corresponding unit is respectively communicatively connected to the computing unit at the corresponding position in L other N-element interconnected computing matrices, wherein, any one The N - element interconnected computing matrix and the other N - element interconnected computing matrices constitute the N - element extended interconnected computing matrix;

[0011] For each of the computing units in any one N - element extended interconnected computing matrix, make the corresponding units respectively communicate and connect with the computing units in the other N - element extended interconnected computing matrix and at the corresponding positions, where, any one N - element extended interconnected computing matrix and the other N - element extended interconnected computing matrices constitute the N - element extended interconnected computing matrix.

[0012] Based on the above - mentioned invention content, a large - bandwidth real - time channel simulation system with flexible expansion is provided, that is, it includes multiple N - element extended interconnected computing matrices, and through the connection relationships between the upper and lower levels of the extended interconnected computing matrices, between the extended interconnected computing matrix and the interconnected computing matrix, and between the computing units inside the interconnected computing matrix, computing arrays with different topological structures and different scales can be constructed. And the more the number of array elements of the interconnected computing matrix and the more the number of extended interconnected levels, the larger the scale of the computing matrix, the greater the total computing power and storage space, which can meet the channel simulation requirements of larger scales, achieve the goal of adapting to different channel scales and instantaneous bandwidths. Furthermore, users can easily customize the channel simulation system according to their own needs, and can gradually expand the product functions and channel scales through phased construction, reduce costs, improve the product utilization rate, solve the problems existing in existing medium - large - scale channel simulation instruments and equipment, such as fixed form, relatively single function, extremely high price, and difficulty in changing product characteristics, expanding product functions and adjusting channel scales according to different user needs, and is convenient for practical application and promotion.

[0013] In a possible design, it further includes a control computer, where the control computer is respectively communicatively connected to the controlled ends of each of the computing units in the N - element extended interconnected computing matrix and is used for reading and writing the parameters and / or data of the computing units.

[0014] In a possible design, each computing unit is communicatively connected to at least one signal transceiver unit;

[0015] The signal transceiver unit is used for receiving the input digital signal converted from the input radio - frequency signal, and sending the output digital signal for conversion into the output radio - frequency signal;

[0016] Alternatively, the signal transceiver unit is configured to receive the input radio frequency signal and convert it into the input digital signal, and convert the output digital signal into the output radio frequency signal and transmit it.

[0017] In a possible design, when the signal transceiver unit is configured to receive the input radio frequency signal and convert it into the input digital signal, and convert the output digital signal into the output radio frequency signal and transmit it, the signal transceiver unit includes an analog receive front-end module, an analog transmit front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module, and a second high-speed serial interface. Among them, the analog receive front-end module is configured to receive the input radio frequency signal, the analog transmit front-end module is configured to transmit the output radio frequency signal, and the second high-speed serial interface is used for communication connection with the computing unit;

[0018] The output end of the analog receive front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmit front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

[0019] In a possible design, the signal transceiver unit further includes a clock and trigger signal interface, an on-board OCXO module, and a clock generation and distribution circuit module based on a phase-locked loop mechanism. Among them, the clock and trigger signal interface is configured to receive an external sampling clock signal, a reference clock signal, a GPS second pulse signal, and a trigger signal, and the on-board OCXO module is configured to generate a time base signal;

[0020] The trigger signal output end of the clock and trigger signal interface is communicatively connected to the second FPGA module, the non-trigger signal output end of the clock and trigger signal interface and the time base signal output end of the on-board OCXO module are respectively communicatively connected to the input end of the clock generation and distribution circuit module, and the clock signal output end of the clock generation and distribution circuit module is respectively communicatively connected to the analog receive front-end module, the analog transmit front-end module, the ADC module, the DAC module, and the second FPGA module.

[0021] In a possible design, when the signal transceiver unit includes a second FPGA module, a second storage module, and a second high-speed serial interface that are respectively communicatively connected to the second FPGA module, the signal transceiver unit is further configured to serve as an extended computing unit relative to the computing unit, and is configured to execute any one or any combination of the following extended computing tasks (A) to (I):

[0022] (A) Increase the signal instantaneous bandwidth by using interpolation processing;

[0023] (B) Reduce the signal instantaneous bandwidth by using decimation processing;

[0024] (C) Change the center frequency of the signal by using digital frequency conversion;

[0025] (D) Calculate the spectrum of the signal in real time;

[0026] (E) Calculate the target echo or clutter in real time;

[0027] (F) Simulate the signal phase offset at each port of the multi-channel direction-finding receiver;

[0028] (G) Simulate the signal amplitude and phase of each channel in the radar sum-difference channel;

[0029] (H) Transmit and receive data through a high-speed serial bus;

[0030] (I) Perform amplitude calibration and phase calibration on the transmitted and received signals.

[0031] In a possible design, the signal propagation simulation calculation includes calculations of spatial fading, multipath effect, Doppler effect, time delay, and / or interference superposition during the signal propagation process.

[0032] In a possible design, the meta-expanded interconnection calculation matrix is used to perform symmetric calculation of channel simulation in the following manner:

[0033] Let represent the unique number of the meta-expanded interconnection calculation matrix in the meta-expanded interconnection calculation matrix and take any value within the integer range Let represent the unique number of the meta-expanded interconnection calculation matrix in the meta-expanded interconnection calculation matrix and take any value within the integer range Let represent the unique number of the meta-expanded interconnection calculation matrix in the meta-expanded interconnection calculation matrix and take any value within the integer range Let represent the indicating that the computing unit is in the unique number in the N - element interconnected computing matrix and takes any value within the integer range so that each of the computing units in the N - element extended interconnected computing matrix has a corresponding number sequence ;

[0034] If each of the computing units in the N - element extended interconnected computing matrix is independently communicatively connected to a signal transceiver channel pair, then let indicate that the signal transceiver channel pair is in the unique number in the M - pair signal transceiver channel pair and takes any value within the integer range so that each of the M - pair signal transceiver channel pairs in the M - pair signal transceiver channel pair has a corresponding number sequence , where represents a positive integer;

[0035] For a target signal transmission channel with a number sequence , calculate the corresponding output digital signal for conversion into an output radio - frequency signal and send it out through the corresponding channel, where represents an integer and there is , represents an integer and there is , represents an integer and there is , represents an integer and there is , represents an integer and there is , represents an integer and there is , the output digital signal is calculated according to the following round - by - round steps:

[0036] First round: Inside each of the N - element interconnected computing matrix, the first computing unit with a number sequence first obtains signal data to be subjected to channel simulation calculation from the L signal receiving channels communicatively connected to the first computing unit and L other computing units, and then, for the target signal transmission channel, according to the signal data and the given channel parameters of each of the L signal receiving channels relative to the corresponding transmission channel, simulate and calculate the total of a signal propagation process, and superimpose the calculation results to obtain the corresponding first-round superimposed calculation result;

[0037] The second round: Inside each of the meta-expanded interconnected computing matrices, the second computing units with the serial number sequence respectively perform transmission delay effect calibration and deduction processing on all the computing units with the serial number sequence and the corresponding first-round superimposed calculation results for the target signal transmission channel, and superimpose the processing results to obtain the corresponding second-round superimposed calculation result;

[0038] The th round: Inside each of the meta-expanded interconnected computing matrices, the third computing units with the serial number sequence respectively perform transmission delay effect calibration and deduction processing on all the computing units with the serial number sequence and the corresponding th-round superimposed calculation results for the target signal transmission channel, and superimpose the processing results to obtain the corresponding th-round superimposed calculation result;

[0039] The th round: The fourth computing units with the serial number sequence respectively perform transmission delay effect calibration and deduction processing on all the computing units with the serial number sequence and the corresponding th-round superimposed calculation results for the target signal transmission channel, and superimpose the processing results to obtain the corresponding output digital signal.

[0040] In a possible design, the computing unit includes a first FPGA module, a first storage module, and a first high-speed serial interface, where the number of the first high-speed serial interfaces is at least one and is used for communication connection with a signal transceiver unit or other computing units;

[0041] The first FPGA module is respectively communicatively connected to the first storage module and the first high-speed serial interface.

[0042] In a possible design, the first storage module uses dynamic random access memory, and the first high-speed serial interface uses a Nano-Pitch interface.

[0043] Beneficial effects of the above solution:

[0044] (1) The present invention provides a flexible expandable large-bandwidth real-time channel simulation system, which includes a multi-element expandable interconnected computing matrix. Through the connection relationships between the upper and lower levels of the expandable interconnected computing matrix, between the expandable interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix, computing arrays with different topological structures and different scales can be constructed. The more the number of array elements of the interconnected computing matrix and the more the number of expandable interconnected levels, the larger the scale of the computing matrix, the greater the total computing power and storage space, which can meet the channel simulation requirements of larger scales, achieve the goal of adapting to different channel scales and instantaneous bandwidths. Furthermore, users can easily customize the channel simulation system according to their own needs, and can gradually expand the product functions and channel scales through phased construction, reducing costs and increasing the product utilization rate, solving the problems existing in existing medium and large-sized channel simulation instruments and equipment, such as fixed form, relatively single function, extremely high price, and difficulty in changing product characteristics, expanding product functions, and adjusting channel scales according to different user needs, which is convenient for practical application and promotion;

[0045] (2) Flexible expandability and splitability: The computing topological structure designed by the present invention is applicable to channel simulation systems from several channels to hundreds of channels. It can easily expand a small-scale channel simulation system into a large-scale system, and can also easily split a large-scale system into several small-scale systems;

[0046] (3) Large simulation bandwidth: The bandwidth that the channel simulation system can simulate mainly depends on the computing power and data access ability of a single computing unit. The computing topological structure designed by the present invention can flexibly configure the ratio of the number of computing units and signal transceiver units (as well as the number of transceiver channel groups), and the signal transceiver unit can also provide additional computing power and data access ability support. Therefore, when increasing the ratio of computing units (the maximum can reach a 1:1 ratio of transceiver channel groups and computing units); current advanced FPGAs already have a computing power of more than 3 TOps. At a 1:1 ratio, that is, with 32 computing units plus extended computing units, a total computing power of more than 100 TOps can be provided. At a 2 GHz instantaneous bandwidth, channel simulation of 32T32R with a total of 64 channels can also be achieved;

[0047] (4) Low computing latency: The hardware circuit characteristics of the FPGA itself have the characteristic of low computing latency. At the same time, the computing matrix topological structure designed by the present invention enables data interaction between any two computing units to only pass through a very short data exchange path, so the entire computing matrix has the advantage of low computing latency;

[0048] (5) Low cost: Due to the standardization of computing units and interconnected computing matrices, the construction and expansion of large-scale channel simulation systems no longer need to be customized, thus enabling low costs;

[0049] (6) Easy to develop: Since the computing topology designed in the present invention is a completely symmetric structure, only the algorithm and program need to be designed for a single computing unit to complete the program design of the entire computing matrix.

[0050] (7) Customizable: The signal transceiver unit provides extended computing capabilities, and the implementation of this part of the computing power is completely decoupled from the computing matrix. Therefore, it is easy to provide customized signal processing capabilities for the channel simulation port device. Brief Description of the Drawings

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0052] Figure 1 It is a schematic diagram of the specific structure of the computing unit in the channel simulation system provided by the embodiment of the present invention.

[0053] Figure 2 It is a schematic diagram of the specific structure of the 2-element interconnected computing matrix provided by the embodiment of the present invention.

[0054] Figure 3 Provided by the embodiment of the present invention Schematic diagram of the structure of the -element interconnected computing matrix, where Figure 3 (a) in shows the schematic diagram of the structure of the 3-element interconnected computing matrix, Figure 3 (b) in shows the schematic diagram of the structure of the 4-element interconnected computing matrix, Figure 3 (c) in shows the schematic diagram of the structure of the 5-element interconnected computing matrix.

[0055] Figure 4 It is a schematic diagram of the structure of the 3×3 -element extended interconnected computing matrix provided by the embodiment of the present invention.

[0056] Figure 5 It is a schematic diagram of the structure of the 4×3 -element extended interconnected computing matrix provided by the embodiment of the present invention.

[0057] Figure 6 It is a schematic diagram of the structure of the 4×4 -element extended interconnected computing matrix provided by the embodiment of the present invention.

[0058] Figure 7 It is a schematic diagram of the specific structure of the signal transceiver unit in the channel simulation system provided by the embodiment of the present invention.

[0059] Figure 8 It is an example diagram of the connection relationship between the 4×4 -element interconnected computing matrix and the signal transceiver unit provided by the embodiment of the present invention.

[0060] Figure 9 This is an example diagram of the topological structure after the calculation extension of the 4×4 element interconnected computing matrix provided by the embodiment of the present invention.

[0061] Figure 10 This is an example diagram of the connection relationship between the 4×3 element interconnected computing matrix and the signal transceiver unit provided by the embodiment of the present invention.

[0062] Figure 11 This is an example diagram of implementing the channel simulation calculation logic based on the 4×4 element extended interconnected computing matrix provided by the embodiment of the present invention. Detailed implementation manners

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these embodiments without creative efforts. It should be noted here that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation to the present invention.

[0064] It should be understood that although terms such as first and second etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, the first object can be called the second object, and similarly the second object can be called the first object, without departing from the scope of the exemplary embodiments of the present invention.

[0065] It should be understood that for the term "and / or" that may appear in this article, it is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, B exists alone, or A and B exist simultaneously, etc.; and for another example, A, B and / or C can represent any one of A, B and C or any combination of them; for the term " / and" that may appear in this article, it is a description of another association object relationship, indicating that two relationships can exist. For example, A / and B can represent: A exists alone or A and B exist simultaneously, etc.; in addition, for the character " / " that may appear in this article, generally it represents that the front and back associated objects are an "or" relationship.

[0066] Embodiment

[0067] As Figures 1 to 11 shown, the channel simulation system provided and flexibly configurable and extensible in this embodiment includes, but is not limited to, element extended interconnected computing matrix, where the The N - th extended interconnected computing matrix includes ones of the N - th extended interconnected computing matrix, and the N - th extended interconnected computing matrix includes ones of the (N - 1)-th extended interconnected computing matrix, and so on until the 2 - th extended interconnected computing matrix includes ones of the 1 - th interconnected computing matrix, and the 1 - th interconnected computing matrix includes ones of the 0 - th interconnected computing matrix, and the 0 - th interconnected computing matrix includes computing units, where is an abbreviation, and the computing units are used to perform signal propagation simulation calculations on the input digital signals obtained by converting the input radio frequency signals to obtain the output digital signals for converting to output radio frequency signals. , , , and respectively represent integers greater than or equal to 2, represents an integer greater than or equal to 2, exists when is greater than or equal to 3 and represents an integer greater than or equal to 0 and less than ; any two of the computing units are communicatively connected; for each of the computing units in any one 0 - th interconnected computing matrix, the corresponding unit is communicatively connected to the corresponding computing unit in ones of the 1 - th interconnected computing matrix at the corresponding position, where any one 0 - th interconnected computing matrix and the ones of the 1 - th interconnected computing matrix constitute the 1 - th extended interconnected computing matrix; for each of the computing units in any one 1 - th extended interconnected computing matrix, the corresponding unit is communicatively connected to the corresponding computing unit in ones of the 2 - th extended interconnected computing matrix at the corresponding position, where any one 1 - th extended interconnected computing matrix and the ones of the 2 - th extended interconnected computing matrix constitute the 2 - th extended interconnected computing matrix.

[0068] As Figures 1 to 11 shown, in the specific structure of the channel simulation system, the N-element extended interconnected computing matrix is the main body for signal propagation simulation calculation, and can be arbitrarily expanded according to the different values of , , , , and to change the scale of the computing unit at will, so as to change product characteristics, expand product functions and adjust channel scale according to different user requirements, and then solve the problems of fixed form, relatively single function and extremely high price existing in existing medium and large-sized channel simulation instruments and equipment. In addition, due to the complete symmetry of the construction of the foregoing computing matrix, when performing channel simulation calculation, if the embedded computing program of a certain computing unit is designed, the embedded computing program of the entire computing matrix can be completed.

[0069] As Figure 1 shown, specifically, the computing unit includes, but is not limited to, a first FPGA module, a first storage module, and a first high-speed serial interface, etc. Among them, the number of the first high-speed serial interfaces is multiple and is used for communicating and connecting a signal transceiver unit or other computing units; the first FPGA module is respectively communicatively connected to the first storage module and the first high-speed serial interface. The first FPGA (Field Programmable Gate Array) module is used for signal propagation simulation calculation, and can be specifically implemented by using existing device products; the number of the first FPGA modules can be one or multiple, and when there are multiple first FPGA modules, the multiple first FPGA modules can be interconnected through a high-speed communication interface, so that data required for calculation can be shared among the FPGA modules (at this time, the computing unit composed of multiple first FPGA modules is still logically regarded as a whole computing unit externally, so as to enhance the computing power, storage capacity and the number of high-speed serial interfaces of a single computing unit, and improve the overall computing power and expansion ability of the interconnected computing matrix). The first storage module (i.e., Figure 1 represented by DRAM in Figure 1It is mainly used for the following four purposes (denoted by D in Chinese): (a) high-speed interconnection with other computing units within the same circuit board; (b) high-speed interconnection with computing units in other circuit boards through connectors of high-speed serial interfaces (such as high-speed connectors like QSFP28 or QSFP56, etc.); (c) connection with the high-speed serial interface of the signal transceiver unit; (d) connection with the high-speed serial interface of other peripherals. More specifically, the first high-speed serial interface can, but is not limited to, adopt a Nano-Pitch interface. Preferably, a Nano-Pitch standard 42-pin (not limited to this standard) connector is used as a compact and high-rate connection interface. Each connector can provide up to 6 unidirectional data transmission links with a rate of up to 16 Gbps, for a total of 96 Gbps (12 GB / s) of bidirectional data transmission links.

[0070] As Figure 2 shown, the 2 computing units can communicate with each other through a high-speed serial interface to form a 2-element interconnected computing matrix; the 2-element interconnected computing matrix can be connected through high-speed serial cables or can be implemented on the same circuit board. The latter can eliminate high-speed serial connectors and cables, simplify the connection between them, reduce the interconnection cost, and increase the interconnection data rate; the 2 computing units can exchange and share data at high speed through high-speed interconnection, and at the same time perform parallel computing on different data, increasing the computing power. Moreover, the two 2-element interconnected computing matrices can be further extended and interconnected through a high-speed serial interface to construct a 2 2 -element extended interconnected computing matrix (the method of its extended interconnection is: each computing unit of one 2-element interconnected computing matrix is connected pairwise with the corresponding computing unit of another 2-element interconnected computing matrix). Each computing unit in the 2 2 -element extended interconnected matrix can perform high-speed data exchange with any other computing unit through at most one intermediate computing unit, thus ensuring that each computing unit can efficiently obtain the required computing data from other computing units.

[0071] Based on the above construction method of the 2-element interconnected computing matrix, further: The computing units are fully interconnected (here, full interconnection means that any one computing unit is directly connected pairwise through a high-speed serial connection with the other computing units) to form an -element interconnected computing matrix; for example, a 3-element interconnected computing matrix is as shown in (a) of Figure 3 , a 4-element interconnected computing matrix is as shown in (b) of Figure 3 , a 5-element interconnected computing matrix is as shown in (c) of Figure 3 , and so on.

[0072] Based on the above 2 2The construction method of the N - extended interconnected computing matrix is further as follows: One N - interconnected computing matrix can be extended and interconnected with other up to N N - interconnected computing matrices to form a maximum N×N - extended interconnected computing matrix (the method of its extended interconnection is each computing unit of the N - interconnected computing matrix is pairwise connected with the corresponding computing unit of other N - interconnected computing matrices). For example, as Figure 4 shown: 3 three - N interconnected computing matrices are extended to a 3×3 - extended interconnected computing matrix; as Figure 5 shown: 4 three - N interconnected computing matrices are extended to a 4×3 - extended interconnected computing matrix; as Figure 6 shown: 4 four - N interconnected computing matrices are extended to a 4×4 - extended interconnected computing matrix, and so on.

[0073] Based on the above Figures 4 to 6 it can be seen that: the topological structure in the N - extended interconnected computing matrix is completely symmetric; that is to say, the position and connection relationship of each computing unit in the matrix are completely consistent and symmetric with respect to other computing units. Therefore, each computing unit in the extended interconnected computing matrix is equivalent, which makes the computing matrix very suitable for performing highly parallel and symmetric computations. In addition to the symmetry of the topological structure, each computing unit in the N - extended interconnected computing matrix only needs to pass through at most one intermediate computing unit to complete data exchange with any other computing unit, thereby ensuring that each computing unit can easily establish low - latency communication with other computing units, and thus can obtain all the data in the entire computing matrix with low latency. At the same time, the calculations of large - scale signal propagation simulations exactly meet these two characteristics: (1) The calculation of each channel is related to all input signals; (2) The calculation of each channel is completely consistent and symmetric. Thus, one N - extended interconnected computing matrix can be extended and interconnected with other up to N N - interconnected computing matrices (here N represents an integer greater than or equal to 2) to form a maximum N×N - extended interconnected computing matrix (i.e., N×N - interconnected computing matrix), and can be further extended by analogy to N×N×N - extended interconnected computing matrix (i.e., the aforementioned N - extended interconnected computing matrix). The aforementioned Each computing unit within the meta-expanded interconnected computing matrix is also equivalent, and there is at most intermediate computing units between it and any other computing unit to enable high-speed data exchange, thus ensuring that each computing unit can efficiently and with low latency obtain the required computing data from other computing units.

[0074] Based on the aforementioned expansion method of the interconnected computing matrix, different topologies and scales of computing arrays can be constructed according to different channel simulation computing requirements. The more the number of array elements in the interconnected computing matrix and the more the number of levels of expanded interconnection, the larger the scale of the computing matrix, the greater the total computing power and storage space, and the larger the scale of channel simulation requirements that can be adapted. Furthermore, it solves the problems existing in existing medium and large-sized channel simulation instruments and equipment, such as fixed form, relatively single function, extremely high price, and difficulty in changing product characteristics, expanding product functions, and adjusting channel scales according to different user requirements.

[0075] Preferably, it further includes a control computer, wherein the control computer is respectively communicatively connected to the controlled ends of each of the computing units in the meta-expanded interconnected computing matrix, and is used for reading and writing operations on the parameters and / or data of the computing units. As shown in Figure 1 and Figure 2 , the controlled end of the computing unit is specifically a control bus interface (i.e., Figure 1 denoted by C in

[0076] ), and it is preferably connected to the bus interface circuit with a PCIe bus or a PCIe-based instrument expansion bus (such as PXIe, CPCIe, VPX, etc.) as the communication and control bus. The PCIe bus and PCIe-based instrument expansion buses have mature and complete hardware and software ecosystems, enabling users to easily add a variety of I / O modules based on such bus platforms and use mature system and data management software to control and manage the system. Such bus platforms also provide modular architectures, enabling users to easily expand the functions and capabilities of the system using different types and quantities of modules.Preferably, the computing unit is communicatively connected to at least one signal transceiver unit; the signal transceiver unit is configured to receive the input digital signal converted from the input radio frequency signal, and transmit the output digital signal for conversion into the output radio frequency signal; alternatively, the signal transceiver unit is configured to receive the input radio frequency signal and convert it into the input digital signal, and convert the output digital signal into the output radio frequency signal and transmit it. Since the computing input of the aforementioned interconnected computing matrix usually comes from an external radio frequency signal, and the computing output usually also needs to be sent to the outside, the signal transceiver unit is required to collect, obtain, generate, and transmit. In addition to being responsible for the high-speed transceiver of digital signals or analog signals, the signal transceiver unit can also perform signal processing according to specific requirements, mainly composed of an FPGA module, a high-speed serial interface, etc. Specifically, when the signal transceiver unit is configured to receive the input radio frequency signal and convert it into the input digital signal, and convert the output digital signal into the output radio frequency signal and transmit it, the signal transceiver unit includes, but is not limited to, an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module, and a second high-speed serial interface, etc. Among them, the analog receiving front-end module is configured to receive the input radio frequency signal, the analog transmitting front-end module is configured to transmit the output radio frequency signal, and the second high-speed serial interface is configured to communicatively connect to the computing unit; the output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

[0077] Such as Figure 7As shown, in the specific structure of the signal transceiver unit, the analog receiving front-end module and the analog transmitting front-end module respectively cooperate with the ADC module and the DAC module in a one-to-one correspondence, and are used for frequency conversion, amplification, conditioning, filtering, receiving and transmitting analog signals, and realizing the conversion between analog signals and digital signals. The second FPGA module has high-speed data throughput capacity and is a key device connecting the ADC / DAC and the analog front-end. With its characteristics suitable for high-speed parallel fixed-point number calculation, it can provide real-time signal preprocessing capabilities for the system. On the one hand, it completes part of the signal processing work, and on the other hand, it can also complete the extraction and compression of valid data, reducing the amount of data transmitted to the backend signal processor. The second FPGA module can also have a signal processing delay as low as the ns level, and realizes low-delay signal transceiver through the ADC module and the DAC module. The second storage module specifically includes but is not limited to DRAM and FLASH. Among them, the former is used for local caching and temporary storage of high-speed signal data, and the latter is used to store firmware programs. The second high-speed serial interface can specifically be implemented by a high-speed serial bus interface adopting the Aurora communication protocol, that is, preferably adopting a high-speed serial transmission protocol of Aurora 16Gbps x6 or higher speed. It has a peak data throughput rate of 11GB / s and a transmission delay as short as the microsecond level. It can provide a large enough transmission bandwidth and a short enough transmission delay for most real-time signal processing applications, ensuring the continuity and timeliness of data transmission and providing basic conditions for real-time signal processing; The second high-speed serial interface is further preferably implemented by using a Nano-Pitch series connector produced by Molex. This series of connectors can provide a data transmission capacity of up to 25Gbps x8, which is sufficient to meet the full-duplex transmission requirements of 2-way 2GHz instantaneous bandwidth signals.

[0078] Further preferably, the signal transceiver unit further includes but is not limited to a clock and trigger signal interface, an on-board OCXO module, and a clock generation and distribution circuit module based on a phase-locked loop mechanism, etc. Among them, the clock and trigger signal interface ( Figure 7 represented by DIO in the figure) is used for but not limited to receiving external sampling clock signals, reference clock signals, GPS second pulse signals, trigger signals, etc. The on-board OCXO module ( Figure 7 represented by OCXO in the figure) is used to generate a time base signal; The trigger signal output end of the clock and trigger signal interface is communicatively connected to the second FPGA module, and the non-trigger signal output end of the clock and trigger signal interface and the time base signal output end of the on-board OCXO module are respectively communicatively connected to the input end of the clock generation and distribution circuit module. The clock generation and distribution circuit module ( Figure 7The clock signal output terminals (represented by PLL in Chinese) are respectively communicatively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module, and the second FPGA module. The connector of the clock and trigger signal interface can be selected according to the specific signal frequency and quantity. The sampling clock signal, the reference clock signal, the GPS second pulse signal, and the time base signal are used to provide clock signals for the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module, and the second FPGA module respectively through the clock generation and distribution circuit module based on the phase-locked loop. The trigger signal is connected to the second FPGA module and is used for the internal processing logic triggered by external events. Thus, through the aforementioned clock and trigger mechanism, multiple parallel or distributed signal transceiver units can work synchronously to achieve the reception or transmission of coherent signals.

[0079] Since the connection of the complete interconnection computing matrix to the signal transceiver unit is also completely symmetric, therefore for the n-element extended interconnection computing matrix, if all m computing units are connected to ( m represents a positive integer) signal transceiver units, and each signal transceiver unit has k pairs of transceiver channels, then this channel simulation system has a total of m×k pairs of transceiver channels, that is, it forms m receive m transmit channel simulation systems. At the same time, according to the structure of the signal transceiver unit, it can be known that: the signal transceiver unit actually also includes the structure of the computing unit, that is, a combination of FPGA, DRAM, and high-speed serial port. Therefore, when the signal transceiver unit is connected to the interconnection computing matrix, it is actually equivalent to connecting new computing units to each node of the interconnection computing matrix. As Figure 8 shown, in a 4-element interconnection computing matrix, each computing unit is connected to 2 signal transceiver units, and the signal transceiver units are used to receive and transmit radio frequency signals; since the signal transceiver unit includes the computing unit structure, this interconnection computing matrix is equivalent to being expanded into as Figure 9The extended interconnected computing matrix topology shown. Although each computing unit of the extended interconnected computing matrix does not have as sufficient interconnection of computing units as the interconnected computing matrix or the extended interconnected computing matrix (i.e., each computing unit is interconnected with other computing units by multiple high-speed serial interfaces), the computing power of each computing unit of the original extended interconnected computing matrix has been enhanced. This enables the extended interconnected computing matrix to not only perform fully symmetric channel simulation calculations but also complete further signal processing work related to the devices connected to each channel simulation port. That is, further preferably, when the signal transceiver unit includes a second FPGA module, a second storage module, and a second high-speed serial interface that are respectively communicatively connected to the second FPGA module, the signal transceiver unit is also used as an extended computing unit relative to the computing unit and is used to execute any one or any combination of the following extended computing tasks (A) to (I): (A) increasing the signal instantaneous bandwidth by interpolation processing; (B) reducing the signal instantaneous bandwidth by decimation processing; (C) changing the center frequency of the signal by digital frequency conversion; (D) calculating the spectrum of the signal in real time; (E) calculating the target echo or clutter in real time; (F) simulating the signal phase offset at each port of the multi-channel direction-finding receiver; (G) simulating the signal amplitude and phase of each channel in the radar sum-difference channel; (H) performing data transceiver through a high-speed serial bus; (I) performing amplitude calibration and phase calibration of the transceiver signals. This aforementioned extended computing ability greatly increases the functions that the channel simulation system can simulate. Figure 9 shows the topological structure after the computing extension of the 4-element interconnected computing matrix, and so on for all element extended interconnected computing matrices can form an extended extended interconnected computing matrix by connecting the signal transceiver unit to any number of computing units. As Figure 10 shown, a 3 2 element extended interconnected computing matrix, and each computing unit is connected to 1 signal transceiver unit. In addition, the computing input of the aforementioned interconnected computing matrix can also be injected in the form of a digital signal via a high-speed serial interface, and its computing output can also be output in the form of a digital signal via a high-speed serial interface. In this case, the relevant computing unit may not be connected to the signal transceiver unit.

[0080] Since the signals generated by each RF output channel in channel simulation are obtained by separately performing independent channel propagation simulation calculations on the signals received by all RF input channels. Specifically, the signal propagation simulation calculations include, but are not limited to, calculations of spatial fading, multipath effect, Doppler effect, time delay, and / or interference superposition during signal propagation. At the same time, in the extended interconnection calculation matrix, the positions and connection relationships of each calculation unit in the matrix are completely consistent and symmetric. Therefore, when the number of transceiver channels connected to each calculation unit is the same and the topological structure of channel simulation is also consistent and symmetric, the calculation logic of each calculation unit will be completely symmetric and consistent. The specific calculation process of channel simulation is as follows: According to the given channel parameters of a certain RF output channel for the selected RF input channel, perform corresponding signal propagation simulation calculations on the signals received by the selected RF input channel, and then perform superposition calculations (i.e., mathematical addition calculations of this signal type), and transmit the result after superposition calculation from the selected RF output channel (the above process is repeated for all selected RF output channels). Thus, preferably, the -element extended interconnection calculation matrix is used to perform symmetric calculations of channel simulation in the following manner: Let represent the -element extended interconnection calculation matrix in the -element extended interconnection calculation matrix and take any value within the integer range . Let represent the -element extended interconnection calculation matrix in the -element extended interconnection calculation matrix and take any value within the integer range . Let represent the -element extended interconnection calculation matrix in the -element extended interconnection calculation matrix and take any value within the integer range . Let represent the -element interconnection calculation matrix in the -element extended interconnection calculation matrix and take any value within the integer range . Let represent the unique number of the calculation unit in the -element interconnection calculation matrix and take any value within the integer range to enable each of the calculation units in the -element extended interconnection calculation matrix to have a corresponding number sequence ; If each of the calculation units in the -element extended interconnection calculation matrix is independently communicatively connected to For a signal transceiver channel (i.e., communicatively connected with signal receiving channels and signal transmitting channels), let represent the unique number of the signal transceiver channel among the pairs of signal transceiver channels and take any value within the integer range so that each pair of signal transceiver channels among the pairs of signal transceiver channels has a corresponding number sequence (that is, each signal receiving channel or each signal transmitting channel has a corresponding number sequence ), where represents a positive integer; for the target signal transmitting channel with the number sequence , calculate the corresponding output digital signal for conversion into an output radio frequency signal and send it out through the corresponding channel, where represents an integer and there is , represents an integer and there is , represents an integer and there is , represents an integer and there is , represents an integer and there is , represents an integer and there is , and the output digital signal is calculated according to the following round of steps.

[0081] The first round: Inside each of the n - element interconnected calculation matrices, the first calculation unit with the number sequence first obtains the signal data to be subjected to channel simulation calculation from the signal receiving channels communicatively connected with the first calculation unit and other calculation units, and then, for the target signal transmitting channel, according to the signal data and the given channel parameters of each signal receiving channel among the signal receiving channels with respect to the corresponding transmitting channel, simulates and calculates the total signal propagation processes of each signal receiving channel with respect to the corresponding transmitting channel, and superimposes the calculation results to obtain the corresponding first - round superimposed calculation result.

[0082] In the first round, since there are such n - element interconnected calculation matrices, and there is one such first calculation unit with the number sequence in each The first computing unit, and each of the first computing units further has signal transmission channels, and will perform simulation calculations on the signal propagation processes for all the signal transmission channels of all the first computing units. Therefore, in fact, each of the first computing units will calculate a total of signal propagation processes, and for each signal transmission channel, superimpose all the corresponding calculation results to obtain the corresponding first-round superimposed calculation result, that is, first-round superimposed calculation results will be obtained. The specific simulation calculation process and superimposition technical process of the foregoing signal propagation process are all prior arts and will not be elaborated herein. Considering that compared with the first signal data obtained from the signal receiving channels communicatively connected to the first computing unit, the second signal data obtained from the signal receiving channels communicatively connected to the other computing units will have a certain transmission delay due to the transmission path from the other computing units to the first computing unit. Therefore, before superimposing all the corresponding calculation results for the target signal transmission channel, the transmission delay effect calibration and deduction processing can also be performed on all the calculation results first, and then the processed results are superimposed to obtain the corresponding first-round superimposed calculation result. In addition, the first round can also be subdivided into the following A1 round and A2 round.

[0083] A1 round: Inside each of the meta-interconnection computing matrices, the fifth computing unit with the serial number sequence first obtains the signal data to be subjected to channel simulation calculation from the signal receiving channels communicatively connected to the fifth computing unit, and then for the target signal transmission channel, according to the signal data and the given channel parameters of each signal receiving channel in the signal receiving channels relative to the corresponding transmission channel, simulates and calculates a total of signal propagation processes of each signal receiving channel relative to the corresponding transmission channel.

[0084] In the A1 round, each of the meta-interconnection computing matrices contains the fifth computing units with the serial number sequence .

[0085] A2 round: Inside each of the meta-interconnection computing matrices, the first computing unit with the serial number sequence for the target signal transmission channel, respectively for all the The fifth computing unit and the corresponding The simulation calculation results of the signal propagation processes are subjected to transmission delay effect calibration and deduction processing, and the processing results are superimposed to obtain the corresponding first-round superimposed calculation results.

[0086] In the A2 round, the The simulation calculation results of the signal propagation processes are specifically transmitted at high speed through a high-speed serial connection between the fifth computing unit and the first computing unit (if the first computing unit is also the fifth computing unit at the same time, since the simulation calculation results of the signal propagation processes of this first computing unit are already local, there is no need to complete the high-speed transmission through the aforementioned high-speed serial connection).

[0087] Second round: Inside each of the meta-expansion interconnected computing matrices, the second computing unit with the serial number sequence For the target signal transmission channel, respectively, for all the computing units with the serial number sequence And the corresponding first-round superimposed calculation results are subjected to transmission delay effect calibration and deduction processing, and the processing results are superimposed to obtain the corresponding second-round superimposed calculation results.

[0088] In the second round, the first-round superimposed calculation results are specifically transmitted at high speed through a high-speed serial connection between the second computing unit and the first computing unit (if the second computing unit is also the first computing unit at the same time, since the first-round superimposed calculation results of this first computing unit are already local, there is no need to complete the high-speed transmission through the aforementioned high-speed serial connection). In addition, the specific process of the transmission delay effect calibration and deduction processing is prior art and will not be elaborated here.

[0089] The Round: Inside each of the meta-expansion interconnected computing matrices, the third computing unit with the serial number sequence For the target signal transmission channel, respectively, for all the computing units with the serial number sequence And the corresponding Round superimposed calculation results are subjected to transmission delay effect calibration and deduction processing, and the processing results are superimposed to obtain the corresponding Round superimposed calculation results.

[0090] In the Round, the transmission method of the Round superimposed calculation results is similar to that of the first-round superimposed calculation results and can be obtained by conventional derivation, which will not be elaborated here. ​

[0091] Round : The fourth computing unit with a numbered sequence performs transmission delay effect calibration deduction processing on all the computing units with a numbered sequence for the target signal transmission channel, and superimposes the processing results to obtain the corresponding output digital signal. In the

[0092] round, the transmission mode of the round superimposed calculation result is similar to that of the first round superimposed calculation result and can be conventionally deduced, so it will not be elaborated here.

[0093] Figure 11 For the convenience of explaining the calculation logic of the computing unit, here a 4 2 -element extended interconnected computing matrix and the (0, 0, 0) signal transmission channel are taken as an example. As Figure 11 shown, the calculation of its channel simulation is divided into two rounds:

[0094] In the first round, inside all four 4 - element interconnected computing matrices, the first computing unit with a numbered sequence (N2,0) first obtains the signal data to be subjected to channel simulation calculation from the 4×2 signal receiving channels that are communicatively connected to the first computing unit and 3 other computing units. Then, for the (0,0,0) signal transmission channel, according to the signal data and the given channel parameters of each signal receiving channel in the 4×2 signal receiving channels relative to the corresponding transmission channel, it simulates the 4×2 signal propagation processes of each signal receiving channel relative to the corresponding transmission channel, and superimposes the calculation results to obtain the corresponding first - round superimposed calculation result, where the value of N2 is 0, 1, 2, and 3 respectively, the value of N1 is 0, 1, 2, and 3 respectively, and J takes integer values (such as 0 and 1);

[0095] In the second round, the first computing unit with the serial number sequence (N2, 0) transmits the first-round superposition calculation result of the (0, 0, 0) signal transmission channel to the second computing unit with the serial number sequence (0, 0) through a high-speed serial connection (the above superposition calculation result of the first computing unit with the serial number sequence (0, 0) is local and does not need to be transmitted through the aforementioned high-speed serial connection). Then, the second computing unit calibrates and deducts the data transmission delay effect for the local superposition calculation result and the remote superposition calculation result of the (0, 0, 0) signal transmission channel (i.e., from the first computing units with the serial number sequences (1, 0), (2, 0), and (3, 0)), and then performs a superposition calculation on these four superposition calculation results again to obtain the calculation result of the final signal propagation process of the (0, 0, 0) signal transmission channel, and generates and sends the signal through the (0, 0, 0) signal transmission channel.

[0096] The same shall apply to all other channels.

[0097] When the extended interconnection computing matrix is further extended to elements, this calculation process is correspondingly divided into three rounds, that is, for any (n3, n2, n1, j) signal transmission channel:

[0098] In the first round, within all basic N1-element interconnection computing matrices, the first computing unit with the serial number sequence (N3, N2, n1) obtains the signal data required for channel simulation calculation from all N1×J signal receiving channels connected to itself and another N1 - 1 other computing units, and respectively simulates and calculates the total N1×J signal propagation processes of the (n3, n2, n1, j) signal transmission channel according to the signal data and the given channel parameters of each signal receiving channel relative to the (n3, n2, n1, j) signal transmission channel, and then performs a superposition calculation to obtain the first-round superposition calculation result of the (n3, n2, n1, j) signal transmission channel;

[0099] In the second round, within all basic N2×N1-element extended interconnection computing matrices, the second computing unit with the serial number sequence (N3, n2, n1) aggregates all the first-round superposition calculation results of the (n3, n2, n1, j) signal transmission channel through the high-speed serial connections between them, and after calibrating and deducting the data transmission delay effect, performs a superposition calculation on the above superposition calculation results again to obtain the second-round superposition calculation result of the (n3, n2, n1, j) signal transmission channel;

[0100] In the third round, the third computing unit with the serial number sequence (n3, n2, n1) aggregates all the second-round superposition calculation results of the (n3, n2, n1, j) signal transmission channels through high-speed serial connections between this computing unit and the second computing units with the serial number sequence (N3, n2, n1) in the other N3 - 1 N2×N1 element computing matrices. After calibrating and deducting the data transmission delay effect, the superposition calculation is performed again on the above superposition calculation results to obtain the calculation results of the final signal propagation process of the (n3, n2, n1, j) signal transmission channel, and the signal is sent out through the (n3, n2, n1, j) signal transmission channel.

[0101] The same shall apply to all other channels.

[0102] All The calculation method of all the N-element extended interconnected computing matrices can also be further extrapolated in this way. The calculation needs to be divided into rounds for execution.

[0103] In summary, adopting the channel simulation system provided by this embodiment has the following technical effects:

[0104] (1) This embodiment provides a large-bandwidth real-time channel simulation system that can be flexibly expanded, that is, it includes an N M -element extended interconnected computing matrix. By means of the connection relationships between the upper and lower extended interconnected computing matrix levels, between the extended interconnected computing matrix and the interconnected computing matrix, and between the computing units inside the interconnected computing matrix, computing arrays with different topological structures and different scales can be constructed. The more the number of array elements of the interconnected computing matrix and the more the number of extended interconnection levels, the larger the scale of the computing matrix, the greater the total computing power and storage space, the larger-scale channel simulation requirements can be met, the goal of adapting to different channel scales and instantaneous bandwidths can be achieved. Furthermore, users can easily customize the channel simulation system according to their own needs, and can gradually expand the product functions and channel scales through phased construction, reducing costs, increasing the product utilization rate, and solving the problems existing in existing medium and large-sized channel simulation instruments and equipment, such as fixed form, relatively single function, extremely high price, and difficulty in changing product characteristics, expanding product functions, and adjusting channel scales according to different user needs, which is convenient for practical application and promotion;

[0105] (2) Flexible expansion and splitting: The computing topological structure designed in this embodiment is applicable to channel simulation systems with several channels to several hundred channels. It can conveniently expand a small-scale channel simulation system into a large-scale system, and can also easily split a large-scale system into several small-scale systems;

[0106] (3) Large simulation bandwidth: The bandwidth that the channel simulation system can simulate mainly depends on the computing power and data access capabilities of a single computing unit. The computing topology designed in this embodiment can flexibly configure the ratio of the number of computing units and signal transceiver units (as well as the number of transceiver channel groups). Moreover, the signal transceiver unit can also provide additional computing power and data access capabilities support. Therefore, when increasing the ratio of computing units (the maximum can reach a 1:1 ratio of transceiver channel groups and computing units); current advanced FPGAs already have a computing power of more than 3 TOps. At a 1:1 ratio, that is, with 32 computing units plus extended computing units, a total computing power of more than 100 TOps can be provided. At an instantaneous bandwidth of 2 GHz, channel simulation with a total of 64 channels of 32T32R can also be achieved.

[0107] (4) Low computing latency: The hardware circuit characteristics of the FPGA itself have the feature of low computing latency. At the same time, the computing matrix topology designed in this embodiment enables data interaction between any two computing units to only pass through a very short data exchange path. Therefore, the entire computing matrix has the advantage of low computing latency.

[0108] (5) Low cost: Due to the standardization of computing units and the interconnected computing matrix, the construction and expansion of large-scale channel simulation systems no longer need to be customized, thus enabling low cost.

[0109] (6) Easy to develop: Since the computing topology designed in this embodiment is a completely symmetric structure, only the algorithm and program need to be designed for a single computing unit to complete the program design of the entire computing matrix.

[0110] (7) Customizable: The signal transceiver unit provides extended computing capabilities, and the implementation of this part of the computing power is completely decoupled from the computing matrix. Therefore, it is easy to provide customized signal processing capabilities for channel simulation port devices.

[0111] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A flexibly constructed and expandable channel simulation system, characterized in that: It includes a control computer and a signal propagation simulation computing body. Meta-extended interconnection computing matrix, wherein the Meta-Extended Interconnection Computing Matrix includes indivual Meta-Extended Interconnection Computing Matrix, the Meta-Extended Interconnection Computing Matrix includes indivual Meta-extended interconnected computing matrix, and so on Meta-Extended Interconnection Computing Matrix includes indivual Meta-extends the interconnected computing matrix until Meta-Extended Interconnection Computing Matrix includes indivual Meta-interconnection computing matrix, The Meta-interconnection Computing Matrix includes A computing unit, for The abbreviation of , wherein the calculation unit is used to perform a signal propagation simulation calculation on an input digital signal obtained by converting an input radio frequency signal to obtain an output digital signal for conversion into an output radio frequency signal, , , , and Respectively represent integers greater than or equal to 2, represents an integer greater than or equal to 2, exist Exists when greater than or equal to 3, and indicates greater than or equal to 0 and less than integer; In the Any two of the computing units are connected in communication; For any Each of the computing units in the element interconnection computing matrix enables the corresponding units to be respectively connected to Other The computing units in corresponding positions in the meta-interconnect computing matrix are connected in communication, wherein any one Meta-interconnection computing matrix and the Other The meta-interconnection computing matrix is ​​described Meta-extended interconnected computing matrix; For any Each of the computing units in the interconnected computing matrix is ​​extended so that the corresponding units are connected to each other in Other The computing units in corresponding positions in the meta-extension interconnection computing matrix are connected in communication, wherein any one Meta-Extended Interconnection Computing Matrix and the Other The meta-extension interconnection computing matrix is ​​described Meta-extended interconnected computing matrix; The control computers are respectively connected in communication with the The controlled end of each computing unit in the meta-extended interconnected computing matrix is ​​used to read and write parameters and / or data of the computing unit.

2. The channel simulation system as claimed in claim 1, characterized in that: The computing unit is communicatively connected to at least one signal transceiver unit; The signal transceiver unit is used to receive the input digital signal obtained by conversion based on the input radio frequency signal, and send the output digital signal for conversion into the output radio frequency signal; Alternatively, the signal transceiver unit is used to receive the input radio frequency signal and convert it into the input digital signal, and to convert the output digital signal into the output radio frequency signal and send it out.

3. The channel simulation system as claimed in claim 2, characterized in that: When the signal transceiver unit is used to receive the input RF signal and convert it into the input digital signal, and convert the output digital signal into the output RF signal and send it out, the signal transceiver unit includes an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module and a second high-speed serial interface, wherein the analog receiving front-end module is used to receive the input RF signal, the analog transmitting front-end module is used to send the output RF signal, and the second high-speed serial interface is used to communicate with the computing unit; The output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

4. The channel simulation system as claimed in claim 3, characterized in that: The signal transceiver unit also includes a clock and trigger signal interface, an onboard OCXO module and a clock generation and distribution circuit module based on a phase-locked loop mechanism, wherein the clock and trigger signal interface is used to receive an external sampling clock signal, a reference clock signal, a GPS second pulse signal and a trigger signal, and the onboard OCXO module is used to generate a time base signal; The trigger signal output end of the clock and trigger signal interface is communicatively connected to the second FPGA module, the non-trigger signal output end of the clock and trigger signal interface and the time base signal output end of the onboard OCXO module are respectively communicatively connected to the input end of the clock generation and distribution circuit module, and the clock signal output end of the clock generation and distribution circuit module is respectively communicatively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module.

5. The channel simulation system as claimed in claim 2, characterized in that: When the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively communicatively connected to the second FPGA module, the signal transceiver unit is also used as an extended computing unit relative to the computing unit, and is used to perform any one of the following extended computing tasks (A) to (I) or any combination thereof: (A) Using interpolation processing to increase the instantaneous bandwidth of the signal; (B) Using decimation to reduce the instantaneous bandwidth of the signal; (C) Using digital frequency conversion to change the center frequency of the signal; (D) Calculate the signal's spectrum in real time; (E) Real-time calculation of target echo or clutter; (F) Simulate the phase offset of the signal arriving at each port of the multi-channel direction finding receiver; (G) Simulating the signal amplitude and phase of each channel in the radar sum and difference channels; (H) Data transmission and reception via a high-speed serial bus; (I) Perform amplitude calibration and phase calibration of the transmit and receive signals.

6. The channel simulation system as claimed in claim 1, characterized in that: The signal propagation simulation calculation includes calculation of spatial fading, multipath effect, Doppler effect, time delay and / or interference superposition during the signal propagation process.

7. The channel simulation system as claimed in claim 1, characterized in that: Said The meta-extended interconnection computing matrix is ​​used to perform symmetric computation of channel simulation in the following manner: set up Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the The Meta-interconnection Computational Matrix is ​​described in Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates that the computing unit is in the Unique number in the meta-interconnection matrix and in the integer range In order to make Each of the computing units in the meta-extension interconnection computing matrix has a corresponding numbering sequence ; If in the Each of the computing units in the meta-extended interconnected computing matrix is ​​independently connected to each other in communication. For the signal receiving and sending channel, set Indicates that the signal receiving and sending channel is in A unique number in the signal receiving and sending channel and is in the integer range In order to make Each pair of signal transceiver channels in the signal transceiver channel has a corresponding number sequence ,in, represents a positive integer; For numbered sequences The target signal sending channel is calculated to obtain the corresponding output digital signal for conversion into the output RF signal, and the output digital signal is sent out through the corresponding channel, wherein, represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has The output digital signal is as follows The round step calculation yields: First round: In each of the The interior of the meta-interconnection computing matrix consists of a numbered sequence The first computing unit starts with the first computing unit and Other computing units communicate with each other The signal data to be channel simulated is obtained on a signal receiving channel, and then the target signal sending channel is calculated based on the signal data and the The given channel parameters of each signal receiving channel in the signal receiving channels relative to the corresponding transmitting channel are simulated and calculated. signal propagation process, and superimpose the calculation results to obtain the corresponding first round of superposition calculation results; Second round: In each of the The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The second computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence Performing a transmission delay effect calibration and deduction process on all the calculation units and the corresponding first round superposition calculation results, and superimposing the processing results to obtain the corresponding second round superposition calculation results; No. Wheel: In each The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The third computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The transmission delay effect calibration and deduction processing are performed on the results of the round superposition calculation, and the processing results are superimposed to obtain the corresponding Wheel superposition calculation results; No. Round: consists of a numbered sequence The fourth computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The round superposition calculation results are subjected to transmission delay effect calibration and subtraction processing, and the processing results are superimposed to obtain the corresponding output digital signal.

8. The channel simulation system as claimed in claim 1, characterized in that: The computing unit includes a first FPGA module, a first storage module and a first high-speed serial interface, wherein the first high-speed serial interface has at least one and is used for communication connection with a signal transceiver unit or other computing units; The first FPGA module is communicatively connected to the first storage module and the first high-speed serial interface respectively.

9. The channel simulation system as claimed in claim 8, characterized in that: The first storage module adopts dynamic random access memory, and the first high-speed serial interface adopts Nano-Pitch interface, MiniSAS HD interface, SFP interface, SFP+ interface, QSFP interface, QSFP+ interface, QSFP28 interface or QSFP56 interface.

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