A cross-chip routing method, device, equipment and storage medium

Abstract

The present invention discloses a cross-chip routing method, device, equipment and storage medium, including: updating an operation request according to the association information of a first port to obtain an update operation request; querying a configurable request routing table according to a target address to determine a second port in an inter-chip access network, and sending the update operation request to a target object matching the target address through the second port; obtaining a response generated by the target object, and querying a designated routing table according to dynamic identification information in the response to determine a response route. In the routing request phase, the configurable request routing table is queried according to the target address to determine the request routing information, and in the response phase, the response routing information is determined based on the dynamic identification information and the designated routing table, and cross-chip interconnection is achieved based on the request routing information and the response routing information, and the routing process does not require additional protocol development and additional hardware device support, thereby significantly simplifying the complexity of inter-chip access.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a cross-chip routing method, device, equipment and storage medium. Background Art

[0002] With the development of artificial intelligence, extremely high computing power and memory bandwidth are required when processing large-scale data sets and complex algorithms. A single chip or server can no longer meet the demand. At this time, it is necessary to build a computing group consisting of dozens or hundreds of nodes to meet the demand. A server and several or dozens of accelerator card chips are often required to be connected within a node. The accelerator card chips are interconnected at high speed through a specific protocol, thereby providing extremely high bandwidth and low latency within the node. Currently, the more common intra-node interconnection technologies include Compute Express Link (CXL) or the memory semantic interconnection protocol Gen-Z.

[0003] However, the node-to-node interconnection technologies currently used are relatively complex, usually requiring a lot of software work to support new protocols, and additional hardware devices such as switches are required to achieve routing communication between chips. Therefore, the existing node-to-node routing communication is relatively complex in system design and implementation. Summary of the invention

[0004] The present invention provides a cross-chip routing method to achieve cross-chip routing connection.

[0005] According to a first aspect of the present invention, there is provided a cross-chip routing method, comprising: receiving an operation request through a first port in an inter-chip access network of a current chip, wherein the operation request includes a target address and a transaction identifier;

[0006] The operation request is updated according to the association information of the first port to obtain an update operation request, wherein the update operation request includes dynamic identification information generated based on the transaction identifier;

[0007] querying a configurable request routing table according to the target address to determine a second port in the inter-chip access network, and sending the update operation request to a target object matching the target address through the second port;

[0008] Obtain a response generated by the target object, query a designated routing table according to the dynamic identification information in the response to determine a response route, and feed the response back to the source object through the response route, wherein the designated routing table includes a configurable response routing table, an inbound routing table, or a local routing table.

[0009] According to another aspect of the present invention, a cross-chip routing device is provided, comprising: an operation request receiving module, configured to receive an operation request through a first port in an inter-chip access network of a current chip, wherein the operation request includes a target address and a transaction identifier;

[0010] an operation request updating module, configured to update the operation request according to the associated information of the first port to obtain an update operation request, wherein the update operation request includes dynamic identification information generated based on the transaction identifier;

[0011] An update operation request sending module, configured to query a configurable request routing table according to the target address to determine a second port in the inter-chip access network, and send the update operation request to a target object matching the target address through the second port;

[0012] A response feedback module is used to obtain the response generated by the target object, query the specified routing table according to the dynamic identification information in the response to determine the response route, and feed back the response to the source object through the response route, wherein the specified routing table includes a configurable response routing table, an internal access routing table or a local routing table.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform the method described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method described in any embodiment of the present invention when executed.

[0018] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, and when the computer program is executed by a processor, the method described in any embodiment of the present invention is implemented.

[0019] The beneficial technical effect of the present invention is that in the routing request stage, the configurable request routing table is queried according to the target address to determine the request routing information, and in the response stage, the response routing information is determined based on the dynamic identification information and the specified routing table, and cross-chip interconnection is achieved based on the request routing information and the response routing information, and the routing process does not require additional protocol development and additional hardware device support, thereby significantly simplifying the complexity of inter-chip access.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flow chart of a cross-chip routing method provided according to the first embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of a chipset network structure provided according to Embodiment 1 of the present invention;

[0024] Figure 3 is a flow chart of a cross-chip routing method provided according to Embodiment 2 of the present invention;

[0025] Figure 4 is a schematic structural diagram of a cross-chip routing device provided according to Embodiment 3 of the present invention;

[0026] Figure 5 It is a schematic diagram of the structure of an electronic device provided by Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] Embodiment 1

[0030] Figure 1 A flowchart of a cross-chip routing method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of performing cross-chip routing between different chips. The method can be executed by a cross-chip routing device, which can be implemented in the form of hardware and / or software. Figure 1 As shown, the method includes:

[0031] Step S101: receiving an operation request through a first port in an inter-chip access network of a current chip.

[0032] Optionally, the current chip also includes an intra-chip access network, which communicates with the inter-chip access network through direct memory access DMA, wherein the number of first ports and second ports in the inter-chip access network is the same, and the first port includes an input port or a direct memory access DMA agent port, and the second port includes an output port or an internal access port.

[0033] Specifically, Figure 2The schematic diagram of the structure of the chip networking in this embodiment is shown. The networking structure includes three chips, namely Chip1, Chip2 and Chip3. Of course, this embodiment is only an example, and the number of chips included in the chip networking is not limited. Each chip must be divided into at least two subnets, namely the inter-chip access network and the intra-chip access network, and the two subnets are directly connected through the AXI protocol. In this embodiment, the routing delivery to the target object is completed through the target address in the operation request, and then the target object completes the local memory access or peripheral operation according to the target address in the operation request, and finally completes the routing return to the source object based on the dynamic identification information in the request. Among them, the inter-chip access network of each chip in the chip networking of this embodiment is only responsible for the information delivery within its own network, and the inter-chip access network of all chips in the node is only responsible for the information delivery within its own network. The chips in the node will be uniformly addressed to facilitate identification in the target address. For example, if the address within the chip is 32 bits and the node supports up to 64 chips for networking, the system must support 6+32=38 bits of address, among which the upper 6 bits of the address are used to resolve the target chip number, and the lower 32 bits of the address are the address for accessing the resources within the target chip. Because the requested address information will be transmitted continuously, each chip can complete the routing resolution accordingly.

[0034] Among them, in this implementation, the inter-chip access network of each chip includes a first port and a second port with the same number as the first port, wherein the first port includes an input port IN or a direct memory access (DMA) agent port MM, and the second port includes an output port OUT or an internal access port SS. For example, the inter-chip access network of Chip1 includes three input ports IN0, IN1 and IN2, two DMA agent ports MM0 and MM1, three output ports OUT0, OUT1 and OUT2, and two internal access ports SS0 and SS1. Of course, this implementation is only an example, and the type and quantity of the first port and the second port are not limited. As long as the quantity corresponds to each other and the routing connection between chips can be completed, it is within the protection scope of this application. In the inter-chip access network of the current chip, the operation request is specifically received through the first port. Taking the cross-chip write operation as an example, when the current chip is the source object Chip1, Chip1 generates an operation request after completing the transfer of internal data to DMA0, wherein the operation request includes the transaction identifier axiid, such as 4, and the operation request also includes the target address of the write object corresponding to the transferred data, and the target address includes the chip identification address bit and the chip internal address bit. When it is necessary to write to the second memory of Chip3, such as the target address addr can be 00001100...10, so for the source object Chip1, the operation request sent by DMA0 is received through the DMA proxy port, such as MMO. In addition, the operation request also includes the data transferred from Chip1. The specific content contained in the operation request is not limited in this embodiment.

[0035] In addition, when the current chip is a non-source object, the operation request is received through the input port. For example, for the networking intermediate chip Chip2, the operation request sent by Chip1 is received through IN0; for the target object Chip3, the operation request sent by Chip2 is received through IN2. Of course, this implementation does not limit the first port used by each chip to receive the operation request, which is specifically determined according to the chip connection relationship determined in the chip networking stage.

[0036] Step S102: updating the operation request according to the associated information of the first port to obtain an updated operation request.

[0037] Optionally, before updating the operation request according to the associated information of the first port to obtain the updated operation request, it also includes: when the current chip is a source object, obtaining the identifier of the source object and the identifier of the first port on the source object that receives the operation request, and using the identifier of the source object and the identifier of the first port as the associated information of the first port, wherein the first port includes a DMA proxy port; when the current chip is a non-source object, obtaining the identifier of the first port on the non-source object that receives the operation request, and using the identifier of the first port as the associated information of the first port, wherein the first port includes an input port, wherein the non-source object includes a target object or a networking intermediate chip.

[0038] Optionally, the operation request is updated according to the associated information of the first port to obtain an updated operation request, including: when the current chip is a source object, the identifier of the source object, the identifier of the DMA proxy port of the source object and the transaction identifier are concatenated to generate dynamic identification information, and an update operation request is generated according to the dynamic identification information and the target address; when the current chip is a non-source object, the dynamic identification information already in the operation request is updated according to the identifier of the input port to obtain updated dynamic identification information, and an update operation request is generated based on the updated dynamic identification information, wherein the updated dynamic identification information includes the identifier of the input port of the non-source object, the identifier of the source object, the identifier of the DMA proxy port of the source object and the transaction identifier.

[0039] Specifically, in this embodiment, after receiving the operation request through the first port, each chip will obtain the associated information of the first port, and update the received operation request according to the associated information of the first port to obtain an updated operation request. For example, when the current chip is the source object Chip1, since the operation request sent by the internal DMA0 is received through the first port MMO, the identification information of the first port is specifically the identification of the source object, represented by Src_chipid(6'h1), and the identification of the first port, represented by Mstid(1'b0), as the association information of the first port, and the association information of the first port is spliced ​​with the transaction identifier axiid to generate dynamic identification information, that is, the ID is {Src_chipid(6'h1), Mstid(1'b0), axiid}. Since the above three parameters are fixed, and the dynamic change of ID is mainly reflected in the fact that the input ports for subsequent chips to receive operation requests are different, it is necessary to add an identifier for the input port for non-source objects to receive operation requests in the ID information, represented by Inter_mstid(2'hx). Since the operation request for the source object does not involve the transmission of the input port, this parameter can be a fixed arbitrary value for the source object Chip1. After the source object Chip1 obtains the dynamic identification information, it combines the dynamic identification information ID with the target address and the transferred data to generate an update operation request. In addition, when the current chip is a non-source object Chip2, since the operation request sent by the source object Chip1 is received through the first port IN0, INO updates Inter_mstid in the dynamic identification information ID to Inter_mstid(2'h0), and the other three parameters in the ID remain unchanged, thereby obtaining the updated dynamic identification information ID as {Inter_mstid(2'h0), Src_chipid(6'h1), Mstid(1'b0), axiid}, and generates an update operation request based on the updated ID, that is, for IN0, only the ID has changed and the other contents in the request remain unchanged. When the current chip is a non-source object Chip3, since the operation request sent by the networking intermediate chip Chip2 is received through the first port IN2, the way IN2 updates the received operation request is roughly the same as IN0 in Chip2, so it is not limited in this embodiment.

[0040] It is worth mentioning that in this implementation mode, the parameter Inter-mstid in the ID changes dynamically, and other parameters remain unchanged in the request. When the request crosses different chips, the Inter-mstid will be replaced by the Inter-msterid of the chip at the IN port of each chip. As the MM port that initially generates the request, its Inter_mstid can be given a fixed arbitrary value. The Inter-mstid will only really play a role when the request is judged to have entered the target object according to the address. Therefore, the specific role of Inter-mstid will be specifically determined when the response route is determined later.

[0041] Step S103: query the configurable request routing table according to the target address to determine a second port in the inter-chip access network, and send the update operation request to the target object matching the target address through the second port.

[0042] Optionally, the target address includes a chip identification address bit and an internal chip address bit; querying a configurable request routing table according to the target address to determine a second port in the inter-chip access network includes: determining a number of the target object according to the chip identification address bit in the target address; querying a configurable request routing table according to the number to obtain second port routing information corresponding to the second port.

[0043] Among them, in this embodiment, after receiving the update operation request from the first port, the second port of each chip can send the update operation request to the input port IN of the target object directly or indirectly through the output port OUT according to the connection relationship configured when the chips are networked. However, for the inter-chip access network, the networking forms are diverse, and the connection conditions of the upstream and downstream of each chip inter-chip access network are different, which requires a configurable request routing table to support. The configurable request routing table is located on the first port of the inter-chip access network, for example, the DMA agent port MM or the input port IN. Therefore, after the first port obtains the update operation request, it can determine through which output port the update operation request is sent in the inter-chip access network by querying the configurable request routing table.

[0044] In a specific implementation, Figure 2Taking the structure of the chip network shown in the figure as an example, the connection between OUT1 of chip1 and chip2 is a form of networking. In actual networking, it may become that OUT2 of chip1 is connected to chip2. The routing information of OUT1 is "1" and the routing information of OUT2 is "2". The routing information of the target chip number = 2 in the configurable request routing table should be filled in according to the networking connection situation. If OUT1 of chip1 is not connected to chip2 but chip4, the routing information of the target chip number = 4 in the configurable request routing table should be filled in with "1". In the figure below, chip3 is not directly connected to chip1. Chip3 is connected after chip2. Therefore, when chip1 wants to access chip3 resources, the routing information of the target chip number = 3 in the configurable request routing table of chip1 should be filled in with the same information as the target chip number = 2. The following Table 1 shows an example of a configurable request routing table on the MMO port of Chip1:

[0045] Table 1

[0046]

[0047] Among them, when the MM0 port in Chip1 extracts the target address in the update operation request, such as "00001100...10", and extracts the chip identification address bits "000011" of the upper six bits in the target address, it is determined that the number of the target object corresponding to the upper six bits is 3, then the request routing information corresponding to the row numbered 3 in des_chipid in Table 1 is queried to determine the OUT1 port, so that the update operation request is delivered to OUT1. After receiving the update operation request, OUT1 transmits the operation request to the IN0 port on Chip2 according to the corresponding connection relationship when the chip is networked. Of course, this embodiment only takes the configurable request routing table on the MM0 port on CHIP1 as an example for explanation, and there is a corresponding configurable request routing table on each first port. This embodiment does not limit the content of the configurable request routing table on each first port.

[0048] Optionally, the method also includes: when the current chip determines that the number of the target object is the same as its own number, sending the update operation request to its own on-chip access network through the second port; determining the on-chip target resource in the on-chip access network according to the on-chip address bits, performing the request operation on the target resource based on the update operation request and generating a response, wherein the response includes dynamic identification information.

[0049] Specifically, the current chip updates the received operation request and obtains the number of the target object according to the update operation request. When it is determined that the number of the target object is 3, it is compared with its own number. When it is determined to be consistent, it means that the current chip is the target object, namely Chip3. At this time, the input port IN2 will determine the second port in the inter-chip access network according to its own configurable request routing table, such as SS0, and then send the update operation request to the intra-chip access network through SS0. At this time, the intra-chip access network will extract the chip address bits from the target address, such as the lower 32 bits "00...10", and determine the intra-chip target resource according to the lower 32 bits, namely the second main memory, and write the data moved from Chip1 in the update operation request into the second main memory. After the write operation is completed, the SS0 port will obtain a response from the intra-chip access network. At this time, the response includes dynamic identification information ID, and the ID includes inter_mstid(2'h2).

[0050] Step S104, obtaining a response generated by the target object, querying a designated routing table to determine a response route according to dynamic identification information in the response, and feeding back the response to the source object through the response route.

[0051] Optionally, the response route is determined by querying a designated routing table according to the dynamic identification information in the response, including: when the current chip is the target object, querying a pre-saved internal access routing table according to the identification of the input port, and obtaining a response route that matches the identification of the input port; when the current chip is a networking intermediate chip, querying a configurable response routing table according to the identification of the source object, and obtaining a response route that matches the identification of the source object; when the current chip is the source object, querying a local routing table according to the identification of the DMA proxy port of the source object, and obtaining a response route that matches the identification of the DMA proxy port of the source object.

[0052] Among them, the designated routing table includes a configurable response routing table, an internal access routing table or a local routing table. In this embodiment, when each chip determines the response route according to the dynamic identification information in the response, such as ID{Inter_mstid(2'h2), Src_chipid(6'h1), Mstid(1'b0), axiid}, it will extract different parameters in the dynamic identification information according to the type of the current chip, and query the corresponding type of routing table. For example, when the current chip is the target object, namely Chip3, the identifier Inter_mstid(2'h2) of the input port is extracted and the pre-saved internal access routing table is queried to obtain the response route, and the response is delivered to the IN2 port of Chip3. The input port of Chip3 in the response direction and the output port of the downstream Chip2 are connected through a physical link, so that the response reaches the intermediate chip or source object from the input port of Chip3; when the type of the current chip is the networking intermediate chip, namely Chip2, the identifier Src_chipid(6'h1) of the source object is extracted to query the configurable response routing table to obtain the response route, and the response is delivered to the OUT 1, and the configuration of the configurable response routing table is roughly the same as that of the configurable request routing table, the only difference is that the configurable request routing table uses the specified high bit in the target address, such as the chip identification address bit for indexing, while the configurable response routing table uses the source object identifier in the ID, such as Src_chipid for indexing; when the type of the current chip is the source object, i.e., Chip1, the identifier Mstid (1'b0) of the DMA proxy port of the source object is extracted and the pre-saved local routing table is queried to obtain the response route, and the response is delivered to the MM0 port of Chip1, and the MM0 port is connected to the direct memory access DMA0, so that the response is finally returned to DMA0, completing a write process. The internal access routing table and the local routing table are related to the topological structure of the inter-chip access network. When the hardware structure configuration is completed, the information of the internal access routing table and the local routing table is fixed. The generation process of the internal access routing table and the local routing table is not the focus of this application, so it will not be repeated in this embodiment. Of course, in this embodiment, only the cross-chip write operation is used as an example to illustrate the cross-chip routing method. The routing method for the cross-chip read operation is roughly the same and will not be repeated in this embodiment.

[0053] In a specific implementation, in this embodiment, Figure 2 Take steps 1 to 11 involved in the cross-shard write operation as an example to explain in detail:

[0054] Step 1: chip1 completes the transfer of internal data to DMA0.

[0055] Step 2: Generate inter-chip access AXI request and provide axiid.

[0056] Step 3: MM searches the configurable request routing table based on the high 6 bits of ADDR, i.e. des_chipid(6), to complete the delivery to chip1OUT1, and combines to generate the ID information {inter_mstid(2'hx), src_chipid(6'h1), mstid(1'b0), axiid}

[0057] Step 4: Chip2's IN0 port uses the high 6 bits of the ADDR of the received request, i.e. des_chipid(6), to configure the request routing table to complete the delivery to chip2 OUT1 and replace the ID information {inter_mstid(2'h0), src_chipid(6'h1), mstid(1'b0), axiid}

[0058] Step 5: Chip3's IN2 port completes the delivery to chip3 SS0 based on the high 6 bits of ADDR of the received request, i.e. des_chipid(6), and replaces the ID information {inter_mstid(2'h2), src_chipid(6'h1), mstid(1'b0), axiid}

[0059] Step 6: Chip3's on-chip access network M3 completes the delivery of the request to the on-chip resources based on the ADDR low bit of the received request.

[0060] Step 7: Chip3's on-chip resources complete the operation and return the response to M3. M3 is directly connected to SS0, and the response reaches the target chip's inter-chip access network.

[0061] Step 8: Chip3's SS0 port searches the "internal access routing table" based on the inter_mstid (2'h2) information carried in the response to complete the delivery of the response to chip3's IN2 port. IN2 is directly connected to chip2's OUT1, so the response reaches chip2.

[0062] Step 9: Chip2's OUT1 determines that the response target is not itself based on the src_chipid information carried in the response, and then uses the src_chipid information to find the configurable response routing table to complete the delivery of the response to chip2's IN0 port. The response arrives at chip1's OUT1.

[0063] Step 10: Chip1's OUT1 port determines that the response target is itself based on the src_chipid information carried in the response, and then uses mstid to search the "local routing table" to complete the delivery of the response to chip1 MM0.

[0064] Step 11: Chip1 MM0 removes the inter_mstid, src_chipid, and mstid information in the response and only returns the axiid and other response information to the master. A cross-chip access transaction is completed.

[0065] In the implementation manner of the present application, in the routing request stage, the configurable request routing table is queried according to the target address to determine the request routing information, and in the response stage, the response routing information is determined based on the dynamic identification information and the specified routing table, and cross-chip interconnection is achieved based on the request routing information and the response routing information, and the routing process does not require additional protocol development and additional hardware device support, thereby significantly simplifying the complexity of inter-chip access.

[0066] Embodiment 2

[0067] Figure 3 A flowchart of a cross-chip routing method provided in Embodiment 2 of the present invention. This embodiment is based on the above embodiment. Before receiving an operation request through a first port in an inter-chip access network of a current chip, the method further includes: when the current chip is powered on and loaded, obtaining a configurable request routing table and a configurable response routing table generated when the chips are networked; saving the configurable request routing table to a first port of the inter-chip access network, and saving the configurable response routing table to a second port of the inter-chip access network. The method includes:

[0068] Step S201, when the current chip is powered on and loaded, a configurable request routing table and a configurable response routing table generated when the chips are networked are obtained.

[0069] Specifically, in the present embodiment, during the chipset networking stage, a configurable request routing table and a configurable response routing table can be generated according to the interconnection mode of the inter-chip access network of each chip, and the corresponding relationship between the chip identification address bit in the destination address and the request route is saved in the configurable request routing table, and the request route of each chip in the inter-chip access network can be determined through the configurable request routing table. Similarly, the corresponding relationship between the source object identification and the response route is saved in the configurable response routing table, and the response route of each chip in the inter-chip access network can be determined through the configurable response routing table.

[0070] It should be noted that, in this embodiment, for the same chip, when it is determined that it includes multiple first ports and second ports, a corresponding configurable request routing table will be generated for each first port, and a configurable response routing table will be generated for each second port. In this embodiment, the number of configuration request routing tables and configurable response routing tables corresponding to each chip is not limited.

[0071] Step S202: Save the configurable request routing table to a first port of the inter-chip access network, and save the configurable response routing table to a second port of the inter-chip access network.

[0072] Specifically, in this embodiment, after obtaining the configuration request routing table corresponding to each first port and the configurable response routing table corresponding to the second port, the configurable request routing table matching itself is saved in each first port of each chip, and the configurable response routing table matching itself is saved in each second port of each chip. This embodiment does not limit the specific contents of the configurable request routing table saved in each first port and the configurable response routing table saved in each second port.

[0073] Step S203: receiving an operation request through a first port in the inter-chip access network of the current chip.

[0074] Optionally, the current chip also includes an intra-chip access network, which communicates with the inter-chip access network through direct memory access DMA, wherein the number of first ports and second ports in the inter-chip access network is the same, and the first port includes an input port or a direct memory access DMA agent port, and the second port includes an output port or an internal access port.

[0075] Step S204: updating the operation request according to the associated information of the first port to obtain an updated operation request.

[0076] Optionally, before updating the operation request according to the associated information of the first port to obtain the updated operation request, it also includes: when the current chip is a source object, obtaining the identifier of the source object and the identifier of the first port on the source object that receives the operation request, and using the identifier of the source object and the identifier of the first port as the associated information of the first port, wherein the first port includes a DMA proxy port; when the current chip is a non-source object, obtaining the identifier of the first port on the non-source object that receives the operation request, and using the identifier of the first port as the associated information of the first port, wherein the first port includes an input port, wherein the non-source object includes a target object or a networking intermediate chip.

[0077] Optionally, the operation request is updated according to the associated information of the first port to obtain an updated operation request, including: when the current chip is a source object, the identifier of the source object, the identifier of the DMA proxy port of the source object and the transaction identifier are concatenated to generate dynamic identification information, and an update operation request is generated according to the dynamic identification information and the target address; when the current chip is a non-source object, the dynamic identification information already in the operation request is updated according to the identifier of the input port to obtain updated dynamic identification information, and an update operation request is generated based on the updated dynamic identification information, wherein the updated dynamic identification information includes the identifier of the input port of the non-source object, the identifier of the source object, the identifier of the DMA proxy port of the source object and the transaction identifier.

[0078] Step S205 , querying the configurable request routing table according to the target address to determine a second port in the inter-chip access network, and sending the update operation request to the target object matching the target address through the second port.

[0079] Optionally, the target address includes a chip identification address bit and an internal chip address bit; querying a configurable request routing table according to the target address to determine a second port in the inter-chip access network includes: determining a number of the target object according to the chip identification address bit in the target address; querying a configurable request routing table according to the number to obtain second port routing information corresponding to the second port.

[0080] Optionally, the method also includes: when the current chip determines that the number of the target object is the same as its own number, sending the update operation request to its own on-chip access network through the second port; determining the on-chip target resource in the on-chip access network according to the on-chip address bits, performing the request operation on the target resource based on the update operation request and generating a response, wherein the response includes dynamic identification information.

[0081] Step S206, obtaining the response generated by the target object, querying the designated routing table according to the dynamic identification information in the response to determine the response route, and feeding back the response to the source object through the response route.

[0082] Optionally, the response route is determined by querying a designated routing table according to the dynamic identification information in the response, including: when the current chip is the target object, querying a pre-saved internal access routing table according to the identification of the input port, and obtaining a response route that matches the identification of the input port; when the current chip is a networking intermediate chip, querying a configurable response routing table according to the identification of the source object, and obtaining a response route that matches the identification of the source object; when the current chip is the source object, querying a local routing table according to the identification of the DMA proxy port of the source object, and obtaining a response route that matches the identification of the DMA proxy port of the source object.

[0083] In the implementation manner of the present application, in the routing request stage, the configurable request routing table is queried according to the target address to determine the request routing information, and in the response stage, the response routing information is determined based on the dynamic identification information and the specified routing table, and cross-chip interconnection is achieved based on the request routing information and the response routing information, and the routing process does not require additional protocol development and additional hardware device support, thereby significantly simplifying the complexity of inter-chip access.

[0084] Embodiment 3

[0085] Figure 4 This is a schematic diagram of the structure of a cross-chip routing device provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes: an operation request receiving module 310, an operation request updating module 320, an update operation request sending module 330 and a response feedback module 340.

[0086] The operation request receiving module 310 is used to receive an operation request through a first port in an inter-chip access network of the current chip, wherein the operation request includes a target address and a transaction identifier;

[0087] An operation request updating module 320, configured to update the operation request according to the associated information of the first port to obtain an updated operation request, wherein the updated operation request includes dynamic identification information generated based on the transaction identifier;

[0088] An update operation request sending module 330 is used to query the configurable request routing table according to the target address to determine the second port in the inter-chip access network, and send the update operation request to the target object matching the target address through the second port;

[0089] The response feedback module 340 is used to obtain the response generated by the target object, query the specified routing table according to the dynamic identification information in the response to determine the response route, and feed back the response to the source object through the response route, wherein the specified routing table includes a configurable response routing table, an internal access routing table or a local routing table.

[0090] Optionally, the current chip also includes an intra-chip access network, which communicates with the inter-chip access network via direct memory access DMA.

[0091] The number of first ports and second ports in the inter-chip access network is the same, and the first ports include input ports or direct memory access DMA agent ports, and the second ports include output ports or internal access ports.

[0092] Optionally, the device further comprises a routing table storage module, which is used to obtain a configurable request routing table and a configurable response routing table generated when the chips are networked when the chips are powered on and loaded;

[0093] A configurable request routing table is saved to a first port of the inter-chip access network, and a configurable response routing table is saved to a second port of the inter-chip access network.

[0094] Optionally, the device further includes a first port associated information acquisition module, which is used to, when the current chip is a source object, acquire an identifier of the source object and an identifier of a first port on the source object that receives the operation request, and use the identifier of the source object and the identifier of the first port as the associated information of the first port, wherein the first port includes a DMA proxy port;

[0095] When the current chip is a non-source object, the identifier of the first port receiving the operation request on the non-source object is obtained, and the identifier of the first port is used as the association information of the first port, wherein the first port includes an input port, and wherein the non-source object includes a target object or a networking intermediate chip.

[0096] Optionally, an operation request update module is used to, when the current chip is a source object, concatenate the source object identifier, the source object DMA proxy port identifier and the transaction identifier to generate dynamic identification information, and generate an update operation request according to the dynamic identification information and the target address;

[0097] When the current chip is a non-source object, the existing dynamic identification information in the operation request is updated according to the identification of the input port to obtain the updated dynamic identification information, and an update operation request is generated based on the updated dynamic identification information, wherein the updated dynamic identification information includes the identification of the input port of the non-source object, the identification of the source object, the identification of the DMA agent port of the source object and the transaction identifier.

[0098] Optionally, the target address includes a chip identification address bit and a chip internal address bit; the update operation request sending module is further used to determine the number of the target object according to the chip identification address bit in the target address;

[0099] The configurable request routing table is queried according to the number to obtain second port routing information corresponding to the second port.

[0100] Optionally, the device further comprises a response generation module, which is used to send the update operation request to its own on-chip access network through the second port when the current chip determines that the number of the target object is the same as its own number;

[0101] In the on-chip access network, an on-chip target resource is determined according to the on-chip address bit, and a request operation is performed on the target resource based on the update operation request and a response is generated, wherein the response includes dynamic identification information.

[0102] Optionally, the response feedback module is further used to query a pre-stored internal access routing table according to the identifier of the input port when the current chip is the target object, and obtain a response route matching the identifier of the input port;

[0103] When the current chip is a networking intermediate chip, a configurable response routing table is queried according to the identifier of the source object to obtain a response route matching the identifier of the source object;

[0104] When the current chip is the source object, the local routing table is queried according to the identifier of the DMA proxy port of the source object to obtain a response route matching the identifier of the DMA proxy port of the source object.

[0105] The cross-chip routing device provided in the embodiment of the present invention can execute the cross-chip routing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0106] Embodiment 4

[0107] Figure 5 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0108] like Figure 5 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0109] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0110] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a cross-chip routing method.

[0111] In some embodiments, the routing method applied to cross-chips may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the cross-chip routing method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the cross-chip routing method in any other appropriate manner (e.g., by means of firmware).

[0112] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0113] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0114] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0115] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0116] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0117] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0118] Embodiment 5

[0119] An embodiment of the present invention further provides a computer program product, including a computer program, which, when executed by a processor, implements the cross-chip routing method provided in any embodiment of the present application.

[0120] In the process of implementation, the computer program product can be written in one or more programming languages ​​or a combination thereof to perform the computer program code of the present invention, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0121] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned, and they should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0122] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A cross-chip routing method, characterized in that: include: Receiving an operation request through a first port in an inter-chip access network of a current chip, wherein the operation request includes a target address and a transaction identifier; The operation request is updated according to the association information of the first port to obtain an update operation request, wherein the update operation request includes dynamic identification information generated based on the transaction identifier; querying a configurable request routing table according to the target address to determine a second port in the inter-chip access network, and sending the update operation request to a target object matching the target address through the second port; Obtain a response generated by the target object, query a designated routing table according to the dynamic identification information in the response to determine a response route, and feed the response back to the source object through the response route, wherein the designated routing table includes a configurable response routing table, an inbound routing table, or a local routing table.

2. The method according to claim 1, characterized in that The current chip also includes an intra-chip access network, and the intra-chip access network communicates with the inter-chip access network via direct memory access DMA. The number of the first ports and the second ports in the inter-chip access network is the same, and the first ports include input ports or direct memory access DMA agent ports, and the second ports include output ports or internal access ports.

3. The method according to claim 1, characterized in that Before receiving the operation request through the first port in the inter-chip access network of the current chip, the method further includes: When the current chip is powered on and loaded, the configurable request routing table and the configurable response routing table generated when the chips are networked are acquired; The configurable request routing table is saved to the first port of the inter-chip access network, and the configurable response routing table is saved to the second port of the inter-chip access network.

4. The method according to claim 1, characterized in that: Before updating the operation request according to the association information of the first port to obtain the update operation request, the method further includes: When the current chip is a source object, obtaining an identifier of the source object and an identifier of the first port on the source object that receives the operation request, and using the identifier of the source object and the identifier of the first port as association information of the first port, wherein the first port includes a DMA proxy port; When the current chip is a non-source object, the identifier of the first port on the non-source object that receives the operation request is obtained, and the identifier of the first port is used as the associated information of the first port, wherein the first port includes an input port, and wherein the non-source object includes a target object or a networking intermediate chip.

5. The method according to claim 4, characterized in that The updating of the operation request according to the association information of the first port to obtain the updated operation request includes: When the current chip is a source object, concatenating an identifier of the source object, an identifier of a DMA proxy port of the source object and the transaction identifier to generate the dynamic identification information, and generating the update operation request according to the dynamic identification information and the target address; When the current chip is a non-source object, the existing dynamic identification information in the operation request is updated according to the identification of the input port to obtain updated dynamic identification information, and the update operation request is generated based on the updated dynamic identification information, wherein the updated dynamic identification information includes the identification of the input port of the non-source object, the identification of the source object, the identification of the DMA agent port of the source object and the transaction identifier.

6. The method according to claim 1, characterized in that The target address includes a chip identification address bit and a chip internal address bit; The step of querying a configurable request routing table according to the target address to determine the second port in the inter-chip access network includes: Determine the serial number of the target object according to the chip identification address bit in the target address; The configurable request routing table is queried according to the number to obtain the second port routing information corresponding to the second port.

7. The method according to claim 6, characterized in that The method further comprises: When the current chip determines that the number of the target object is the same as its own number, sending the update operation request to its own on-chip access network through the second port; In the on-chip access network, an on-chip target resource is determined according to the on-chip address bit, and a request operation is performed on the target resource based on the update operation request and the response is generated, wherein the response includes the dynamic identification information.

8. The method according to claim 5, characterized in that The step of querying a designated routing table according to the dynamic identification information in the response to determine the response route includes: When the current chip is the target object, querying a pre-stored inbound routing table according to the identifier of the input port to obtain the response route matching the identifier of the input port; When the current chip is a networking intermediate chip, querying the configurable response routing table according to the identifier of the source object to obtain the response route matching the identifier of the source object; When the current chip is a source object, the local routing table is queried according to the identifier of the DMA proxy port of the source object to obtain the response route matching the identifier of the DMA proxy port of the source object.

9. A cross-chip routing device, characterized in that: The device comprises: An operation request receiving module, configured to receive an operation request through a first port in an inter-chip access network of a current chip, wherein the operation request includes a target address and a transaction identifier; an operation request updating module, configured to update the operation request according to the associated information of the first port to obtain an update operation request, wherein the update operation request includes dynamic identification information generated based on the transaction identifier; An update operation request sending module, configured to query a configurable request routing table according to the target address to determine a second port in the inter-chip access network, and send the update operation request to a target object matching the target address through the second port; A response feedback module is used to obtain the response generated by the target object, query the specified routing table according to the dynamic identification information in the response to determine the response route, and feed back the response to the source object through the response route, wherein the specified routing table includes a configurable response routing table, an internal access routing table or a local routing table.

10. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method according to any one of claims 1 to 8 when executed.

12. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 8 when being executed by a processor.

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