Video monitoring network and recording system based on ARINC818

Abstract

The invention belongs to the technical field of video monitoring networks and recording, and particularly relates to a video monitoring network and recording system based on ARINC818. Through the array design of hardware units, the software modularization and the plug and play design, the flexibility and the expandability of the ARINC818 video monitoring network are improved; the method comprises the following steps: constructing a data format, adaptively processing a video and displaying ARINC818 videos in different formats; by adding an SOC (System On Chip) array, the coding and decoding capability of a system video is provided, and a data storage array is provided for capacity expansion and storage.

Description

Technical Field

[0001] The invention belongs to the field of video surveillance network and recording technology, and in particular relates to a video surveillance network and recording system based on ARINC818. Background Art

[0002] At present, the video resolution and frame rate in the field of airborne video are constantly improving. Combined with the influence of the complex electromagnetic environment on board, more and more airborne equipment such as optoelectronic turrets, radars, reconnaissance pods, vision enhancement systems, and displays are using the ARINC818 video protocol.

[0003] However, the existing ARINC818 video transmission systems are all point-to-point transmission, which seriously restricts the increase and decrease of video nodes, cannot realize video network transmission, cannot meet the dynamic video scheduling requirements, and the system has no scalability and plug-and-play performance. In addition, due to the complexity and diversity of airborne equipment, its ARINC818 video also has a variety of video formats such as different resolutions and different frame rates. The existing system cannot meet the adaptive ARINC818 video processing. In addition, video surveillance has high-value picture content, and the existing system does not record and store the video network and perform online playback. Since the video end nodes are scattered in different locations, there is no unified way to upgrade and maintain, and the system maintainability is poor. Summary of the invention

[0004] In view of this, the present invention provides a video surveillance network and recording system based on ARINC818, which improves the flexibility and scalability of the ARINC818 video surveillance network through the array design of hardware units, software modularization, and plug-and-play design; through the construction of data formats, video adaptive processing and display of ARINC818 videos in different formats; by adding a SOC (system-on-chip) array, the system video encoding and decoding capabilities are provided, and a data storage array is provided for expanded storage.

[0005] The technical solution of the present invention is:

[0006] A video surveillance network and recording system based on ARINC818, the system comprising:

[0007] The photoelectric conversion module receives the optical signal of the ARINC818 video and converts it into an electrical signal, and is provided with multiple optical fiber receiving MPO / MT interfaces and multiple ARINC818 electrical signal output interfaces;

[0008] A video scheduling management array, communicating with the photoelectric conversion module, includes a plurality of logic management units, the number of which is expanded based on the number of video channels to be processed;

[0009] A video codec array, communicating with the video scheduling management array, includes a plurality of video codec units, for compressing and encoding the video signal output by the video scheduling management array, and writing the encoded video into a data storage unit via a PCIe bus; the number of the video codec units is expanded based on the number of video paths to be processed;

[0010] A data storage array, communicating with the video codec array, comprising a plurality of data storage units for recording video data into a storage disk; the number of the data storage units is expanded based on the size of the video data;

[0011] Wherein: the video encoding and decoding unit is configured to read the specified video segment in the data storage unit according to the instruction, decode and play it back, and send it to the logic management unit for processing and display.

[0012] The video scheduling management array is configured with a video scheduling management unit;

[0013] The video scheduling management unit is logically provided with multiple interface control units, and a detection module is provided in the interface control unit. When the detection module detects that the logic management unit is connected, the corresponding module control is activated, and the video scheduling logic is started;

[0014] The video scheduling logic collects the number of video channels received by the logic management unit, and after statistics, dynamically allocates them according to the existing FPGA video interface resources in the frequency scheduling management array to ensure that each FPGA can process the assigned video and leave a load margin; if the hardware resources are insufficient, the video scheduling logic will report the corresponding resource-deficient module information to the display console.

[0015] Furthermore, the video scheduling management unit is also used for dynamic resource allocation of the video encoding and decoding array and the data storage array and reporting of insufficient resource information.

[0016] Furthermore, the display console sends its own parameters to the video scheduling management array through the control bus. The video scheduling management array configures the video output interface according to the parameters of the display console and converts the video signal into the format required by the display console for output.

[0017] Furthermore, after receiving the video signal, the video scheduling management array parses the video frame header, obtains the video resolution and frame rate format parameters after parsing, and then adaptively configures the video receiving interface in the video scheduling management array to support the video scheduling management array to normally receive the video signal.

[0018] Furthermore, the logic management unit includes at least one FPGA and one DDR; used to complete high-speed serial data transceiver, ARINC818 bus data generation or analysis, and video data processing functions;

[0019] When the video processing resources are insufficient, the integrated logic management unit is connected to the video scheduling management array.

[0020] Furthermore, the photoelectric conversion module receives ARINC818 video output by various onboard devices, the medium being light, converts the video into an electrical signal, and transmits it to a video scheduling management array. The video scheduling management array can output the designated video to the corresponding display console according to the display console instructions; the video scheduling management array is configured to combine and splice the input videos and output them to the display console. For videos that need to be recorded, the videos are transmitted to a video codec array, compressed through video coding, and stored in a data storage array; the video scheduling management array is configured to decode and display the stored videos according to the online playback instructions of the display console.

[0021] Furthermore, the video scheduling management array includes multiple logic management units, each of which includes a set of programmable logic devices and a corresponding number of double-rate synchronous dynamic random access memories; each logic management unit supports at least 20-channel ARINC818 video processing, and the video scheduling management array is configured to expand its video processing capabilities according to the number required by the video network.

[0022] Furthermore, the logic management unit is used to complete high-speed serial data transmission and reception, ARINC818 bus data generation or analysis, and video data processing.

[0023] Furthermore, the video codec unit supports H.264 and H.265 encoding formats, and writes the encoded video to the data storage unit through the PCIe bus; it can also read the specified video clips inside the data storage unit for decoding and playback according to instructions, and send them to the logic management unit for processing and display.

[0024] Furthermore, the data storage unit is a high-speed NVME storage; a plurality of data storage units form a data storage array to expand the storage capacity;

[0025] The data storage unit contains:

[0026] NVMe protocol controller, used to support data interaction between the chip front-end interface and the PCIe NVMe host;

[0027] The flash memory controller interface module implements the interface function with the back-end, controls the interface timing of the Flash storage chip, and implements the access of the end-user data and system data in the flash memory particles. It has a low-density parity check code LDPC encoding and decoding module inside, which implements the real-time encoding when writing Flash data and the decoding function when reading Flash data and supports soft and hard judgment;

[0028] DDR controller, which realizes data interaction with external DDR4 / DDR3 / LPDDR3 chips. The internal module reads and writes to the external DDR4 / DDR3 / LPDDR3 through DDRController, expanding the internal RAM space;

[0029] On-chip memory is an internal shared storage space shared by all sub-modules;

[0030] One-time programmable module, responsible for storing some key data and some factory setting information, and can lock the logical and physical interface according to the configuration;

[0031] DMA: used to move data between two data buses, equipped with data comparison, search and alignment functions;

[0032] Redundant Array of Independent Disks support module, providing RAID-level data protection in addition to LDPC protection.

[0033] Compared with the prior art, the advantages of the present invention are:

[0034] (1) The system provided by the present invention can realize the transmission of video network, can meet the requirements of dynamic video scheduling, has good system scalability, and is plug-and-play for video;

[0035] (2) The logic management unit implements the data organization format required by the ARINC818 protocol, is compatible with special color depths, encoding methods, etc., and can configure the input video format to support video resolution and frame rate adaptation;

[0036] (3) The video codec unit implements video compression encoding and supports mainstream encoding formats such as H.264 and H.265. The encoded video is written into the data storage unit through the PCIe bus to realize video storage, and the recorded and stored images can be played back online through decoding;

[0037] (4) The MicroBlaze processor soft core embedded in the FPGA is used to distribute and upgrade the software of the video end node equipment through the network bus. This upgrade method can upgrade at least 20 end nodes at the same time, improving the upgrade efficiency of the video network. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1: Schematic diagram of a video surveillance network and recording system based on ARINC818 in a specific implementation manner of the present invention;

[0040] Figure 2 : A schematic diagram of a method for generating or parsing ARINC818 bus data in a specific embodiment of the present invention;

[0041] Figure 3 : A schematic diagram of an ARINC818 logic control method in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0042] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0043] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0044] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0045] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0046] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0047] In one embodiment of the present invention, a video surveillance network and recording system based on ARINC818 is proposed, the system comprising:

[0048] The photoelectric conversion module receives the optical signal of the ARINC818 video and converts it into an electrical signal, and is provided with multiple optical fiber receiving MPO / MT interfaces and multiple ARINC818 electrical signal output interfaces;

[0049] A video scheduling management array, communicating with the photoelectric conversion module, includes a plurality of logic management units, the number of which is expanded based on the number of video channels to be processed;

[0050] A video codec array, communicating with the video scheduling management array, includes a plurality of video codec units, for compressing and encoding the video signal output by the video scheduling management array, and writing the encoded video into a data storage unit via a PCIe bus; the number of the video codec units is expanded based on the number of video paths to be processed;

[0051] A data storage array, communicating with the video codec array, comprising a plurality of data storage units for recording video data into a storage disk; the number of the data storage units is expanded based on the size of the video data;

[0052] Wherein: the video encoding and decoding unit is configured to read the specified video segment in the data storage unit according to the instruction, decode and play it back, and send it to the logic management unit for processing and display.

[0053] The video scheduling management array is configured with a video scheduling management unit;

[0054] The video scheduling management unit is logically provided with multiple interface control units, and a detection module is provided in the interface control unit. When the detection module detects that the logic management unit is connected, the corresponding module control is activated, and the video scheduling logic is started;

[0055] The video scheduling logic collects the number of video channels received by the logic management unit, and after statistics, dynamically allocates them according to the existing FPGA video interface resources in the frequency scheduling management array to ensure that each FPGA can process the assigned video and leave a load margin; if the hardware resources are insufficient, the video scheduling logic will report the corresponding resource-deficient module information to the display console.

[0056] In this embodiment, the video scheduling management unit is also used for dynamic resource allocation of the video codec array and the data storage array and reporting of insufficient resource information.

[0057] In this embodiment, the display console sends its own parameters to the video scheduling management array through the control bus. The video scheduling management array configures the video output interface according to the parameters of the display console and converts the video signal into the format required by the display console for output.

[0058] In this embodiment, after receiving the video signal, the video scheduling management array parses the video frame header, obtains the video resolution and frame rate format parameters after the analysis, and then adaptively configures the video receiving interface in the video scheduling management array to support the video scheduling management array to normally receive the video signal.

[0059] In this embodiment, the logic management unit includes at least one FPGA and one DDR; used to complete high-speed serial data transmission and reception, ARINC818 bus data generation or analysis, and video data processing functions;

[0060] When the video processing resources are insufficient, the integrated logic management unit is connected to the video scheduling management array.

[0061] The present embodiment provides a video surveillance network and recording system based on ARINC818, the purpose of which is to improve the flexibility and scalability of the ARINC818 video surveillance network through the array design of hardware units, software modularization, and plug-and-play design; through the construction of data formats, video adaptive processing and display of ARINC818 videos in different formats; by adding a SOC (system-on-chip) array, providing system video encoding and decoding capabilities, and providing a data storage array for expanded storage.

[0062] For better explanation, but not as a limitation of the present invention, a specific description is given below with reference to the accompanying drawings.

[0063] like Figure 1 As shown, the video surveillance network and recording system of this embodiment includes an optoelectronic conversion module, a video scheduling management array, a video codec array and a data storage array. Among them, the optoelectronic conversion module receives the ARINC818 video output by each onboard device, the medium is light, converts the video into an electrical signal, and transmits it to the video scheduling management array. The video scheduling management array can output the designated video to the corresponding display console according to the display console instruction. In addition, the video scheduling management array can also combine and splice the input video and output it to the display console. For the video that needs to be recorded, the video can be transmitted to the video codec array, compressed by video coding, and stored in the data storage array. It can also decode the stored video and display it according to the online playback instruction of the display console.

[0064] More specifically, the photoelectric conversion module can be composed of one or more military photoelectric conversion module devices, and the number of photoelectric conversion module devices can be determined according to the input ARINC818 video 1 (optical), ARINC818 video 2 (optical) ... ARINC818 video N (optical). The photoelectric conversion module has an operating wavelength of 850nm, can receive multiple ARINC818 videos in parallel, and has an optical interface with a pigtail MPO / MT interface, can operate within a wide operating temperature range, and has a transmission speed of not less than 4.25Gbps. The photoelectric conversion module converts the ARINC818 video optical medium into an ARINC818 video electrical signal output. The ARINC818 video electrical signal is transmitted to the FPGA in the logic management unit.

[0065] More specifically, the video scheduling management array includes multiple logic management units, each of which contains a set of programmable logic devices (FPGA) and corresponding double-rate synchronous dynamic random access memory (DDR). Each logic management unit supports at least 20-channel ARINC818 video processing. The logic management unit uses a programmable logic device (FPGA) and a corresponding double-rate synchronous dynamic random access memory (DDR) to form a core processing unit, which is responsible for completing high-speed serial data reception and transmission, ARINC818 bus data generation or analysis, video data processing and other functions.

[0066] Furthermore, if Figure 2 As shown in the figure, the ARINC818 protocol defines that one image data uses one container, and each container contains different frame types and numbers. The segmentation of all ADVB frames follows the segmentation rules of Object 0 and Object 2: a) Single video stream (single container); b) Obj0 frame: the first frame in each container, which is transmitted first; c) Obj2 frame: there are 2 Obj2 frames with the number of video row pixels * 2; d) All Obj2 ADVB frames, each frame should contain 1 / 2 line of video data.

[0067] Furthermore, if Figure 3 As shown, the MicroBlaze Block Design in the logic management unit provides resources such as clock signals and multiple reset signals, DDR data read and write interfaces required for logic operation; the video reception starts receiving video data based on the synchronization signal, and processes and converts the video data stream; the data buffer control controls DMA through the AXI Lite bus, controls the video data stream to be written into and read out of the DDR buffer space according to the AXI bus format, and processes the video content according to the predetermined algorithm; the ARINC818 sending control unit packages the video data according to the ARINC818 ICD, and provides a GTP high-number data transmission interface.

[0068] More specifically, the logic management unit implements the data organization format required by the ARINC818 protocol, is compatible with special color depths, encoding methods, etc., and can configure the input video format, supporting common configurations such as 640×512, 1024×768, 1280×1024, 1920×1080, and supports a maximum resolution of 4K. It can adaptively support a video refresh rate of 30Hz / 60Hz frame rate, and can also edit custom information in the frame header to achieve composite transmission of video and data information.

[0069] More specifically, the logic management unit realizes video splicing output and can input the specified configuration file to combine the input ARINC818 videos into a display screen. According to the configuration requirements, 2, 3, 4, and up to 8 video screens can be combined on the output ARINC818 video screen, so that one display console can monitor multiple input videos at the same time. At the same time, multiple display consoles can realize the video combination and splicing function, the number of videos is scalable, and the video network can be plug-and-play.

[0070] More specifically, the video codec unit implements video compression encoding, supports mainstream encoding formats such as H.264 and H.265, and writes the encoded video to the data storage unit through the PCIe bus; it can also read the specified video clip inside the data storage unit for decoding and playback according to instructions, and send it to the logic management unit for processing and display. When video compression encoding needs to be expanded, codec units can be added as needed to form a video codec array.

[0071] More specifically, the data storage unit uses high-speed NVME storage, and multiple data storage units can form a data storage array to expand the storage capacity. The data storage unit includes an NVMe protocol controller, which is mainly responsible for data interaction between the chip front-end interface and the PCIe NVMe host; NAND Flash Interface (NFI): Flash controller interface module, which mainly implements the interface function with the back-end, controls the interface timing of the Flash storage chip, and implements the access of end-user data and system data in the flash memory particles. It has a low-density parity check code LDPC encoding and decoding module inside, which realizes real-time encoding when writing Flash data and decoding when reading Flash data and supports soft and hard judgment; DDR Controller: DDR controller, which mainly realizes data interaction with external DDR4 / DDR3 / LPDDR3 chips on the chip. The internal module can read and write external DDR4 / DDR3 / LPDDR3 through the DDR Controller to expand the internal RAM space; On Chip Memory: On-chip memory, this RAM is an internal shared storage space shared by all sub-modules; eFuse: One-time programmable module, responsible for storing some key data and some factory settings, and can lock the logical physical interface according to the configuration; DMA: The module is responsible for moving data between the two data buses, and also has some data comparison, search, alignment and other functions; RAID: Redundant array of independent disks support module, providing RAID-level data protection in addition to LDPC protection, making user data safer.

[0072] More specifically, the FPGA in the logic management unit uses an embedded MicroBlaze processor soft core to distribute and upgrade the software of the video end node device through the network bus through the protocol address, send the upgrade data packet to the storage buffer, and add data packet verification. If the verification fails, the data packet is resent to ensure that the upgrade process is reliable and stable. In addition, this upgrade method can upgrade at least 20 end nodes at the same time, improving the upgrade efficiency of the video network.

[0073] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A video surveillance network and recording system based on ARINC818, characterized in that: The system comprises: The photoelectric conversion module receives the optical signal of the ARINC818 video and converts it into an electrical signal, and is provided with multiple optical fiber receiving MPO / MT interfaces and multiple ARINC818 electrical signal output interfaces; A video scheduling management array, communicating with the photoelectric conversion module, includes a plurality of logic management units, the number of which is expanded based on the number of video channels to be processed; A video codec array, communicating with the video scheduling management array, includes a plurality of video codec units, for compressing and encoding the video signal output by the video scheduling management array, and writing the encoded video into a data storage unit via a PCIe bus; the number of the video codec units is expanded based on the number of video paths to be processed; A data storage array, communicating with the video codec array, comprising a plurality of data storage units for recording video data into a storage disk; the number of the data storage units is expanded based on the size of the video data; Wherein: the video encoding and decoding unit is configured to read the specified video segment in the data storage unit according to the instruction, decode and play it back, and send it to the logic management unit for processing and display. The video scheduling management array is configured with a video scheduling management unit; The video scheduling management unit is logically provided with multiple interface control units, and a detection module is provided in the interface control unit. When the detection module detects that the logic management unit is connected, the corresponding module control is activated, and the video scheduling logic is started; The video scheduling logic collects the number of video channels received by the logic management unit, and after statistics, dynamically allocates them according to the existing FPGA video interface resources in the frequency scheduling management array to ensure that each FPGA can process the assigned video and leave a load margin; if the hardware resources are insufficient, the video scheduling logic will report the corresponding resource-deficient module information to the display console.

2. The video surveillance network and recording system based on ARINC818 according to claim 1, characterized in that: The video scheduling management unit is also used for dynamic resource allocation of the video encoding and decoding array and the data storage array and reporting of insufficient resource information.

3. The video surveillance network and recording system based on ARINC818 according to claim 2, characterized in that: The display console sends its own parameters to the video scheduling management array through the control bus. The video scheduling management array configures the video output interface according to the parameters of the display console and converts the video signal into the format required by the display console for output.

4. The ARINC818-based video surveillance network and recording system according to claim 3, characterized in that: After receiving the video signal, the video scheduling management array parses the video frame header, obtains the video resolution and frame rate format parameters after parsing, and then adaptively configures the video receiving interface in the video scheduling management array to support the video scheduling management array to normally receive the video signal.

5. The ARINC818-based video surveillance network and recording system according to claim 4, characterized in that: The logic management unit includes at least one FPGA and one DDR; used to complete high-speed serial data transmission and reception, ARINC818 bus data generation or analysis, and video data processing functions; When the video processing resources are insufficient, the integrated logic management unit is connected to the video scheduling management array.

6. The ARINC818-based video surveillance network and recording system according to claim 5, characterized in that: The photoelectric conversion module receives the ARINC818 video output by each onboard device, the medium is light, converts the video into an electrical signal, and transmits it to the video scheduling management array. The video scheduling management array can output the designated video to the corresponding display console according to the display console instruction; the video scheduling management array is configured to combine and splice the input video and output it to the display console. For the video that needs to be recorded, the video is transmitted to the video codec array, compressed by video coding, and stored in the data storage array; The video scheduling management array is configured to decode and display the stored video according to the online playback instruction of the display console.

7. The ARINC818-based video surveillance network and recording system according to claim 6, characterized in that: The video scheduling management array includes multiple logic management units, each of which includes a set of programmable logic devices and a corresponding number of double-rate synchronous dynamic random access memories; each logic management unit supports at least 20-channel ARINC818 video processing, and the video scheduling management array is configured to expand its video processing capability according to the number required by the video network.

8. The ARINC818-based video surveillance network and recording system according to claim 7, characterized in that: The logic management unit is used to complete high-speed serial data transmission and reception, ARINC818 bus data generation or analysis, and video data processing.

9. The ARINC818-based video surveillance network and recording system according to claim 8, characterized in that: The video codec unit supports H.264 and H.265 encoding formats, and writes the encoded video into the data storage unit through the PCIe bus. It can also read the specified video clips inside the data storage unit for decoding and playback according to instructions, and send them to the logic management unit for processing and display.

10. The ARINC818-based video surveillance network and recording system according to claim 9, characterized in that: The data storage unit is a high-speed NVME storage; multiple data storage units form a data storage array to expand the storage capacity; The data storage unit contains: NVMe protocol controller, used to support data interaction between the chip front-end interface and the PCIe NVMe host; The flash memory controller interface module implements the interface function with the back-end, controls the interface timing of the Flash storage chip, and implements the access of the end-user data and system data in the flash memory particles. It has a low-density parity check code LDPC encoding and decoding module inside, which implements the real-time encoding when writing Flash data and the decoding function when reading Flash data and supports soft and hard judgment; DDR controller, which realizes data interaction with external DDR4 / DDR3 / LPDDR3 chips. The internal module reads and writes to the external DDR4 / DDR3 / LPDDR3 through DDRController, expanding the internal RAM space; On-chip memory is an internal shared storage space shared by all sub-modules; One-time programmable module, responsible for storing some key data and some factory setting information, and can lock the logical and physical interface according to the configuration; DMA: used to move data between two data buses, equipped with data comparison, search and alignment functions; Redundant Array of Independent Disks support module, providing RAID-level data protection in addition to LDPC protection.

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