Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device, wherein the array substrate comprises: a substrate having a first surface and a second surface opposite to each other, wherein the first surface comprises a first region and a second region adjacent to each other; a pixel circuit and a gate driving circuit, wherein the pixel circuit is arranged in the first region; a connecting line, wherein the gate driving circuit and the pixel circuit are electrically connected to the connecting line, and at least a part of the connecting line is located on the second surface. The technical solution of the present application can greatly improve the phenomenon of pixel layout space being occupied and pixel density (PPI) being reduced due to the layout of the connecting line, thereby ensuring the realization of high pixel density.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the rapid development of terminal devices, more and more array substrates are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today. At present, users' aesthetic taste is constantly improving, and users have higher demands for the beauty and fashion of display products in display fields such as vehicles and smart homes.

[0003] The display device includes an array substrate, and the display device can be flexibly expanded by splicing the array substrates. However, the existing array substrates have a frame area outside the display area for placing the drive circuit of the array substrate, which results in a large seam being formed during the splicing process, destroying the continuity of the display screen.

[0004] In order to achieve a borderless design, some manufacturers have tried to set the drive circuit of the array substrate in the display area. However, as the core distribution area of ​​the pixel circuit, the built-in drive circuit will inevitably occupy the space of the pixel circuit, which will lead to a decrease in pixel density, that is, a decrease in the number of pixels per inch (PPI). This technical difficulty limits the application of borderless design in high PPI products, because high PPI is crucial to the clarity and fineness of the picture. Summary of the invention

[0005] The technical problem solved by the present invention is to provide an improved array substrate, a display panel and a display device.

[0006] To solve the above technical problems, an embodiment of the present invention provides an array substrate, comprising: a substrate having a first surface and a second surface relative to each other, wherein the first surface comprises a first area and a second area adjacent to each other; a pixel circuit and a gate driving circuit, wherein the pixel circuit is arranged in the first area; a connecting line, the gate driving circuit and the pixel circuit are electrically connected to the connecting line, and at least a portion of the connecting line is located on the second surface.

[0007] In order to solve the above technical problems, an embodiment of the present application further provides a display panel, comprising the above array substrate.

[0008] In order to solve the above technical problem, an embodiment of the present application further provides a display device, comprising the above display panel.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0010] To solve the above technical problems, an embodiment of the present invention provides an array substrate, comprising: a substrate having a first surface and a second surface relative to each other, wherein the first surface comprises a first area and a second area adjacent to each other; a pixel circuit and a gate driving circuit, wherein the pixel circuit is arranged in the first area; a connecting line, the gate driving circuit and the pixel circuit are electrically connected to the connecting line, and at least a portion of the connecting line is located on the second surface.

[0011] By adopting the technical solution of the present application, the gate drive circuit is arranged in an area on the array substrate where no pixel circuit is arranged, and at least a part of the connection line for electrically connecting the gate drive circuit and the pixel circuit is arranged on the second surface. Thus, the gate drive circuit and the connection line occupy the layout space of the pixel circuit on the first surface, or even avoid the phenomenon that the pixel layout space is occupied and the pixel density (PPI) is reduced due to the layout of the connection line, and the realization of high pixel density is ensured. Furthermore, at least a part of the connection line is arranged on the second surface, which can also facilitate the electrical connection between the gate drive circuit and the pixel array.

[0012] Furthermore, the gate drive circuit and the pixel circuit are arranged on the same surface of the array substrate. Thus, the active layer can be arranged only on the surface of the substrate where the gate drive circuit and the pixel circuit are arranged, which is conducive to simplifying the manufacturing process and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of a first surface of an array substrate according to an embodiment of the present invention;

[0014] Figure 2 yes Figure 1 A schematic diagram of the second surface of the array substrate shown;

[0015] Figure 3 is a schematic diagram of an array substrate according to a variation of an embodiment of the present invention;

[0016] Figure 4 yes Figure 3 A schematic diagram of the second surface of the array substrate shown;

[0017] Figure 5 is a schematic diagram of an array substrate according to another variation of an embodiment of the present invention;

[0018] Figure 6 yes Figure 5 A schematic diagram of the second surface of the array substrate shown;

[0019] Figure 7 yes Figure 1 a side cross-sectional view of a portion of region A;

[0020] Figure 8is a schematic diagram of a display panel according to an embodiment of the present invention;

[0021] Fig. 9 is a schematic diagram of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] As mentioned in the background art, the layout of the gate driving circuit and the connection lines in the prior art limits the further improvement of the number of pixels per inch of the display panel (or display device).

[0023] To solve the above technical problems, an embodiment of the present invention provides an array substrate, a display panel and a display device, wherein the array substrate includes a substrate having a first surface and a second surface relative to each other, wherein the first surface includes a first area and a second area adjacent to each other; a pixel circuit and a gate driving circuit, wherein the pixel circuit is arranged in the first area; and a connecting line, wherein the gate driving circuit and the pixel circuit are electrically connected to the connecting line, and at least a portion of the connecting line is located on the second surface.

[0024] By adopting the technical solution of the present application, the gate drive circuit is arranged in an area on the array substrate where no pixel circuit is arranged, and at least a part of the connection line for electrically connecting the gate drive circuit and the pixel circuit is arranged on the second surface. Thus, the gate drive circuit and the connection line occupy the layout space of the pixel circuit on the first surface, or even avoid the phenomenon that the pixel layout space is occupied and the pixel density (PPI) is reduced due to the layout of the connection line, and the realization of high pixel density is ensured. Furthermore, at least a part of the connection line is arranged on the second surface, which can also facilitate the electrical connection between the gate drive circuit and the pixel array.

[0025] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figure 1 is a schematic diagram of a first surface 11 of an array substrate 10 according to an embodiment of the present invention, Figure 2 yes Figure 1 A schematic diagram of the second surface 12 of the array substrate 10 is shown.

[0027] Combination Figure 1 and Figure 2 The array substrate 10 may include: a substrate 1 having a first surface 11 and a second surface 12 relative to each other, wherein the first surface 11 includes a first area 111 and a second area 112 adjacent to each other; a pixel circuit 2 and a gate driving circuit 3, wherein the pixel circuit 2 is arranged in the first area 111; a connecting line 4, the gate driving circuit 3 and the pixel circuit 2 are electrically connected to the connecting line 4, and at least a portion of the connecting line 4 is located on the second surface 12.

[0028] In the actual production process, the array substrate 10 is first processed and manufactured so that it is covered with complex circuit structures, such as pixel circuits 2, gate drive circuits 3, and connection lines 4.

[0029] In some embodiments, the substrate 1 is a basic supporting structure of the array substrate 10 , and can provide a stable supporting platform for the pixel circuit 2 and the gate driving circuit 3 .

[0030] In some embodiments, the substrate 1 may be made of glass, plastic or other transparent, insulating materials.

[0031] Furthermore, along the light emitting direction, the array substrate 10 may include an opposite first surface 11 and a second surface 12 , wherein the first surface 11 may be, for example, a light emitting surface, and the pixel circuit 2 is disposed on the first surface 11 .

[0032] In some embodiments, the first surface 11 may be divided into a first area 111 and a second area 112 adjacent to each other. The first area 111 may be used to arrange a pixel circuit 2, which may control the light emission and color of the pixel.

[0033] In some embodiments, a plurality of pixel circuits 2 may be arranged in an array on the first area 111. The pixel circuits 2 may correspond to independent pixels to control the light emitting state of the corresponding pixels.

[0034] It should be understood that Figure 1 , Figure 3 as well as Figure 5 The arrangement features such as size, quantity and density of the pixel circuit 2 are merely exemplary and should not be regarded as any limitation to the technical solution of the present application.

[0035] In some embodiments, the first region 111 is suitable for forming a display area of ​​a display panel or a display device further processed by the array substrate 10 , while the second region 112 is suitable for forming a non-display area of ​​a display panel or a display device further processed by the array substrate 10 .

[0036] In some embodiments, a pixel array may be further provided on the first surface 11. The pixel array may be, for example, an LED (Light Emitting Diode) array. The pixel array is electrically connected to the pixel circuit 2 and emits light under the drive and control of the pixel circuit 2 to display the target image.

[0037] In some embodiments, the pixel circuit 2 can receive control signals from the gate drive circuit 3 and other signal sources, and control the light-emitting state of the pixel accordingly. The gate drive circuit 3 can generate and transmit a scan drive signal (or other control signal) to the pixel circuit 2, thereby controlling the row-by-row (or column-by-column) scanning and light-emitting of the pixel.

[0038] For the convenience of description, the signal generated and transmitted by the gate driving circuit 3 is referred to as a gate control signal hereinafter.

[0039] Furthermore, the connection line 4 electrically connects the gate driving circuit 3 and the pixel circuit 2, and at least a portion of the connection line 4 is located on the second surface 12. Thus, the gate driving circuit 3 and the connection line 4 both avoid the first area 111 for arranging the pixel circuit 2, providing more layout space for the pixel circuit 2.

[0040] As described above, the gate drive circuit 3 is arranged in the second area 112 on the array substrate 10 where the pixel circuit 2 is not arranged, and at least a part of the connection line 4 for electrically connecting the gate drive circuit 3 and the pixel circuit 2 is arranged on the second surface 12. As a result, the gate drive circuit 3 and the connection line 4 occupying the layout space of the pixel circuit 2 on the first surface 11 is reduced or even avoided, which greatly improves the phenomenon of the layout space occupation of the pixel circuit 2 and the decrease in pixel density (PPI) caused by the layout of the connection line 4, and ensures the realization of high pixel density. Furthermore, at least a part of the connection line 4 is arranged on the second surface 12, which can also facilitate the electrical connection between the gate drive circuit 2 and the pixel array 3.

[0041] In some embodiments, the gate driving circuit 3 may be disposed in the second area 112. In other words, the gate driving circuit 3 may be disposed together with the pixel driving circuit 2 on the first surface 11. Thus, during the processing, the active layer may be disposed only on the first surface 11 of the substrate 1, which is conducive to simplifying the manufacturing process and reducing the production cost.

[0042] In some embodiments, the connecting line 4 includes a first section, a second section, and a third section that are electrically connected in sequence, wherein the first section is electrically connected to the pixel circuit 2, the second section is electrically connected to the gate drive circuit 3, at least a portion of the first section and at least a portion of the third section are located on the first surface 11, and the second section is located on the second surface 12 (such as Figure 2 shown).

[0043] In a specific embodiment, in combination Figure 1 and Figure 2, the substrate 1 may include a first side 101, a second side 102, a third side 103 and a fourth side 104 connected in sequence. Among them, the first side 101 and the third side 103 are opposite. At least a portion of the first section of the connecting line 4 may be located in an area of ​​the first surface 11 close to the second side 102, and electrically connected to the pixel circuit 2. Further, the second section of the connecting line 4 may extend from the second side 102 to the first side 101 along the second surface 12. Further, at least a portion of the third section of the connecting line 4 may extend to an area of ​​the first surface 11 close to the first side 10, and electrically connected to the gate driving circuit 2.

[0044] It should be understood that the electrical connection is not limited to a direct physical connection, but also includes a connection method in which a conductive path is formed through other conductors.

[0045] In some embodiments, in combination Figure 7 Since the substrate 1 has a thickness, at least a portion of the connecting line 4 can be located at a side edge of the substrate 1 and extend from the first surface 11 to the second surface 12 along the thickness direction of the substrate 1 .

[0046] In some embodiments, the gate driving circuit 3 may also be disposed on the second surface 12. Thus, the area of ​​the second region 112 of the first surface 11 can be further reduced, which is beneficial to increase the proportion of the first region 11 used to form the display area on the array substrate 1.

[0047] Furthermore, the connecting line 4 includes a fourth segment and a fifth segment which are electrically connected in sequence, wherein the fourth segment is electrically connected to the pixel circuit 2, the fifth segment is electrically connected to the gate driving circuit 3, at least a portion of the fourth segment is located on the first surface 11, and the fifth segment is located on the second surface 12.

[0048] In some embodiments, the connection line 4 may be connected between the first surface 11 and the second surface 12 by a through-hole process or other means, thereby achieving electrical connection between the gate driving circuit 3 and the pixel circuit 2 .

[0049] In some embodiments, at least a portion of the connection line 4 extends along a straight line, an arc line, or a folded line on the second surface 12 .

[0050] In some embodiments, portions of the plurality of connecting wires 4 located on the second surface 12 are insulated from each other.

[0051] In some embodiments, continue to refer to Figure 1, the array substrate 10 may further include a pad 5, the pad 5 is electrically connected to a signal line, the signal line is electrically connected to a source or drain of at least one transistor in the pixel circuit 2, the second area 112 includes a first partition 1121 and a second partition 1122 respectively arranged on opposite sides of the first area 111, the gate drive circuit 3 is arranged in the first partition 1121, and the pad 5 is arranged in the second partition 1122. Among them, the source is an electrode that provides carriers (such as electrons or holes) in a field effect transistor, which is used to provide carriers to the channel inside the transistor so as to form a current under the control of the gate voltage; the drain is an electrode that collects carriers in a field effect transistor, which is used to collect carriers flowing to it through the channel and convert them into current output.

[0052] Specifically, the pixel circuit 2 may include a plurality of transistors. The transistors may be used as switching elements to control the transfer of current or voltage in response to a signal from the gate drive circuit 3, thereby opening or closing the circuit and controlling the light-emitting state of the pixel. Optionally, the pixel circuit 2 is arranged in an array. For ease of description, the pixels in the same row are hereinafter referred to as a pixel row 7, and the figure is simplified to represent the corresponding pixel row with a signal line.

[0053] In some embodiments, the pad 5 may be formed into a driver IC in a subsequent processing step.

[0054] In some embodiments, the first partition 1121 and the second partition 1122 may be formed on both sides of the first area 111 along the first direction D1. In this scenario, the first partition 1121 and the second partition 1122 respectively form two side frames of the array substrate 1 along the first direction D1.

[0055] Furthermore, the first side edge 101 is formed on a side of the first partition 1121 facing the first direction D1 , and the third side edge 103 is formed on a side of the second partition 1122 away from the first direction D1 .

[0056] As described above, by arranging the gate driving circuit 3 in the first partition 1121 and the pad 5 in the second partition 1122, and the first partition 1121 and the second partition 1122 are respectively located on two opposite sides of the first area 111 along the first direction D1, the second side 102 and the fourth side 104 of the array substrate 1 can achieve a borderless effect. In the subsequent manufacturing process, two adjacent array substrates 1 can be seamlessly spliced ​​at the second side 102 and the fourth side 104.

[0057] In some embodiments, the first partition 1121 and the second partition 1122 may be located on the same side of the first area 111. Thus, the other three sides of the array substrate 1 can be used to achieve seamless splicing. For example, the first partition 1121 and the second partition 1122 may both be disposed on the side of the first area 111 facing the first direction D1. In this scenario, the second side 102, the third side 103, and the fourth side 104 may all be used for seamless splicing with other array substrates 1 of the same model.

[0058] In some embodiments, the signal line electrically connected to the pad 5 may include: one or more of a power signal line, a data line, and a reference voltage signal line.

[0059] In some embodiments, the array substrate 10 includes a gate signal line 6 , the gate driving circuit 3 includes a plurality of driving units 31 , and the connecting line 4 is electrically connected to the gate signal line 6 and at least one driving unit 31 , respectively.

[0060] Specifically, the gate signal line 6 can be used to send gate control signals to transistors in the pixel circuit 2 in sequence during each scanning cycle. When the transistor receives a valid gate signal, it turns on, allowing current to flow between the source and the drain, thereby controlling the light emission of the corresponding pixel.

[0061] In some embodiments, Figure 1 , Figure 3 as well as Figure 5 As shown, along the first direction D1, the array substrate 10 includes a plurality of pixel rows 7 extending along the second direction D2.

[0062] In some embodiments, the pixel rows 7 and the selection signal lines 6 may correspond one to one, and the signal lines 6 are selected to transmit gate control signals to the corresponding pixel rows 7 to control the light-emitting states of the pixels in the pixel rows 7 .

[0063] Further, a plurality of strobe signal lines 6 correspond one to one with a plurality of driving units 31. Each strobe signal line 6 can be electrically connected to a corresponding driving unit 31 via an independent connecting line 4. In this scenario, the pixel circuits 2 in the pixel row 7 are electrically connected to the corresponding strobe signal lines 6, and the strobe signal lines 6 are further electrically connected to the corresponding driving units 31 to transmit gate control signals.

[0064] In some embodiments, in combination Figure 3 and Figure 4 , the strobe signal line 6 can also correspond to two driving units 31 at the same time. That is, the two driving units 31 can be electrically connected to the two ends of the strobe signal line 6 respectively to realize dual-drive control of the pixel row 7 corresponding to the strobe signal line 6. This is conducive to improving signal delay and optimizing display effect.

[0065] It should be understood that the electrical connection between the driving unit 31 of the gate driving circuit 3 and the pixel row 7 is actually an electrical connection with the pixel circuit 2 on the pixel row 7 achieved through the selection signal line 6 corresponding to the pixel row 7 .

[0066] In some embodiments, at least two strobe signal lines 6 may also be electrically connected to the same connection line 4 .

[0067] In some embodiments, the plurality of pixel rows 7 include a first portion of pixel rows 71. The array substrate 10 may further include: a plurality of first pins 81, respectively electrically connected to at least one end of the pixel rows 7 in the first portion of pixel rows 71 along the second direction D2; a plurality of second pins 82, respectively electrically connected to the plurality of driving units 31, the first pins 81 and the second pins 82 being electrically connected via the corresponding connecting wires 4. Thus, through the first pins 81 and the second pins 82, the gate driving circuit 3 and the pixel circuit 2 in the pixel row 7 can achieve stable and reliable electrical connection to ensure stable transmission of the gate control signal.

[0068] In some embodiments, the plurality of pixel rows 7 further include a second portion of pixel rows 72, and the pixel rows 7 in the second portion of pixel rows 72 are electrically connected to the first pins 81 electrically connected to the pixel rows 7 in the adjacent first portion of pixel rows 71. Thus, more pixel rows 7 can be arranged on the substrate 1 with the same number of control units 31, thereby further improving the PPI.

[0069] In some embodiments, the first pin 81 is disposed at a single end of the pixel row 7 in the first portion of pixel rows 71 .

[0070] In some embodiments, the first pins 81 may be disposed on the same side of the substrate 1 along the second direction D2 .

[0071] For example, in Figure 1 In the illustrated embodiment, the first pin 81 is disposed on the second side 102 of the substrate 1 .

[0072] In some embodiments, reference Figure 5 The first pin 81 electrically connected to at least one of the pixel rows 7 may also be arranged on a different side of the substrate 1 along the second direction D2 from the first pin 81 electrically connected to other pixel rows 7 .

[0073] In some embodiments, reference Figure 3 , both ends of the pixel row 7 in the first part of the pixel rows 71 are provided with the first pins 81 to respectively electrically connect the two driving units 31 corresponding to the pixel row 7. Thus, it is convenient to realize the dual-drive control of the pixel row 7 by the gate driving circuit 3.

[0074] In some embodiments, the gate driving circuit 3 may include at least one of a scanning driving circuit and a light emitting control driving circuit.

[0075] In a specific embodiment, Figure 5 As shown, the plurality of driving units 31 can be divided into a first group and a second group. The first group of driving units 31 can be arranged in a side area of ​​the first partition 1121 away from the second direction D2, and the second group of driving units 31 can be arranged in a side area of ​​the first partition 1121 toward the second direction D2.

[0076] Furthermore, the first group of driving units 31 may include a scan driving circuit, and the second group of driving units 32 may include a light emitting control driving circuit.

[0077] Furthermore, some of the pixel rows 7 among the plurality of pixel rows 7 are electrically connected to the first group of driving units 31 , and another part of the pixel rows 7 are electrically connected to the second group of driving units 31 .

[0078] As described above, the array substrate 10 using the technical solution of the present application can achieve a borderless effect at the second side 102 and the fourth side 104 of the array substrate 1 by arranging the gate driving circuit 3 in the first partition 1121 and the pad 5 in the second partition 1122, and the first partition 1121 and the second partition 1122 are respectively located on two opposite sides of the first area 111 along the first direction D1. In the subsequent manufacturing process, two adjacent array substrates 1 can be seamlessly spliced ​​at the second side 102 and the fourth side 104.

[0079] Furthermore, the gate drive circuit 3 and the pixel circuit 2 are arranged on the same surface of the array substrate 10. Thus, the active layer can be arranged only on the surface of the substrate 10 where the gate drive circuit 3 and the pixel circuit 2 are arranged, which is conducive to simplifying the manufacturing process and reducing the production cost.

[0080] Figure 8 is a schematic diagram of a display panel 100 according to an embodiment of the present invention.

[0081] refer to Figure 8 In some embodiments, the display panel 100 may include: Figures 1 to 7 The array substrate 10 is shown in the illustrated embodiment.

[0082] For the detailed description of the structure of the array substrate 10, please refer to the above description. Figures 1 to 7 The detailed description of the illustrated embodiment is not repeated here.

[0083] In some embodiments, there are multiple array substrates 10 , and the multiple array substrates 10 are spliced ​​together.

[0084] Furthermore, the sides of two adjacent array substrates 10 where the second area 112 is not formed are spliced ​​with each other. Figure 8 As shown, the frameless sides of two adjacent array substrates 10, namely the second side 102 and the fourth side 104, are seamlessly spliced, thereby optimizing the display effect of the display panel 100.

[0085] In some embodiments, there may be a small gap G between two adjacent array substrates 10 for filling with materials such as optical glue to protect the sides of the array substrate 10 and avoid short circuits between the two adjacent array substrates 10 that may cause failure of the display panel 100.

[0086] It should be understood that Figure 8 The width of the gap G is only exemplary, and in practical applications, the width of the gap G may be smaller than the minimum width observable by the naked eye, such as 0.01 mm, so that the two array substrates 10 can still be visually seamlessly spliced.

[0087] Fig. 9 is a schematic diagram of a display device 1000 according to an embodiment of the present invention.

[0088] refer to Fig. 9 , an embodiment of the present application also provides a display device 1000.

[0089] In some embodiments, the display device 1000 may include the above Figure 8 The display panel 100 in the illustrated embodiment.

[0090] In practical applications, the display device 1000 may be, for example, a vehicle-mounted display screen.

[0091] It should be understood that the term "and / or" herein is merely an association relationship describing associated objects, indicating that three relationships may exist, for example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein indicates that the associated objects before and after are in an "or" relationship. As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless not feasible. For example, if a component is stated to include A or B, then unless otherwise expressly stated or not feasible, the component may include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then unless otherwise expressly stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0092] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0093] Relational terms appearing in the embodiments of the present application, such as first, second, etc., are only used to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "include", "have", "include" and other similar forms are intended to be equivalent in meaning and are open-ended, and one or more items following any of these words are not meant to be an exhaustive list of such one or more items, or to be limited to the listed one or more items.

[0094] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0095] In the foregoing description, embodiments have been described with reference to many specific details, which may vary depending on the implementation. Certain changes and modifications may be made to the described embodiments. In view of the description and practice of the present application disclosed herein, other embodiments will be clear to those skilled in the art. The description and examples are intended to be considered as merely exemplary, and the true scope and spirit of the present application are indicated by the following claims. The order of steps shown in the accompanying drawings is also intended to be used for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, it will be appreciated by those skilled in the art that these steps may be performed in different orders while implementing the same method.

[0096] In the drawings and the specification, exemplary embodiments have been disclosed. However, many variations and modifications may be made to these embodiments. Therefore, although specific terms are employed, they are used only in a general and descriptive sense and not for the purpose of limitation.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An array substrate, characterized in that: include: a substrate having a first side and a second side opposite to each other, wherein the first side includes a first region and a second region adjacent to each other; A pixel circuit and a gate driving circuit, wherein the pixel circuit is arranged in the first area; A connection line, the gate driving circuit and the pixel circuit are electrically connected to the connection line, and at least a portion of the connection line is located on the second surface.

2. The array substrate according to claim 1, characterized in that: The gate driving circuit is disposed in the second area.

3. The array substrate according to claim 2, characterized in that: The connecting line includes a first segment, a second segment, and a third segment that are electrically connected in sequence, wherein the first segment is electrically connected to the pixel circuit, the second segment is electrically connected to the gate driving circuit, at least a portion of the first segment and at least a portion of the third segment are located on the first surface, and the second segment is located on the second surface.

4. The array substrate according to claim 1, characterized in that: It also includes a pad, which is electrically connected to a signal line, and the signal line is electrically connected to a source or a drain of at least one transistor in the pixel circuit. The second area includes a first partition and a second partition respectively arranged on opposite sides of the first area, the gate drive circuit is arranged in the first partition, and the pad is arranged in the second partition.

5. The array substrate according to claim 4, characterized in that: The signal line includes: one or more of a power signal line, a data line, and a reference voltage signal line.

6. The array substrate according to claim 1, characterized in that: The array substrate includes a gate signal line, the gate driving circuit includes a plurality of driving units, and the connecting lines are electrically connected to the gate signal line and at least one driving unit respectively.

7. The array substrate according to claim 6, characterized in that: At least two strobe signal lines are electrically connected to the same connection line.

8. The array substrate according to claim 6, characterized in that: Along the first direction, the array substrate includes a plurality of pixel rows extending along the second direction, the plurality of pixel rows include a first portion of pixel rows, and the array substrate further includes: A plurality of first pins, respectively electrically connected to at least one end of the pixel rows in the first part of pixel rows along the second direction; A plurality of second pins are electrically connected to the plurality of driving units respectively, and the first pins and the second pins are electrically connected via corresponding connecting wires.

9. The array substrate according to claim 8, characterized in that: The plurality of pixel rows further include a second portion of pixel rows, wherein the pixel rows in the second portion of pixel rows are electrically connected to the first pins electrically connected to the pixel rows in the adjacent first portion of pixel rows.

10. The array substrate according to claim 8, characterized in that: The first pin is arranged at a single end of the pixel row in the first part of the pixel rows; wherein, The first pins are arranged on the same side of the substrate along the second direction; or The first pin electrically connected to at least one of the pixel rows and the first pin electrically connected to other pixel rows are arranged on different sides of the substrate along the second direction.

11. The array substrate according to claim 8, characterized in that: Both ends of the pixel rows in the first part of pixel rows are provided with the first pins to electrically connect two driving units corresponding to the pixel rows respectively.

12. The array substrate according to claim 1, characterized in that: The gate driving circuit is disposed on the second surface.

13. The array substrate according to claim 12, characterized in that: The connecting line includes a fourth segment and a fifth segment electrically connected in sequence, wherein the fourth segment is electrically connected to the pixel circuit, the fifth segment is electrically connected to the gate driving circuit, at least a portion of the fourth segment is located on the first surface, and the fifth segment is located on the second surface.

14. The array substrate according to claim 1, characterized in that: The gate driving circuit includes at least one of a scanning driving circuit and a light emitting control driving circuit.

15. A display panel, characterized in that: include: An array substrate as claimed in any one of claims 1 to 14.

16. The display panel according to claim 15, characterized in that: There are multiple array substrates, and the multiple array substrates are spliced ​​together.

17. The display panel according to claim 16, characterized in that: The sides of two adjacent array substrates where the second area is not formed are spliced ​​with each other.

18. A display device, characterized in that: A display panel comprising at least one of claims 15 to 17.

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