Map topological relation reasoning method fused with SD map

Abstract

The invention discloses a map topological relation reasoning method fused with an SD map, and belongs to the technical field of three-dimensional reconstruction. The method comprises the following steps: acquiring an SD map and carrying out vectorization processing to obtain an SD map broken line sequence; encoding the SD map broken line sequence to obtain SD map features; adjusting the 3D lane coordinates by using the SD map position codes to obtain lane position embedding; and carrying out inter-lane topological relation reasoning by fusing the SD map features and the 3D lane features. According to the method, 3D lane coordinates and SD map position codes are combined to generate lane position embedding, in the process, initialization of a topological relation is assisted by the SD map, and lane geometric information provided by the SD map is effectively fused in a topological reasoning stage; the method not only considers the inherent geometrical characteristics of the lane, but also significantly reduces the influence of the inherent endpoint shift on the topological relation in the lane detection.

Description

Technical Field

[0001] The present invention belongs to the technical field of map construction, and in particular relates to a map topology relationship reasoning method integrating SD maps. Background Art

[0002] High-definition (HD) maps are fundamental for autonomous vehicles (AVs) to perceive their static surroundings, providing critical information for downstream behavior prediction and motion planning modules. Currently, online HD vector map methods can directly extract data from onboard sensors to predict HD map information, enabling online integration with downstream tasks. Based on this, topological maps are constructed by capturing the relationships between lanes and traffic elements in the driving scene. This maps demonstrates drivable routes for autonomous driving and provides clear navigation signals for downstream tasks such as motion prediction and planning.

[0003] Topological map construction consists of two stages: map element detection and topological relationship reasoning. Since reasoning performance is limited by detection accuracy, many current panoramic topological map construction methods focus on improving the detection stage. The map element detection stage uses the DETR (Determining, Detection, and Recognition) object detection architecture to achieve end-to-end accurate HD map construction. However, map elements often have irregular and elongated shapes, and traditional object detection architectures cannot be directly applied to map construction problems. Currently, improvements to detection architectures are divided into two categories based on the characteristics of map elements: enhancing map perception by fusing supplementary information and improving the DETR (Determining, Detection, and Recognition) object detection architecture based on map element characteristics.

[0004] Fusion of Supplementary Information Enhances Map Perception: Supplementary information includes key prior information about road topology, which can complement on-board cameras for lane topology inference. For example, using the SD map for query initialization allows queries to focus on specific areas of interest, effectively searching for map elements and accelerating model convergence. Integrating historical map information into the detection framework improves the temporal consistency and quality of vectorized local HD maps, performing well in challenging environments such as occlusion. However, increased memory and latency costs complicate real-time integration into downstream prediction and planning tasks.

[0005] Improvements to the DETR object detection architecture for map element features: Structured and linearized map element modeling is achieved using hierarchical queries, which sequentially performs instance-level matching and point-level matching. However, without structural guidance, a large number of vertices must be predicted to ensure the shape of the element, posing challenges to convergence speed and performance.

[0006] In summary, the prior art has the following shortcomings: Current research on topological map construction methods focuses on lane detection accuracy and real-time performance. These methods, arguing that perception trumps reasoning, enhance lane perception to improve reasoning performance and directly employ MLP to learn lane topology from lane queries. However, these methods ignore the inherent geometric characteristics of lanes and are susceptible to the inherent endpoint shifts in lane detection. Summary of the Invention

[0007] The purpose of the present invention is to provide a method, electronic device, and storage medium for inferring map topology relationships that integrates SD maps. This method utilizes SD map position encoding to assist in generating position embeddings from predicted 3D lane coordinates to address inherent endpoint shifts in lane detection. This method fine-tunes lane connectivity and mitigates the impact of detection bias on topological relationships. By leveraging SD map position priors, the method reduces the reliance of topological reasoning on detection, further improving the accuracy of topological map construction and addressing at least one of the technical issues discussed in the background art.

[0008] In order to solve the above-mentioned technical problems, the present invention is achieved as follows: In a first aspect, an embodiment of the present invention provides a method for reasoning about map topology relationships by integrating an SD map, comprising the following steps: Step S1, obtaining an SD map and performing vectorization processing to obtain an SD map polyline sequence, specifically includes: The M lanes of the SD map are uniformly sampled and N fixed numbers are folded, which is recorded as , M and N are both positive integers, Respectively represent the two-dimensional horizontal and vertical coordinate points of the lane breakline points on the SD map; Use sinusoidal embedding of different frequencies to encode the position of the broken line point to obtain the SD map position code ,in, , d is the embedding dimension; The lane type in the SD map is represented by a one-hot vector of the road type label of dimension K. The lane type is mapped to a one-dimensional vector of length K, where the element corresponding to the road type is 1 and the rest are 0; Connect the polyline position code with the road type one-hot vector to obtain the SD map polyline sequence ,in, ; Step S2, encoding the SD map polyline sequence to obtain SD map features; Step S3, using the SD map position code to adjust the 3D lane coordinates to obtain lane position embedding; In step S4, the SD map features and 3D lane features are integrated to infer the topological relationship between lanes.

[0009] In a second aspect, an embodiment of the present invention provides an electronic device, including: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the steps of the method described in the first aspect.

[0010] In a third aspect, an embodiment of the present invention provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0011] In a fourth aspect, an embodiment of the present invention provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is configured to run a program or instruction to implement the method described in the first aspect.

[0012] Compared with the prior art, the present invention has the following beneficial effects: 1. By combining 3D lane coordinates with SD map position encoding, a lane position embedding is generated. This process uses the SD map to assist in initializing topological relationships and effectively incorporates lane geometry information provided by the SD map during the topological inference phase. This method not only considers the inherent geometric characteristics of lanes, but also significantly reduces the impact of endpoint shifts inherent in lane detection on topological relationships. 2. By fusing SD map features with lane features for topological relationship reasoning, the SD map contains key information about road topology, providing a valuable supplement to the lane topology reasoning performed by on-board cameras. When merging or exit roads are not visible in the camera image due to occlusion or other reasons, the SD map can provide the necessary prior information for downstream planning, thereby achieving more accurate planning. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which: Figure 1 This is a flow chart of a map topology relationship reasoning method for integrating SD maps provided by the present invention; Figure 2 This is one of the hardware structure diagrams of the electronic device provided by the present invention; Figure 3 This is the second schematic diagram of the hardware structure of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0015] The terms "first," "second," and the like in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of a class, and do not limit the number of objects. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0016] The map topology relationship reasoning method for integrating SD maps provided by the embodiment of the present invention is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios.

[0017] See Figure 1 As shown, an embodiment of the present invention provides a map topology relationship reasoning method for integrating SD maps, comprising the following steps: Step S1, obtaining an SD map and performing vectorization processing to obtain an SD map polyline sequence, specifically includes: The M lanes of the SD map are uniformly sampled and N fixed numbers are folded, which is recorded as , M and N are both positive integers, , Respectively represent the two-dimensional horizontal and vertical coordinates of the N points in the lane after the polyline in the SD map; Use sinusoidal embedding of different frequencies to encode the position of the broken line point to obtain the SD map position code ,in, , d is the embedding dimension; The lane type in the SD map is represented by a one-hot vector of the road type label of dimension K. The lane type is mapped to a one-dimensional vector of length K, where the element corresponding to the road type is 1 and the rest are 0; Connect the polyline position code with the road type one-hot vector to obtain the SD map polyline sequence ,in, ; Step S2, encoding the SD map polyline sequence to obtain SD map features; Step S3, using the SD map position code to adjust the 3D lane coordinates to obtain lane position embedding; In step S4, the SD map features and 3D lane features are integrated to infer the topological relationship between lanes.

[0018] In step S1, a SD map is obtained from OpenStreetMap.

[0019] Step S2 specifically includes: SD map polyline sequence Embedded into the linear layer for encoding, and then the multi-head self-attention mechanism is used to extract SD map features from the SD map ,in, , LN represents layer normalization; Represents the multi-head self-attention mechanism.

[0020] Step S3 specifically includes: Query the lane position obtained in the map element detection phase and SD map location coding , a multi-scale deformable attention mechanism is used to achieve the purpose of information aggregation of lane line point positions using SD map positions, and the fusion position embedding is predicted ,in, Represents a multi-scale deformable attention mechanism; Step S4 specifically includes: SD map features Embedded into 3D lane query The fused lane features used as input for the topology reasoning part At the same time, in order to fuse the lane information, the predicted fusion position is embedded in Integrate into lane query feature To enhance topology modeling, specifically expressed as: ; ; ; Where, and are the feature and position embeddings of the mth lane and the nth lane, respectively, where m and n are both positive integers; MLP stands for multi-layer perceptron; express function.

[0021] like Figure 2As shown, an embodiment of the present invention further provides an electronic device 600, which includes a processor 601, a memory 602, and a program or instruction stored in the memory 602 and executable on the processor 601. When the program or instruction is executed by the processor 601, each process of the above-mentioned map topology relationship reasoning method embodiment for integrating SD maps is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0022] It should be noted that the first electronic device in the embodiment of the present invention includes the mobile electronic device and the non-mobile electronic device mentioned above.

[0023] Figure 3 The present invention is a hardware structure diagram of an electronic device.

[0024] The electronic device 700 includes but is not limited to components such as a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, and a processor 710.

[0025] Those skilled in the art will understand that the electronic device 700 may also include a power supply (such as a battery) to power each component. The power supply may be logically connected to the processor 710 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 3 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0026] It should be understood that in this embodiment of the present invention, the input unit 704 may include a graphics processing unit (GPU) 7041 and a microphone 7042. The GPU 7041 processes image data of still images or videos captured by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 706 may include a display panel 7061, which may be configured in the form of a liquid crystal display, organic light-emitting diode, or the like. The user input unit 707 includes a touch panel 7071 and other input devices 7072. The touch panel 7071, also known as a touch screen, may include a touch detection device and a touch controller. Other input devices 7072 may include, but are not limited to, a physical keyboard, function keys (such as volume control buttons, power buttons, etc.), a trackball, a mouse, and a joystick, which are not described in detail here. The memory 709 may be used to store software programs and various data, including, but not limited to, applications and an operating system. The processor 710 may integrate an application processor and a modem processor. The application processor primarily processes the operating system, user interface, and applications, while the modem processor primarily handles wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 710.

[0027] An embodiment of the present invention further provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned map topology relationship reasoning method embodiment for integrating SD maps are implemented, and the same technical effect can be achieved. To avoid repetition, they will not be repeated here.

[0028] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0029] An embodiment of the present invention further provides a chip, which includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned map topology relationship reasoning method embodiment for integrating SD maps, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0030] It should be understood that the chip mentioned in the embodiment of the present invention can also be called a system-on-chip, a system-on-chip, a chip system, or a system-on-chip chip, etc.

[0031] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0032] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is the more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (such as a mobile phone, computer, server, air conditioner, or network device) to execute the methods described in the various embodiments of the present invention.

[0033] An embodiment of the present invention further provides a chip, which includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned map topology relationship reasoning method embodiment for integrating SD maps, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0034] It should be understood that the chip mentioned in the embodiment of the present invention can also be called a system-on-chip, a system-on-chip, a chip system, or a system-on-chip chip, etc.

[0035] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A map topology relationship reasoning method integrating SD map, characterized in that: The following steps are involved: Step S1, obtaining the SD map and performing vectorization processing to obtain the SD map polyline sequence, specifically includes: The M lanes of the SD map are uniformly sampled into N fixed numbers and then polylined, which is recorded as , M and N are both positive integers, representing the two-dimensional horizontal and vertical coordinates of the lane points after the polyline in the SD map; Use sinusoidal embedding of different frequencies to encode the position of the broken line points to obtain the SD map position code ,in, , d is the embedding dimension; The lane type in the SD map is represented by a one-hot vector of the road type label of dimension K. The lane type is mapped to a one-dimensional vector of length K, where the element corresponding to the road type is 1 and the rest are 0; Connect the polyline position encoding with the road type one-hot vector to obtain the SD map polyline sequence ,in, ; Step S2, encoding the SD map polyline sequence to obtain SD map features; Step S3, using the SD map position code to adjust the 3D lane coordinates to obtain lane position embedding; Step S4, integrating the SD map features with the 3D lane features to infer the topological relationship between lanes.

2. The method according to claim 1, characterized in that In step S1, a SD map is obtained from OpenStreetMap.

3. The method according to claim 1, characterized in that Step S2 specifically includes: SD map polyline sequence Embedded into the linear layer for encoding, and then the multi-head self-attention mechanism is used to extract SD map features from the SD map ,in, , LN represents layer normalization; Represents a multi-head self-attention mechanism.

4. The method according to claim 3, characterized in that Step S3 specifically includes: In order to utilize the prior information of the lane position in the SD map, the SD map position is encoded Lane position query in the map element detection phase is embedded via a multi-scale deformable attention mechanism , get the fusion position embedding ,in, Represents a multi-scale deformable attention mechanism.

5. The method according to claim 4, characterized in that Step S4 specifically includes: SD map features Embedded into 3D lane query The fused lane features used as input for the topology reasoning part At the same time, in order to integrate the SD map lane geometry information, the fusion position is embedded in Integrate into lane query feature To enhance topological modeling, specifically expressed as: ; ; ; In the formula, and are the feature and position embeddings of the mth lane and the nth lane, respectively, where m and n are both positive integers; MLP stands for multi-layer perceptron; express function.

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