Cache request processing method and device for dynamic self-adaptive load balancing

Abstract

The invention relates to the technical field of cache memories, and provides a dynamic self-adaptive load balancing cache request processing method and device. The method comprises the following steps: releasing an original binding relationship of a cache line to be released according to the number of uncompleted requests; the method comprises the following steps: responding to all uncompleted requests in a to-be-released cache line to obtain an idle cache line; according to the workload of each bus interface, allocating an idle cache line for the current request so as to establish a dynamic binding relationship between an idle path occupied by the current request and the idle cache line, and completing a response to the current request according to the dynamic binding relationship; according to the method, unbinding is carried out based on the number of the uncompleted requests, binding is carried out based on the workload of each bus interface, and the problem that the Cache cannot well balance the number difference of the cache requests, the response speed difference of downstream modules and the delay difference of BIF return data due to the fact that the path and the cache line of each Cache Bank are fixedly bound is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed cache memory, and in particular to a cache request processing method and device with dynamic adaptive load balancing. Background Art

[0002] For a cache memory that uses set-associative mapping, the cache is divided into multiple sets of the same size, each set contains multiple ways, and each way contains one or more cache lines. A way is a cache block in the cache, which contains multiple cache lines; different memory addresses can be mapped to multiple ways in the same set. A cache line is the smallest access unit in the cache, containing information such as data and valid bits; a cache line corresponds to a data block in the memory.

[0003] A cache includes multiple cache banks, each of which contains multiple groups and corresponding ways; the cache can be accessed in parallel through each cache bank. A traditional cache (i.e., a cache that includes multiple cache banks) generally receives multiple cache requests and has multiple bus interfaces (BIFs) that interact with the next level. Each cache request is mapped to a fixed cache bank in a certain way, and the ways and cache lines of each cache bank are fixedly bound and one-to-one corresponding, so the cache request passed to the downstream module corresponds to a fixed BIF.

[0004] When the number of simultaneous cache requests is unevenly distributed in different time periods or between different modules (i.e., the number of multiple cache requests is unbalanced), or the response speeds of downstream modules of multiple BIFs are different (i.e., the response speeds of downstream modules of multiple BIFs are unbalanced), or different BIFs process data at different times, resulting in differences in the time it takes for the requested data to be returned to the cache (i.e., the delays in returning data from multiple BIFs vary greatly), traditional set-associative caches cannot balance these differences well, thereby affecting cache performance and significantly reducing cache versatility.

[0005] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in the field of this technology. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a cache request processing method and device with dynamic adaptive load balancing, the purpose of which is to dynamically bind or unbind the way and the cache line, unbind according to the number of unfinished requests, and allocate free cache lines to the current request for dynamic binding according to the workload of each bus interface, thereby greatly improving the cache performance and versatility, and solving the problem that the cache cannot balance the differences between different numbers of cache requests, the response speeds of different downstream modules, or the data return delays of different BIFs due to the fixed binding and one-to-one correspondence between the way and cache line of each Cache Bank.

[0007] The present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a cache request processing method with dynamic adaptive load balancing, comprising:

[0009] Determine the cache line to be released according to the number of outstanding requests, and release the original binding relationship of the cache line to be released;

[0010] Complete responses to all outstanding requests in the cache line to be released, and obtain a free cache line;

[0011] According to the workload of each bus interface, an idle cache line is allocated to the current request, so as to establish a dynamic binding relationship between the idle way occupied by the current request and the idle cache line, and complete the response to the current request according to the dynamic binding relationship.

[0012] Further, determining the cache line to be released according to the number of uncompleted requests and releasing the original binding relationship of the cache line to be released includes:

[0013] Determine the number of outstanding requests for each cache line, and determine whether the number of outstanding requests for each cache line is greater than a first threshold;

[0014] If there is a cache line whose number of uncompleted requests is greater than a first threshold, the cache line is determined as a cache line to be released, and an original binding relationship between the cache line to be released and a corresponding way to be released is released;

[0015] If there is no cache line with a number of uncompleted requests greater than the first threshold, determining the number of free cache lines corresponding to the unblocked bus interface; and determining whether the number of free cache lines is less than a second threshold;

[0016] When the number of free cache lines is less than a second threshold, a to-be-unbound group is determined according to a preset selection strategy, a to-be-released cache line is determined from the to-be-unbound group according to a preset replacement strategy, and the original binding relationship between the to-be-released cache line and the corresponding to-be-released way is released.

[0017] Further, allocating free cache lines for the current request according to the workload of each bus interface includes:

[0018] Obtaining the workload of each bus interface, and determining a bus interface whose workload is less than a load threshold as an unblocked bus interface;

[0019] According to the corresponding allocation mode, the free cache line allocated to the current request is selectively determined based on the unblocked bus interface, or based on the number of free cache lines in the unblocked bus interface and the corresponding data response unit.

[0020] Further, the determining of the free cache line allocated to the current request selectively according to the unblocked bus interface according to the corresponding allocation mode, or the determining of the free cache line allocated to the current request according to the number of free cache lines in the unblocked bus interface and the corresponding data response unit comprises:

[0021] Select one of the unblocked bus interfaces, determine an idle cache line corresponding to the selected unblocked bus interface, and assign it to the corresponding current request;

[0022] Or, determining the data response units corresponding to each unblocked bus interface, and obtaining the priority weight of the corresponding data response unit according to the number of free cache lines in the determined data response unit; wherein the smaller the number of free cache lines in the data response unit, the higher the priority weight of the data response unit;

[0023] According to the determined priority weights of the data response units, one of the unblocked bus interfaces is selected, and an idle cache line corresponding to the selected unblocked bus interface is determined and allocated to the corresponding current request.

[0024] Further, completing the response to all the incomplete requests in the cache line to be released to obtain the free cache line includes:

[0025] Acquire the return data required by the uncompleted request from the cache line to be released, so as to complete the response to the uncompleted request;

[0026] After all outstanding requests in the cache line to be released are processed, the cache line to be released is set to a prepared state, so that the cache line to be released is switched to an idle cache line.

[0027] In a second aspect, the present invention further provides a cache request processing device for dynamic adaptive load balancing, which is used to implement the cache request processing method for dynamic adaptive load balancing described in the first aspect, wherein the cache request processing device for dynamic adaptive load balancing includes a request control unit, a cache line release module, and a data response unit;

[0028] The request control unit is used to determine the cache line to be released according to the number of uncompleted requests, and release the original binding relationship of the cache line to be released;

[0029] The data response unit is used to complete the response to all the uncompleted requests in the cache line to be released, and obtain a free cache line;

[0030] The cache line release module is used to allocate free cache lines to the current request according to the workload of each bus interface, so as to establish a dynamic binding relationship between the free way occupied by the current request and the free cache line, and complete the response to the current request according to the dynamic binding relationship.

[0031] Further, the request control unit includes a group binding control module;

[0032] The group binding control module is used to determine the number of outstanding requests for each cache line and determine whether the number of outstanding requests for each cache line is greater than a first threshold;

[0033] It is also used to determine the cache line as a cache line to be released if there is a cache line with the number of uncompleted requests greater than a first threshold, and release the original binding relationship between the cache line to be released and the corresponding way to be released;

[0034] Also used for determining the number of free cache lines corresponding to the unblocked bus interface if there is no cache line with the number of uncompleted requests greater than the first threshold; and determining whether the number of free cache lines is less than the second threshold;

[0035] It is also used to, when the number of the free cache lines is less than a second threshold, determine a to-be-unbound group according to a preset selection strategy, determine a to-be-released cache line from the to-be-unbound group according to a preset replacement strategy, and release the original binding relationship between the to-be-released cache line and the corresponding to-be-released way.

[0036] Further, the data response unit includes an arbitration module, a data storage module, a sequential processing module and a cache line switching module;

[0037] The arbitration module is used to selectively generate a write request, or generate a read request or an eviction request according to the outstanding request;

[0038] The sequential processing module is used to selectively store the return data of the uncompleted request in the data storage module according to the write request, or obtain the return data from the data storage module according to the read request or the eviction request, so as to complete the response to the uncompleted request;

[0039] The cache line switching module is used to set the cache line to be released to a prepared state after processing all the incomplete requests in the cache line to be released, so that the cache line to be released is switched to an idle cache line.

[0040] Further, the request control unit also includes a data hit check module and a free cache line queue module;

[0041] The free cache line queue module is used to obtain the free cache lines from the cache line release module and store the obtained free cache lines;

[0042] The data hit check module is used to determine whether a dynamic binding relationship needs to be established for the current request; it is also used to obtain the free cache line from the free cache line queue module when a dynamic binding relationship needs to be established between the free way occupied by the current request and the free cache line, so as to respond to the current request according to the dynamic binding relationship.

[0043] Furthermore, the cache line release module is further used to obtain the workload of each bus interface, and determine the bus interface with a workload less than a load threshold as a non-blocked bus interface;

[0044] Also used to select one of the unblocked bus interfaces, determine the free cache line corresponding to the selected unblocked bus interface, and allocate it to the current request;

[0045] It is also used to determine the data response units corresponding to each unblocked bus interface, and obtain the priority weight of the corresponding data response unit according to the number of free cache lines in the determined data response unit; wherein, the fewer the number of free cache lines in the data response unit, the higher the priority weight of the data response unit; according to the determined priority weight of the data response unit, select one of the unblocked bus interfaces, determine the free cache line corresponding to the selected unblocked bus interface, and allocate it to the current request.

[0046] In another optional embodiment, the cache request processing device of dynamic adaptive load balancing includes:

[0047] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor to execute the cache request processing method for dynamic adaptive load balancing described in the first aspect.

[0048] In a third aspect, the present invention further provides a non-volatile computer storage medium, wherein the computer storage medium stores computer executable instructions, which are executed by one or more processors to complete the dynamic adaptive load balancing cache request processing method described in the first aspect.

[0049] In a fourth aspect, a chip is provided, comprising: a processor and an interface, for calling and running a computer program stored in the memory from a memory, and executing the cache request processing method of dynamic adaptive load balancing as in the first aspect.

[0050] In a fifth aspect, a computer program product comprising instructions is provided, which, when executed on a computer or a processor, enables the computer or the processor to execute a cache request processing method with dynamic adaptive load balancing as described in the first to fourth aspects and any one of the aspects.

[0051] In the sixth aspect, a dynamic adaptive load balancing cache request processing method system is provided, comprising a dynamic adaptive load balancing cache request processing device as in the second aspect, and using the dynamic adaptive load balancing cache request processing method as described in the first aspect to complete the interaction of the dynamic adaptive load balancing cache request processing device of the second aspect.

[0052] Different from the prior art, the present invention has at least the following beneficial effects:

[0053] The present invention releases the original binding relationship of the cache line to be released according to the number of unfinished requests; obtains the free cache line by responding to all the unfinished requests in the cache line to be released; allocates the free cache line to the current request according to the workload of each bus interface, so as to establish a dynamic binding relationship between the free way occupied by the current request and the free cache line, and completes the response to the current request according to the dynamic binding relationship; in this process, the unbinding is performed according to the number of unfinished requests, and the free cache line is allocated to the current request for dynamic binding according to the workload of each bus interface, thereby greatly improving the cache performance and versatility, and solving the problem that the cache cannot balance the differences between different cache request numbers, the response speeds of different downstream modules or the delays of returning data of different BIFs due to the fixed binding and one-to-one correspondence between the ways and cache lines of each Cache Bank. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0055] Figure 1 is a schematic diagram of a binding relationship in the prior art provided by an embodiment of the present invention;

[0056] Figure 2 It is a flowchart of a single-address cache request processing method provided by an embodiment of the present invention;

[0057] Figure 3 is a schematic diagram of a first binding relationship provided by an embodiment of the present invention;

[0058] Figure 4 It is a schematic diagram of the architecture of a readable and writable single-address cache request processing device provided by an embodiment of the present invention;

[0059] Figure 5 is a flow chart of step 10 provided in an embodiment of the present invention;

[0060] Figure 6 is a flow chart of step 20 provided in an embodiment of the present invention;

[0061] Figure 7 is a schematic diagram of a second binding relationship provided by an embodiment of the present invention;

[0062] Figure 8 is a schematic diagram of a third binding relationship provided by an embodiment of the present invention;

[0063] Fig. 9 is a flowchart of the first step 201 provided in an embodiment of the present invention;

[0064] Fig.10 It is a schematic diagram of a processing flow of a current request whose command type is normal loading provided by an embodiment of the present invention;

[0065] Fig.11 It is a schematic diagram of a processing flow of a current request of bypassing loading provided by an embodiment of the present invention;

[0066] Fig.12 is a flow chart of the second step 201 provided in an embodiment of the present invention;

[0067] Fig.13 It is a schematic diagram of a processing flow of a current request whose command type is normal storage provided by an embodiment of the present invention;

[0068] Fig.14 is a flowchart of the third step 201 provided in an embodiment of the present invention;

[0069] Fig.15 It is a schematic diagram of a processing flow of a command type of bypassing a stored current request provided by an embodiment of the present invention;

[0070] Fig.16 It is a schematic diagram of a multi-address cache request processing method provided by an embodiment of the present invention;

[0071] Fig.17 is a flow chart of step 40 provided in an embodiment of the present invention;

[0072] Fig.18 is a flow chart of step 50 provided in an embodiment of the present invention;

[0073] Fig.19 is a flow chart of step 60 provided in an embodiment of the present invention;

[0074] Fig. 20 It is a schematic diagram of the architecture of a multi-address cache request processing device provided by an embodiment of the present invention;

[0075] Fig.21 is another flowchart of step 60 provided in an embodiment of the present invention;

[0076] Fig. 22 It is a schematic diagram of a cache request processing method of dynamic adaptive load balancing provided by an embodiment of the present invention;

[0077] Fig.23 It is a schematic diagram of the architecture of a cache request processing device for dynamic adaptive load balancing applicable to single-address requests provided by an embodiment of the present invention;

[0078] Fig.24 It is a schematic diagram of the architecture of a cache request processing device for dynamic adaptive load balancing applicable to multi-address requests provided by an embodiment of the present invention;

[0079] Fig.25 It is a partial architecture diagram of a cache request processing device for dynamic adaptive load balancing provided by an embodiment of the present invention;

[0080] Fig.26 is a flowchart of step 71 provided in an embodiment of the present invention;

[0081] Fig. 27 It is a schematic diagram of a process of releasing an original binding relationship provided by an embodiment of the present invention;

[0082] Fig.28is a flow chart of step 72 provided in an embodiment of the present invention;

[0083] Fig.29 is a flowchart of step 73 provided by an embodiment of the present invention;

[0084] Fig.30 It is a schematic diagram of a flow chart of allocating free cache lines provided by an embodiment of the present invention;

[0085] Fig.31 It is a schematic diagram of the architecture of another single-address cache request processing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0086] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0087] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as open inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner, that is, although they may be carried in the embodiments or examples of the above terms due to reasons such as the order and position of appearance, it is not limited to that they can be carried in combination by one embodiment or example.

[0088] In the description of the present invention, it is necessary to understand that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0089] In the description of the present invention, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "multiple" is two or more. In addition, for example, the same type of nouns may be described as two independent individuals by adding "A" and "B" at the end. In this case, the corresponding features defined as "A" and "B" are only used to distinguish the same type of individuals for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0090] When describing some embodiments, the expressions "coupling", "coupling" and "connection" and their derivatives may be used. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupling" may be used to indicate that two or more components are in direct physical or electrical contact. However, the terms "connection" or "coupling" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other, such as "optical path coupling", "wireless connection", etc. The embodiments disclosed herein are not necessarily limited to the contents of the present invention.

[0091] In the description of the present invention, the expression "A and / or B" (where A and B are used to formally represent specific characteristic contents) will be involved, and the corresponding expressions include the following three combinations: only A, only B, and a combination of A and B.

[0092] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0093] like Figure 1 As shown, in the prior art, the ways and cache lines of the cache are fixedly bound one by one, so the number of ways is equal to the number of cache lines; for example, way 0 is fixedly bound to cache line 0, way 1 is fixedly bound to cache line 1, way 2 is fixedly bound to cache line 2, and way 3 is fixedly bound to cache line 3, and each group has 4 ways and corresponding 4 cache lines.

[0094] In the case of a fixed one-to-one binding between a way and a cache line, if all ways in a group are occupied, and a subsequent cache request requires a new way to be allocated from the group, it can only wait until a released way appears in the group, and then allocate the released way to the cache request. In this case, the number of outstanding requests issued by the cache will be greatly reduced, and the cache cannot process multiple requests at the same time, and the parallel processing capability will be significantly reduced. Since waiting for the allocation of a new way will cause delays, and the number of outstanding requests that the cache can issue has been significantly reduced, the cache cannot process other cache requests in parallel while waiting for a cache request to return data. During this period, the cache is idle, so it cannot issue a large number of outstanding requests to cover the delay of the subsequent module returning data and responding to cache requests, resulting in a lot of waste of computing resources and a significant reduction in cache performance.

[0095] A cache includes multiple cache banks, each of which contains multiple groups and corresponding ways; the cache can be accessed in parallel through each cache bank. Since traditional multi-bank caches generally receive multiple cache requests and have multiple bus interfaces (Bus Interface, abbreviated as BIF) for interacting with the next level. Each cache request is mapped to a fixed cache bank in a certain way, and the ways and cache lines in each cache bank are fixedly bound and one-to-one corresponding, so the cache request passed to the downstream module corresponds to which BIF is also fixed; the downstream module is a module located downstream of the cache, and the cache exchanges data with the downstream module through the BIF.

[0096] When the number of simultaneous cache requests is unevenly distributed in different time periods or between different modules (i.e., the number of multiple cache requests is unbalanced), or the response speeds of downstream modules of multiple BIFs are different (i.e., the response speeds of downstream modules of multiple BIFs are unbalanced), or different BIFs process data at different times, resulting in differences in the time it takes for the requested data to be returned to the Cache (i.e., the latency differences in data returned by multiple BIFs are large), since requests can only be passed to fixed BIFs, the cache lines and BIFs used cannot be flexibly controlled according to actual needs. Therefore, the traditional set-associative Cache cannot balance these differences well, thereby affecting the Cache performance and greatly reducing the versatility of the Cache.

[0097] In addition, since the configuration of the cache can be set to different ratio combinations by weighing the application scenario and performance-power-area (PPA). In actual circuits, static random-access memory (SRAM) is often used in cache. Since the single-bit area of ​​SRAM is generally smaller than the single-bit area of ​​registers, in some processes, the single-bit area of ​​SRAM may differ from the single-bit area of ​​registers by an order of magnitude. Therefore, in some application scenarios, a cache line number of 2 to 3 times the number of ways is a better choice for PPA, but traditional caches cannot support this.

[0098] In order to solve the above problems, Figure 2 As shown, an embodiment of the present invention provides a single-address cache request processing method, including:

[0099] Step 10: Perform a data hit check on the current request to obtain the data status of the data required by the current request.

[0100] Among them, the current request refers to the cache request currently being processed; it should be noted that each current request in the embodiment of the present invention contains an address, and the single-address cache request processing method in the embodiment of the present invention can be widely used in artificial intelligence (AI) processors, graphics processing units (GPUs), general-purpose graphics processors (GPGPUs), neural network processors (NPUs) and other systems. In the case where each current request contains multiple addresses, the multi-address cache request processing method in the embodiment of the present invention described below can be used to solve the above-mentioned problem caused by the fixed one-to-one binding of the way and the cache line.

[0101] The data hit check of the embodiment of the present invention is used to determine whether there is the required data for a current request in the cache. The data status includes a hit status (Hit) and a miss status (Miss). When a device attempts to access a memory address, if a cache line in the cache contains the data corresponding to the address, the current request is in a hit status; this means that the device can read or write data directly from the cache without waiting to read data from the main memory. When a device attempts to access a memory address, if a cache line in the cache does not contain the data corresponding to the address, the current request is in a miss status; in this case, the device must read the data from the main memory.

[0102] Step 20: According to the data state and whether there are free ways in the current group of the current request, selectively establish a dynamic binding relationship between the free ways in the current group and the free cache lines; or, release the original binding relationship of the to-be-replaced ways in the current group, and establish a dynamic binding relationship between the to-be-replaced ways and the free cache lines.

[0103] Among them, an idle way refers to a way that is not occupied by any cache request. An idle cache line refers to a cache line that has not been accessed or updated for a period of time. The method of allocating idle cache lines to idle ways is selected by technical personnel in this field according to the specific usage scenario; in an optional embodiment, the idle cache lines can be determined according to the dynamic adaptive load balancing cache request processing method of the embodiment of the present invention described below, so as to make full use of the external BIF bandwidth and balance the load of each cache line, thereby further improving the cache performance.

[0104] The way to be replaced refers to the way with the original binding relationship. The method of determining the way to be replaced from the current group is selected by those skilled in the art according to the specific usage scenario; in an optional embodiment, the way to be replaced can be determined according to the cache request processing method of the dynamic adaptive load balancing of the embodiment of the present invention described below, so as to release the cache line by releasing the original binding relationship of the way to be replaced, thereby further improving the cache performance. The original binding relationship refers to the binding relationship between the way to be replaced and the cache line to which it is originally bound.

[0105] In the embodiment of the present invention, each way can be mapped to each cache line, and there is a dynamic binding (tag) and unbinding (untag) relationship between the way and the cache line. Figure 3As shown, the original dynamic binding relationship (i.e., original binding relationship) in the current group (i.e., group i) includes: there is an original binding relationship between way 1 and cache line j, there is an original binding relationship between way N and cache line l, there is no original binding relationship between way 0 and way N-1 in the current group, and there is no original binding relationship between cache line h and cache line k. When a current request appears, it can first occupy an idle way, such as way N-1, and allocate an idle cache line to it, such as cache line k, and then establish a dynamic binding relationship between way N-1 and cache line k. When another current request appears, it can also select a to-be-replaced way from the current group, such as way N, so that the current request occupies the to-be-replaced way; since there is an original binding relationship between way N and cache line l, it is necessary to first release the original binding relationship between way N and cache line l; and allocate an idle cache line, such as cache line h, to the current request, and then establish a dynamic binding relationship between way N and cache line h.

[0106] According to the single-address cache request processing method of the embodiment of the present invention, for each way in a group, the way in the group can be unbound from the originally bound cache line before the way in the group is used up and the return data required by the current request occupying the corresponding way is received, and then a free cache line is bound. This not only avoids the situation where all the ways in a group are occupied and the cache request can only wait for the released way in the group to appear, avoiding the generation of this part of the delay, but also ensures that the number of outstanding requests issued by the cache is the number of cache lines of the entire cache.

[0107] Step 30: Complete the response to the current request according to the data state and the corresponding dynamic binding relationship.

[0108] The present invention performs a data hit check on the current request to obtain the data status of the data required by the current request; based on the data status and whether there are idle roads in the current group of the current request, a dynamic binding relationship between the idle roads and idle cache lines in the current group is selectively established; or, the original binding relationship of the road to be replaced in the current group is released, and a dynamic binding relationship between the road to be replaced and the idle cache line is established; according to the data status and the corresponding dynamic binding relationship, the response to the current request is completed. The present invention enables each idle road to be dynamically bound to any idle cache line, and the cache lines of the Cache are used evenly, ensuring that the number of outstanding requests issued by the Cache is equal to the number of cache lines in the entire Cache, thereby greatly reducing the delay of the Cache returning data to the subsequent module, avoiding delays and waste of computing resources when the current request waits for the allocation of a new road, and greatly improving the cache performance.

[0109] In order to better illustrate the single-address cache request processing method of the embodiment of the present invention, Figure 4As shown, the embodiment of the present invention provides a specific example of a Cache structure; the single-address cache request processing method of the embodiment of the present invention will be described below in conjunction with the Cache structure.

[0110] In order to explain the process of data hit checking, Figure 5 As shown, the step 10 includes:

[0111] Step 101: Determine current groups corresponding to multiple current requests respectively.

[0112] like Figure 4 As shown, the Cache can receive multiple current requests, such as current request 0, current request 1, and current request r, etc. Each current request received will pass through the group mapping unit, be mapped to a current group of a request control unit, and then be assigned to the corresponding request control unit.

[0113] Step 102: Obtain the request context ID and request address of the current request in sequence.

[0114] In each request control unit, the current request assigned to the request control unit is first read by the reading module and cached. In an optional embodiment, in order to fully utilize computing resources and improve cache performance in the process of assigning each current request to the request control unit, the reading module can be a "multi-write-one-read" first-in-first-out buffer that can write multiple current requests in one shot and only read out one current request.

[0115] Then, the current request is obtained from the reading module in sequence through the binding relationship search module, and the request context ID and request address carried by the current request are obtained. In order to perform data hit check, it is also necessary to obtain information related to the data hit check of each way in the current group. In an optional embodiment, considering factors such as PPA and timing, the information of the current group in the binding relationship register can be read out in a pipeline manner in multiple cycles through the binding relationship search module.

[0116] Step 103: When the request context ID is equal to the way context ID of any valid way in the current group, and the request address is equal to the way address of the valid way, the data state of the data required by the current request is a hit state.

[0117] Among them, the valid way refers to the way that actually stores valid data or instructions in the current cache state.

[0118] Step 104: When the request context ID is not equal to the way context ID of any valid way in the current group, or the request address is not equal to the way address of the valid way, the data state is a miss state.

[0119] Perform a data hit check on the current request, that is, determine whether the request context ID is equal to the path context ID of any valid path in the current group, and determine whether the request address is equal to the path address of the valid path; when both are equal, the data state of the data required by the current request is a hit state. It should be noted that when performing a data hit check on the current request, only one context ID and address will be equal, or there will be no equal context ID and address; if one is equal, it is a hit state, otherwise it is a miss state.

[0120] In order to explain the process of establishing or releasing a dynamic binding relationship, Figure 6 As shown, the step 20 includes:

[0121] Step 201: Determine whether a dynamic binding relationship needs to be established based on the command type of the current request and the data status.

[0122] Generally, all command types of Cache can be roughly divided into: normal load (NORMAL_LD), bypass load (BYPASS_LD), normal store (NORMAL_ST) and bypass store (BYPASS_ST), as well as refresh (FLUSH), invalidate (INVALIDATE), refresh and invalidate (FLUSH_INV) and barrier (Barrier), etc. In addition, there are requests for atomic operations. For current requests with command types of normal load, bypass load, normal store and bypass store, it often involves operations such as establishing dynamic binding relationships or releasing original binding relationships. The specific processing methods under different command types and different data states will be explained below; for current requests with command types of refresh, invalidate, refresh and invalidate and barrier, the current request will be broadcast to all Cache Banks, and refresh or invalidate all or part of the cache lines; for current requests of atomic operations, Cache only passes the current request to the downstream module.

[0123] Step 202: When a dynamic binding relationship needs to be established, it is determined whether there is an idle path in the current group of the current request.

[0124] Step 203: when there is an idle way, allocate an idle way and an idle cache line to the current request, and establish a dynamic binding relationship between the idle way and the idle cache line.

[0125] For example, Figure 7As shown, there is an idle way N-1 in the current group (i.e., group i), and cache lines k and m are in an idle state, so the current request can occupy the way N-1, and select an idle cache line, such as cache line k, to establish a dynamic binding relationship between the way N-1 and the cache line k. The method of selecting an idle cache line from multiple idle cache lines is selected by those skilled in the art according to the specific usage scenario.

[0126] Step 204: when there is no free way, obtain a to-be-replaced way from the current group, release the original binding relationship of the to-be-replaced way, make the current request occupy the to-be-replaced way, allocate a new free cache line for the current request, and establish a dynamic binding relationship between the to-be-replaced way and the new free cache line.

[0127] For example, Figure 8 As shown, there is no free way in the current group (i.e., group i), and cache line m is in an idle state; therefore, a way to be replaced is first selected from the current group, such as way N, but since there is an original binding relationship between way N and cache line l, when it is necessary to allocate a way for the current request, the original binding relationship between way N and cache line l is first released, and then the current request occupies way N, and a new free cache line is allocated to the current request, such as cache line m, to establish a dynamic binding relationship between way N and cache line m.

[0128] The following describes the specific processing methods for different command types and different data states for current requests and whether a dynamic binding relationship needs to be established.

[0129] When the command type is normal load, the current request needs to read the data in the cache. When the data status is a miss, the cache will read the return data from the downstream module, store it in the cache, and return it to the current request; when the data status is a hit, the data in the cache will be directly returned to the current request; Fig. 9 As shown, step 201 includes:

[0130] Step 2011a: When the data state is a miss state, a dynamic binding relationship is established between the free ways and free cache lines in the current group, the cache lines in the dynamic binding relationship are determined as cache lines for processing the current request, and the current request and the corresponding cache line ID are sent to the miss module.

[0131] In an optional embodiment, if Fig.10 As shown, when the command type is normal loading, the current request is processed according to the following specific control logic:

[0132] When the data status is a miss state and there is a free cache line corresponding to the current group, an idle way and an idle cache line are allocated to the current request, and a dynamic binding relationship between the two is established. The cache line in the dynamic binding relationship is determined as the cache line for processing the current request, and the current request and the cache line ID of the cache line are sent to the request bus module. A miss read request (miss read) is sent to the BIF through the request bus module to use the cache line according to the cache line ID to obtain the return data required for the current request.

[0133] When the data state is a miss state, the corresponding current group has no free cache line, and the way to be replaced is in a dirty state, first unbind the original binding relationship of the way to be replaced, evict the cache line in the original binding relationship, and obtain a new free way; wherein, after the original binding relationship is released, the corresponding cache line generally takes a certain amount of time to become a free cache line, and the way to be replaced can immediately become a new free way, and then the new free way is assigned to the current request, and a free cache line is assigned to the current request, and a dynamic binding relationship between the two is established, and the cache line in the dynamic binding relationship is determined as the cache line for processing the current request, and the cache line ID of the current request and the cache line is sent to the request bus module, and a miss read request is sent to the BIF through the request bus module to use the cache line according to the cache line ID to obtain the return data required for the current request. It should be noted that when there is no free cache line in the current group, first determine a way to be replaced from the current group, and then determine whether the way to be replaced is in a dirty state. Among them, the dirty state means that a cache line that has a binding relationship with the way contains data that has been modified but has not yet been written back to the main memory.

[0134] When the data status is a miss state, there is no free cache line in the corresponding current group and the way to be replaced is not in a dirty state, first unbind the original binding relationship of the way to be replaced; then allocate an free cache line to the free way, establish a dynamic binding relationship between the two, determine the cache line in the dynamic binding relationship as the cache line for processing the current request, send the current request and the cache line ID of the cache line to the request bus module, and send a miss read request to the BIF through the request bus module to use the cache line according to the cache line ID to obtain the return data required for the current request.

[0135] Step 2012a: When the data state is a hit state, the current request and the corresponding cache line ID are sent to a hit module without establishing a dynamic binding relationship.

[0136] In an optional embodiment, if Fig.10As shown, if the data status is a hit status and the hit way can be used directly, the read current request is sent to the hit module; otherwise, the current request is processed according to the steps when the data status is a miss status. The hit way refers to: when performing a data hit check, the way context ID is equal to the request context ID of the current request, and the way address is equal to the request address.

[0137] When the data status is a hit status and the required return data is in a prepared status, the current request is an outstanding request, the number of outstanding requests for the cache line is increased according to the cache line ID, and the return data is obtained from the data response unit. The prepared status means that the corresponding cache line contains read data, or there is no data that has not been returned from the BIF.

[0138] When the data state is a hit state and the required return data is an unready state, first release the original binding relationship of the hit valid way to obtain the corresponding idle way, then allocate an idle cache line to the idle way, establish a dynamic binding relationship between the two, determine the cache line in the dynamic binding relationship as the cache line for processing the current request, send the current request and the cache line ID of the cache line to the request bus module, and send a miss read request to the BIF through the request bus module to use the cache line according to the cache line ID to obtain the return data required for the current request. Among them, the unready state means that the corresponding cache line does not contain read data, or there is data that has not been returned from the BIF.

[0139] When the command type is bypass loading, the current request needs to read data from the downstream module. When the data status is a miss state, the cache will read the data back from the downstream and store it in the cache, and return it to the current request; when the data status is a hit state, the hit cache line storing the data is first invalidated, and then the data is read back from the downstream module and stored in the cache, and returned to the current request. The step 201 includes:

[0140] A dynamic binding relationship between the idle ways and the idle cache lines in the current group is established, the cache lines in the dynamic binding relationship are determined as the cache lines for processing the current request, and the current request and the corresponding cache line ID are sent to the request bus module. That is, regardless of whether the data state is a hit state or a miss state, the current request is sent to the request bus module; wherein the request bus module is a request bus module in the request control unit that performs a data hit check on the current request. An idle way and an idle cache line are allocated to the current request, and a dynamic binding relationship between the two is established.

[0141] In an optional embodiment, if Fig.11 As shown in the figure, when the command type is to bypass loading, the current request is processed according to the following specific control logic:

[0142] When the data status is a miss state, the processing steps in the corresponding situation are the same as when the command type is normal load and the data status is a miss state; when the data status is a hit state and the required return data is not ready, the processing steps in the corresponding situation are the same as when the command type is normal load, the data status is a miss state and the required return data is not ready.

[0143] When the data status is a hit state and the required return data is in a prepared state, the original binding relationship between the hit way and the hit cache line is first released; wherein, when the hit cache behavior performs a data hit check, the cache line that has an original binding relationship with the hit way; if the hit cache behavior is in a dirty state, the hit cache line is evicted. Then, an idle cache line is allocated to the idle way obtained by unbinding, and a dynamic binding relationship between the two is established. The cache line in the dynamic binding relationship is determined as the cache line for processing the current request, and the cache line ID of the current request and the cache line is sent to the request bus module. A miss read request is sent to the BIF through the request bus module to use the cache line according to the cache line ID to obtain the return data required for the current request.

[0144] When the command type is normal storage, the current request needs to store the write data in the cache. When the data status is a miss state, the cache stores the write data in a new free cache line; when the data status is a hit state, according to the cache architecture, in different situations, the cache can store the write data in a hit cache line or in a new free cache line; Fig.12 As shown, step 201 includes:

[0145] Step 2011b: When the data state is a miss state, a dynamic binding relationship is established between the free ways and free cache lines in the current group, the cache lines in the dynamic binding relationship are determined as cache lines for processing the current request, and the current request and the corresponding cache line ID are sent to the hit module.

[0146] In an optional embodiment, if Fig.13 As shown, when the command type is normal storage, the current request is processed according to the following specific control logic:

[0147] When the data state is a miss state and there is a free cache line corresponding to the current group, first allocate an idle way and an idle cache line, establish a dynamic binding relationship between the two, determine the cache line in the dynamic binding relationship as the cache line for processing the current request, send the current request and the cache line ID of the cache line to the hit module, and store the return data in the free cache line in the data storage module.

[0148] When the data state is a miss state and the corresponding current group has no free cache line, first unbind the original binding relationship of the way to be replaced to obtain a new free way and a new free cache line; if the way to be replaced is in a dirty state, the cache line in the original binding relationship must be evicted; then allocate a free way and a free cache line, establish a dynamic binding relationship between the two, determine the cache line in the corresponding dynamic binding relationship as the cache line for processing the current request, send the current request and the cache line ID of the cache line to the hit module, and store the return data in the free cache line in the data storage module.

[0149] Step 2012b: When the data state is a hit state and the data required in the hit cache line is in an unprepared state, the original binding relationship between the hit cache line and the hit way is released, and a dynamic binding relationship between the hit way and the free cache line is established. The cache line in the dynamic binding relationship is determined as the cache line for processing the current request, and the current request and the corresponding cache line ID are sent to the hit module.

[0150] Step 2013b: When the data state is a hit state, the data required in the hit cache line is in a prepared state, and there is no outstanding request in the hit cache line, the current request and the corresponding cache line ID are sent to the miss module without establishing a dynamic binding relationship.

[0151] Step 2014b: When the data state is a hit state, the data required in the hit cache line is in a prepared state, and there is an uncompleted request in the hit cache line, the current request and the corresponding cache line ID are sent to the hit module without establishing a dynamic binding relationship.

[0152] When the data state is a hit state, and the data required in the hit cache line is in a prepared state, the number of outstanding requests of the hit cache line is increased according to the cache line ID, and the returned data is obtained from the data response unit.

[0153] When the data state is a hit state, and the data required in the hit cache line is in an unprepared state, the original binding relationship between the hit way and the hit cache line is first released to obtain the corresponding free way; then an free cache line is allocated to the free way, and a dynamic binding relationship between the two is established. The cache line in the dynamic binding relationship is determined as the cache line for processing the current request, the current request and the cache line ID of the cache line are sent to the hit module, and the returned data is stored in the free cache line.

[0154] When the command type is bypass storage, the current request needs to pass the write data to the downstream module. When the data status is a miss, the cache directly passes the write data to the downstream module; when the data status is a hit, the hit cache line is invalidated first, and then the write data is passed to the downstream module; whether the cache saves the write data is determined by the cache architecture; Fig.14 As shown, step 201 includes:

[0155] Step 2011c: When the data status is a miss status, a dynamic binding relationship is established between the free ways and free cache lines in the current group, the cache lines in the dynamic binding relationship are determined as cache lines for processing the current request, the current request and the corresponding cache line ID are sent to the request bus module, and the write data of the current request is sent to the bypass data bus module.

[0156] In an optional embodiment, if Fig.15 As shown in the figure, when the command type is to bypass storage, the current request is processed according to the following specific control logic:

[0157] When the data status is a miss state and the corresponding current group has a free cache line, the current request is first sent to the request bus module; then an idle way and an idle cache line are allocated, and a dynamic binding relationship between the two is established. The cache line in the dynamic binding relationship is determined as the cache line for processing the current request, and the cache line ID and write data of the cache line are sent to the bypass data bus module to be sent to the data response module through the BIF, and the return data required for the current request is obtained from the BIF, and stored in the data storage module according to the cache line ID.

[0158] When the data state is a miss state and the corresponding current group has no free cache line, first unbind the original binding relationship of the to-be-replaced way to obtain the corresponding free way and free cache line; if the to-be-replaced way is in a dirty state, the cache line in the original binding relationship must also be evicted; then the current request is sent to the request bus module; then a free cache line is allocated to the free way, a dynamic binding relationship between the two is established, the cache line in the dynamic binding relationship is determined as the cache line for processing the current request, the cache line ID and write data of the cache line are sent to the bypass data bus module, so as to be sent to the data response module through the BIF, the return data required for the current request is obtained from the BIF, and stored in the data storage module according to the cache line ID.

[0159] Step 2012c: When the data status is a hit status, obtain the hit way corresponding to the current request, obtain the original binding relationship of the hit way, and release the original binding relationship; establish a dynamic binding relationship between the hit way and the free cache line, determine the cache line in the dynamic binding relationship as the cache line for processing the current request, send the current request and the corresponding cache line ID to the request bus module, and send the write data of the current request to the bypass data bus module.

[0160] When the data state is a hit state, the original binding relationship between the hit cache line and the hit way is first released, and an evict request is sent to the miss module, and then the corresponding steps when the data state is a miss state are executed.

[0161] In an optional embodiment, if Fig.15 As shown, when the data state is a hit state, the original binding relationship between the hit way and the hit cache line is first released to obtain the corresponding free way; when the required return data is in a prepared state and the hit cache line is in a dirty state, the hit cache line must also be evicted. Then, an idle cache line is allocated to the idle way, a dynamic binding relationship between the two is established, the cache line in the dynamic binding relationship is determined as the cache line for processing the current request, the cache line ID and write data of the cache line are sent to the bypass data bus module, so as to be sent to the data response module through the BIF, the return data required for the current request is obtained from the BIF, and stored in the data storage module according to the cache line ID.

[0162] like Figure 4As shown, after the current request is classified and processed by the request control module according to the above steps, since the dynamic binding relationship corresponding to the current request has been determined by the data hit check module, the cache line used to process the current request is known, so that the current request carries the corresponding cache line ID, and the current request and the cache line ID are sent to the data response unit through the hit module or the miss module. When processing each current request, the data response unit uses the corresponding cache line in the data storage module to obtain or write the return data according to the cache line ID carried by it to respond to the current request; wherein the data storage module is divided into multiple cache lines; in an optional embodiment, a data reading module can be set downstream of the data storage module, and the data reading module is a first-in-first-out register. The current request in the request bus module that belongs to the miss state generates a corresponding miss read request after arbitration, and is sent from a BIF to the downstream module; after a delay, the read data corresponding to the miss read request is returned to the corresponding data response unit from the corresponding BIF interface in a sequential or non-sequential manner. After arbitration, the hit module or miss module of each request control unit distributes the current request stored in itself to each corresponding data response unit. The arbitration module in the data response unit arbitrates the return data obtained from the BIF, the return data obtained from the current request in the miss module, and the return data obtained from the current request in the hit module according to a certain priority, and generates a corresponding request. The sequential processing module in the data response unit can process the write request, read request and eviction request generated by the arbitration module in a first-in-first-out order; if a write request is generated after arbitration, the corresponding write data is written into the data storage module; if a read request or an eviction request is generated, the return data is read out from the data storage module; when reading the return data from the data storage module, the corresponding return data can be first stored in the data reading module, and then the return data of the read request is sent to the corresponding return data interface through the exchange unit (Cross Bar) through the data reading module; wherein, the return data of each current request is sent to the corresponding return data interface; when processing an eviction request, the corresponding return data is written into the eviction data bus module in the request control unit that processes the current request. It should be noted that, under the control of the command type in the request bus module, the command type is to bypass the current request stored in the request bus module, and the corresponding write data in the bypass data bus module, and send them to the corresponding BIF after arbitration; the eviction request sends the write request in the request bus module and the data required to be expelled from the data bus module to the BIF.

[0163] It is worth noting that the present invention separates the process of establishing a dynamic binding relationship from the process of responding to the current request; first, the request control unit establishes a dynamic binding relationship for each current request in turn to determine the cache line used by the corresponding current request; then, in the data response unit, the current request and return data are received, and the response is completed according to the cache line used by the current request; when the current request is sent to the miss module or the hit module, the cache line used by the current request has been determined, and after the corresponding dynamic binding relationship is released, the cache line can also be used until the response to the current request is completed, so the dynamic binding relationship of the current request can be untied at this time, and there is no need to wait for the data response module to complete processing the current request, which can greatly improve the efficiency of Cache processing requests and greatly improve Cache performance.

[0164] And in actual use, the current requests with data status of miss state are often more than the current requests with hit state. After checking the data status of the current request, the prior art stores all the current requests in the same first-in-first-out module in the order of acquisition, and then acquires and processes each current request in sequence from the first-in-first-out module in the order of storage. In this case, for the current request in miss state, the following three steps are required: step (1) sending the current request from the data hit check module to the request bus module, step (2) generating the corresponding miss read request after arbitration, and step (3) BIF responding to the miss read request and returning data; the external delay of obtaining the return data from BIF through this process is often large, and the external delay needs to be measured in hundreds of petabytes (PB) of data. Since the current request in the hit state can be processed immediately, it cannot be processed in time because the first-in-first-out module has to process the current request in sequence; especially when the current request before it is in the miss state, the current request in the hit state cannot be processed until the request is completed, resulting in a large cache delay in the prior art, and many modules in the cache need to wait for BIF to obtain return data before they can start working, resulting in a waste of computing resources.

[0165] The present invention divides the current requests with different data states into miss modules and hit modules, and processes them separately, so that the current request in the hit state does not need to wait for multiple current requests in the miss state before it in the acquisition order, which greatly reduces the delay of this part and can make full use of computing resources.

[0166] In a Single Instruction Multiple Data (SIMD) or Single Instruction Multiple Threads (SIMT) processor or system, each cache request contains multiple addresses. The command and data length of each cache request are the same. The return data of multiple addresses carried by the same cache request need to be returned together. In order to be applicable to SIMD or SIMT systems, such as Fig.16 As shown, an embodiment of the present invention provides a multi-address cache request processing method, including:

[0167] Step 40: Allocate each sub-request in the current request to a different request control unit.

[0168] The current request refers to the cache request currently being processed; it should be noted that each current request in the embodiment of the present invention includes multiple addresses, and a current request may include multiple sub-requests, and each address corresponds to a sub-request.

[0169] Step 50: The request control unit selectively establishes a dynamic binding relationship between the idle ways in the current group and the idle cache lines according to the data status of the sub-request and whether there are idle ways in the current group of the sub-request; or, releases the original binding relationship of the way to be replaced in the current group, and establishes a dynamic binding relationship between the way to be replaced and the idle cache lines; and determines the cache lines used by the sub-request according to the dynamic binding relationship.

[0170] Step 60: Send the sub-request to the corresponding data response unit, respond to the sub-request according to the data status and the corresponding cache line, and complete the response to the current request.

[0171] When each sub-request in the current request is sent to the corresponding data response unit, the next current request is continuously obtained so as to process multiple current requests.

[0172] The present invention allocates each sub-request in the current request to different request control units, and selectively establishes a dynamic binding relationship between the idle way and the idle cache line in the current group according to the data status of the sub-request and whether there is an idle way in the current group of the sub-request, and / or releases the original binding relationship of the way to be replaced in the current group to determine the cache line used by the sub-request; responds to each sub-request based on the data status and the corresponding cache line; wherein, when each sub-request in the current request is sent to the corresponding data response unit, the next current request is obtained, and multiple return data of the same current request are returned together, and at the same time, the number of outstanding requests issued by the cache is equal to the number of cache lines in the entire cache, thereby greatly reducing the sensitivity of the cache to the delay of returning data from the subsequent module, and solving the problem that the cache performance is greatly reduced because the number of outstanding requests that can be issued by the cache cannot cover the delay of the response of the subsequent module.

[0173] To illustrate the process of allocating each sub-request, Fig.17 As shown, the step 40 includes:

[0174] Step 401: Acquire multiple request addresses carried in the current request, convert the current request into multiple sub-requests according to the multiple request addresses, and determine the current groups corresponding to the multiple sub-requests respectively.

[0175] Step 402: Allocate the sub-request to a corresponding request control unit according to the request address of the sub-request, and establish a first mapping relationship between the sub-request and the request control unit.

[0176] In order to explain the process of determining whether to establish a dynamic binding relationship for a sub-request, Fig.18 As shown, in step 50, the request control unit selectively establishes a dynamic binding relationship between the idle ways in the current group and the idle cache lines according to the data state of the sub-request and whether there are idle ways in the current group of the sub-request; or, releases the original binding relationship between the ways to be replaced in the current group, and establishes a dynamic binding relationship between the ways to be replaced and the idle cache lines, including:

[0177] Step 501: Match the request context ID of the sub-request with the way context ID of any valid way in the current group, and the request address of the sub-request with the way address of the valid way, and selectively determine whether the data state is a hit state or a miss state.

[0178] Step 502: Determine whether a dynamic binding relationship needs to be established according to the command type of the sub-request and the data status.

[0179] Step 503: When a dynamic binding relationship needs to be established, it is determined whether there is an idle path in the current group of the sub-request.

[0180] Step 504: when there is a free way, allocate an free way and a free cache line to the sub-request, and establish a dynamic binding relationship between the free way and the free cache line; when there is no free way, obtain a to-be-replaced way from the current group, release the original binding relationship of the to-be-replaced way, make the sub-request occupy the to-be-replaced way, allocate a new free cache line to the sub-request, and establish a dynamic binding relationship between the to-be-replaced way and the new free cache line.

[0181] In the multi-address cache request processing method of the embodiment of the present invention, the processing flow of determining whether to establish a dynamic binding relationship for a sub-request based on sub-requests of different data states and command types is the same as the processing flow of determining whether to establish a dynamic binding relationship for a current request based on current requests of different data states and command types in the single-address cache request processing method of the embodiment of the present invention, and will not be repeated here.

[0182] In order to illustrate the process of the request control module processing multiple sub-requests of the current request, as shown in Fig.19 As shown, in step 60, sending the sub-request to the corresponding data response unit includes:

[0183] Step 601a: According to the first mapping relationship, obtain the sub-request from the corresponding request control unit.

[0184] like Fig. 20 The figure shows a specific example of a cache structure provided by an embodiment of the present invention. One current request corresponds to one control mapping unit, and the control mapping unit is used to store all first mapping relationships of the corresponding current request. One current request corresponds to one lock-step control unit, and one current request corresponds to one request module.

[0185] Step 602a: Determine a data response unit that processes the sub-request, and establish a second mapping relationship between the sub-request and the data response unit.

[0186] One current request corresponds to one return mapping unit, and the return mapping unit is used to store all the second mapping relationships corresponding to the current request.

[0187] Step 603a: According to the second mapping relationship, send the sub-request to the corresponding data response unit.

[0188] Each lock-step control unit takes out each sub-request from the corresponding request module according to the first mapping relationship of all sub-requests of the current request, and sends it to the corresponding data response unit after arbitration. The lock-step control unit ensures that each sub-request of a valid address of a current request is sent to the corresponding data response unit before continuing to read out the sub-request of the next current request from the control mapping unit and starting processing.

[0189] After each sub-request is sent to the data response unit according to the second mapping relationship, Fig.21 As shown, in step 60, responding to the sub-request according to the data state and the corresponding cache line to complete the response to the current request includes:

[0190] Step 601b: when the data status is a hit status, obtaining return data from the cache line used by the sub-request; according to the second mapping relationship, obtaining the return data from the corresponding data response unit, and sending the return data to the return data interface corresponding to the current request.

[0191] When the data status is a hit status, the arbitration module generates a read request or an eviction request, and the sequential sending module obtains the return data from the corresponding cache line in the data storage module. Then the response module obtains the second mapping relationship of the sub-request from the return mapping unit, and according to the second mapping relationship, sends the return data obtained from the cache line to the return data interface corresponding to the current request, responding to the generated read request or eviction request to complete the response to the sub-request; in an optional embodiment, the return data interface can be set with multiple sub-interfaces, so that the response module can send the return data of the sub-request to the corresponding sub-interface.

[0192] Step 602b: When the data state is a miss state, based on the sub-request, the returned data is stored in the cache line used by the sub-request; and according to the second mapping relationship, a storage success signal is sent to the corresponding returned data interface. The storage success signal is a signal used to indicate that the returned data is successfully stored in the cache line used by the sub-request.

[0193] When the data state is a miss state, the arbitration module generates a write request, and the sequential sending module stores the returned data. Then the response module obtains the second mapping relationship of the sub-request from the return mapping unit, and according to the second mapping relationship, sends a storage success signal to the return data interface corresponding to the current request, responds to the generated write request, and completes the response to the sub-request.

[0194] The control mapping unit ensures that all sub-requests of each request address of the current request are sent to each data response unit before continuing to read the second mapping relationship of the next sub-request from the control mapping unit and starting to process the next sub-request.

[0195] In the multi-address cache request processing method of the embodiment of the present invention, the processing flow of the data response unit processing each sub-request is different from the processing flow of the data response unit processing each current request in the single-address cache request processing method of the embodiment of the present invention in that the arbitration module in the data response unit arbitrates the return data obtained from the BIF and the return data obtained from the current request in each request module according to a certain priority, and generates corresponding read requests, write requests and eviction requests; other than that, the remaining processing steps are the same and will not be repeated here.

[0196] The return mapping unit ensures that the read request, write request or eviction request of each sub-request in each data response unit is executed before processing the next sub-request of the current request. Each return data interface is used to return the return data (ie, read data) of multiple addresses of the current request.

[0197] It is worth noting that Fig. 20 As shown, when the group mapping unit assigns both the current request 1 and the current request r to the request control unit 1 for processing, the reading module can cache the current request 1 and the current request r at the same time. Since the binding relationship search module reads one current request from the reading module each time, when the current request 1 is read first and then the current request r is read, the data hit check module will first perform a data hit check on each sub-request of the current request 1, and then send the corresponding sub-request to the request module of the current request 1. Since each request control unit of the present invention only processes one multi-address current request each time, that is, the request control unit 1 needs to send all sub-requests of the current request 1 to the request module before the data hit check module can perform a data hit check on each sub-request of the current request r; therefore, even if the current request 1 and the current request r have the same request address, the current request 1 and the current request r are processed in sequence, and there will be no errors in the data in the cache rows corresponding to the corresponding request addresses.

[0198] Based on the above single-address cache request processing method and multi-address cache request processing method, the embodiment of the present invention also provides a dynamic adaptive load balancing cache request processing method, which can dynamically and adaptively adjust the load of each cache line according to the BIF and the load of each cache line, determine the cache line to be released, and release the binding relationship of the cache line to be released. After completing the response, the cache line to be released is changed back to an idle cache line. Fig. 22 As shown, including:

[0199] Step 71: determining the cache lines to be released according to the number of uncompleted requests, and releasing the original binding relationship of the cache lines to be released.

[0200] like Fig.23FIG. 4 is a specific example of a cache structure applicable to a single address request provided by an embodiment of the present invention; Fig.24 The figure shows a specific example of a cache structure suitable for multi-address requests provided by an embodiment of the present invention. The group binding control module is used to determine the way to be replaced from the current group. The group binding control module adaptively releases the original binding relationship of certain cache lines according to the number of uncompleted requests of each cache line and the number of free cache lines in the data response unit corresponding to the unblocked BIF, thereby gradually releasing the corresponding cache lines.

[0201] Step 72: Complete responses to all outstanding requests in the cache line to be released, and obtain a free cache line.

[0202] Step 73: Allocate free cache lines for the current request according to the workload of each bus interface, so as to establish a dynamic binding relationship between the free ways occupied by the current request and the free cache lines, and complete the response to the current request according to the dynamic binding relationship.

[0203] Among them, according to step 72, the cache line to be released can be changed to a free cache line to increase the number of free cache lines; the free cache line in step 73 is selected from multiple free cache lines, which can be a free cache line just released, a free cache line released before, or a free cache line that has never been occupied.

[0204] like Fig.25 As shown, each request control module can be allocated some free cache lines by the cache line release module; the selection module in the data response unit determines the allocated free cache lines, and passes the cache line ID of the free cache line to the cache line release module; in an optional embodiment, the selection module can determine the free cache lines according to the reading order. The embodiment of the present invention comprehensively considers the congestion of BIF, the number of free cache lines in each data response unit, etc., and performs balanced allocation. In this way, the external BIF bandwidth is fully utilized, and the cache lines in each data response unit can be used evenly, thereby improving the tolerance of the cache to each request and BIF emergency, balancing the load of each cache line, and thus improving the overall performance of the cache.

[0205] The present invention releases the original binding relationship of the cache line to be released according to the number of unfinished requests; obtains the free cache line by responding to all the unfinished requests in the cache line to be released; allocates the free cache line to the current request according to the workload of each bus interface, so as to establish a dynamic binding relationship between the free way occupied by the current request and the free cache line, and completes the response to the current request according to the dynamic binding relationship; in this process, the unbinding is performed according to the number of unfinished requests, and the free cache line is allocated to the current request for dynamic binding according to the workload of each bus interface, thereby greatly improving the cache performance and versatility, and solving the problem that the cache cannot balance the differences between different cache request numbers, the response speeds of different downstream modules or the delays of returning data of different BIFs due to the fixed binding and one-to-one correspondence between the ways and cache lines of each Cache Bank.

[0206] It should be noted that the cache request processing method of dynamic adaptive load balancing in the embodiment of the present invention is applicable to single-address requests and multi-address requests, and the embodiment of the present invention is described by taking a single-address request as an example.

[0207] In order to ensure the number of free cache lines in each data response unit, such as Fig.26 and Fig. 27 As shown, step 71 includes:

[0208] Step 711: Determine the number of outstanding requests for each cache line, and determine whether the number of outstanding requests for each cache line is greater than a first threshold.

[0209] The first threshold is selected by those skilled in the art based on specific usage scenarios and experience, and is not limited here.

[0210] Step 712: If there is a cache line with the number of uncompleted requests greater than the first threshold, the cache line is determined as a cache line to be released, and the original binding relationship between the cache line to be released and the corresponding way to be released is released.

[0211] Step 713: If there is no cache line with the number of uncompleted requests greater than the first threshold, determine the number of free cache lines corresponding to the unblocked bus interface; and determine whether the number of free cache lines is less than the second threshold.

[0212] The second threshold is selected by a person skilled in the art based on specific usage scenarios and experience, and is not limited here. When the number of free cache lines corresponding to an unblocked bus interface is less than the second threshold, it indicates that the load of the unblocked bus interface and the free cache line is small. In order to balance the load of each cache line in the Cache, the embodiment of the present invention gives priority to allocating free cache lines with smaller loads when establishing a new dynamic binding relationship.

[0213] Step 714: When the number of free cache lines is less than a second threshold, determine a to-be-unbound group according to a preset selection strategy, determine a to-be-released cache line from the to-be-unbound group according to a preset replacement strategy, and release the original binding relationship between the to-be-released cache line and the corresponding to-be-released way.

[0214] The preset selection strategy is selected by those skilled in the art according to the specific usage scenario. In an optional embodiment, the to-be-unbound group may be selected in the reading order. The preset replacement strategy is selected by those skilled in the art according to the specific usage scenario. In an optional embodiment, the preset replacement strategy may use the least recently used (Least Recently Used, abbreviated as LRU) algorithm.

[0215] On the basis of ensuring the number of free cache lines, in order to explain the process of obtaining free cache lines after unbinding the relationship, such as Fig.28 As shown, step 72 includes:

[0216] Step 721: Obtain the return data required by the outstanding request from the cache line to be released, so as to complete the response to the outstanding request.

[0217] Among them, the unfinished request is the current request that the data response unit has not yet completed responding to; in an optional embodiment, the corresponding processing steps of the data response unit in the single-address cache request processing method of an embodiment of the present invention, or the multi-address cache request processing method of an embodiment of the present invention, can complete the response to the unfinished request.

[0218] Step 722: After processing all outstanding requests in the cache line to be released, set the cache line to be released to a prepared state, so that the cache line to be released is switched to an idle cache line.

[0219] Each time a response to an outstanding request of the cache line to be released is completed, the number of outstanding requests of the cache line to be released is reduced by one; when the number of outstanding requests of the cache line to be released is 0, the cache line to be released is released to obtain a corresponding free cache line.

[0220] In order to allocate free cache lines to corresponding request control units, such as Fig.29 and Fig.30 As shown, step 73 includes:

[0221] Step 731: Obtain the workload of each bus interface, and determine the bus interface whose workload is less than the load threshold as a non-blocked bus interface.

[0222] The load threshold is selected by those skilled in the art based on specific usage scenarios and experience, and is not limited here.

[0223] Step 732: According to the corresponding allocation mode, selectively determine the free cache line allocated to the current request based on the unblocked bus interface, or determine the free cache line allocated to the current request based on the number of free cache lines in the unblocked bus interface and the corresponding data response unit.

[0224] The embodiment of the present invention provides two allocation modes, which are as follows:

[0225] The first mode: selecting one of the unblocked bus interfaces, determining the free cache line corresponding to the selected unblocked bus interface, and allocating the free cache line to the corresponding current request.

[0226] In an optional embodiment, a round robin algorithm may be used to select an unblocked bus interface from all unblocked bus interfaces (ie, unblocked BIFs).

[0227] The second mode: determine the data response units corresponding to each unblocked bus interface, and obtain the priority weight of the corresponding data response unit according to the number of free cache lines in the determined data response unit; wherein, the fewer the number of free cache lines in the data response unit, the higher the priority weight of the data response unit. According to the determined priority weight of the data response unit, select one of the unblocked bus interfaces, determine the free cache line corresponding to the selected unblocked bus interface, and allocate it to the corresponding current request.

[0228] The present invention can dynamically and adaptively adjust the load of the data response unit and the request sent to each BIF according to the load conditions of each data response unit and BIF, thereby using each data response unit and BIF more evenly, avoiding performance loss introduced by these imbalances, and improving instantaneous and overall performance.

[0229] The embodiment of the present invention also provides a cache request processing device with dynamic adaptive load balancing, such as Fig.19 As shown, the cache request processing device of the dynamic adaptive load balancing according to the embodiment of the present invention can implement the cache request processing method of the dynamic adaptive load balancing according to the embodiment of the present invention based on the hardware pipeline of the cache request processing device of the dynamic adaptive load balancing according to the embodiment of the present invention and the software operation logic for controlling the hardware pipeline.

[0230] In a possible implementation, the cache request processing device with dynamic adaptive load balancing includes a request control unit, a cache line release module, and a data response unit.

[0231] The request control unit is used to determine the cache line to be released according to the number of uncompleted requests, and release the original binding relationship of the cache line to be released.

[0232] The data response unit is used to complete the response to all the uncompleted requests in the cache line to be released, and obtain a free cache line.

[0233] The cache line release module is used to allocate free cache lines to the current request according to the workload of each bus interface, so as to establish a dynamic binding relationship between the free way occupied by the current request and the free cache line, and complete the response to the current request according to the dynamic binding relationship.

[0234] The cache solution proposed in the embodiment of the present invention supports single or multiple cache bank designs, separates the functions of controlling binding relationships from those of controlling cache lines and data, uses a request control unit to control the binding relationship, and uses a data response unit for control; both the request control unit and the data response unit can be configured independently.

[0235] The request control unit has a binding relationship register, which is divided into multiple ways, each of which is used to store the binding relationship corresponding to the data of one or more cache lines. The data response unit has a data storage module, which includes multiple cache lines and is used to store the data of one or more cache lines written into the cache.

[0236] In one embodiment, the request control unit includes a group binding control module. The group binding control module is used to determine the number of outstanding requests for each cache line, and to determine whether the number of outstanding requests for each cache line is greater than a first threshold. It is also used to determine the cache line as a cache line to be released if there is a cache line with a number of outstanding requests greater than the first threshold, and to release the original binding relationship between the cache line to be released and the corresponding way to be released. It is also used to determine the number of free cache lines corresponding to the unblocked bus interface if there is no cache line with a number of outstanding requests greater than the first threshold; and to determine whether the number of free cache lines is less than a second threshold. It is also used to determine the group to be unbound according to a preset selection strategy when the number of free cache lines is less than the second threshold, determine the cache line to be released from the group to be unbound according to a preset replacement strategy, and release the original binding relationship between the cache line to be released and the corresponding way to be released.

[0237] In one embodiment, the data response unit includes an arbitration module, a data storage module, a sequential processing module and a cache line switching module. The arbitration module is used to selectively generate a write request, or generate a read request or an eviction request according to an outstanding request. The sequential processing module is used to selectively store the return data of the outstanding request to the data storage module according to the write request, or obtain the return data from the data storage module according to the read request or the eviction request to complete the response to the outstanding request. The cache line switching module is used to set the cache line to be released to a prepared state when all outstanding requests in the cache line to be released are processed, so that the cache line to be released is switched to an idle cache line.

[0238] In one embodiment, the request control unit also includes a data hit check module and a free cache line queue module. The free cache line queue module is used to obtain free cache lines from the cache line release module and store the obtained free cache lines. The data hit check module is used to determine whether the current request needs to establish a dynamic binding relationship; it is also used to obtain free cache lines from the free cache line queue module when it is necessary to establish a dynamic binding relationship between the free way occupied by the current request and the free cache line, so as to respond to the current request according to the dynamic binding relationship. The cache line release module is also used to obtain the workload of each bus interface, and determine the bus interface with a workload less than the load threshold as an unblocked bus interface. It is also used to select one of the unblocked bus interfaces, determine the free cache line corresponding to the selected unblocked bus interface, and allocate it to the current request. It is also used to determine the data response units corresponding to each unblocked bus interface, and obtain the priority weight of the corresponding data response unit according to the number of free cache lines in the determined data response unit; wherein, the fewer the number of free cache lines in the data response unit, the higher the priority weight of the data response unit; according to the determined priority weight of the data response unit, select one of the unblocked bus interfaces, determine the free cache line corresponding to the selected unblocked bus interface, and allocate it to the current request.

[0239] It is worth noting that since the ways and cache lines of the embodiments of the present invention do not need to correspond one-to-one according to a fixed pattern, the number of request control units and the number of data response units can be configured independently, and the number of ways and the number of cache lines can also be configured independently. Based on the application scenario and PPA, different proportion combinations can be configured, so that a balance can be achieved as much as possible between PPA factors such as a larger number of outstanding requests, higher data throughput, smaller miss costs, and smaller power consumption and area, breaking through the cache performance bottleneck caused by the fixed pattern.

[0240] In another optional embodiment, if Fig.31 , is a schematic diagram of the architecture of a cache request processing device for dynamic adaptive load balancing according to an embodiment of the present invention. The cache request processing device for dynamic adaptive load balancing according to this embodiment includes one or more processors 21 and a memory 22. Fig.31 A processor 21 is taken as an example.

[0241] The processor 21 and the memory 22 may be connected via a bus or other means. Fig.31 In the example, the connection through the bus is taken as an example. The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer executable programs, such as the cache request processing method for dynamic adaptive load balancing in this embodiment. The processor 21 executes the cache request processing method for dynamic adaptive load balancing by running the non-volatile software programs and instructions stored in the memory 22. The memory 22 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 22 may optionally include a memory remotely arranged relative to the processor 21, and these remote memories may be connected to the processor 21 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The program instructions / modules are stored in the memory 22, and when executed by the one or more processors 21, the cache request processing method for dynamic adaptive load balancing in the above-mentioned embodiment is executed, for example, the various steps of the cache request processing method for dynamic adaptive load balancing described above are executed.

[0242] An embodiment of the present invention further provides a non-volatile computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are executed by one or more processors, such as Fig.31 A processor 21 can enable the above one or more processors to execute the cache request processing method of dynamic adaptive load balancing in the specific implementation of the present invention, for example, to execute each step of the cache request processing method of dynamic adaptive load balancing described above; it can also realize Fig.31 The modules and units described above; or executing the cache request processing method for dynamic adaptive load balancing in the specific implementation of the present invention, for example, executing the steps of the cache request processing method for dynamic adaptive load balancing described above; it can also be implemented Fig.31 The various modules and units described.

[0243] It is worth noting that the information interaction, execution process, etc. between the modules and units within the above-mentioned devices and systems are based on the same concept as the processing method embodiment of the present invention. The specific contents can be found in the description of the method embodiment of the present invention and will not be repeated here.

[0244] A person skilled in the art may understand that all or part of the steps in the various methods of the embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0245] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A cache request processing method with dynamic adaptive load balancing, characterized in that: include: Determine the cache line to be released according to the number of outstanding requests, and release the original binding relationship of the cache line to be released; Complete responses to all outstanding requests in the cache line to be released, and obtain a free cache line; According to the workload of each bus interface, an idle cache line is allocated to the current request, so as to establish a dynamic binding relationship between the idle way occupied by the current request and the idle cache line, and complete the response to the current request according to the dynamic binding relationship.

2. The cache request processing method of dynamic adaptive load balancing according to claim 1 is characterized in that: Determining the cache line to be released according to the number of uncompleted requests and releasing the original binding relationship of the cache line to be released includes: Determine the number of outstanding requests for each cache line, and determine whether the number of outstanding requests for each cache line is greater than a first threshold; If there is a cache line whose number of uncompleted requests is greater than a first threshold, the cache line is determined as a cache line to be released, and an original binding relationship between the cache line to be released and a corresponding way to be released is released; If there is no cache line with a number of uncompleted requests greater than the first threshold, determining the number of free cache lines corresponding to the unblocked bus interface; and determining whether the number of free cache lines is less than a second threshold; When the number of free cache lines is less than a second threshold, a to-be-unbound group is determined according to a preset selection strategy, a to-be-released cache line is determined from the to-be-unbound group according to a preset replacement strategy, and the original binding relationship between the to-be-released cache line and the corresponding to-be-released way is released.

3. The cache request processing method of dynamic adaptive load balancing according to claim 1, characterized in that: The allocating free cache lines for the current request according to the workload of each bus interface includes: Obtaining the workload of each bus interface, and determining a bus interface whose workload is less than a load threshold as an unblocked bus interface; According to the corresponding allocation mode, the free cache line allocated to the current request is selectively determined based on the unblocked bus interface, or based on the number of free cache lines in the unblocked bus interface and the corresponding data response unit.

4. The cache request processing method of dynamic adaptive load balancing according to claim 3 is characterized in that: The step of selectively determining the free cache line allocated to the current request according to the corresponding allocation mode and based on the unblocked bus interface, or determining the free cache line allocated to the current request according to the number of free cache lines in the unblocked bus interface and the corresponding data response unit comprises: Select one of the unblocked bus interfaces, determine an idle cache line corresponding to the selected unblocked bus interface, and assign it to the corresponding current request; Or, determining the data response units corresponding to each unblocked bus interface, and obtaining the priority weight of the corresponding data response unit according to the number of free cache lines in the determined data response unit; wherein the smaller the number of free cache lines in the data response unit, the higher the priority weight of the data response unit; According to the determined priority weights of the data response units, one of the unblocked bus interfaces is selected, and an idle cache line corresponding to the selected unblocked bus interface is determined and allocated to the corresponding current request.

5. The cache request processing method of dynamic adaptive load balancing according to claim 1, characterized in that: The step of completing the response to all the uncompleted requests in the cache line to be released to obtain the free cache line includes: Acquire the return data required by the uncompleted request from the cache line to be released, so as to complete the response to the uncompleted request; After all outstanding requests in the cache line to be released are processed, the cache line to be released is set to a prepared state, so that the cache line to be released is switched to an idle cache line.

6. A cache request processing device with dynamic adaptive load balancing, characterized in that: It includes a request control unit, a cache line release module and a data response unit; The request control unit is used to determine the cache line to be released according to the number of uncompleted requests, and release the original binding relationship of the cache line to be released, wherein: The data response unit is used to complete the response to all the uncompleted requests in the cache line to be released, and obtain a free cache line; The cache line release module is used to allocate free cache lines to the current request according to the workload of each bus interface, so as to establish a dynamic binding relationship between the free way occupied by the current request and the free cache line, and complete the response to the current request according to the dynamic binding relationship.

7. The cache request processing device of dynamic adaptive load balancing according to claim 6, characterized in that: The request control unit includes a group binding control module; The group binding control module is used to determine the number of outstanding requests for each cache line and determine whether the number of outstanding requests for each cache line is greater than a first threshold; It is also used to determine the cache line as a cache line to be released if there is a cache line with the number of uncompleted requests greater than a first threshold, and release the original binding relationship between the cache line to be released and the corresponding way to be released; Also used for determining the number of free cache lines corresponding to the unblocked bus interface if there is no cache line with the number of uncompleted requests greater than the first threshold; and determining whether the number of free cache lines is less than the second threshold; It is also used to, when the number of the free cache lines is less than a second threshold, determine a to-be-unbound group according to a preset selection strategy, determine a to-be-released cache line from the to-be-unbound group according to a preset replacement strategy, and release the original binding relationship between the to-be-released cache line and the corresponding to-be-released way.

8. The cache request processing device of dynamic adaptive load balancing according to claim 6, characterized in that: The data response unit includes an arbitration module, a data storage module, a sequential processing module and a cache line switching module; The arbitration module is used to selectively generate a write request, or generate a read request or an eviction request according to the outstanding request; The sequential processing module is used to selectively store the return data of the uncompleted request in the data storage module according to the write request, or obtain the return data from the data storage module according to the read request or the eviction request, so as to complete the response to the uncompleted request; The cache line switching module is used to set the cache line to be released to a prepared state after processing all the incomplete requests in the cache line to be released, so that the cache line to be released is switched to an idle cache line.

9. The cache request processing device of dynamic adaptive load balancing according to claim 6, characterized in that: The request control unit also includes a data hit check module and a free cache line queue module; The free cache line queue module is used to obtain the free cache lines from the cache line release module and store the obtained free cache lines; The data hit checking module is used to determine whether the current request needs to establish a dynamic binding relationship; It is also used to obtain the free cache line from the free cache line queue module when it is necessary to establish a dynamic binding relationship between the free way occupied by the current request and the free cache line, so as to respond to the current request according to the dynamic binding relationship.

10. The cache request processing device of dynamic adaptive load balancing according to claim 9, characterized in that: The cache line release module is further used to obtain the workload of each bus interface, and determine the bus interface with a workload less than a load threshold as an unblocked bus interface; Also used to select one of the unblocked bus interfaces, determine the free cache line corresponding to the selected unblocked bus interface, and allocate it to the current request; It is also used to determine the data response units corresponding to each unblocked bus interface, and obtain the priority weight of the corresponding data response unit according to the number of free cache lines in the determined data response unit; wherein, the fewer the number of free cache lines in the data response unit, the higher the priority weight of the data response unit; according to the determined priority weight of the data response unit, select one of the unblocked bus interfaces, determine the free cache line corresponding to the selected unblocked bus interface, and allocate it to the current request.

Images