Bus communication method, device, equipment and storage medium

Abstract

The present application provides a bus communication method, apparatus, device and storage medium, which are applied to a server, wherein the server includes a processor, a first controller, a second controller, a third controller and a bus. The method includes: determining the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; in response to powering on the server, determining a target controller according to the hardware configuration of the server, wherein the target controller includes a first controller or a second controller; the third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; in response to completion of initialization of the target controller and the processor, the target controller and the processor transmit the startup data of the server through the corresponding communication channel.

Description

Technical Field

[0001] The present invention relates to the field of server technology, and in particular to a bus communication method, device, equipment and storage medium. Background Art

[0002] In the prior art, the BMC interacts with the CPU (Central Processing Unit) through communication protocols such as the ESPI (Enhanced Serial Peripheral Interface) bus to obtain CPU operating status information and adjust the server's operating strategy based on this information. In actual applications, during ESPI (Enhanced Serial Peripheral Interface) communication between the CPU and the BMC, the BMC needs to support both virtual wire channels and logical channels. The CPU uses the virtual wire channel as a GPIO (General Purpose Input / Output) extension between the CPU and BMC, transmitting key signals and opening expansion interfaces. The CPU uses the logical channel to transmit CPU port status and serial port log information.

[0003] The ESPI configuration varies on different platforms. If you change platforms, the initialization design of the virtual line channel on different platforms may be different. If you configure different hardware in the BMC and the corresponding firmware code cannot be modified, the BMC firmware code and hardware may be inconsistent, causing the server to fail to boot.

[0004] Therefore, in view of the shortcomings of the existing technical solutions, the present invention provides a bus communication method. Summary of the Invention

[0005] Based on this, it is necessary to provide a bus communication method, device, equipment and storage medium to address the above technical problems.

[0006] On the one hand, a bus communication method is provided, which is applied to a server, wherein the server includes a processor, a first controller, a second controller, a third controller and a bus, wherein the bus includes a first communication channel and a second communication channel, the first controller communicates with the processor through the first communication channel, the second controller communicates with the processor through the second communication channel, and the third controller communicates with the processor through the first communication channel. The method includes: determining the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; in response to the server being powered on, determining the target controller according to the hardware configuration of the server, wherein the target controller includes the first controller or the second controller; the third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; in response to the completion of the initialization of the target controller and the processor, the target controller and the processor transmit the startup data of the server through the corresponding communication channel.

[0007] Optionally, determining the hardware configuration of the server based on the type of the processing platform of the processor includes: determining whether the communication channel of the bus includes a second communication channel based on the type of the processing platform of the processor; when the communication channel of the bus includes the second communication channel, the second controller is connected to the processor; when the communication channel of the bus does not include the second communication channel, the second controller is disconnected from the processor.

[0008] Optionally, before the third controller sends a trigger signal to the target controller and the processor, the method further includes: the third controller monitors the power signal of the server; when the third controller monitors the power stability signal, the third controller sends a trigger signal to the target controller and the processor.

[0009] Optionally, determining the target controller according to the hardware configuration of the server includes: when the second controller is connected to the processor, determining the target controller to be the second controller; when the second controller is disconnected from the processor, determining the target controller to be the first controller.

[0010] Optionally, before the target controller and the processor transmit the startup data of the server through the corresponding communication channel, the method includes: the processor obtains and configures the communication parameters of the target controller; verifies the communication interface of the target controller and the communication interface of the processor; establishes a communication protocol between the target controller and the processor; and determines the initialization of the target controller and the processor based on the communication parameters, the communication interface and the communication protocol.

[0011] Optionally, the processor obtains and configures the communication parameters of the target controller, including: the processor obtains the communication information of the target controller from the first register of the target controller; the processor configures the parameters of the first register of the target controller based on the communication information; the processor obtains the information of the communication channel corresponding to the target controller from the second register of the target controller; the processor configures the parameters corresponding to the communication channel in the second register of the target controller based on the information of the communication channel.

[0012] Optionally, the target controller and the processor transmit the startup data of the server through the corresponding communication channel, including: when the target controller is the second controller, the processor reads the level of the expansion pin through the second communication channel, and determines whether there is an abnormality in the current startup state according to the level of the expansion pin, wherein the expansion pin is the pin used by the processor to connect to the second controller; when the current startup state is abnormal, an alarm signal is generated and sent to the server; when the current startup state is normal, the processor sends the first startup data to the second controller through the second communication channel; the second controller modifies the corresponding register according to the first startup data and sends the modified register value to the corresponding first controller and / or third controller; in response to the server releasing the The second communication channel initializes the first communication channel between the first controller and the processor based on communication parameters, communication interface and communication protocol; in response to the completion of the initialization of the first communication channel, the processor sends second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, the first controller generates and sends an alarm signal to the server; when the target controller is the first controller, the processor sends second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, the first controller generates and sends an alarm signal to the server.

[0013] On the other hand, a bus communication device is provided, which is applied to a server, wherein the server includes a processor, a first controller, a second controller, a third controller and a bus, wherein the bus includes a first communication channel and a second communication channel, the first controller communicates with the processor through the first communication channel, the second controller communicates with the processor through the second communication channel, and the third controller communicates with the processor through the first communication channel. The device includes: a configuration module, which is used to determine the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; a processing module, which is used to determine the target controller according to the hardware configuration of the server in response to power-on of the server, wherein the target controller includes the first controller or the second controller; a trigger module, which is used for the third controller to send a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; and a transmission module, which is used for the target controller and the processor to transmit the startup data of the server through the corresponding communication channel in response to the completion of initialization of the target controller and the processor.

[0014] On the other hand, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: determining the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; in response to powering on the server, determining the target controller according to the hardware configuration of the server, wherein the target controller includes a first controller or a second controller; a third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; in response to completion of initialization of the target controller and the processor, the target controller and the processor transmit the startup data of the server through the corresponding communication channel.

[0015] On the other hand, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: determining the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; in response to the server being powered on, determining the target controller according to the hardware configuration of the server, wherein the target controller includes a first controller or a second controller; a third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; in response to the completion of the initialization of the target controller and the processor, the target controller and the processor transmit the startup data of the server through the corresponding communication channel.

[0016] The above-mentioned bus communication method, device, equipment and storage medium, the method includes: determining the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; in response to the server being powered on, determining the target controller according to the hardware configuration of the server, wherein the target controller includes a first controller or a second controller; a third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; in response to the completion of the initialization of the target controller and the processor, the target controller and the processor transmit the startup data of the server through the corresponding communication channel; in this way, different hardware configurations can be adapted according to different processing platforms, and functional problems of the server can be avoided due to differences in configurations of different platforms because the same controller is used to implement the functions of virtual line channels and peripheral channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a system architecture in the prior art;

[0018] Figure 2 A schematic flow chart of a bus communication method according to an embodiment;

[0019] Figure 3 A schematic diagram of a system architecture of a bus communication method in one embodiment;

[0020] Figure 4 FIG1 is another system architecture diagram of a bus communication method in one embodiment;

[0021] Figure 5 A schematic flow chart of a bus communication method according to an embodiment;

[0022] Figure 6 FIG1 is another flow chart of a bus communication method according to an embodiment;

[0023] Figure 7 is a structural block diagram of a bus communication device in one embodiment;

[0024] Figure 8 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0025] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be understood that in the description of this application, unless the context clearly requires otherwise, words such as "include", "comprises", and the like throughout the specification should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to".

[0027] It should also be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0028] It should be noted that the terms "S1", "S2", etc. are used only for the purpose of describing the steps and do not specifically refer to the order or sequence, nor are they used to limit this application. They are merely for the convenience of describing the method of this application and should not be understood as indicating the order of the steps. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0029] Figure 1 It is a schematic diagram of the system architecture in the prior art, such as Figure 1 As shown, the system architecture includes: CPU, BMC, CPLD (Complex Programmable Logic Device) and ESPI bus. The ESPI bus includes peripheral channels and virtual line channels.

[0030] Specifically, the CPU transmits the pin expansion data to the CPLD through the peripheral channel;

[0031] Specifically, the CPU transmits pin expansion data to the BMC through the peripheral channel;

[0032] Specifically, the CPU transmits the port status and serial port logs to the BMC through the virtual line channel;

[0033] Specifically, the CPLD sends a trigger signal to the BMC.

[0034] Among them, in the ESPI communication between the CPU and the BMC, the BMC needs to support both the virtual line channel and the peripheral channel.

[0035] In the prior art, the configuration of ESPI varies on different platforms. If the platform is changed, the initialization design of the virtual line channel may be different. In the prior art, both the virtual line channel and the peripheral channel are configured in the BMC. Different hardware configurations may cause the machine to fail to boot.

[0036] In one embodiment, Figure 2 As shown, a bus communication method is provided, which is applied to a server. The server includes a processor, a first controller, a second controller, a third controller, and a bus, wherein the bus includes a first communication channel and a second communication channel. The first controller communicates with the processor through the first communication channel, the second controller communicates with the processor through the second communication channel, and the third controller communicates with the processor through the first communication channel. The method includes the following steps:

[0037] S201: Determine a hardware configuration of a server according to a type of a processing platform of a processor, wherein the hardware configuration includes a controller configuration and a bus configuration.

[0038] Here, the types of processing platforms of the processor may include INTEL platform and AMD platform, etc.

[0039] Here, the controller may include an MCU (Microcontroller Unit), a CPLD, a BMC, an FPGA (Field Programmable Gate Array), and the like.

[0040] Here, the bus configuration can be the different communication channels included in the bus. If the bus is an ESPI bus, the corresponding bus configuration can be a virtual wire channel (Virtual Wire Channel), a peripheral channel (Peripheral Channel), an out-of-band channel (OOB Channel), and a flash channel (Flash Channel). For example, when the CPU communicates with the BMC, CPLD, etc. via ESPI, the ESPI channels commonly used by general servers are the peripheral channel and the virtual wire channel.

[0041] Here, the bus is the ESPI bus, which is an enhanced SPI (Serial Peripheral Interface) bus, used for communication between the x86 CPU platform and peripherals. The ESPI bus saves physical pins, has low power consumption, high speed, scalable protocol, and supports one master and multiple slaves.

[0042] Among them, different types of processor processing platforms correspond to different communication methods, and different communication methods correspond to different hardware configurations.

[0043] Specifically, the processor may be a CPU. When the CPU is processed through an INTEL platform, it corresponds to a set of hardware configurations. When the CPU is processed through an AMD platform, it corresponds to another set of hardware configurations.

[0044] S202: In response to the server being powered on, determining a target controller according to a hardware configuration of the server, wherein the target controller includes a first controller or a second controller.

[0045] Here, the first controller may be a BMC, the second controller may be an MCU, a CPLD, an FPGA, etc., and the third controller may be a CPLD.

[0046] Among them, the first controller is used to obtain the processor's 80 port information and serial information to display the self-test code and parse the system serial port log; the second controller is used to obtain the information of key signals that the processor needs to transmit to the outside world.

[0047] S203: The third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize.

[0048] Here, the trigger signal can be a power management signal, a reset signal, a BMC-related signal, a peripheral device connection and status change, a network communication, a timer and a timer overflow, an external input signal, a software request, etc.

[0049] In one embodiment, the trigger signal may be used to instruct each controller and processor to reset first, and after receiving the reset release signal sent by the server, the target controller and processor are initialized.

[0050] S204: In response to the target controller and the processor completing initialization, the target controller and the processor transmit startup data of the server through corresponding communication channels.

[0051] The server startup data may include pin information, port status, serial port logs, and other information.

[0052] Specifically, when the target controller is the first controller, the first controller transmits data to the processor through the first communication channel; when the target controller is the second controller, the second controller transmits data to the processor through the second communication channel.

[0053] In one embodiment, the controller and the processor can transmit data during the server startup process and data during the server operation process through the communication channel.

[0054] In one embodiment, when the target controller and the processor transmit the server's startup data through the communication channel, a check code can be generated and sent to the receiver when the sender sends the data. The receiver verifies the check code to ensure the correctness of the transmitted data. For example, the check code can be a check code such as CRC32 (Cyclic Redundancy Check).

[0055] It should be noted that the present application can be adapted to different hardware configurations according to different platforms, and can avoid functional problems of the server due to differences in configurations of different platforms when the same controller is used to implement the functions of the virtual line channel and the peripheral channel.

[0056] In some specific implementations, determining the hardware configuration of the server based on the type of the processing platform of the processor includes:

[0057] determining, according to a type of a processing platform of the processor, whether the communication channel of the bus includes a second communication channel;

[0058] When the communication channel of the bus includes the second communication channel, the second controller is connected to the processor;

[0059] When the communication channels of the bus do not include the second communication channel, the second controller disconnects from the processor.

[0060] Here, the second communication channel may be a virtual line channel, and the second controller may be an MCU.

[0061] Among them, the second controller and the processor can be connected through pins. For example, the processor side can be connected to the pin corresponding to the ESPI module of the second controller through the ESPI_CS0 pin, and the second controller can be connected to the pin corresponding to the ESPI module of the processor through CS#, ESPI_CLK, ESPI_IO<0:3>, and ESPI_RST signals.

[0062] Specifically, when the processor is a CPU, the second communication channel is a virtual line channel, and the second controller is an MCU, when the processing platform of the processor is an INTEL platform, the communication channel includes the virtual line channel, and the pins between the second controller and the processor remain connected; when the processing platform of the processor is an AMD platform, the communication channel does not include the virtual line channel, and the pins between the second controller and the processor are disconnected.

[0063] In one embodiment, the server hardware configuration corresponds to server firmware, which includes the processor, the firmware for the first and third controllers, and the firmware for the second controller. The second controller firmware is a separate component, while the remaining slave processors and the processor firmware are integrated. When the hardware configuration includes the second controller, the second controller firmware is burned into the second controller; when the hardware configuration does not include the second controller, the firmware for the first, third, and processors serves as the server firmware. The firmware is pre-designed. Accordingly, the second controller firmware can be updated and modified separately.

[0064] In this way, the first controller can be reused on different platforms without having to be replaced according to the change of the platform.

[0065] In some specific implementations, before the third controller sends a trigger signal to the target controller and the processor, the method further includes:

[0066] The third controller monitors the power signal of the server;

[0067] When the third controller detects a power stabilization signal, the third controller sends a trigger signal to the target controller and the processor.

[0068] Here, the power stabilization signal may be an AUX PWRGD signal.

[0069] Specifically, after the server is powered on, the CPLD monitors whether the server sends an AUX PWRGD signal. When the CPLD monitors the AUX PWRGD signal, it indicates that the AUX Power is ready.

[0070] In one embodiment, a time range may be preset. If the third controller fails to detect the power stabilization signal within the preset time range, the server fails the detection.

[0071] In one embodiment, the power stabilization signal may also be other signal identifiers used to indicate that the power supply is ready.

[0072] In this way, by using the power stabilization signal included in different types of processors as a trigger signal, different types of processors can all use the same trigger signal, thereby simplifying the firmware code.

[0073] In some specific implementations, determining a target controller based on a hardware configuration of the server includes:

[0074] When the second controller is connected to the processor, determining that the target controller is the second controller;

[0075] When the second controller is disconnected from the processor, the target controller is determined to be the first controller.

[0076] In some specific implementations, before the target controller and the processor transmit the boot data of the server through the corresponding communication channel, the method includes:

[0077] The processor acquires and configures communication parameters of the target controller;

[0078] Verifying the communication interface of the target controller and the communication interface of the processor;

[0079] establishing a communication protocol between the target controller and the processor;

[0080] Based on the communication parameters, the communication interface, and the communication protocol, initialization of the target controller and the processor is determined.

[0081] Here, configuring the communication parameters may be used to set initial parameters for communication, ensuring that both communicating parties use the same communication standard.

[0082] Here, verifying the communication interface can be used to check the correctness of the connection, check functional integrity, and identify potential problems.

[0083] Here, establishing a communication protocol can clarify the communication rules between the processor and the target controller to ensure data integrity and consistency.

[0084] The target controller may be the first controller or the second controller.

[0085] The processor can obtain information from the target controller through the pins.

[0086] In this way, by initializing the communication channel between the processor and the controller, a robust and efficient communication link is built between the controller and the processor, ensuring the correctness and speed of transmission.

[0087] In some specific implementations, the processor obtains and configures the communication parameters of the target controller, including:

[0088] The processor obtains the communication information of the target controller from the first register of the target controller;

[0089] The processor configures parameters of a first register of the target controller according to the communication information;

[0090] The processor obtains information of the communication channel corresponding to the target controller from the second register of the target controller;

[0091] The processor configures parameters corresponding to the communication channel in the second register of the target controller according to the information of the communication channel.

[0092] Here, the communication information may include the communication capabilities supported by the target controller, such as the types of commands that can be processed, the data transmission method, etc.

[0093] Here, the first register may include basic operating parameters of the MCU as a slave device for ESPI bus communication, such as clock rate, communication mode, and error handling mechanism.

[0094] Here, the information of the communication channel corresponding to the target controller may include status information about the channel, such as which channel signals are being activated, or their logic levels.

[0095] Here, the parameters corresponding to the communication channel in the second register may include the behavior of the processor changing the channel, such as enabling or disabling certain channel signals, setting their initial levels, or defining how to update these signals when a specific event occurs.

[0096] Specifically, assuming that the processor is a CPU and the target controller is an MCU, the CPU obtains the communication capabilities supported by the MCU by reading the 0x08 register of the MCU, and the CPU resets the basic parameters of the MCU by configuring the 0x08 register of the MCU through pins; the CPU obtains the relevant status of the virtual line channel by reading the 0x20 register of the MCU, and the CPU sets the virtual line related registers of the 0x20 register of the MCU through pins.

[0097] In some specific implementations, the target controller and the processor transmit the boot data of the server through a corresponding communication channel, including:

[0098] When the target controller is the second controller, the processor reads the level of an expansion pin through the second communication channel, and determines whether there is an abnormality in the current power-on state according to the level of the expansion pin, where the expansion pin is a pin used by the processor to connect to the second controller;

[0099] When the current boot state is abnormal, generating and sending an alarm signal to the server;

[0100] When the current startup state is normal, the processor sends the first startup data to the second controller through the second communication channel;

[0101] The second controller modifies the corresponding register according to the first startup data and sends the modified register value to the corresponding first controller and / or third controller;

[0102] In response to the server releasing the second communication channel, initializing a first communication channel between the first controller and the processor based on communication parameters, a communication interface, and a communication protocol;

[0103] In response to the completion of initialization of the first communication channel, the processor sends second startup data to the first controller through the first communication channel;

[0104] The first controller monitors and records the power-on status of the server according to the second power-on data;

[0105] When the startup state is detected to be abnormal, an alarm signal is generated and sent to the server;

[0106] When the target controller is the first controller, the processor sends second startup data to the first controller through the first communication channel;

[0107] The first controller monitors and records the power-on status of the server according to the second power-on data;

[0108] When the startup state is detected to be abnormal, an alarm signal is generated and sent to the server.

[0109] Here, the expansion pin is an expansion GPIO, and whether the current state is abnormal is determined according to the level of the expansion GPIO.

[0110] Here, the first startup data may be key signals such as SLP_S3 and SLP_S5, and the second startup data may include port 80 status and serial port logs.

[0111] Here, the first communication channel can be a peripheral channel that supports I / O and memory access and provides access to Super-I / O logical peripherals such as KBC, ECI, UART, and Shared Memory. For example, the first communication channel can be configured to transmit port 80 status and serial port logs.

[0112] Here, the second communication channel can be a virtual line channel, which is used to eliminate some functional pins of the x86 platform and transmit pin status between the master device and the slave device using data packets, such as SCI, SLP_S3 / S4, PLTRST#, SERIRQ, and other signals. Exemplarily, the second communication channel can be configured as a GPIO expansion to transmit information between the master device and the slave device.

[0113] The second controller communicates with the first controller or the third controller through other buses, such as I2C (Inter-Integrated Circuit, two-wire serial bus), SMBUS (System Management Bus), UART (Universal Asynchronous Receiver / Transmitter), IPMI (Intelligent Platform Management Interface) and other buses.

[0114] Specifically, when the target controller is the second controller, data transmission via the second communication channel is performed first, and then data transmission via the first communication channel corresponding to the first controller is performed.

[0115] In one embodiment, data transmission on the second communication channel and the first communication channel may be performed simultaneously, or data transmission on the first communication channel may be performed first and then data transmission on the second communication channel.

[0116] Specifically, the CPU reads and writes extended GPIO data, and writes the corresponding values ​​of the key signals to be transmitted into the MCU's registers. After the MCU obtains the corresponding GPIO values, it rewrites the corresponding storage registers and transmits the corresponding register values ​​to the BMC through I2C or other communication methods with the BMC. The BMC records and monitors the machine's startup.

[0117] For example, Figure 3 A schematic diagram of a system architecture in an embodiment of the present application is shown in FIG. Figure 3 As shown, the architecture in this application includes: CPU, BMC, MCU, CPLD and ESPI bus, and the ESPI bus includes peripheral channels and virtual line channels.

[0118] Specifically, the CPU transmits the pin expansion data to the CPLD through the peripheral channel;

[0119] Specifically, the CPU transmits pin expansion data to the BMC through the peripheral channel;

[0120] Specifically, the CPU transmits the port status and serial port log to the MCU through the virtual line channel;

[0121] Specifically, the CPLD sends a trigger signal to the MCU.

[0122] For example, Figure 4 This is another system architecture diagram in the embodiment of the present application, such as Figure 4 As shown, the architecture in this application includes: CPU, BMC, CPLD and ESPI bus, and the ESPI bus includes peripheral channels and virtual line channels.

[0123] Specifically, the CPU transmits the pin expansion data to the CPLD through the peripheral channel;

[0124] Specifically, the CPU transmits pin expansion data to the BMC through the peripheral channel;

[0125] Specifically, the CPLD sends a trigger signal to the BMC.

[0126] For example, Figure 5 This is a flow chart of an embodiment of the present application, such as Figure 5 As shown, the process in this application includes: S501: server power-on; S502: CPLD sends a trigger signal; S503: CPU releases a reset signal; S504: CPU and MCU initialize the virtual line channel; S504 specifically includes: S504.1: obtain configuration; S504.2: perform configuration; S505: transfer GPIO expansion; S506: release the virtual line channel; S507: CPU and BMC initialize the peripheral channel; S507 specifically includes: S507.1: obtain configuration; S507.2: perform configuration; S508: update port status and serial log.

[0127] For example, Figure 6 This is another flow chart of an embodiment of the present application, such as Figure 6 As shown, the process in this application includes: S601: server power-on; S602: CPLD sends a trigger signal; S603: CPU releases a reset signal; S604: CPU and BMC initialize peripheral channels; S604 specifically includes: S604.1: obtain configuration; S604.2: perform configuration; S605: update port status and serial log.

[0128] In this way, the GPIO transmission function implemented by the virtual line channel between the processor and the first controller is transferred to the second controller for implementation, thereby realizing the distinction between the devices corresponding to the virtual line channel and the peripheral channel in ESPI; at the same time, the second controller has flexible configuration and can be configured according to the platform characteristics under different platforms, thereby improving the flexibility of transmission.

[0129] In some embodiments, the method further comprises:

[0130] The third controller monitors the corresponding characteristic data of the bus to determine whether there is any transmission abnormality in the bus communication;

[0131] When the third controller monitors that there is a transmission anomaly, it determines the communication channel in which the anomaly occurs according to the transmission content, where the transmission channel includes a first transmission channel and a second transmission channel;

[0132] The third controller generates and sends an alarm signal according to the abnormal communication channel.

[0133] Here, the characteristic data may be a command / address cycle signal, a data transmission signal, a status signal (such as SDP, etc.), an interrupt request, a clock signal, a handshake protocol signal, and the like.

[0134] Here, different transmission channels transmit different data contents, and the transmission channel with abnormality can be distinguished according to the transmission content.

[0135] Specifically, when the CPLD monitors that the clock signal has problems such as clock stop and frequency deviation, the transmission abnormality can be determined; when the CPLD monitors an interrupt request, the transmission abnormality can be determined; when the CPLD monitors that the handshake protocol signal is not correctly confirmed, the transmission abnormality can be determined; when the CPLD monitors signals such as parity error and timeout error, the transmission abnormality can be determined.

[0136] In this way, security risks in bus communication can be promptly reported, abnormal communication channels can be easily located, and security risks brought by the ESPI bus can be effectively resolved.

[0137] In one embodiment, when the processor is a CPU, the first controller is a BMC, the second controller is an MCU, the third controller is a CPLD, the first communication channel is a virtual line channel, and the second communication channel is a peripheral channel, the steps for the server to communicate through the ESPI bus in an Intel platform are as follows:

[0138] S1: After receiving AC (Alternating Current) power, the server enters S5. In this state, the ESPI devices (i.e., slave processors, MCU, BMC, and CPLD) ensure their ESPI modules remain in a ready state, waiting for the ESPI module of the master device (i.e., CPU) to become ready. Both parties then perform an ESPI handshake. The MCU's VirtualWire Channel relies on the VW_RST trigger signal (i.e., trigger signal) sent by the system as the startup instruction for the MCU configuration. Based on the ESPI signaling requirements, an appropriate platform signal is selected as the VW_RST trigger source, such as the AUX PWRGOOD signal issued by the system after AUX Power is ready. S5 represents AC power-on.

[0139] S2: After successfully receiving the VW_RST trigger signal (i.e., the trigger signal), the MCU first performs a series of internal processing to ensure that its virtual wire channel is ready. Once the VW channel (i.e., the virtual wire channel) is ready, the CPU releases the RESET pin on the ESPI. This operation is a crucial prerequisite for the MCU and CPU's ESPI modules to begin initialization. This initialization process includes configuring ESPI communication parameters, verifying the communication interface, and establishing the necessary communication protocols to ensure stable and efficient data transmission between the MCU and CPU.

[0140] S3: The MCU and CPU complete the ESPI handshake communication. The CPU transmits key signals such as SLP_S3 and SLP_S5 to the MCU through the ESPI Virtual Wire Channel.

[0141] S4: After the CPU completes the transmission of key signals through ESPI, it releases the global reset signal as a sign that the VirtualWire Channel (i.e., virtual wire channel) has completed the transmission of key signals;

[0142] S5: The CPU and BMC communicate via the peripheral channel (i.e., port 80) and serial logs, enabling the BMC to monitor the CPU components and capture boot information during the boot process.

[0143] In the above general server system, the communication steps of the Virtual Wire Channel between the CPU and MCU in eSPI communication are as follows:

[0144] S3.1: When the CPU enters S0, it needs to communicate with the slave (i.e., slave processor). The CPU completes the initial ESPI handshake communication by reading and configuring the value of the slave register. Among them, the S0 state is DC (Direct Current) power-on.

[0145] The steps of handshake communication are as follows: S3.1.1: CPU reads register 0x08 of MCU to obtain the communication capabilities supported by eSPI_Slave; S3.1.2: CPU configures register 0x08 of MCU to reset basic parameters of Slave; S3.1.3: CPU reads register 0x20 of MCU to obtain Vwire related status; S3.1.4: CPU sets Vwire related registers of register 0x20 of MCU.

[0146] S3.2: CPU Get / Put vWire GPIO: The CPU reads and writes 128 GPIO (i.e., pin) data and writes the corresponding values ​​of the key signals to be transmitted into the MCU's registers.

[0147] S3.3: After the MCU obtains the value of the corresponding GPIO, it transmits it to the BMC through I2C or other communication methods with the BMC. The BMC records and monitors the boot process.

[0148] It should be understood that although Figure 1-6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1-6 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0149] In one embodiment, Figure 7As shown, a bus communication device is provided, which is applied to a server, wherein the server includes a processor, a first controller, a second controller, a third controller and a bus, wherein the bus includes a first communication channel and a second communication channel, the first controller communicates with the processor through the first communication channel, the second controller communicates with the processor through the second communication channel, and the third controller communicates with the processor through the first communication channel. The device includes: a configuration module 701, which is used to determine the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; a processing module 702, which is used to determine the target controller according to the hardware configuration of the server in response to the server being powered on, wherein the target controller includes the first controller or the second controller; a trigger module 703, which is used for the third controller to send a trigger signal to the target controller and the processor, wherein the trigger signal is used to indicate that the target controller and the processor are initialized; a transmission module 704, which is used to transmit the startup data of the server through the corresponding communication channel in response to the completion of the initialization of the target controller and the processor.

[0150] As a preferred implementation, in an embodiment of the present application, the configuration module 701 is specifically used to: determine whether the communication channel of the bus includes a second communication channel based on the type of the processing platform of the processor; when the communication channel of the bus includes the second communication channel, the second controller is connected to the processor; when the communication channel of the bus does not include the second communication channel, the second controller is disconnected from the processor.

[0151] As a preferred implementation, in an embodiment of the present application, the device also includes a detection module, which is used to: the third controller monitors the power signal of the server; when the third controller monitors the power stability signal, the third controller sends a trigger signal to the target controller and the processor.

[0152] As a preferred implementation, in an embodiment of the present application, the processing module 702 is specifically used to: when the second controller is connected to the processor, determine that the target controller is the second controller; when the second controller is disconnected from the processor, determine that the target controller is the first controller.

[0153] As a preferred implementation, in an embodiment of the present application, the device also includes an initialization module, which is specifically used to: the processor obtains and configures the communication parameters of the target controller; verifies the communication interface of the target controller and the communication interface of the processor; establishes a communication protocol between the target controller and the processor; and determines the initialization of the target controller and the processor based on the communication parameters, the communication interface and the communication protocol.

[0154] As a preferred implementation, in an embodiment of the present application, the initialization module is specifically further used for: the processor obtains the communication information of the target controller from the first register of the target controller; the processor configures the parameters of the first register of the target controller based on the communication information; the processor obtains the information of the communication channel corresponding to the target controller from the second register of the target controller; the processor configures the parameters corresponding to the communication channel in the second register of the target controller based on the information of the communication channel.

[0155] As a preferred implementation manner, in the embodiment of the present application, the transmission module 704 is specifically used for: when the target controller is the second controller, the processor reads the level of the expansion pin through the second communication channel, and determines whether there is an abnormality in the current power-on state according to the level of the expansion pin, wherein the expansion pin is the pin used by the processor to connect to the second controller; when the current power-on state is abnormal, an alarm signal is generated and sent to the server; when the current power-on state is normal, the processor sends the first power-on data to the second controller through the second communication channel; the second controller modifies the corresponding register according to the first power-on data and sends the modified register value to the corresponding first controller and / or third controller; in response to the server releasing the second communication channel, initializes the first communication channel between the first controller and the processor based on communication parameters, communication interface and communication protocol; in response to the completion of the initialization of the first communication channel, the processor sends second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, generates and sends an alarm signal to the server; when the target controller is the first controller, the processor sends the second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, generates and sends an alarm signal to the server.

[0156] For the specific definition of the bus communication device, please refer to the definition of the bus communication method above and will not be repeated here. Each module in the above-mentioned bus communication device can be implemented in whole or in part through software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each of the above modules.

[0157] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 8 As shown. The computer device includes a processor, memory, and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When executed by the processor, the computer program implements a bus communication method.

[0158] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0159] In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: S1: determining a hardware configuration of a server according to the type of a processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; S2: in response to powering on the server, determining a target controller according to the hardware configuration of the server, wherein the target controller includes a first controller or a second controller; S3: a third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; S4: in response to completion of initialization of the target controller and the processor, the target controller and the processor transmit startup data of the server through corresponding communication channels.

[0160] In one embodiment, when the processor executes the computer program, it further implements the following steps: determining whether the communication channel of the bus includes a second communication channel based on the type of the processing platform of the processor; when the communication channel of the bus includes the second communication channel, connecting the second controller to the processor; when the communication channel of the bus does not include the second communication channel, disconnecting the second controller from the processor.

[0161] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the third controller monitors the power signal of the server; when the third controller monitors the power stability signal, the third controller sends a trigger signal to the target controller and the processor.

[0162] In one embodiment, when executing the computer program, the processor further implements the following steps: when the second controller is connected to the processor, determining that the target controller is the second controller; when the second controller is disconnected from the processor, determining that the target controller is the first controller.

[0163] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the processor obtains and configures the communication parameters of the target controller; verifies the communication interface of the target controller and the communication interface of the processor; establishes a communication protocol between the target controller and the processor; and determines the initialization of the target controller and the processor based on the communication parameters, the communication interface and the communication protocol.

[0164] In one embodiment, when the processor executes the computer program, the following steps are further implemented: the processor obtains communication information of the target controller from the first register of the target controller; the processor configures parameters of the first register of the target controller based on the communication information; the processor obtains information of the communication channel corresponding to the target controller from the second register of the target controller; and the processor configures parameters corresponding to the communication channel in the second register of the target controller based on the information of the communication channel.

[0165] In one embodiment, when the processor executes the computer program, the following steps are further implemented: when the target controller is the second controller, the processor reads the level of the expansion pin through the second communication channel, and determines whether there is an abnormality in the current power-on state according to the level of the expansion pin, wherein the expansion pin is the pin used by the processor to connect to the second controller; when the current power-on state is abnormal, an alarm signal is generated and sent to the server; when the current power-on state is normal, the processor sends first power-on data to the second controller through the second communication channel; the second controller modifies the corresponding register according to the first power-on data and sends the modified register value to the corresponding first controller and / or third controller; in response to the server releasing the second communication channel, Based on communication parameters, communication interface and communication protocol, the first communication channel between the first controller and the processor is initialized; in response to the completion of initialization of the first communication channel, the processor sends second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, an alarm signal is generated and sent to the server; when the target controller is the first controller, the processor sends second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, an alarm signal is generated and sent to the server.

[0166] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: S1: determining the hardware configuration of the server according to the type of the processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; S2: in response to the server being powered on, determining the target controller according to the hardware configuration of the server, wherein the target controller includes a first controller or a second controller; S3: a third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; S4: in response to the completion of the initialization of the target controller and the processor, the target controller and the processor transmit the startup data of the server through the corresponding communication channel.

[0167] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: determining whether the communication channel of the bus includes a second communication channel based on the type of the processing platform of the processor; when the communication channel of the bus includes the second communication channel, connecting the second controller to the processor; when the communication channel of the bus does not include the second communication channel, disconnecting the second controller from the processor.

[0168] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the third controller monitors the power signal of the server; when the third controller monitors the power stability signal, the third controller sends a trigger signal to the target controller and the processor.

[0169] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the second controller is connected to the processor, determining that the target controller is the second controller; when the second controller is disconnected from the processor, determining that the target controller is the first controller.

[0170] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: the processor obtains and configures the communication parameters of the target controller; verifies the communication interface of the target controller and the communication interface of the processor; establishes a communication protocol between the target controller and the processor; and determines the initialization of the target controller and the processor based on the communication parameters, the communication interface and the communication protocol.

[0171] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: the processor obtains communication information of the target controller from the first register of the target controller; the processor configures parameters of the first register of the target controller based on the communication information; the processor obtains information of the communication channel corresponding to the target controller from the second register of the target controller; and the processor configures parameters corresponding to the communication channel in the second register of the target controller based on the information of the communication channel.

[0172] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the target controller is the second controller, the processor reads the level of the expansion pin through the second communication channel, and determines whether there is an abnormality in the current power-on state according to the level of the expansion pin, wherein the expansion pin is the pin used by the processor to connect to the second controller; when the current power-on state is abnormal, an alarm signal is generated and sent to the server; when the current power-on state is normal, the processor sends first power-on data to the second controller through the second communication channel; the second controller modifies the corresponding register according to the first power-on data and sends the modified register value to the corresponding first controller and / or third controller; in response to the server releasing the second communication channel, Based on communication parameters, communication interface and communication protocol, the first communication channel between the first controller and the processor is initialized; in response to the completion of initialization of the first communication channel, the processor sends second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, an alarm signal is generated and sent to the server; when the target controller is the first controller, the processor sends second startup data to the first controller through the first communication channel; the first controller monitors and records the startup status of the server according to the second startup data; when the startup status is abnormal, an alarm signal is generated and sent to the server.

[0173] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0174] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0175] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A bus communication method, characterized in that: The method is applied to a server, the server including a processor, a first controller, a second controller, a third controller, and a bus, wherein the bus includes a first communication channel and a second communication channel, the first controller communicates with the processor via the first communication channel, the second controller communicates with the processor via the second communication channel, and the third controller communicates with the processor via the first communication channel. The method includes: Determining a hardware configuration of the server according to a type of a processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; In response to the server being powered on, determining a target controller according to a hardware configuration of the server, wherein the target controller includes a first controller or a second controller; A third controller sends a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; In response to the target controller and the processor completing initialization, the target controller and the processor transmit startup data of the server through corresponding communication channels.

2. The bus communication method according to claim 1, wherein: Determining the hardware configuration of the server according to the type of the processing platform of the processor includes: determining, according to a type of a processing platform of the processor, whether the communication channel of the bus includes a second communication channel; When the communication channel of the bus includes the second communication channel, the second controller is connected to the processor; When the communication channels of the bus do not include the second communication channel, the second controller disconnects from the processor.

3. The bus communication method according to claim 1, wherein: Before the third controller sends the trigger signal to the target controller and the processor, the method further includes: The third controller monitors the power signal of the server; When the third controller detects a power stabilization signal, the third controller sends a trigger signal to the target controller and the processor.

4. The bus communication method according to claim 2, wherein: Determining the target controller according to the hardware configuration of the server includes: When the second controller is connected to the processor, determining that the target controller is the second controller; When the second controller is disconnected from the processor, the target controller is determined to be the first controller.

5. The bus communication method according to claim 1, wherein: Before the target controller and the processor transmit the startup data of the server through the corresponding communication channel, the method includes: The processor acquires and configures communication parameters of the target controller; Verifying the communication interface of the target controller and the communication interface of the processor; establishing a communication protocol between the target controller and the processor; Based on the communication parameters, the communication interface, and the communication protocol, initialization of the target controller and the processor is determined.

6. The bus communication method according to claim 5, characterized in that: The processor obtains and configures communication parameters of the target controller, including: The processor obtains the communication information of the target controller from the first register of the target controller; The processor configures parameters of a first register of the target controller according to the communication information; The processor obtains information of the communication channel corresponding to the target controller from the second register of the target controller; The processor configures parameters corresponding to the communication channel in the second register of the target controller according to the information of the communication channel.

7. The bus communication method according to claim 4, wherein: The target controller and the processor transmit the startup data of the server through the corresponding communication channel, including: When the target controller is the second controller, the processor reads the level of an expansion pin through the second communication channel, and determines whether there is an abnormality in the current power-on state according to the level of the expansion pin, wherein the expansion pin is a pin used by the processor to connect to the second controller, and the expansion pin is a pin used by the processor to connect to the second controller; When the current boot state is abnormal, generating and sending an alarm signal to the server; When the current startup state is normal, the processor sends the first startup data to the second controller through the second communication channel; The second controller modifies the corresponding register according to the first startup data and sends the modified register value to the corresponding first controller and / or third controller; In response to the server releasing the second communication channel, initializing a first communication channel between the first controller and the processor based on communication parameters, a communication interface, and a communication protocol; In response to the completion of initialization of the first communication channel, the processor sends second startup data to the first controller through the first communication channel; The first controller monitors and records the power-on status of the server according to the second power-on data; When the startup state is detected to be abnormal, an alarm signal is generated and sent to the server; When the target controller is the first controller, the processor sends second startup data to the first controller through the first communication channel; The first controller monitors and records the power-on status of the server according to the second power-on data; When the startup state is detected to be abnormal, an alarm signal is generated and sent to the server.

8. A bus communication device, characterized in that: Applied to a server, the server including a processor, a first controller, a second controller, a third controller, and a bus, wherein the bus includes a first communication channel and a second communication channel, the first controller communicates with the processor via the first communication channel, the second controller communicates with the processor via the second communication channel, and the third controller communicates with the processor via the first communication channel, the device including: A configuration module, configured to determine a hardware configuration of the server according to a type of a processing platform of the processor, wherein the hardware configuration includes a controller configuration and a bus configuration; a processing module, configured to determine a target controller in response to powering on the server and according to a hardware configuration of the server, wherein the target controller includes a first controller or a second controller; A trigger module, configured for a third controller to send a trigger signal to the target controller and the processor, wherein the trigger signal is used to instruct the target controller and the processor to initialize; The transmission module is configured to transmit the startup data of the server to the target controller and the processor via corresponding communication channels in response to completion of initialization of the target controller and the processor.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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