Driver substrate, display panel and display device

Abstract

This disclosure provides a driving substrate, a display panel, and a display device, belonging to the field of display technology. The driving substrate includes a decomposition circuit region; the decomposition circuit region includes a first decomposition circuit subregion and a second decomposition circuit subregion located on the side of the first decomposition circuit subregion away from the display area; in the first decomposition circuit subregion, the driving substrate is provided with a plurality of multiplexer circuits arranged in a row direction, each multiplexer circuit including a plurality of transistor units; the first electrode of each transistor in the same multiplexer circuit is electrically connected to the same source signal line, and the second electrode of each transistor in the same transistor unit is electrically connected to the same data line; the second decomposition circuit subregion has a plurality of gating signal lines corresponding one-to-one with the plurality of transistor units in the multiplexer circuit and extending in a row direction, and the gate of each transistor in the transistor unit is electrically connected to the corresponding gating signal line. The driving substrate can reduce the limitation of the multiplexer circuit on the performance of the display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a driving substrate, a display panel and a display device. BACKGROUND

[0002] Micro OLED technology is an OLED display technology driven by a silicon-based driving substrate, which often has a high resolution, for example, the resolution can be more than 3000 PPI. With the increasing demand of users for small-size products, the requirements for display definition and display effect are also increasing.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a driving substrate, a display panel and a display device, which reduce the restriction of the demultiplexing circuit on the performance of the display panel.

[0005] According to one aspect of the present disclosure, a driving substrate is provided, comprising a display area and a demultiplexing circuit area; the display area is provided with a data line for loading a data voltage to a pixel driving circuit; the demultiplexing circuit area comprises a first demultiplexing circuit sub-area and a second demultiplexing circuit sub-area located on the side of the first demultiplexing circuit sub-area away from the display area;

[0006] In the first demultiplexing circuit sub-area, the driving substrate is provided with a plurality of demultiplexing circuits arranged in a row direction, each demultiplexing circuit comprising a plurality of transistor units; the first poles of the transistors in the same demultiplexing circuit are electrically connected to the same source signal line, and the second poles of the transistors in the same transistor unit are electrically connected to the same data line;

[0007] The second demultiplexing circuit sub-area has a plurality of gate signal lines corresponding to the plurality of transistor units in the demultiplexing circuit and extending in the row direction, and the gates of the transistors of the transistor units are electrically connected to the corresponding gate signal lines.

[0008] According to one embodiment of the present disclosure, the size of the demultiplexing circuit in the column direction is a first size; the distance between the edge of the gate signal line closest to the display area and the edge of the gate signal line farthest from the display area is a second size; the second size is greater than the first size.

[0009] According to one embodiment of the present disclosure, the width of the gate signal line is greater than half the width of the channel region of the transistor in the demultiplexing circuit.

[0010] According to an embodiment of the present disclosure, the driving substrate comprises a transistor layer and a plurality of metal layers which are sequentially stacked; the transistor layer and the first metal layer are electrically connected through a metalized via, and two adjacent metal layers are electrically connected through a metalized via.

[0011] In the second decomposition circuit sub-region, the driving substrate is provided with a gate-on selection signal first transfer line corresponding to each transistor unit; the gate-on selection signal first transfer line extends along the column direction and is electrically connected to the gate of each transistor of the corresponding transistor unit.

[0012] The metal layer in which the gate-on selection signal first transfer line is located and the metal layer in which the gate-on selection signal line is located have at least one metal layer.

[0013] According to an embodiment of the present disclosure, the gate-on selection signal first transfer line is arranged to overlap with each gate-on selection signal line.

[0014] According to an embodiment of the present disclosure, the gate-on selection signal first transfer line and the electrically connected gate-on selection signal line have a gate-on selection signal fourth transfer line; the gate-on selection signal first transfer line is electrically connected to the corresponding gate-on selection signal line through the gate-on selection signal fourth transfer line; when the metal layer in which the gate-on selection signal fourth transfer line is located and the metal layer in which the gate-on selection signal first transfer line is located are arranged adjacently, the gate-on selection signal first transfer line and the gate-on selection signal fourth transfer line are electrically connected to each other through at least two columns of metalized vias; each column of metalized vias comprises at least three metalized vias arranged sequentially along the column direction.

[0015] According to an embodiment of the present disclosure, the first metal layer in the first decomposition circuit sub-region has a gate-on selection signal second transfer line corresponding to each transistor unit; the gate-on selection signal second transfer line is electrically connected to the gate of each transistor of the corresponding transistor unit through a metalized via.

[0016] The gate-on selection signal second transfer line has a via part for connecting with a metalized via and a wire part connected with the via part; the width of the wire part of the gate-on selection signal second transfer line is smaller than the width of the gate-on selection signal first transfer line.

[0017] According to an embodiment of the present disclosure, the driving substrate comprises a transistor layer and a plurality of metal layers which are sequentially stacked; the transistor layer and the first metal layer are electrically connected through a metalized via, and two adjacent metal layers are electrically connected through a metalized via.

[0018] In the second sub-decomposition circuit area, the driving substrate is provided with a source signal first adapter line extending along the column direction, one end of the source signal first adapter line is electrically connected with the source signal line, and the other end is electrically connected with the first electrode of each transistor of at least one transistor unit.

[0019] The metal layer between which the source signal first adapter line is located and the metal layer in which the gate signal line is located has at least one metal layer.

[0020] According to an embodiment of the present disclosure, the transistor unit comprises a plurality of transistors connected in parallel, each of the transistors is arranged along the column direction in sequence, and the length direction of the channel region of each transistor is the row direction.

[0021] The driving substrate is provided with a driving voltage first adapter line corresponding to each transistor unit and extending along the column direction in the first sub-decomposition circuit area, the driving voltage first adapter line is electrically connected with the second electrode of each transistor of the transistor unit, and is electrically connected with the data line.

[0022] According to an embodiment of the present disclosure, the multi-way decomposition circuit comprises a plurality of transistor unit groups, each of the transistor unit groups comprises two adjacent transistor units.

[0023] The driving substrate is provided with a source signal second adapter line corresponding to each transistor unit group in the first sub-decomposition circuit area, the source signal second adapter line is electrically connected with the first electrode of each transistor in the corresponding transistor unit group.

[0024] According to an embodiment of the present disclosure, the driving substrate comprises a data line group corresponding to at least part of the transistor unit groups, the data line group comprises two non-adjacent data lines, and the pixel driving circuit driven by the two data lines of the data line group is used to drive sub-pixels of the same color.

[0025] One data line of the data line group is electrically connected with the second electrode of each transistor of one transistor unit of the corresponding transistor unit group, and the other data line of the data line group is electrically connected with the second electrode of each transistor of the other transistor unit of the corresponding transistor unit group.

[0026] According to an embodiment of the present disclosure, the first sub-decomposition circuit area has a back gate structure in a ring shape, and each multi-way decomposition circuit is located in the space surrounded by the back gate structure.

[0027] The gate signal line is located on the side of the back gate structure away from the display area.

[0028] According to an embodiment of the present disclosure, the driving substrate comprises a semiconductor substrate and a plurality of metal layers which are sequentially stacked.

[0029] The back gate structure comprises a ring-shaped back gate doped region of the semiconductor substrate and a back gate trace of the first metal layer, the back gate trace being electrically connected with the back gate doped region through a metallized via.

[0030] The driving substrate further comprises a metal structure crossing the back gate structure, the metal layer where the metal structure crossing the back gate structure is located and the first metal layer being separated by at least one metal layer.

[0031] According to another aspect of the present disclosure, a display panel is provided, comprising the above-mentioned driving substrate.

[0032] According to still another aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0033] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0035] Figure 1 For an embodiment of the present disclosure, a structural schematic diagram of a display panel.

[0036] Figure 2 For an embodiment of the present disclosure, a structural schematic diagram of a display panel.

[0037] Figure 3 For an embodiment of the present disclosure, a partial structural schematic diagram of a driving substrate.

[0038] Figure 4 For an embodiment of the present disclosure, a partial structural schematic diagram of a driving substrate.

[0039] Figure 5 For an embodiment of the present disclosure, a partial structural schematic diagram of a driving substrate.

[0040] Figure 6 For an embodiment of the present disclosure, a principle schematic diagram of a demultiplexing circuit of a driving substrate.

[0041] Figure 7For an embodiment of the present disclosure, a driving timing diagram of a demultiplexing circuit of a driving substrate.

[0042] Figure 8 For an embodiment of the present disclosure, a structure diagram of a doped region of a driving substrate.

[0043] Figure 9 For an embodiment of the present disclosure, a structure diagram of a gate layer.

[0044] Figure 10 For an embodiment of the present disclosure, a structure diagram of a doped region and a gate layer.

[0045] Figure 11 For an embodiment of the present disclosure, a partial enlarged diagram of a doped region of a driving substrate.

[0046] Figure 12 For an embodiment of the present disclosure, a partial enlarged diagram of a doped region and a gate layer.

[0047] Figure 13 For an embodiment of the present disclosure, a structure diagram of a first metal layer.

[0048] Figure 14 For an embodiment of the present disclosure, a structure diagram of a first metal layer, a first metallized via, a gate layer, and a doped region.

[0049] Figure 15 For an embodiment of the present disclosure, a structure diagram of a second metal layer.

[0050] Figure 16 For an embodiment of the present disclosure, a structure diagram of a first metal layer, a second metallized via, and a second metal layer.

[0051] Figure 17 For an embodiment of the present disclosure, a structure diagram of a third metal layer.

[0052] Figure 18 For an embodiment of the present disclosure, a structure diagram of a second metal layer, a third metallized via, and a third metal layer.

[0053] Figure 19 For an embodiment of the present disclosure, a structure diagram of a fourth metal layer.

[0054] Figure 20 For an embodiment of the present disclosure, a structure diagram of a third metal layer, a fourth metallized via, and a fourth metal layer.

[0055] Figure 21For an embodiment of the present disclosure, a schematic diagram of a stack structure of a doped region, a gate layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer.

[0056] Figure 22 For an embodiment of the present disclosure, a schematic diagram of a stack structure of a doped region, a gate layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. DETAILED DESCRIPTION

[0057] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the specification. It will be understood that, although the terms first, second, third etc. can be used herein to describe various elements / regions, these elements / regions should not be limited by these terms since such elements / regions can be labeled by other terms as long as the elements / regions are clearly traceable.

[0058] Although relative terms are used herein, such as "on", "under", to describe a relative position of one component to another in the figures, these terms are used herein for convenience only and are not intended to limit the scope of the application to only such relative positions as shown in the figures. It is to be understood that if the device of the figures is turned over, such that what is described as "on" is then "under", then such will be within the scope of the application. When a structure is "on" another structure, it can mean that the structure is formed directly on the other structure or that the structure is "directly on" the other structure, or that the structure is "indirectly on" the other structure by having another structure interposed therebetween.

[0059] The terms "one", "a", "an", "the", and "at least one" are used to indicate that "one or more" of the indicated element / s can be present with the understanding that these terms should be interpreted in the light of the number of the element / s or components actually present. The terms "including" and "having" should be construed as "open" inclusive meaning that there can be additional elements / s or components present in addition to those listed. The terms "first", "second", and "third" and the like are merely used to identify one of the elements / s, and are not to be construed as limiting the number of the elements / s.

[0060] The present disclosure provides a display panel PNL and a driving substrate BP used in the display panel PNL. Referring to Figure 1 The display panel PNL includes a display area AA and a peripheral area BB located at least one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with display units UU arranged in an array, the display units UU include sub-pixels PX and pixel driving circuits PDC for driving the sub-pixels PX. The display panel PNL is not provided with display units UU in the peripheral area BB, or the display units UU provided are not used for displaying a picture. Referring toFigure 1 The display panel PNL is provided with a plurality of scan signal lines GateL extending along the row direction DH in the display area AA, each scan signal line GateL being provided in one-to-one correspondence with each display unit UU row. The pixel driving circuit PDC of each display unit UU in the display unit UU row is electrically connected with the corresponding scan signal line GateL. The display panel PNL is further provided with a plurality of data lines DL extending along the column direction DV in the display area AA, each data line DL being provided in one-to-one correspondence with each display unit UU column. The pixel driving circuit PDC of each display unit UU in the display unit UU column is electrically connected with the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit UU is connected with one scan signal line GateL and one data line DL. When a scan signal is loaded on the scan signal line GateL, the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PX according to the written driving voltage.

[0061] In some embodiments of the present disclosure, the sub-pixels PX can include sub-pixels PX of multiple different colors, for example, red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PX in the display area AA can also have sub-pixels PX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0062] In an embodiment of the present disclosure, referring to Figure 2 The display panel PNL includes a driving substrate BP and a sub-pixel layer PXL which are sequentially stacked. The sub-pixel layer PXL is provided with a light emitting element LD for emitting light, for example, an OLED; the driving substrate BP is provided with a pixel driving circuit PDC for driving the light emitting element LD. In Figure 2 In the example, the sub-pixel PX includes a light emitting element LD and a color film unit located on the light emitting side (for example, the side away from the driving substrate BP) of the light emitting element LD. The light emitting element LD can emit white light, for example, the light emitting element LD can emit white light formed by mixing multiple colored light; the white light emitted by the light emitting element LD is filtered by the color film unit and emitted as colored light. For example, the white light emitted by the light emitting element LD is filtered by the red color film unit and emitted as red light, and this sub-pixel PX is a red sub-pixel; the white light emitted by the light emitting element LD is filtered by the green color film unit and emitted as green light, and this sub-pixel PX is a green sub-pixel; the white light emitted by the light emitting element LD is filtered by the blue color film unit and emitted as blue light, and this sub-pixel PX is a blue sub-pixel.

[0063] Optionally, the light emitting element LD can be a current-driven self-luminous element, for example, can be any one of OLED, PLED, QLED, MicrOLED, MiNiLED, etc.

[0064] In an example, the light emitting element LD is an OLED, for example, is a white light OLED.

[0065] It can be understood that in other embodiments of the present disclosure, the sub-pixel PX can also adopt other structures, for example, the OLED or MicrOLED light emitting element can directly emit light and display as the sub-pixel PX without further color conversion.

[0066] In an embodiment of the present disclosure, referring to Figure 3 , the driving substrate BP includes a transistor layer ML and a multi-layer metal layer which are sequentially stacked; the transistor layer ML is provided with transistors, for example, transistors required by the pixel driving circuit PDC, transistors required by the multi-channel decomposition circuit DM, etc. As needed, the transistors can be NMOS transistors or PMOS transistors.

[0067] In the embodiment of the present disclosure, the metal layer closest to the transistor layer ML is referred to as the first metal layer M1. An insulating layer (for example, an inorganic insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer) is provided between the first metal layer M1 and the transistor layer ML and between adjacent metal layers; a metalized via (for example, a tungsten column) is provided in the insulating layer to electrically connect the first metal layer M1 and the transistor layer ML and to electrically connect adjacent metal layers.

[0068] In an example, referring to Figure 3 , the driving substrate BP includes a semiconductor substrate SBT (for example, a single crystal silicon substrate), and a CMOS process can be used to form the required doped regions on the semiconductor substrate SBT, wherein part of the doped regions can be used as active areas BAA to form transistors. On the surface of the semiconductor substrate SBT, a gate insulating layer GI and a gate layer GT can be sequentially formed and patterned. In this way, the active areas BAA of the semiconductor substrate SBT, the gate insulating layer GI, and the gate layer GT can form the required transistors. In an example, the gate layer GT can be made of a non-metallic material, for example, the gate layer can be made of a polycrystalline silicon which is conductorized.

[0069] In an example, referring to Figure 3The driving substrate BP includes a first insulating layer D1, a first metal layer M1, a second insulating layer D2, a second metal layer M2, a third insulating layer D3, a third metal layer M3, a fourth insulating layer D4, a fourth metal layer M4, and the like, which are sequentially stacked on one side of the transistor layer ML. The first insulating layer D1 is embedded with a tungsten column as a first metallized via V1. The transistor layer ML is electrically connected to the first metal layer M1 through the first metallized via V1, for example, the source, drain, gate, and the like of the transistor are electrically connected to the first metal layer M1 through the first metallized via V1. The second metallized via V2 is provided in the second insulating layer D2, and the second metal layer M2 is electrically connected to the first metal layer M1 through the second metallized via V2; the third metallized via V3 is provided in the third insulating layer D3, and the third metal layer M3 is electrically connected to the second metal layer M2 through the third metallized via V3; the fourth metallized via V4 is provided in the fourth insulating layer D4, and the fourth metal layer M4 is electrically connected to the third metal layer M3 through the fourth metallized via V4, and so on. In the example of Figure 3 In the example of the present disclosure, only four metal layers are shown. According to needs, the driving substrate BP can be provided with more metal layers.

[0070] In an embodiment of the present disclosure, the driving substrate BP is prepared by using a single crystal silicon CMOS process.

[0071] In an embodiment of the present disclosure, the driving substrate BP can support high-resolution display, for example, support 4K display. In an example, the resolution of the display panel PNL can reach 3956PPI or higher.

[0072] Figure 4 In an embodiment of the present disclosure, a planar structure diagram of the driving substrate BP is shown. Referring to Figure 4 In the example of the present disclosure, the driving substrate BP is provided with a decomposition circuit area DMA and a source signal line SL in the peripheral area BB, the decomposition circuit area DMA is provided with a plurality of decomposition circuits DM, and the source signal line SL can be electrically connected to the signal end of the source driving circuit. The plurality of decomposition circuits DM are one-to-one corresponding to the source signal line SL, and the plurality of decomposition circuits DM are electrically connected to a plurality of data lines DL and a plurality of gate signal lines. Under the control of the gate signal on the gate signal line, the plurality of decomposition circuits DM can make the source signal line SL and the data line DL electrically connected one by one and selectively, and then make the driving voltage loaded on the source signal line SL loaded on different data lines DL. In this way, one signal end of the source driving circuit can drive a plurality of data lines DL, thereby reducing the cost or size of the source driving circuit.

[0073] In one example, the source driving circuit can be a part of the driving substrate BP, for example, the source driving circuit is fabricated synchronously with the display area AA, or the source driving circuit is pre-packaged on the driving substrate BP by packaging process.

[0074] In another example, the source driving circuit is not a part of the driving substrate BP, but is connected to the driving substrate BP after the driving substrate BP is fabricated, for example, the source driving circuit (which can be a source driving chip or a display driving chip or other chip capable of realizing source driving) is bound or bonded to the chip binding area reserved on the driving substrate BP by patching process.

[0075] The demultiplexing circuit DM has a plurality of channel units, each of which includes one or more transistors. The channel unit is electrically connected with a data line DL and a gate signal line, and is electrically connected with a source signal line SL. Specifically, the gate of each transistor in the channel unit is electrically connected with a gate signal line, the second pole of each transistor in the channel unit is electrically connected with a data line DL, and the first pole of each transistor in the channel unit is electrically connected with a source signal line SL. When the gate signal line to which the channel unit is electrically connected is loaded with a gate signal (for example, a high level or a low level capable of making each transistor in the channel unit conductive) that makes the transistor conductive, the channel unit is opened, thereby enabling the signal loaded on the source signal line SL to be loaded to the data line DL.

[0076] As an example, the demultiplexing circuit DM can have 3-12 channel units, for example, the demultiplexing circuit DM can have 6 channel units.

[0077] In this embodiment, for ease of description, each conductive structure can be assigned to a corresponding signal channel based on its connection to the channel unit. Each signal channel is a set of conductive structures carrying the same type of signal. Specifically, a structure electrically connected to the gate of each transistor in the channel unit, such as the transistor gate, a gating signal line electrically connected to the transistor gate, or a trace electrically connecting the transistor gate to the gating signal line, is considered a gating signal channel. When a gating signal (e.g., a low-level signal or a high-level signal) is applied to the gating signal line of this gating signal channel, the channel unit controlled by this gating signal channel is turned on. A structure electrically connected to the second electrode of each transistor in the channel unit, such as the second electrode of the transistor, a data line DL electrically connected to the second electrode of the transistor, or a trace electrically connecting the second electrode of the transistor to the data line DL, is considered a data voltage channel. When each transistor in the channel unit is turned on, the voltage on the first electrode of the transistor can be written into this data voltage channel. A structure electrically connected to the first terminal of each transistor in a channel unit, such as the first terminal of the transistor, the source signal line SL electrically connected to the first terminal of the transistor, and the trace that electrically connects the first terminal of the transistor to the source signal line SL, constitutes a source signal channel. As an example, a multiplexer circuit DM connects a source signal channel and connects multiple gating signal channels and drive voltage channels.

[0078] In the peripheral area BB, the driving substrate BP can be provided with other circuits. These circuits can be directly fabricated by CMOS process during the fabrication of the driving substrate BP, or they can be formed on the driving substrate BP by packaging process.

[0079] In one example, the driving substrate BP has a variety of functional units with different functions pre-fabricated or packaged on the peripheral region BB. For example, one or more of the functional units such as memory, timing controller, communication interface, image processing module, source driving circuit, and gate driving circuit are provided on the peripheral region BB.

[0080] In another example, the driver substrate BP has one or more chip bonding areas on its peripheral area BB, and each chip bonding area contains bonding pads for bonding with a specific chip. For example, the driver substrate BP may have pre-selected chip bonding areas on its peripheral area BB for bonding a display driver chip, and the driver substrate BP can be bonded and connected to the display driver chip.

[0081] The display panel and the display device provided by the embodiments of the present disclosure can be used in wearable devices, personal digital assistants, clocks, global positioning system receivers / navigators, virtual reality devices, augmented reality devices, mixed reality devices, extended reality devices, sights, range finders, and other display products or components with high pixel density.

[0082] In the related art, the demultiplexing circuit DM is arranged in overlap with the strobe signal lines for controlling the demultiplexing circuit DM, which causes the data line DL connected to any one channel to be arranged in overlap with each strobe signal line, which causes the load of the data line DL to be large and obvious driving voltage transmission delay phenomenon to occur, which not only easily causes the picture display effect to be poor (e.g., horizontal lines occur) due to insufficient charging of the sub-pixel PX, but also limits the improvement of the refresh rate of the display panel PNL.

[0083] The embodiments of the present disclosure reduce the interference between different signal channels by optimizing the structure in the demultiplexing circuit region DMA, which is beneficial to improve the display quality and the refresh rate.

[0084] In the embodiments of the present disclosure, referring to Figure 5 and Figure 6 , the driving substrate BP is arranged with the demultiplexing circuit region DMA in the peripheral region BB, and the demultiplexing circuit region DMA includes a first demultiplexing circuit sub-region DMA1 and a second demultiplexing circuit sub-region DMA2 located away from the display region AA on the side of the first demultiplexing circuit sub-region DMA1. In the first demultiplexing circuit sub-region DMA1, the driving substrate BP is arranged with a plurality of demultiplexing circuits DM arranged in sequence along the row direction DH, and each demultiplexing circuit DM includes a plurality of transistor units MU as channel units; the first electrode MS of each transistor in the same demultiplexing circuit DM is electrically connected to the same source signal line SL, and the second electrode MD of each transistor in the same transistor unit MU is electrically connected to the same data line DL. The second demultiplexing circuit sub-region DMA2 has a plurality of strobe signal lines MUXL corresponding to the plurality of transistor units MU in the demultiplexing circuit DM one by one, and the gate electrode MG of each transistor of the transistor unit MU is electrically connected to the corresponding strobe signal line MUXL; the strobe signal line MUXL extends along the row direction DH.

[0085] In the embodiment of the present disclosure, the demultiplexing circuit DM is arranged in the first demultiplexing sub-region DMA1, and the selection signal line MUXL is arranged in the second demultiplexing sub-region DMA2, so that the second poles MD of the transistors of the demultiplexing circuit DM are not overlapped with the selection signal line MUXL, which makes the coupling capacitance between the driving voltage channel and the selection signal channel not formed or substantially not formed, avoids the problem that the excessive parasitic capacitance of the driving voltage channel causes the signal delay of the driving voltage to be excessively large when the driving voltage is loaded, and further avoids the problem that the excessive parasitic capacitance of the driving voltage channel causes the charging rate of the pixel driving circuit PDC to be insufficient. This can improve the display quality caused by the insufficient charging rate. Moreover, the signal delay of the driving voltage on the driving voltage channel is small, which is beneficial to improve the refresh rate of the display panel.

[0086] On the other hand, the coupling capacitance between the selection signal line MUXL and the data line DL is not formed or substantially not formed, which can reduce the influence of the signal change on the selection signal channel on the signal on the driving voltage channel, and further improve the accuracy and stability of the driving voltage on the driving voltage channel, and further improve the quality of the display panel.

[0087] Furthermore, each transistor unit MU of the demultiplexing circuit DM is a channel unit, which has a plurality of transistors, and the transistors in the same channel unit are arranged in parallel, which is beneficial to improve the current when the source signal channel loads the driving voltage to the driving voltage channel, and avoids the restriction of the insufficient driving capability of the transistor unit MU on the refresh rate.

[0088] Furthermore, the coupling capacitance between the data line DL and the selection signal line MUXL is reduced, and the crosstalk of the driving voltage on the driving voltage channel to the selection signal line MUXL is also reduced, the stability of the selection signal on the selection signal line MUXL is improved, and the signal waveform on the selection signal line MUXL is further avoided to be deteriorated to restrict the refresh rate of the display panel PNL.

[0089] In Figure 6In the example of FIG. 1, each demultiplexing circuit DM includes six transistor units MU, respectively labeled as a first transistor unit MU1, a second transistor unit MU2, a third transistor unit MU3, a fourth transistor unit MU4, a fifth transistor unit MU5, and a sixth transistor unit MU6, each of which includes three transistors. Correspondingly, the number of selection signal lines MUXL is six and corresponds to the six transistor units MU one-to-one, respectively a first selection signal line MUXL1, a second selection signal line MUXL2, a third selection signal line MUXL3, a fourth selection signal line MUXL4, a fifth selection signal line MUXL5, and a sixth selection signal line MUXL6. That is, the first selection signal line MUXL1 is electrically connected to the gate MG of each transistor of the first transistor unit MU1, the second selection signal line MUXL2 is electrically connected to the gate MG of each transistor of the second transistor unit MU2, the third selection signal line MUXL3 is electrically connected to the gate MG of each transistor of the third transistor unit MU3, the fourth selection signal line MUXL4 is electrically connected to the gate MG of each transistor of the fourth transistor unit MU4, the fifth selection signal line MUXL5 is electrically connected to the gate MG of each transistor of the fifth transistor unit MU5, and the sixth selection signal line MUXL6 is electrically connected to the gate MG of each transistor of the sixth transistor unit MU6. The source signal line SL is electrically connected to the first pole MS of each transistor.

[0090] In an embodiment of the present disclosure, referring to FIG. 1, Figure 5 the first demultiplexing circuit sub-region DMA1 has a back gate structure BG in a ring shape, and each demultiplexing circuit DM is located in a space surrounded by the back gate structure BG; and the selection signal line MUXL is located on a side of the back gate structure BG away from the display region AA.

[0091] Optionally, referring to FIG. 1, Figure 3 the back gate structure BG includes a back gate doped region BG1 on the semiconductor substrate SBT and a back gate trace BG2 on the first metal layer M1, and the back gate trace BG2 is electrically connected to the back gate doped region BG1 through a metalized via. The driving substrate BP is further provided with a metal structure crossing the back gate structure BG, and the metal layer on which the metal structure crossing the back gate structure BG is located is spaced apart from the first metal layer M1 by at least one metal layer, so as to reduce the coupling between the metal structure crossing the back gate structure BG and the back gate trace BG2.

[0092] For example, the source signal channel needs to cross the back gate structure BG to be electrically connected to the first pole MS of the transistor, and the metal structure of the source signal channel crossing the back gate structure BG can be provided on the third metal layer M3, the fourth metal layer M4, or a metal layer farther away from the semiconductor substrate SBT.

[0093] For example, the selection signal channel needs to cross the back gate structure BG to be electrically connected with the gate MG of the transistor, and the metal structure of the selection signal channel crossing the back gate structure BG can be arranged in the third metal layer M3, the fourth metal layer M4, or a metal layer farther away from the semiconductor substrate SBT.

[0094] For example, the driving voltage channel needs to cross the back gate structure BG to be electrically connected with the demultiplexing circuit DM, and the metal structure of the driving voltage channel crossing the back gate structure BG can be arranged in the third metal layer M3, the fourth metal layer M4, or a metal layer farther away from the semiconductor substrate SBT.

[0095] In the related art, the selection signal lines are arranged to overlap the demultiplexing circuit DM so that the signals on the selection signal lines can be loaded to the gates of the transistors of the demultiplexing circuit DM. The total width of each selection signal line and the gap between the selection signal lines cannot exceed the width of the demultiplexing circuit DM. However, the width (the size in the column direction DV) of the demultiplexing circuit DM is limited, which leads to the width of the selection signal lines and the gap between the selection signal lines being restricted. The selection signal lines cannot be arranged to have a larger width as needed, which leads to the impedance of the selection signal lines being large and the delay of the selection signal being large. The size of the gap between the selection signal lines is limited, which leads to crosstalk being prone to occur between the selection signal lines, and further leads to the waveform of the selection signal being deteriorated; the coupling capacitance between the selection signal lines is large, which further increases the load of the selection signal and further increases the delay of the selection signal. Therefore, in the related art, there is a risk that the delay of the selection signal is large and the waveform of the selection signal is deteriorated, which further restricts the improvement of the refresh rate of the display panel PNL.

[0096] In the embodiments of the present disclosure, the selection signal lines MUXL are no longer arranged to overlap the demultiplexing circuit DM, and the width of the selection signal lines MUXL and the width of the gap between adjacent selection signal lines MUXL are no longer restricted by the size of the demultiplexing circuit DM. Therefore, the delay and the waveform of the selection signal can be improved by increasing the width of the selection signal lines MUXL, or by increasing the gap between the selection signal lines MUXL, or by increasing the width of the selection signal lines MUXL and increasing the gap between the selection signal lines MUXL at the same time.

[0097] In an embodiment of the present disclosure, referring to Figure 12 , the size of the demultiplexing circuit DM in the column direction DV is a first size X1; referring to Figure 17The distance between the edge of the selection signal line MUXL closest to the display area AA and the edge of the selection signal line MUXL farthest from the display area AA is a second dimension X2; the second dimension X2 is greater than the first dimension X1. The second dimension is the sum of the width of each selection signal line MUXL and the width of the gap between the selection signal lines MUXL.

[0098] Optionally, the second dimension is 1.5 to 5 times the first dimension. For example, the second dimension is 1.5 times, 1.7 times, 1.9 times, 2.1 times, 2.3 times, 2.5 times, 2.7 times, 2.9 times, or 3.1 times the first dimension.

[0099] In an embodiment of the present disclosure, the width of the selection signal line MUXL is greater than half the width of the channel region of the transistor in the demultiplexing circuit DM. In this way, the selection signal line MUXL has a greater width and can reduce the impedance.

[0100] Optionally, the width of the selection signal line MUXL is 0.6 to 1.5 times the width of the channel region of the transistor, for example, 0.6 times, 0.7 times, 0.8 times, 0.9 times, 1 times, 1.1 times, 1.2 times, 1.3 times, 1.4 times, or 1.5 times. As an example, the width of the selection signal line MUXL is 0.9 to 1.1 times the width of the channel region of the transistor.

[0101] In an embodiment of the present disclosure, the width of the gap between the selection signal lines MUXL can be no less than 0.2 times the width of the channel region of the transistor in the demultiplexing circuit DM. In this way, the gap between the selection signal lines MUXL is large, the parasitic capacitance between adjacent selection signal lines MUXL is small, the load of the selection signal channel can be reduced to reduce power consumption, and the delay and waveform of the selection signal on the selection signal channel can be improved.

[0102] Optionally, the width of the selection signal line MUXL is 0.3 to 0.7 times the width of the channel region of the transistor, for example, 0.3 times, 0.35 times, 0.4 times, 0.45 times, 0.5 times, 0.55 times, 0.6 times, 0.65 times, or 0.7 times.

[0103] In an example, the distance between the selection signal lines MUXL is no less than 0.5 microns, for example, 0.5 to 1.0 microns. For example, the distance between the selection signal lines MUXL is 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, or 1.0 microns.

[0104] In an example, the width of the selection signal line MUXL is not less than 1.75 microns, in particular not less than 2 microns, for example between 2.0-3.5 microns. For example, the width of the selection signal line MUXL is 2.0 microns, 2.3 microns, 2.6 microns, 2.9 microns, 3.2 microns or 3.5 microns.

[0105] In an embodiment of the present disclosure, each selection signal line MUXL is arranged on the same metal layer, so that the coupling capacitance caused by the overlapping of the selection signal lines MUXL can be avoided.

[0106] In an embodiment of the present disclosure, referring to Figure 6 , Figure 13 and Figure 14 , the driving substrate BP is provided with a selection signal first transfer line GL1 corresponding to each transistor unit MU in the second decomposition circuit sub-region DMA2, the selection signal first transfer line GL1 extends along the column direction DV and is electrically connected to the gate MG of each transistor of the corresponding transistor unit MU. The metal layer on which the selection signal first transfer line GL1 is arranged is at least one metal layer different from the metal layer on which the selection signal line MUXL is arranged.

[0107] In this embodiment, the selection signal on the selection signal line MUXL can be transferred to the selection signal first transfer line GL1, and then loaded to the gate MG of each transistor of the corresponding transistor unit MU through the selection signal first transfer line GL1. At least part of the selection signal first transfer line GL1 inevitably overlaps with the selection signal lines MUXL of other selection signal channels in the second decomposition circuit sub-region DMA2. In this embodiment, the selection signal first transfer line GL1 and the selection signal line MUXL are arranged on different metal layers, so that a larger spacing between the selection signal first transfer line GL1 and the selection signal lines MUXL of other selection signal channels can be ensured, thereby reducing the coupling capacitance between the selection signal first transfer line GL1 and the selection signal lines MUXL of other selection signal channels.

[0108] In an example, the selection signal line MUXL and the selection signal first transfer line GL1 are spaced apart by 1-3 metal layers, for example, 1 metal layer, 2 metal layers or 3 metal layers.

[0109] In an example, referring to Figure 6 and Figure 21 , each selection signal first transfer line GL1 overlaps with each selection signal line MUXL. For example, each selection signal first transfer line GL1 has the same length and overlaps with each selection signal line MUXL, so that the load of different selection signal channels can be ensured to be the same.

[0110] In this embodiment, compared with the gate signal first transition line GL1, the gate signal line MUXL can be arranged in a metal layer closer to the transistor layer ML, or in a metal layer farther away from the transistor layer ML.

[0111] In this embodiment, referring to Figure 13 to Figure 18 , each metal layer between the gate signal first transition line GL1 and the gate signal line MUXL to which it is electrically connected can be provided with a gate signal fourth transition line GL4 corresponding to the gate signal first transition line GL1, and the gate signal first transition line GL1, the gate signal fourth transition line GL4 adjacent to the gate signal first transition line GL1, the adjacent gate signal fourth transition line GL4, the gate signal line MUXL and the adjacent gate signal fourth transition line GL4 are electrically connected through a metallized via. In this way, the gate signal first transition line GL1 and the corresponding gate signal line MUXL are electrically connected through the metallized via and the gate signal fourth transition line GL4. In other words, on the same gate signal channel, the gate signal first transition line GL1 and the first gate signal line MUXL are electrically connected through the gate signal fourth transition line GL4.

[0112] In an example, referring to Figure 16 and Figure 18 , the normal projection of the gate signal fourth transition line GL4 corresponding to the gate signal first transition line GL1 on the plane of the driving substrate BP is located within the normal projection range of the gate signal first transition line GL1 on the plane of the driving substrate BP, and is located within the normal projection range of the corresponding gate signal line MUXL on the plane of the driving substrate BP. In this way, the gate signal fourth transition line GL4 only overlaps with the gate signal first transition line GL1 and the gate signal line MUXL of the same gate signal channel, and does not overlap with the gate signal line MUXL and the gate signal first transition line GL1 of other gate signal channels, and will not cause the load of the gate signal channel to increase.

[0113] In an example, referring to Figure 16 , within the same gate signal channel, the gate signal first transition line GL1 and the adjacent gate signal fourth transition line GL4 are electrically connected to each other through at least two columns of metallized vias, and each column of metallized vias includes at least three metallized vias arranged in sequence along the column direction DV. In this way, the gate signal first transition line GL1 and the adjacent gate signal fourth transition line GL4 have multiple metallized vias and have a smaller resistance, which is beneficial to reducing the load and delay of the gate signal channel.

[0114] In this example, the first gate line GL1 is connected to the fourth gate line GL4 by not less than 6 metalized vias, and these metalized vias are arranged in at least two columns. This is mainly due to the fact that the gate line MUXL is arranged in the second decomposition circuit sub-region DMA2 and its size is no longer limited by the size of the first decomposition circuit sub-region DMA1, and the electrical connection between different metal layers also has more flexible design space to reduce resistance. Optionally, the first gate line GL1 is connected to the fourth gate line GL4 by not less than 6 metalized vias, such as 6, 8, 10, 12, 14, 16, 18 or 20 metalized vias, and these metalized vias are arranged in at least two columns. Further, the first gate line GL1 is connected to the fourth gate line GL4 by at least 10 metalized vias.

[0115] Correspondingly, in the same gate channel, the fourth gate line GL4 is connected to the adjacent fourth gate line GL4 by not less than 6 metalized vias, and these metalized vias are arranged in at least two columns. For example, connected by 6-20 metalized vias. It can be understood that when there is only one layer of metal between the first gate line GL1 and the gate line MUXL, only one fourth gate line GL4 is arranged between the first gate line GL1 and the gate line MUXL instead of multiple fourth gate lines GL4.

[0116] Correspondingly, referring to Figure 18 , in the same gate channel, the fourth gate line GL4 is connected to the adjacent fourth gate line GL4 by not less than 6 metalized vias, and these metalized vias are arranged in at least two columns; for example, connected by 6-20 metalized vias. Further, the fourth gate line GL4 is connected to the adjacent fourth gate line GL4 by at least 10 metalized vias.

[0117] In an embodiment of the present disclosure, referring to Figure 6 , Figure 13 and Figure 14The first metal layer M1 has a second gating signal adapter GL2 in the first decomposition circuit subregion DMA1, corresponding one-to-one with each transistor unit MU. The second gating signal adapter GL2 is electrically connected to the gate MG of each transistor in the corresponding transistor unit MU through a metallized via. The first metal layer M1 also needs to provide a second source signal adapter SL2 in the first decomposition circuit subregion DMA1. This second source signal adapter SL2 is electrically connected to the first terminal MS of each transistor in the transistor unit MU through a metallized via. The first metal layer M1 also needs to provide a first driving voltage adapter DL1 in the first decomposition circuit subregion DMA1, corresponding one-to-one with each transistor unit MU. This first driving voltage adapter DL1 is electrically connected to the second terminal MD of each transistor in the corresponding transistor unit MU. Thus, the first driving voltage adapter DL1, the second gating signal adapter GL2, and the second source signal adapter SL2 are all located in the first metal layer M1 and are all electrically connected to the transistors, but belong to different signal channels. To reduce the coupling between the three signal channels, the width of the second gating signal adapter GL2 needs to be limited. For example, the second adapter line GL2 for the strobe signal has a via portion L22 for connection to a metallized via and a trace portion L21 connected to the via portion L22. The via portion has a larger width so that it can be electrically connected to the gate MG of the transistor through more first metallized vias V1. The width of the trace portion L21 is smaller than that of the via portion to reduce the spacing between the trace portion L21 and the first adapter line DL1 for the drive voltage and the second adapter line SL2 for the source signal.

[0118] In one example, participants Figure 16 The width of the trace portion of the second gating signal adapter GL2 is smaller than the width of the first gating signal adapter GL1. In other words, the first gating signal adapter GL1 located in the second decomposition circuit subregion DMA2 can have a larger width. Since no drive voltage path is provided in this second decomposition circuit subregion DMA2, there is sufficient space to accommodate a larger width for the first gating signal adapter GL1. Furthermore, the width of the first gating signal adapter GL1 is greater than the width of the via portion of the second gating signal adapter GL2. Therefore, the resistance of the first gating signal adapter GL1 is smaller, and although the gating signal line MUXL is located outside the first decomposition circuit subregion DMA1, it does not result in a large resistance between the gating signal line MUXL and the second gating signal adapter GL2.

[0119] In one embodiment of this disclosure, the first switching line GL1 and the second switching line GL2 of the gating signal are directly connected to each other, or they can be connected through other metal structures to ensure the electrical continuity of the gating signal channel.

[0120] In an example, referring to Figure 6 The gate signal channel further comprises a gate signal third jumper line GL3 crossing the back gate structure BG and electrically connected with the gate signal first jumper line GL1 and the gate signal second jumper line GL2 at both ends. It can be understood that the gate signal third jumper line GL3 can be directly electrically connected with the gate signal first jumper line GL1 through the metallized via VV, or indirectly electrically connected with the gate signal first jumper line GL1 through other metal layers. The gate signal third jumper line GL3 can be directly electrically connected with the gate signal second jumper line GL2 through the metallized via VV, or indirectly electrically connected with the gate signal second jumper line GL2 through other metal layers. Further, the metal layer where the gate signal third jumper line GL3 is located is at least one layer of metal layer apart from the first metal layer M1.

[0121] In an embodiment of the present disclosure, referring to Figure 6 and Figure 16 In the second decomposition circuit sub-region DMA2, the driving substrate BP is provided with a source signal first jumper line SL1 extending along the column direction DV, one end of the source signal first jumper line SL1 being electrically connected with the source signal line SL, and the other end being electrically connected with the first electrode MS of each transistor of at least one transistor unit MU. Wherein, the metal layer where the source signal first jumper line SL1 is located is at least one layer of metal layer apart from the metal layer where the gate signal line MUXL is located. In this way, the coupling between the source signal channel and the gate signal channel can be reduced.

[0122] In an embodiment of the present disclosure, referring to Figure 16 The source signal first jumper line SL1 and the gate signal first jumper line GL1 can be arranged on the same metal layer and arranged side by side.

[0123] In an embodiment of the present disclosure, referring to Figure 16 The source signal line SL and the source signal first jumper line SL1 can be arranged on the same metal layer. For example, the source signal line SL has a branch extending along the row direction DH near the end of the second decomposition circuit sub-region DMA2, and the source signal first jumper line SL1 is connected with the branch of the source signal line SL near the end of the source signal line SL.

[0124] In an embodiment of the present disclosure, referring to Figure 6The source signal channel further comprises a source signal third jumper line SL3 crossing the back gate structure BG and electrically connected at both ends to the source signal first jumper line SL1 and the source signal second jumper line SL2 respectively. It can be understood that the source signal third jumper line SL3 can be directly electrically connected to the source signal first jumper line SL1 through the metallized via VV, or indirectly electrically connected to the source signal first jumper line SL1 through other metal layers. The source signal third jumper line SL3 can be directly electrically connected to the source signal second jumper line SL2 through the metallized via VV, or indirectly electrically connected to the source signal second jumper line SL2 through other metal layers.

[0125] In an embodiment of the present disclosure, referring to Figure 6 The drive voltage channel further comprises a drive voltage second jumper line DL2 crossing the back gate structure BG and electrically connected at both ends to the drive voltage first jumper line DL1 and the data line DL respectively. It can be understood that the drive voltage second jumper line DL2 can be directly electrically connected to the drive voltage first jumper line DL1 through the metallized via VV, or indirectly electrically connected to the drive voltage first jumper line DL1 through other metal layers. The drive voltage second jumper line DL2 can be directly electrically connected to the data line DL through the metallized via VV, or indirectly electrically connected to the data line DL through other metal layers.

[0126] In an embodiment of the present disclosure, referring to Figure 6 and Figure 12 The transistor unit MU comprises a plurality of parallel transistors, each of which is arranged in sequence along the column direction DV, and the channel region length direction of each transistor is the row direction DH. Among the same transistor unit MU, the gates MG of each transistor are arranged in a straight line along the column direction DV, the first poles MS of each transistor are arranged in a straight line along the column direction DV, and the second poles MD of each transistor are arranged in a straight line along the column direction DV. The drive voltage first jumper line DL1 electrically connected to the transistor unit MU can extend along the column direction DV and be electrically connected to the second poles MD of each transistor through the first metallized via V1.

[0127] Correspondingly, referring to Figure 6 The gate signal second jumper line GL2 electrically connected to the transistor unit MU can also extend along the column direction DV and be electrically connected to the gates MG of each transistor through the first metallized via V1.

[0128] Correspondingly, referring to Figure 6 The source signal second jumper line SL2 electrically connected to the transistor unit MU can also extend along the column direction DV and be electrically connected to the first poles MS of each transistor through the first metallized via V1.

[0129] In one embodiment of the present disclosure, referring to Figure 6 and Figure 12 , the demultiplexing circuit DM comprises a plurality of transistor unit groups MUS, each of which comprises two adjacent transistor units MU; the driving substrate BP is provided with a source signal second transfer line SL2 corresponding to each transistor unit group MUS in the first demultiplexing circuit sub-region DMA1, and the source signal second transfer line SL2 is electrically connected to the first electrode MS of each transistor in the corresponding transistor unit group MUS. In other words, the two transistor units MU in the same transistor unit group MUS can share the same source signal second transfer line SL2, thereby reducing the number of source signal second transfer lines SL2, source signal first transfer lines SL1, etc. This not only helps to improve the distribution density of the demultiplexing circuit DM in the demultiplexing circuit region DMA, but also helps to reduce the coupling capacitance between the source signal channel and the gate signal channel.

[0130] In one example, referring to Figure 12 , the transistor unit group MUS comprises a plurality of transistor pairs MP arranged in sequence along the column direction DV, each transistor pair MP comprising transistors belonging to two transistor units MU respectively, and the two transistors of the transistor pair MP share the first electrode. The two transistors of the transistor pair are arranged along the row direction DH.

[0131] In one example, referring to Figure 6 , each transistor unit group MUS is connected to two gate signal second transfer lines GL2, two driving voltage first transfer lines DL1 and one source signal second transfer line SL2; along the row direction DH, the driving voltage first transfer lines DL1, the gate signal second transfer lines GL2, the source signal second transfer lines SL2, the gate signal second transfer lines GL2 and the driving voltage first transfer lines DL1 are arranged in sequence, and these lines all extend linearly along the column direction DV.

[0132] In one example, referring to Figure 11 and Figure 12, the semiconductor substrate SBT has an active region BAA corresponding to each transistor pair in the first decomposition circuit sub-region DMA1, and a transistor pair MP is arranged in each active region BAA. In other words, the transistor pair shares the same active region. In this way, the arrangement of the transistor pair can be more compact. For example, in the row direction DH, the active region includes a first doped region A1, a second doped region B1, a third doped region A2, a fourth doped region B2, and a fifth doped region A3 arranged in sequence. The first doped region A1, the third doped region A2, and the fifth doped region A3 can be of the same type and be conductive, and the second doped region B1 and the fourth doped region B2 can be of the opposite type and maintain semiconductor properties. When the first doped region A1, the third doped region A2, and the fifth doped region A3 are all N-type doped, and the second doped region B1 and the fourth doped region B2 are P-type doped, the transistors of the transistor pair are N-type transistors, and the corresponding selection signal of the transistor unit MU is at a high level. When the first doped region A1, the third doped region A2, and the fifth doped region A3 are all P-type doped, and the second doped region B1 and the fourth doped region B2 are N-type doped, the transistors of the transistor pair are P-type transistors, and the corresponding selection signal of the transistor unit MU is at a low level.

[0133] The first doped region A1, the third doped region A2, and the fifth doped region A3 can be electrically connected to the driving voltage first transfer line DL1, the source signal second transfer line SL2, and the driving voltage first transfer line DL1 through the first metalized via V1, respectively. The second doped region B1 and the fourth doped region B2 can be arranged to overlap the gates of the two transistors, respectively, and overlap the two selection signal second transfer lines GL2, respectively.

[0134] In an example, referring to Figure 6 The driving substrate BP includes a data line group DLS corresponding to each transistor unit group MUS, and the data line group DLS includes two non-adjacent data lines DL. The pixel driving circuit PDC driven by the two data lines DL of the data line group DLS is used to drive sub-pixels of the same color. One data line DL of the data line group DLS is electrically connected to the second electrode MD of each transistor of one transistor unit MU of the corresponding transistor unit group MUS, and the other data line DL of the data line group DLS is electrically connected to the second electrode MD of each transistor of the other transistor unit MU of the corresponding transistor unit group MUS.

[0135] For example, in Figure 6In the example of FIG. 1, each demultiplexing circuit DM drives six data lines DL, and the six data lines DL are sequentially labeled as a first data line DL(1), a second data line DL(2), a third data line DL(3), a fourth data line DL(4), a fifth data line DL(5), and a sixth data line DL(6) in the order of arrangement of the display area AA in the row direction DH. Among them, the sub-pixels driven by the first data line DL(1) and the fourth data line DL(4) are red sub-pixels, the sub-pixels driven by the second data line DL(2) and the fifth data line DL(5) are green sub-pixels, and the sub-pixels driven by the third data line DL(3) and the sixth data line DL(6) are blue sub-pixels. The demultiplexing circuit DM includes three transistor unit groups MUS, and each transistor unit group MUS includes two transistor units MU. In the row direction DH, the six transistor units MU are sequentially labeled as a first transistor unit MU1, a second transistor unit MU2, a third transistor unit MU3, a fourth transistor unit MU4, a fifth transistor unit MU5, and a sixth transistor unit MU6. Among them, the first transistor unit MU1 and the second transistor unit MU2 are in the same transistor unit group MUS, the first data line DL(1) and the fourth data line DL(4) are in the same data line group DLS, the first transistor unit MU1 drives the first data line DL(1), and the second transistor unit MU2 drives the fourth data line DL(4). The third transistor unit MU3 and the fourth transistor unit MU4 are in the same transistor unit group MUS, the second data line DL(2) and the fifth data line DL(5) are in the same data line group DLS, the third transistor unit MU3 drives the second data line DL(2), and the fourth transistor unit MU4 drives the fifth data line DL(5). The fifth transistor unit MU5 and the sixth transistor unit MU6 are in the same transistor unit group MUS, the third data line DL(3) and the sixth data line DL(6) are in the same data line group DLS, the fifth transistor unit MU5 drives the third data line DL(3), and the sixth transistor unit MU6 drives the sixth data line DL(6).

[0136] In this embodiment, although the same transistor unit group MUS provides two different drive voltage channels, the sub-pixels PX driven by the two drive voltage channels are sub-pixels of the same color. Since the required drive voltages of the sub-pixels of the same color are consistent, the fluctuation range of the drive voltage is not large, the drive voltage fluctuation caused by the transistor to the common source region is small, and the crosstalk between the two drive voltage channels of the transistor unit group MUS is reduced.

[0137] In this embodiment, the selection signal lines MUXL driving the demultiplexing circuit DM are one-to-one corresponding to the data lines DL driven by the demultiplexing circuit DM, so as to ensure the correct driving algorithm. For example, the transistor unit MU controlled by the first selection signal line MUXL1 is used to drive the first data line DL(1), the transistor unit MU controlled by the second selection signal line MUXL2 is used to drive the second data line DL(2), the transistor unit MU controlled by the third selection signal line MUXL3 is used to drive the third data line DL(3), the transistor unit MU controlled by the fourth selection signal line MUXL4 is used to drive the fourth data line DL(4), the transistor unit MU controlled by the fifth selection signal line MUXL5 is used to drive the fifth data line DL(5), and the transistor unit MU controlled by the sixth selection signal line MUXL6 is used to drive the sixth data line DL(6). Therefore, it is necessary to determine the selection signal line MUXL controlling the transistor unit MU according to the data line DL driven by the transistor unit MU, and then change the connection order between the selection signal line MUXL and the transistor unit MU without changing the position of the selection signal line MUXL.

[0138] For example, in the example of Figure 6 the first selection signal line MUXL1 is electrically connected with the selection signal first switching line GL1 connected with the first transistor unit MU1, the fourth selection signal line MUXL4 is electrically connected with the selection signal first switching line GL1 connected with the second transistor unit MU2, the second selection signal line MUXL2 is electrically connected with the selection signal first switching line GL1 connected with the third transistor unit MU3, the fifth selection signal line MUXL5 is electrically connected with the selection signal first switching line GL1 connected with the fourth transistor unit MU4, the third selection signal line MUXL3 is electrically connected with the selection signal first switching line GL1 connected with the fifth transistor unit MU5, and the sixth selection signal line MUXL6 is electrically connected with the selection signal first switching line GL1 connected with the sixth transistor unit MU6.

[0139] In an example, referring to Figure 6 and Figure 22The driving substrate BP is provided with a transition area BA between the first decomposing circuit sub-area DMA1 and the display area AA, and the driving voltage channel is provided with a driving voltage third transition line DL3 in the transition area BA, which is used to electrically connect the driving voltage second transition line DL2 and the corresponding data line DL. In the row direction DH, the sequence of the driving voltage second transition line DL2 of each transistor unit MU of the multi-decomposing circuit DM can not be consistent with the sequence of the data line DL to which each transistor unit MU of the multi-decomposing circuit DM needs to be electrically connected, so at least part of the driving voltage third transition line DL3 needs to be bent in the row direction DH to ensure the electrical connection between the driving voltage second transition line DL2 and the data line DL in the same driving voltage channel.

[0140] It can be understood that part of the driving voltage third transition line DL3 can also not be bent in the row direction DH, and the electrical continuity of the driving voltage channel shall be ensured.

[0141] In an example, referring to Figure 6 and Figure 22 , the driving voltage first transition line DL1 and the driving voltage second transition line DL2 of the same driving voltage channel can be arranged linearly along the column direction DV. In this way, the arrangement sequence of the end of the driving voltage second transition line DL2 is consistent with the sequence of the driving voltage output by the multi-decomposing circuit DM.

[0142] In Figure 6 and Figure 22In the example, the third sub-transformer line DL3 of the driving voltage includes the first sub-transformer line DL31 corresponding to the first transistor unit MU1, the second sub-transformer line DL32 corresponding to the second transistor unit MU2, the third sub-transformer line DL33 corresponding to the third transistor unit MU3, the fourth sub-transformer line DL34 corresponding to the fourth transistor unit MU4, the fifth sub-transformer line DL35 corresponding to the fifth transistor unit MU5, and the sixth sub-transformer line DL36 corresponding to the sixth transistor unit MU6. Among them, the second driving voltage adapter DL2 corresponding to the first transistor unit MU1 is electrically connected to the first data line DL(1) through the first sub-adapter DL31; the second driving voltage adapter DL2 corresponding to the second transistor unit MU2 is electrically connected to the fourth data line DL(4) through the second sub-adapter DL32; the second driving voltage adapter DL2 corresponding to the third transistor unit MU3 is electrically connected to the second data line DL(2) through the third sub-adapter DL33; the second driving voltage adapter DL2 corresponding to the fourth transistor unit MU4 is electrically connected to the fifth data line DL(5) through the fourth sub-adapter DL34; the second driving voltage adapter DL2 corresponding to the fifth transistor unit MU5 is electrically connected to the third data line DL(3) through the fifth sub-adapter DL35; and the second driving voltage adapter DL2 corresponding to the sixth transistor unit MU6 is electrically connected to the sixth data line DL(6) through the sixth sub-adapter DL36.

[0143] As follows, Figure 6 Taking the example of the multi-channel decomposition circuit DM, the driving method of the multi-channel decomposition circuit DM provided in this disclosure will be described by way of example. Figure 7 This is a schematic diagram of the driving timing of the multiplexing circuit DM. It can be understood that... Figure 6 The example multiplexer circuit DM can also be driven using other timing sequences.

[0144] join Figure 7 Within a display frame (from one horizontal sync signal HSYNC to another), the source signal line SL is sequentially loaded with reset voltage Vofs, first drive voltage S1, second drive voltage S2, third drive voltage S3, fourth drive voltage S4, fifth drive voltage S5, and sixth drive voltage S6 during time intervals t0 to t6. At time t0, the first gating signal line MUXL1 to the sixth gating signal line MUXL6 are simultaneously loaded with gating signals (in... Figure 7In the example, the selection signal is a low-level signal, which makes the first transistor unit MU1 to the sixth transistor unit MU6 simultaneously conduct, so that the pixel driving circuit PDC on the six data lines DL driven by the demultiplexing circuit DM is synchronously reset. At time t1, the first selection signal line MUXL1 loads the selection signal, which makes the first transistor unit MU1 conduct, and the first driving voltage S1 on the source signal line SL is loaded to the data line DL driven by the first transistor unit MU1. At time t2, the second selection signal line MUXL2 loads the selection signal, which makes the second transistor unit MU2 conduct, and the second driving voltage S2 on the source signal line SL is loaded to the data line DL driven by the second transistor unit MU2. Similarly, at time t3, the third selection signal line MUXL3 loads the selection signal, the third transistor unit MU3 conducts, and the third driving voltage S3 on the source signal line SL is loaded to the data line DL driven by the third transistor unit MU3. At time t4, the fourth selection signal line MUXL4 loads the selection signal, the fourth transistor unit MU4 conducts, and the fourth driving voltage S4 on the source signal line SL is loaded to the data line DL driven by the fourth transistor unit MU4. At time t5, the fifth selection signal line MUXL5 loads the selection signal, the fifth transistor unit MU5 conducts, and the fifth driving voltage S5 on the source signal line SL is loaded to the data line DL driven by the fifth transistor unit MU5. At time t6, the sixth selection signal line MUXL6 loads the selection signal, the sixth transistor unit MU6 conducts, and the sixth driving voltage S6 on the source signal line SL is loaded to the data line DL driven by the sixth transistor unit MU6.

[0145] In an example, the driving substrate BP can be prepared by wafer process, for example, by semiconductor process of 0.04-0.4 microns, for example, by semiconductor process of 0.11 microns.

[0146] In an example, the width-length ratio of the channel region of the transistor can be 4:1-8:1, for example, 5:1.

[0147] In an example, the display panel PNL provided by the embodiments of the present disclosure can provide a refresh rate of 90 Hz or higher, for example, a refresh rate of 120 Hz, 144 Hz or 180 Hz, by reducing the influence of the demultiplexing circuit DM on the refresh rate.

[0148] For example, the display panel PNL provided by the embodiments of the present disclosure can provide a display capability of 120 Hz refresh rate at a resolution of 4K (for example, 3956 PPI or higher), and the picture is stable and smooth, which can reduce the dizziness in VR application and the screen door effect in AR application, greatly increase the sense of immersion and improve the user experience.

[0149] Figure 8 to Figure 22 For Figure 6 An example of a specific film layer arrangement of the demultiplexing circuit DM is shown. In Figure 8 to Figure 22 An example of the arrangement of the demultiplexing circuit DM of the driving substrate BP is shown. In Figure 8 to Figure 22 In the example, only one demultiplexing circuit DM and its related signal channels are shown.

[0150] Referring to Figure 8 to Figure 22 In the demultiplexing circuit region DMA, the driving substrate BP comprises at least a semiconductor substrate SBT, a gate insulating layer GI, a gate layer GT, a first insulating layer D1, a first metal layer M1, a second insulating layer D2, a second metal layer M2, a third insulating layer D3, a third metal layer M3, a fourth insulating layer D4 and a fourth metal layer M4, which are arranged in sequence.

[0151] Referring to Figure 8 to Figure 12 The semiconductor substrate SBT is doped to form active areas BAA and back gate doping areas BG1 corresponding to each transistor pair MP in the first demultiplexing circuit sub-region DMA1; each active area BAA is divided into a first doping area A1, a second doping area B1, a third doping area A2, a fourth doping area B2 and a fifth doping area A3, and each doping area obtains the expected doping characteristics through subsequent further doping (e.g. ion implantation after forming the gate layer GT). The gate layer GT forms the gate MG of each transistor. The gates MG of each transistor in the same transistor unit MU are arranged in common, i.e. the gates MG of each transistor in the same transistor unit MU are directly connected. The gate MG of the transistor can be arranged to overlap the second doping area B1 or the fourth doping area B2, so as to protect the second doping area B1 and the fourth doping area B2 during ion implantation after forming the gate layer GT.

[0152] The doped region of the semiconductor substrate SBT and the gate insulating layer GI and the gate layer GT together form a transistor layer, so as to arrange each transistor required for the transistor unit MU in the demultiplexing circuit region DMA.

[0153] Referring to Figure 13 to Figure 22 The first metal layer M1 to the fourth metal layer M4 are used to arrange each trace to load signals to the demultiplexing circuit DM and to output signals from the demultiplexing circuit DM. In the example, the traces are mainly distributed in the first metal layer M1 and the third metal layer M3, and the second metal layer M2 and the fourth metal layer M4 are mainly used for signal switching. In the example, the data line DL is arranged in the fourth metal layer M4.

[0154] In this example, the first metal layer M1 is provided with a back gate trace BG2 substantially coinciding with the back gate doped region BG1, and the back gate doped region BG1 is electrically connected with the back gate trace BG2 through the first metallization via V1 in advance to form a back gate structure BG.

[0155] In this example, the source signal channel includes source signal line SL, source signal first transfer line SL1, source signal fourth transfer line SL4, source signal third transfer line SL3, source signal fifth transfer line SL5, source signal second transfer line SL2 connected in sequence, and finally connected to the first electrode MS of the transistor. The source signal line SL is arranged on the side of the decomposition circuit region DMA away from the display region AA, and is arranged on the first metal layer M1; the source signal first transfer line SL1 has a side branch portion near the end of the decomposition circuit region DMA. The source signal first transfer line SL1 is arranged on the first metal layer M1 and located in the second decomposition circuit sub-region DMA2, and one end close to the source signal line SL is connected with the side branch portion of the source signal line SL. The source signal line SL extends to the vicinity of the back gate structure BG and is transferred to the source signal fourth transfer line SL4 located on the second metal layer M2 through the second metallization via V2; the source signal fourth transfer line SL4 is transferred to the source signal third transfer line SL3 located on the third metal layer M3 through the third metallization via V3. The source signal third transfer line SL3 crosses the back gate structure BG, i.e. is arranged across the first decomposition circuit sub-region DMA1 and the second decomposition circuit sub-region DMA2. The source signal third transfer line SL3 is transferred to the source signal fifth transfer line SL5 located on the second metal layer M2 through the third metallization via V3 at the end of the first decomposition circuit sub-region DMA1, and the source signal fifth transfer line SL5 is transferred to the source signal second transfer line SL2 located on the first metal layer M1 in the first decomposition circuit sub-region DMA1 through the second metallization via V2. The source signal second transfer line SL2 is electrically connected with the first electrode MS of the transistor through the first metallization via V1.

[0156] In this example, the gate signal channel includes gate signal line MUXL, gate signal fourth transfer line GL4, gate signal first transfer line GL1, gate signal fifth transfer line GL5, gate signal third transfer line GL3, gate signal sixth transfer line GL6, gate signal second transfer line GL2 connected in sequence, and finally connected to the gate MG of the transistor. Among them, the gate signal line MUXL is located in the second decomposition circuit sub-region DMA2 and extends along the row direction DH; the gate signal line MUXL is arranged on the third metal layer M3. The gate signal line MUXL is electrically connected to the gate signal fourth transfer line GL4 on the second metal layer M2 through the third metalization via V3, and the gate signal fourth transfer line GL4 is electrically connected to the gate signal first transfer line GL1 on the first metal layer M1 through the second metalization via V2. The gate signal first transfer line GL1 extends along the column direction DV to the vicinity of the back gate structure BG, and the end of the gate signal first transfer line GL1 close to the back gate structure BG is electrically connected to the gate signal fifth transfer line GL5 on the second metal layer M2 through the second metalization via V2, and the gate signal fifth transfer line GL5 is electrically connected to the gate signal third transfer line GL3 on the third metal layer M3 through the third metalization via V3. The gate signal third transfer line GL3 crosses the back gate structure BG, that is, one end is located in the first decomposition circuit sub-region DMA1 and the other end is located in the second decomposition circuit sub-region DMA2. The end of the gate signal third transfer line GL3 located in the first decomposition circuit sub-region DMA1 is electrically connected to the gate signal sixth transfer line GL6 on the second metal layer M2 through the third metalization via V3, and the gate signal sixth transfer line GL6 is electrically connected to the gate signal second transfer line GL2 on the first metal layer M1 through the second metalization via V2, and the gate signal second transfer line GL2 is electrically connected to the gate MG of the transistor through the first metalization via V1.

[0157] In this example, the first transistor unit MU1 is used to drive the first data line DL(1), thus making the first transistor unit MU1 electrically connected to the gate line GL1 and the first gate line MUXL1. The second transistor unit MU2 is used to drive the fourth data line DL(4), thus making the second transistor unit MU2 electrically connected to the gate line GL1 and the fourth gate line MUXL4. The third transistor unit MU3 is used to drive the second data line DL(2), thus making the third transistor unit MU3 electrically connected to the gate line GL1 and the second gate line MUXL2. The fourth transistor unit MU4 is used to drive the fifth data line DL(5), thus making the fourth transistor unit MU4 electrically connected to the gate line GL1 and the fifth gate line MUXL5. The fifth transistor unit MU5 is used to drive the third data line DL(3), thus making the fifth transistor unit MU5 electrically connected to the gate line GL1 and the fifth gate line MUXL5. The sixth transistor unit MU6 is used to drive the sixth data line DL(6), thus making the sixth transistor unit MU6 electrically connected to the gate line GL1 and the sixth gate line MUXL6. In this way, the source driving circuit can output signals according to the arrangement order of the data lines DL in the display area AA without changing the driving algorithm; the demultiplexing circuit DM loads the source signals to the corresponding data lines DL through hardware conversion.

[0158] In this example, the driving voltage channel includes the second electrode MD of the transistor, the driving voltage first transfer line DL1, the first transfer pad DLP1, the second transfer pad DLP2, the driving voltage second transfer line DL2, and the data line DL connected in sequence, wherein the driving voltage third transfer line DL3 and the necessary structures required to make the driving voltage third transfer line DL3 electrically connected to the driving voltage second transfer line DL2 and the data line DL are arranged between the driving voltage second transfer line DL2 and the data line DL.

[0159] The driving voltage first transfer line DL1 is arranged on the first metal layer M1 and located in the first decomposition circuit sub-region DMA1, and is electrically connected with the second electrode MD of the transistor through the first metallized via V1. The driving voltage first transfer line DL1 extends to the back gate structure BG (the end of the side close to the display area AA), and is transferred to the first transfer pad DLP1 on the second metal layer M2 through the second metallized via V2; the first transfer pad DLP1 is transferred to the second transfer pad DLP2 on the third metal layer M3 through the third metallized via V3, and the second transfer pad DLP2 is transferred to the driving voltage second transfer line DL2 on the fourth metal layer M4 through the fourth metallized via V4. The driving voltage second transfer line DL2 crosses the back gate structure BG, that is, one end of the driving voltage second transfer line DL2 is located in the first decomposition circuit sub-region DMA1, and the other end extends to the transfer area BA. The data line DL is arranged on the fourth metal layer M4.

[0160] The driving voltage channel connected with the first transistor unit MU1 includes the first sub-transfer line DL31 on the fourth metal layer M4, and the driving voltage second transfer line DL2, the first sub-transfer line DL31 and the first data line DL(1) are sequentially and directly connected.

[0161] The driving voltage channel connected with the second transistor unit MU2 further includes the third transfer pad DLP3, the fourth transfer pad DLP4, the second sub-transfer line DL32, the fifth transfer pad DLP5 and the sixth transfer pad DLP6 which are sequentially connected from the driving voltage second transfer line DL2. The driving voltage second transfer line DL2 is connected to the third transfer pad DLP3 on the third metal layer M3 through the fourth metallized via V4 at the end of the transfer area BA, the third transfer pad DLP3 is connected to the fourth transfer pad DLP4 on the second metal layer M2 through the third metallized via V3, the fourth transfer pad DLP4 is connected to the second sub-transfer line DL32 on the first metal layer M1 through the second metallized via V2, the second sub-transfer line DL32 extends to the position corresponding to the fourth data line DL(4) in the row direction DH, and is connected to the fifth transfer pad DLP5 on the second metal layer M2 through the second metallized via V2, the fifth transfer pad DLP5 is transferred to the sixth transfer pad DLP6 on the third metal layer M3 through the third metallized via V3, and the sixth transfer pad DLP6 is transferred to the fourth data line DL(4) through the fourth metallized via V4.

[0162] The driving voltage channel connected with the third transistor unit MU3 further includes the third sub-transfer line DL33 on the fourth metal layer M4, and the driving voltage second transfer line DL2, the third sub-transfer line DL33 and the second data line DL(2) are sequentially and directly connected.

[0163] The driving voltage channel connected with the fourth transistor unit MU4 further comprises a fourth sub-connection line DL34 located in the fourth metal layer M4, and the driving voltage second connection line DL2, the fourth sub-connection line DL34 and the fifth data line DL(5) are sequentially and directly connected.

[0164] The driving voltage channel connected with the fifth transistor unit MU5 further comprises a seventh connection pad DLP7, an eighth connection pad DLP8, a fifth sub-connection line DL35, a ninth connection pad DLP9 and a tenth connection pad DLP10 sequentially connected from the driving voltage second connection line DL2. The driving voltage second connection line DL2 is connected to the seventh connection pad DLP7 located in the third metal layer M3 through the fourth metallization via V4 at the end of the connection area BA, the seventh connection pad DLP7 is connected to the eighth connection pad DLP8 located in the second metal layer M2 through the third metallization via V3, the eighth connection pad DLP8 is connected to the fifth sub-connection line DL35 located in the first metal layer M1 through the second metallization via V2, the fifth sub-connection line DL35 is connected to the ninth connection pad DLP9 located in the second metal layer M2 through the second metallization via V2 after being connected to the end of the third data line DL(3), the ninth connection pad DLP9 is connected to the tenth connection pad DLP10 located in the third metal layer M3 through the third metallization via V3, and the tenth connection pad DLP10 is connected to the third data line DL(3) located in the fourth metal layer M4 through the fourth metallization via V4.

[0165] The driving voltage channel connected with the sixth transistor unit MU6 further comprises a sixth sub-connection line DL36 located in the fourth metal layer M4, and the driving voltage second connection line DL2, the sixth sub-connection line DL36 and the sixth data line DL(6) are sequentially and directly connected.

[0166] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure. The present application is intended to cover any and all variations of the present disclosure comprising adaptations, modifications, and equivalents of the concepts disclosed herein, following in general the principles of the present disclosure and including such variants in the present disclosure that occur to those skilled in the art in the practice of the present disclosure. The specification and examples are intended to be exemplary only and the true scope and spirit of the present disclosure should be indicated by the appended claims.

Claims

1. A driving substrate, comprising a display area and a decomposition circuit area; the display area is provided with a data line for loading a data voltage to a pixel driving circuit; the decomposition circuit area comprises a first decomposition circuit sub-area and a second decomposition circuit sub-area located away from the display area on a side of the first decomposition circuit sub-area; in the first decomposition circuit sub-area, the driving substrate is provided with a plurality of multi-decomposition circuits arranged along a row direction, each multi-decomposition circuit comprising a plurality of transistor units; the first poles of the transistors in the same multi-decomposition circuit are electrically connected to the same source signal line, and the second poles of the transistors in the same transistor unit are electrically connected to the same data line; the second decomposition circuit sub-area has a plurality of gate signal lines corresponding to the plurality of transistor units in the multi-decomposition circuit and extending along the row direction, and the gates of the transistors in the transistor unit are electrically connected to the corresponding gate signal line; the gates of the transistors in the same transistor unit are connected to the same gate signal line; the multi-decomposition circuit comprises a plurality of transistor unit groups, each transistor unit group comprising two adjacent transistor units; the driving substrate is provided with a source signal second transfer line corresponding to the transistor unit group in the first decomposition circuit sub-area, and the source signal second transfer line is electrically connected to the first poles of the transistors in the corresponding transistor unit group.

2. The drive substrate according to claim 1, wherein the multi-decomposition circuit has a first size along a column direction; the distance between the edge of the gate signal line closest to the display area and the edge of the gate signal line farthest from the display area is a second size; the second size is greater than the first size.

3. The drive substrate according to claim 2, wherein the width of the gate signal line is greater than half the width of the channel region of the transistor in the multi-decomposition circuit.

4. The drive substrate according to claim 1, wherein the driving substrate comprises a transistor layer and a plurality of metal layers arranged in sequence; the transistor layer and the first metal layer are electrically connected through a metalized via, and two adjacent metal layers are electrically connected through a metalized via; in the second decomposition circuit sub-area, the driving substrate is provided with a gate signal first transfer line corresponding to each transistor unit, the gate signal first transfer line extending along the column direction and being electrically connected to the gates of the transistors in the corresponding transistor unit; wherein, the metal layer in which the gate signal first transfer line is located and the metal layer in which the gate signal line is located have at least one metal layer.

5. The drive substrate according to claim 4, wherein the gate signal first transfer line and each gate signal line are arranged in overlap.

6. The drive substrate according to claim 4, wherein the gate signal first transfer line and the gate signal line to which it is electrically connected have a gate signal fourth transfer line, the gate signal first transfer line being electrically connected to the corresponding gate signal line through the gate signal fourth transfer line; when the metal layer in which the gate signal fourth transfer line is located and the metal layer in which the gate signal first transfer line is located are arranged adjacently, the gate signal first transfer line and the gate signal fourth transfer line are electrically connected to each other through at least two columns of metalized vias, each column of metalized vias comprising at least three metalized vias arranged in sequence along the column direction.

7. The drive substrate according to claim 4, wherein The first metal layer has a gate signal second transfer line corresponding to each transistor unit in the first sub-decomposition circuit area, and the gate signal second transfer line is electrically connected to the gate of each transistor of the corresponding transistor unit through a metalized via hole; The gate signal second transfer line has a via hole part for connecting with the metalized via hole and a wire part connected with the via hole part; the width of the wire part of the gate signal second transfer line is smaller than the width of the gate signal first transfer line.

8. The drive substrate according to claim 1, wherein The driving substrate comprises a transistor layer and a plurality of metal layers which are sequentially stacked; the transistor layer and the first metal layer are electrically connected through a metalized via hole, and two adjacent metal layers are electrically connected through a metalized via hole; In the second sub-decomposition circuit area, the driving substrate is provided with a source signal first transfer line extending along the column direction, one end of the source signal first transfer line is electrically connected to the source signal line, and the other end is electrically connected to the first electrode of each transistor of at least one transistor unit; The metal layer between which the source signal first transfer line is located and the metal layer in which the gate signal line is located has at least one metal layer.

9. The drive substrate according to claim 1, wherein The transistor unit comprises a plurality of transistors connected in parallel, each transistor is arranged along the column direction in sequence, and the length direction of the channel region of each transistor is the row direction; The driving substrate is provided with a driving voltage first transfer line corresponding to each transistor unit and extending along the column direction in the first sub-decomposition circuit area, the driving voltage first transfer line is electrically connected to the second electrode of each transistor of the transistor unit and is electrically connected to the data line.

10. The drive substrate according to claim 1, wherein The multi-decomposition circuit comprises a plurality of transistor unit groups, each transistor unit group comprises two adjacent transistor units; The driving substrate is provided with a source signal second transfer line corresponding to each transistor unit group in the first sub-decomposition circuit area, and the source signal second transfer line is electrically connected to the first electrode of each transistor in the corresponding transistor unit group.

11. The drive substrate according to any one of claims 1 to 10, wherein The first sub-decomposition circuit area has a ring-shaped back gate structure, and each multi-decomposition circuit is located in the space surrounded by the back gate structure; The gate signal line is located on the side of the back gate structure away from the display area.

12. The drive substrate according to claim 11, wherein, The driving substrate comprises a semiconductor substrate and a plurality of metal layers which are sequentially stacked; The back gate structure comprises a ring-shaped back gate doped area on the semiconductor substrate and a back gate wire on the first metal layer, and the back gate wire is electrically connected to the back gate doped area through a metalized via hole; The driving substrate is further provided with a metal structure across the back gate structure, and the metal layer in which the metal structure across the back gate structure is located is separated from the first metal layer by at least one metal layer.

13. A display panel comprising the driving substrate according to any one of claims 1-12.

14. A display device comprising the display panel according to claim 13.

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