Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes: a display panel including a plurality of pixels; a gate driver that outputs a gate signal to the display panel; a data driver that generates a data voltage applied to the display panel; and a multiplexer block that outputs the data voltage to the display panel. The multiplexer block includes: an output control transistor including: a control electrode receiving an output control signal; a first electrode connected to the first data line; and a second electrode connected to the second data line.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices and electronic devices. More specifically, embodiments of the present invention relate to display devices and electronic devices in which integration is improved and power consumption is reduced. Background Technology

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a drive controller that controls the gate driver and the data driver.

[0003] Generally, a display device may include a multiplexer for selectively applying data voltages to data lines. Summary of the Invention

[0004] Embodiments of the present invention provide a display device in which integration is improved and power consumption is reduced.

[0005] Embodiments of the present invention also provide electronic devices in which integration is improved and power consumption is reduced.

[0006] In embodiments of this disclosure, the display device includes: a display panel including a plurality of pixels; a gate driver that outputs a gate signal to the display panel; a data driver that generates a data voltage applied to the display panel; and a multiplexer block that outputs the data voltage to the display panel, the multiplexer block including: an output control transistor including: a control electrode for receiving an output control signal; a first electrode connected to a first data line; and a second electrode connected to a second data line.

[0007] In this embodiment, the data voltage may include a first data voltage and a second data voltage. The first data line may be connected to a first output amplifier that outputs the data voltage. The second data line may be connected to the first data line via a multiplexer block.

[0008] In one embodiment, when the output control signal has an active level, the data driver can output a second data voltage.

[0009] In one embodiment, the data driver can output a first data voltage when the output control signal has an inactive level.

[0010] In one embodiment, when the output control signal has an inactive level, the first data voltage can be applied to the first data line.

[0011] In an embodiment, the length of the active period of the output control signal with an active level can be longer than the length of the inactive period of the output control signal with an inactive level.

[0012] In one embodiment, the data driver may include a first output amplifier and a second output amplifier that output data voltage. The display panel may also include a first data line, a second data line, a third data line, and a fourth data line arranged sequentially. The multiplexer block may further include a first output control transistor connected to the first and second data lines, and a second output control transistor connected to the third and fourth data lines. The first output amplifier may be connected to the first data line. The second output amplifier may be connected to the third data line.

[0013] In one embodiment, the data driver may include a first output amplifier and a second output amplifier that output data voltage. The display panel may also include a first data line, a second data line, a third data line, and a fourth data line arranged sequentially. The multiplexer block may further include a first output control transistor connected to the first and second data lines, and a second output control transistor connected to the third and fourth data lines. The first output amplifier may be connected to the second data line. The second output amplifier may be connected to the fourth data line.

[0014] In this embodiment, the data voltage may include a first data voltage and a second data voltage. When the output control signal is at an active level, the data driver may output the first data voltage.

[0015] In one embodiment, the data driver can output a second data voltage when the output control signal is at an inactive level.

[0016] In one embodiment, the data driver may be spaced apart from the display panel in a first positioning direction. The multiplexer block may be spaced apart from the display panel in a second positioning direction different from the first positioning direction.

[0017] In this embodiment, the display panel may further include a foldable area and a non-foldable area adjacent to the foldable area. A multiplexer block may be located in the foldable area.

[0018] In an embodiment, the non-folding region may include a first non-folding region and a second non-folding region. The first non-folding region may include a first data line group, and the second non-folding region includes a second data line group. The first data line group may be disposed next to (adjacent to) the data driver. When the output control signal has an active level, a data voltage may be applied to the first data line group and the second data line group.

[0019] In one embodiment, when the output control signal has an inactive level, the operation of applying data voltage to the second data line group is stopped.

[0020] In this embodiment, the output control signal has an inactive level, and the second non-folded region can stop transmitting.

[0021] In this embodiment, the display panel may further include a first data line, a second data line, a third data line, and a fourth data line. The multiplexer block may further include a first output control transistor connected to the first and second data lines, and a second output control transistor connected to the third and fourth data lines. A first-color pixel having a first color and a second-color pixel having a second color different from the first color may be connected to the first data line. A third-color pixel having a third color different from the first and second colors may be connected to the second data line. The first-color pixel and the second-color pixel may be connected to the third data line. The third-color pixel may be connected to the fourth data line.

[0022] In one embodiment, the data driver may include a first output amplifier and a second output amplifier that output data voltages. The first output amplifier may be connected to a first data line and the second output amplifier may be connected to a third data line. When the output control signal is at an inactive level, the first output amplifier may output a first color data voltage, and the second output amplifier may output a second color data voltage. When the output control signal is at an active level, both the first and second output amplifiers may output a third color data voltage.

[0023] In embodiments of this disclosure, the electronic device includes: a display panel including a plurality of pixels; a gate driver that outputs a gate signal to the display panel; a data driver that generates a data voltage applied to the display panel; a multiplexer block that outputs the data voltage to the display panel; and a processor that controls the gate driver, the data driver, and the multiplexer block. The multiplexer block includes: a first output control transistor including: a control electrode for receiving a second output signal; a first electrode connected to a first output line; and a second electrode connected to a first data line; and a second output control transistor including: a control electrode for receiving a first output control signal; a first electrode connected to the first output line; and a second electrode connected to a second data line. The data driver may be spaced apart from the display panel in a first positioning direction. The multiplexer block may be spaced apart from the display panel in a second positioning direction different from the first positioning direction.

[0024] In this embodiment, the data voltage may include a first data voltage and a second data voltage. The period for applying the data voltage may include a first period and a second period. During the first period, the data voltage may have the second data voltage, the first output control signal may have an active level, the second output control signal may have an inactive level, and the second data voltage may be applied to the second data line.

[0025] In an embodiment, during the second cycle, the data voltage may have a first data voltage, the first output control signal may have an inactive level, the second output control signal may have an active level, and the first data voltage may be applied to the first data line.

[0026] As described above, the data driver can be spaced apart from the display panel in the first positioning direction, and the multiplexer block can be spaced apart from the display panel in the second positioning direction, thereby reducing the bezel of the display device. For example, the bezel in the bottom region of the display device can be reduced. Attached Figure Description

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating an embodiment of a display device according to a concept conceived in the present invention.

[0029] Figure 2 It is shown Figure 1 A block diagram of an embodiment showing the position of the display device.

[0030] Figure 3 It is shown Figure 2 A block diagram of an embodiment of the output control transistor included in the multiplexer block.

[0031] Figure 4 It is shown Figure 3 Circuit diagram of an embodiment of the display panel, data driver, and multiplexer block.

[0032] Figure 5 It is shown in Figure 1 The timing diagram of the input signals during the effective cycle of the display device.

[0033] Figure 6 It is shown Figure 5 Timing diagram of an embodiment of the input signals in the activation and non-activation cycles included in the scan cycle.

[0034] Figure 7 It is shown Figure 5 Timing diagram of an embodiment of the input signals in the activation and non-activation cycles included in the scan cycle.

[0035] Figure 8 It is shown Figure 3 Circuit diagram of an embodiment of the display panel, data driver, and multiplexer block.

[0036] Figure 9 It is shown in Figure 1 The timing diagram of the input signals during the effective cycle of the display device.

[0037] Figure 10 It is shown Figure 3 Circuit diagram of an embodiment of the display panel, data driver, and multiplexer block.

[0038] Figure 11 It is shown in Figure 1 The timing diagram of the input signals during the effective cycle of the display device.

[0039] Figure 12 This is a perspective view showing an embodiment of the display device.

[0040] Figure 13 It shows along Figure 12 A side view of an embodiment of the display device in its folded state, captured by line I-I'.

[0041] Figure 14 It shows along Figure 12 A side view of an embodiment showing the location of the data driver and multiplexer block included in the display device, as captured by line I-I'.

[0042] Figure 15 It is shown Figure 1 A circuit diagram of an embodiment showing the location of the display panel, data driver, and multiplexer block.

[0043] Figure 16 It is shown Figure 1 A circuit diagram of an embodiment showing the location of the display panel, data driver, and multiplexer block.

[0044] Figure 17 It is shown Figure 1 A block diagram of an embodiment showing the position of the display device.

[0045] Figure 18 It is shown Figure 17 Circuit diagram of an embodiment of the display panel, data driver, and multiplexer block.

[0046] Figure 19 It is shown Figure 1 The timing diagram of the input signals during the effective cycle of the display device.

[0047] Figure 20 It is shown Figure 19Timing diagram of an embodiment of the input signals in the activation and non-activation cycles included in the scan cycle.

[0048] Figure 21 It is shown Figure 1 A circuit diagram of an embodiment showing the location of the display panel, data driver, and multiplexer block.

[0049] Figure 22 This is a block diagram illustrating an embodiment of an electronic device conceived according to the present invention. Detailed Implementation

[0050] The concept of the present invention will be described in detail below with reference to the accompanying drawings.

[0051] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or an intermediary element may exist between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, no intermediary element exists.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as “second element,” “second component,” “second region,” “second layer,” or “second part.”

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms (including “at least one”). “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises and / or comprising” or “includes and / or including” indicate the presence of the stated features, regions, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, regions, integrals, steps, operations, elements, components, and / or groups thereof.

[0054] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device in one of the drawings is flipped, an element described as being “below” the other elements will subsequently be oriented to be “above” the other elements. Thus, depending on the specific orientation of the drawing, the exemplary term “below” can cover both “below” and “above” orientations. Similarly, if the device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will subsequently be oriented to be “above” the other elements. Thus, the exemplary terms “below” or “under” can cover both “above” and “below” orientations.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and will not be interpreted in an idealized or overly formalized sense.

[0056] Figure 1 This is a block diagram illustrating an embodiment of a display device 1 according to the present invention.

[0057] Reference Figure 1 The display device 1 may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. In an embodiment, the display device 1 may also include a multiplexer block.

[0058] The display panel 100 may have a display area in which an image is displayed and a peripheral area next to (adjacent to) the display area.

[0059] The display panel 100 may include multiple gate lines GL, multiple data lines DL, and multiple pixels PX electrically connected to the gate lines GL and data lines DL. The gate lines GL may extend in a first direction DR1, and the data lines DL may extend in a second direction DR2 intersecting the first direction DR1.

[0060] The drive controller 200 can receive input image data IMG, input control signal CONT, and multiplexer block control signal MCS from an external device. In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal. The drive controller 200 can control the multiplexer block based on the multiplexer block control signal MCS.

[0061] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0062] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0063] The drive controller 200 can generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0064] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0065] The drive controller 200 can generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0066] The gate driver 300 can generate a gate signal to drive the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0067] In one embodiment, the gate driver 300 may be disposed in the peripheral region. Alternatively, the gate driver 300 may be integrated into the peripheral region.

[0068] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0069] In an embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0070] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage VDATA of analog type. The data driver 500 outputs the data voltage VDATA to the data line DL. In an embodiment, the data driver 500 can also output a pulsed data voltage. In an embodiment, the data driver 500 can generate a data current based on the data signal DATA.

[0071] In one embodiment, the data driver 500 may be located in the peripheral area. Alternatively, the data driver 500 may be integrated into the peripheral area.

[0072] Figure 2 It is shown Figure 1 A block diagram of an embodiment showing the position of the display device 1.

[0073] Reference Figure 1 and Figure 2 The display device 1 may include a display panel 100A, a data driver 500A, and a multiplexer block 600A. The display panel 100A may include a first data line DLA[1], a second data line DLA[2], a third data line DLA[3], a fourth data line DLA[4], a fifth data line DLA[5], a sixth data line DLA[6] to a second data line DLA[2P-1] and a second data line DLA[2P]. In an embodiment, for example, the data driver 500A may be connected to the multiplexer block 600A via odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1]. When the data driver 500A is connected to the multiplexer block 600A via odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1], the even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P] may not be connected. Figure 4The output amplifiers OAMP1 and OAMP2. In an embodiment, for example, data driver 500A can be connected to multiplexer block 600A via even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P]. When data driver 500A is connected to multiplexer block 600A via even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P], odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1] may not be connected. Figure 4 The output amplifiers are OAMP1 and OAMP2.

[0074] In the illustrated embodiment, the data driver 500A may be spaced apart from the display panel 100A in a first positioning direction D1. Furthermore, the multiplexer block 600A may be spaced apart from the display panel 100A in a second positioning direction D2. In this embodiment, the first positioning direction D1 and the second positioning direction D2 may be opposite to each other in the second direction D1, but are not limited thereto, and may be opposite to each other in another direction. In this embodiment, for example, the data driver 500A may be disposed in the bottom region of the display panel 100A. In this embodiment, for example, the multiplexer block 600A may be disposed in the upper region of the display panel 100A. The data driver 500A may be spaced apart from the display panel 100A in the first positioning direction D1, and the multiplexer block 600A may be spaced apart from the display panel 100A in the second positioning direction D2, thereby reducing the bezel of the display device 1. In this embodiment, for example, the bezel of the bottom region of the display device 1 may be reduced.

[0075] Figure 3 It is shown Figure 2 A block diagram of an embodiment of the output control transistor MTR included in the multiplexer block 600A.

[0076] Reference Figures 1 to 3 The multiplexer block 600A may include an output control transistor MTR. The multiplexer block 600A may include multiple output control transistors MTR. In an embodiment, for example, when the number of data lines DL included in the display panel 100A is 2P (where P is a positive integer), the multiplexer block 600A may include P output control transistors MTR. However, the inventive concept is not limited to the number of output control transistors MTR.

[0077] The output control transistor MTR may include a control electrode that receives the output control signal CLA, a first electrode connected to the odd-numbered data lines, and a second electrode connected to the even-numbered data lines. The output control transistor MTR may connect the odd-numbered and even-numbered data lines in response to the output control signal CLA.

[0078] In an embodiment, for example, the multiplexer block 600A may include a first output control transistor to a Pth output control transistor.

[0079] The first output control transistor may include a control electrode for receiving the output control signal CLA, a first electrode connected to the first data line DLA[1], and a second electrode connected to the second data line DLA[2]. The second output control transistor may include a control electrode for receiving the output control signal CLA, a first electrode connected to the third data line DLA[3], and a second electrode connected to the fourth data line DLA[4]. The third output control transistor may include a control electrode for receiving the output control signal CLA, a first electrode connected to the fifth data line DLA[5], and a second electrode connected to the sixth data line DLA[6]. The P-th output control transistor may include a control electrode for receiving the output control signal CLA, a first electrode connected to the 2P-1 data line DLA[2P-1], and a second electrode connected to the 2P data line DLA[2P].

[0080] Figure 4 It is shown Figure 3 Circuit diagram of an embodiment of the display panel 100A, data driver 500A, and multiplexer block 600A. Figure 5 It is shown in Figure 1 The timing diagram of the input signals during the effective period of the display device 1. Figure 6 It is shown Figure 5 Timing diagram of an embodiment of the input signals in the activation and non-activation cycles included in the scan cycle.

[0081] Reference Figures 1 to 6 The data driver 500A may include output amplifiers OAMP1 and OAMP2. Output amplifiers OAMP1 and OAMP2 can output a data voltage VDATA. The data voltage VDATA may include odd-numbered data voltages OVDATA and even-numbered data voltages EVDATA. In an embodiment, for example, the odd-numbered data voltage OVDATA may be referred to as the first data voltage. In an embodiment, for example, the even-numbered data voltage EVDATA may be referred to as the second data voltage.

[0082] The first data line DLA[1] can be connected to the first pixel column. The second data line DLA[2] can be connected to the second pixel column. The third data line DLA[3] can be connected to the third pixel column. The fourth data line DLA[4] can be connected to the fourth pixel column.

[0083] In the illustrated embodiment, during the active period, a data voltage VDATA can be applied to the pixel circuitry of pixel PX. In this embodiment, for example, the active period may include a first scan period SP1A, a second scan period SP2A, a third scan period SP3A, and a fourth scan period SP4A. Each of the first scan period SP1A, the second scan period SP2A, the third scan period SP3A, and the fourth scan period SP4A may include an active period and an inactive period. During the active period, the output control signal CLA may have an active level. During the inactive period, the output control signal CLA may have an inactive level.

[0084] In an embodiment, for example, in a first scan cycle SP1A, a data voltage VDATA can be applied to a first pixel row. In a second scan cycle SP2A, the data voltage VDATA can be applied to a second pixel row. In a third scan cycle SP3A, the data voltage VDATA can be applied to a third pixel row. In a fourth scan cycle SP4A, the data voltage VDATA can be applied to a fourth pixel row.

[0085] In the illustrated embodiment, the first output amplifier OAMP1 can be connected to the first data line DLA[1]. The second output amplifier OAMP2 can be connected to the third data line DLA[3]. In the embodiment, for example, output amplifiers OAMP1 and OAMP2 can be connected to odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1]. Output amplifiers OAMP1 and OAMP2 can output odd-numbered data voltages OVDATA and even-numbered data voltages EVDATA. In the embodiment, for example, the voltage output from the first output amplifier OAMP1 can be called the first output amplification voltage OAMP1V. In the embodiment, for example, the voltage output from the second output amplifier OAMP2 can be called the second output amplification voltage OAMP2V.

[0086] In the illustrated embodiment, the first cycle TP1A can be the active cycle. During the first cycle TP1A, the data voltage VDATA can have an even-numbered data voltage EVDATA. During the first cycle TP1A, output amplifiers OAMP1 and OAMP2 can output even-numbered data voltages EVDATA, and the output control signal CLA can have an active level.

[0087] In the first cycle TP1A, the output control signal CLA can have an active level, enabling the output control transistor MTR to conduct. The first output control transistor can conduct, allowing even-numbered data voltage EVDATA to be applied to the first data line DLA[1] and the second data line DLA[2]. The second output control transistor can conduct, allowing even-numbered data voltage EVDATA to be applied to the third data line DLA[3] and the fourth data line DLA[4]. In an embodiment, for example, even-numbered data voltage EVDATA can be applied to odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1] and even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P]. In an embodiment, for example, even-numbered data voltage EVDATA can be applied to both odd-numbered and even-numbered pixel rows.

[0088] In the illustrated embodiment, the second period TP2A can be an inactive period. During the second period TP2A, the data voltage VDATA can have an odd-numbered data voltage OVDATA. During the second period TP2A, output amplifiers OAMP1 and OAMP2 can output an odd-numbered data voltage OVDATA, and the output control signal CLA can have an inactive level.

[0089] In the second cycle TP2A, the output control signal CLA can have an inactive level, allowing the output control transistor MTR to be turned off. In the second cycle TP2A, the odd-numbered data voltage OVDATA can be applied to the first data line DLA[1]. The first output control transistor can be turned off, allowing the first data line DLA[1] and the second data line DLA[2] to be disconnected. Since the first data line DLA[1] and the second data line DLA[2] are not connected, the odd-numbered data voltage OVDATA can not be applied to the second data line DLA[2]. Therefore, the second pixel column can maintain the even-numbered data voltage EVDATA. In addition, the odd-numbered data voltage OVDATA can be applied to the first pixel column. In the second cycle TP2A, the odd-numbered data voltage OVDATA can be applied to the third data line DLA[3]. The second output control transistor can be turned off, allowing the third data line DLA[3] and the fourth data line DLA[4] to be disconnected. The third data line DLA[3] and the fourth data line DLA[4] may not be connected, and the odd-numbered data voltage OVDATA may not be applied to the fourth data line DLA[4]. Therefore, the fourth pixel column may maintain the even-numbered data voltage EVDATA. In addition, the odd-numbered data voltage OVDATA may be applied to the third pixel column. In an embodiment, for example, the odd-numbered data voltage OVDATA may be applied to the odd-numbered pixel column. In addition, the odd-numbered data voltage OVDATA may not be applied to the even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P]. In an embodiment, for example, the even-numbered pixel column may maintain the even-numbered data voltage EVDATA.

[0090] In the illustrated embodiment, the data voltage VDATA applied to the first data line DLA[1] and the second data line DLA[2] can be selected by the first output control transistor. In the embodiment, for example, the data voltage applied to both data lines can be controlled by a single transistor. Therefore, the number of output control transistors included in the multiplexer block 600A can be reduced. The reduction in the number of output control transistors included in the multiplexer block 600A improves the integration density of the multiplexer block 600A. Therefore, the integration density of the display device 1 can be improved. Furthermore, the reduction in the number of output control transistors included in the multiplexer block 600A reduces the power consumption of the display device 1.

[0091] Figure 7 It is shown Figure 5 Timing diagram of an embodiment of the input signals in the activation and non-activation cycles included in the scan cycle.

[0092] Reference Figure 7The scan cycle can include a first cycle TP1B and a second cycle TP2B. The first cycle TP1B can be an active cycle. The second cycle TP2B can be an inactive cycle.

[0093] Apart from the fact that the length of the first cycle TP1B is different from the length of the second cycle TP2B, Figure 7 The timing diagram and Figure 6 The timing diagrams are essentially the same, so the same reference numerals will be used and any repeated descriptions of the above-mentioned components will be omitted.

[0094] Reference Figures 1 to 5 and Figure 7 In the illustrated embodiment, the length of the first period TP1B may be different from the length of the second period TP2B. In the embodiment, for example, the length of the first period TP1B may be longer than the length of the second period TP2B. Therefore, the length of the period in which the even-numbered data voltage EVDATA is applied to the even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P] can be increased. In the embodiment, for example, the even-numbered data voltage EVDATA may be applied to the even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P] through the odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1]. The length of the period for applying the even-numbered data voltage EVDATA to the even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P] can be increased, thereby reducing the influence of the odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1]. In an embodiment, for example, the influence of the resistance of the odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1] can be reduced. Therefore, the reliability of the even-numbered data voltage EVDATA applied to the even-numbered pixel column can be improved. Therefore, the emission reliability of the pixel circuit of pixel PX can be improved.

[0095] Figure 8 It is shown Figure 3 Circuit diagram of an embodiment of the display panel 100A, data driver 500A, and multiplexer block 600A. Figure 9 It is shown Figure 1 The timing diagram of the input signals during the effective period of the display device 1.

[0096] Reference Figures 1 to 9In the illustrated embodiment, odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1] can be connected to a first color pixel R and a second color pixel B. In the embodiment, for example, the first color pixel R has a first color, and the second color pixel B can have a second color different from the first color. In the embodiment, for example, the first color can be red. In the embodiment, for example, the second color can be blue. In the embodiment, for example, the first color pixel R and the second color pixel B can be alternately arranged on odd-numbered data lines DLA[1], DLA[3], DLA[5]...DLA[2P-1]. In the embodiment, for example, the first color pixel R and the second color pixel B can be alternately arranged on the first data line DLA[1]. In the embodiment, for example, the second color pixel B and the first color pixel R can be alternately arranged on the third data line DLA[3]. Even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P] can be connected to a third color pixel G. In an embodiment, for example, the third color pixel G may have a third color different from the first and second colors. In an embodiment, for example, the third color may be green. In an embodiment, for example, the display panel 100A may have... structure.

[0097] In the illustrated embodiment, a data voltage VDATA can be applied to the pixel circuit of pixel PX during scan cycles SP1B, SP2B, SP3B, and SP4B. The data voltage VDATA may include a first color data voltage RVDATA, a second color data voltage BVDATA, and a third color data voltage GVDATA.

[0098] During the active period of the first scan cycle SP1B, output amplifiers OAMP1 and OAMP2 can output the third color data voltage GVDATA. Therefore, the third color pixel G can receive the third color data voltage GVDATA. During the inactive period of the first scan cycle SP1B, the first output amplifier OAMP1 can output the first color data voltage RVDATA, and the second output amplifier OAMP2 can output the second color data voltage BVDATA. Therefore, the first color pixel R can receive the first color data voltage RVDATA, and the second color pixel B can receive the second color data voltage BVDATA. During the inactive period of the first scan cycle SP1B, the output control transistor MTR can be turned off, allowing the third color pixel G to maintain the third color data voltage GVDATA.

[0099] During the active period of the second scan cycle SP2B, output amplifiers OAMP1 and OAMP2 can output the third color data voltage GVDATA. Therefore, the third color pixel G can receive the third color data voltage GVDATA. During the inactive period of the second scan cycle SP2B, the first output amplifier OAMP1 can output the second color data voltage BVDATA, and the second output amplifier OAMP2 can output the first color data voltage RVDATA. Therefore, the first color pixel R can receive the first color data voltage RVDATA, and the second color pixel B can receive the second color data voltage BVDATA. During the inactive period of the second scan cycle SP2B, the output control transistor MTR can be turned off, allowing the third color pixel G to maintain the third color data voltage GVDATA.

[0100] In the illustrated embodiment, the data voltage VDATA applied to the first data line DLA[1] and the second data line DLA[2] can be selected by the first output control transistor. In the embodiment, for example, the data voltage applied to both data lines can be controlled by a single transistor. Therefore, the number of output control transistors included in the multiplexer block 600A can be reduced. The reduction in the number of output control transistors included in the multiplexer block 600A improves the integration density of the multiplexer block 600A. Therefore, the integration density of the display device 1 can be improved. Furthermore, the reduction in the number of output control transistors included in the multiplexer block 600A reduces the power consumption of the display device 1.

[0101] Figure 10 It is shown Figure 3 Circuit diagram of an embodiment of the display panel 100A, data driver 500A, and multiplexer block 600A. Figure 11 It is shown Figure 1 The timing diagram of the input signals during the effective period of the display device 1.

[0102] Reference Figure 10 Besides the output amplifiers OAMP1 and OAMP2 being able to connect to even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P], Figure 10 The circuit diagram and Figure 8 The circuit diagrams are essentially the same, so the same reference numerals will be used and any repeated descriptions of the above components will be omitted.

[0103] Reference Figures 1 to 7 , Figure 10 and Figure 11Output amplifiers OAMP1 and OAMP2 can be connected to even-numbered data lines DLA[2], DLA[4], DLA[6]...DLA[2P]. Furthermore, during scan cycles SP1C, SP2C, SP3C, and SP4C, the data voltage VDATA can be applied to the pixel circuit of pixel PX.

[0104] During the active period of the first scan cycle SP1C, the first output amplifier OAMP1 outputs the first color data voltage RVDATA, and the second output amplifier OAMP2 outputs the second color data voltage BVDATA. Therefore, the first color pixel R receives the first color data voltage RVDATA, and the second color pixel B receives the second color data voltage BVDATA. During the inactive period of the first scan cycle SP1C, output amplifiers OAMP1 and OAMP2 output the third color data voltage GVDATA. Therefore, the third color pixel G receives the third color data voltage GVDATA. During the inactive period of the first scan cycle SP1C, the output control transistor MTR can be turned off, allowing the first color pixel R to maintain the first color data voltage RVDATA, and the second color pixel B to maintain the second color data voltage BVDATA.

[0105] During the active period of the second scan cycle SP2C, the first output amplifier OAMP1 outputs the second color data voltage BVDATA, and the second output amplifier OAMP2 outputs the first color data voltage RVDATA. Therefore, the first color pixel R receives the first color data voltage RVDATA, and the second color pixel B receives the second color data voltage BVDATA. During the inactive period of the second scan cycle SP2C, output amplifiers OAMP1 and OAMP2 output the third color data voltage GVDATA. Therefore, the third color pixel G receives the third color data voltage GVDATA. During the inactive period of the second scan cycle SP2C, the output control transistor MTR can be turned off, allowing the first color pixel R to maintain the first color data voltage RVDATA, and the second color pixel B to maintain the second color data voltage BVDATA.

[0106] In the illustrated embodiment, the data voltage VDATA applied to the first data line DLA[1] and the second data line DLA[2] can be selected by the first output control transistor. In the embodiment, for example, the data voltage applied to both data lines can be controlled by a single transistor. Therefore, the number of output control transistors included in the multiplexer block 600A can be reduced. The reduction in the number of output control transistors included in the multiplexer block 600A improves the integration density of the multiplexer block 600A. Therefore, the integration density of the display device 1 can be improved. Furthermore, the reduction in the number of output control transistors included in the multiplexer block 600A reduces the power consumption of the display device 1.

[0107] Figure 12 This is a perspective view showing an embodiment of the display device 1A. Figure 13 It shows along Figure 12 A side view of an embodiment of the display device 1A in its folded state, taken by line I-I'. Figure 14 It shows along Figure 12 A side view of an embodiment showing the positions of the data driver 500 and multiplexer block 600A included in the display device 1A, as captured by line I-I'. Figure 15 It is shown Figure 1 A circuit diagram of an embodiment showing the positions of the display panel 100, the data driver 500, and the multiplexer block 600A. Figure 16 It is shown Figure 1 A circuit diagram of an embodiment showing the positions of the display panel 100, the data driver 500, and the multiplexer block 600A.

[0108] Reference Figures 1 to 16 The display device 1A may include a display area DA and a peripheral area PA. The display area DA may display an image. The peripheral area PA may not display an image. The peripheral area PA may be positioned next to (adjacent to) the display area DA.

[0109] In this specification, a plane may be defined along a first direction DR1 and a second direction DR2. In an embodiment, the second direction DR2 may be perpendicular to the first direction DR1. Furthermore, for example, a third direction DR3 may be perpendicular to the plane.

[0110] Display device 1A includes: a foldable region FA, which can be bent by an external force, allowing display device 1A to be folded; and a first non-foldable region NFA1 and a second non-foldable region NFA2, which are not folded and are adjacent to at least one side of the foldable region FA. The foldable region FA and the first non-foldable region NFA1 and the second non-foldable region NFA2 may at least overlap with the display region DA. In an embodiment, for example, the foldable region FA may have a folding axis extending along a first direction DR1.

[0111] The display area DA can be divided into a first display area DA1 and a second display area DA2 that are adjacent to each other on a second direction DR2 that intersects with the first direction DR1. In an embodiment, for example, the second direction DR2 may intersect with the first direction DR1. The first display area DA1 and the second display area DA2 may be continuously connected to substantially form a single display area DA. In an embodiment, for example, when the display area DA is folded along a folding axis, as... Figure 2 As shown, the display device may have an inward folding structure, such that the first display area DA1 and the second display area DA2 face each other. In an optional embodiment, when the display area DA is folded along the folding axis, as... Figure 3 As shown, the display device may have an outward folding structure in which the display area DA is disposed on the outside.

[0112] The display device 1A in the embodiments of this disclosure is not limited to including a single foldable region FA. In embodiments, for example, the display device 1A can be folded multiple times, or can have multiple foldable regions FA to achieve a rollable display device.

[0113] In the illustrated embodiment, the data driver 500 may be located in the peripheral region PA. The multiplexer block 600A may be located in the foldable region FA. The first display region DA1 may include a first data line group DLGA. The second display region DA2 may include a second data line group DLGB. The data driver 500 may be connected to the second data line group DLGB via the multiplexer block 600A. The first data line group DLGA may include a first-first data line DLGA[1], a first-second data line DLGA[2], a first-third data line DLGA[3], ... a first-Pth data line DLGA[P]. The second data line group DLGB may include a second-first data line DLGB[1], a second-second data line DLGB[2], a second-third data line DLGB[3], ... a second-Pth data line DLGB[P]. The first-first data line DLGA[1] may be connected to the second-second data line DLGB[1] via the output control transistor MTR. The first-second data line DLGA[2] may be connected to the second-second data line DLGB[2] via the output control transistor MTR. The first-third data line DLGA[3] can be connected to the second-third data line DLGB[3] via the output control transistor MTR. The first-Pth data line DLGA[P] can be connected to the second-Pth data line DLGB[P] via the output control transistor MTR.

[0114] In this embodiment, the first color pixel R can be connected to the first-first data line DLGA[1] and the second-first data line DLGB[1]. The third color pixel G can be connected to the first-second data line DLGA[2] and the second-second data line DLGB[2]. The second color pixel B can be connected to the first-third data line DLGA[3] and the second-third data line DLGB[3].

[0115] In one embodiment, the first color pixel R and the second color pixel B can be connected to the first-first data line DLGA[1] and the second-first data line DLGB[1]. In another embodiment, for example, the first color pixel R and the second color pixel B can be alternately connected to the first-first data line DLGA[1] and the second-first data line DLGB[1]. The third color pixel G can be connected to the first-second data line DLGA[2] and the second-second data line DLGB[2]. The first color pixel R and the second color pixel B can be connected to the first-third data line DLGA[3] and the second-third data line DLGB[3]. The first color pixel R and the second color pixel B can be alternately connected to the first-third data line DLGA[3] and the second-third data line DLGB[3].

[0116] In an embodiment, for example, when the first display area DA1 and the second display area DA2 emit light, the output control signal CLA can have an active level. Therefore, the output control transistor MTR included in the multiplexer block 600A can be turned on. The output control transistor MTR being turned on allows connection of the first data line group DLGA and the second data line group DLGB. Therefore, the data driver 500 can apply a data voltage VDATA to the second data line group DLGB via the first data line group DLGA and the multiplexer block 600A. Thus, the data voltage VDATA can be applied to the second data line group DLGB. Applying the data voltage VDATA to the second data line group DLGB allows the pixel circuit of the pixel PX connected to the second data line group DLGB to emit light based on the data voltage VDATA.

[0117] In an embodiment, for example, when the first display area DA1 emits light and the second display area DA2 stops emitting light, the output control signal CLA can have an inactive level. Therefore, the output control transistor MTR included in the multiplexer block 600A can be turned off. Therefore, the first data line group DLGA and the second data line group DLGB can be disconnected. The first data line group DLGA and the second data line group DLGB can be disconnected so that the data voltage VDATA can not be applied to the second data line group DLGB. In an embodiment, for example, when the output control signal CLA has an inactive level, the operation of applying the data voltage VDATA to the second data line group DLGB can be omitted. Therefore, the second display area DA2 can stop emitting light.

[0118] In the illustrated embodiment, the transmission operations of the first display area DA1 and the second display area DA2 can be controlled by the multiplexer block 600A. In this embodiment, for example, the data voltage VDATA applied to the second display area DA2 can be controlled by the multiplexer block 600A. Therefore, the power consumption of the display device 1A can be reduced.

[0119] Figure 17 It is shown Figure 1 A block diagram of an embodiment showing the position of the display device 1. Figure 18 It is shown Figure 17 Circuit diagram of an embodiment of the display panel 100B, data driver 500B, and multiplexer block 600B. Figure 19 It is shown Figure 1 The timing diagram of the input signals during the effective period of the display device 1. Figure 20 It is shown Figure 19 Timing diagram of an embodiment of the input signals in the activation and non-activation cycles included in the scan cycle.

[0120] Reference Figure 1 and Figures 17 to 20 The display device 1 may include a display panel 100B, a data driver 500B, and a multiplexer block 600B. The display panel 100B may include a first data line DLB[1], a second data line DLB[2], a third data line DLB[3], a fourth data line DLB[4] to a second data line DLB[2P-1] and a second data line DLB[2P]. The display panel 100B may include a first output line OC[1], a second output line OC[2] to a P-th output line OC[P]. In an embodiment, for example, the data driver 500B may be connected to the multiplexer block 600B via the first output line OC[1], the second output line OC[2] to the P-th output line OC[P].

[0121] In the illustrated embodiment, the data driver 500B may include output amplifiers OAMP1 and OAMP2. Output amplifiers OAMP1 and OAMP2 may be connected to a first output line OC[1], a second output line OC[2], and a P-th output line OC[P]. In one embodiment, for example, the first output amplifier OAMP1 may be connected to the first output line OC[1]. In another embodiment, for example, the second output amplifier OAMP2 may be connected to the second output line OC[2]. The first output amplifier OAMP1 may output a data voltage VDATA to the first output line OC[1]. The second output amplifier OAMP2 may output a data voltage VDATA to the second output line OC[2].

[0122] The multiplexer block 600B may include even-numbered output control transistors EMTR and odd-numbered output control transistors OMTR.

[0123] The even-numbered output control transistor EMTR may include a control electrode that receives a first output control signal CLB, a first electrode connected to an output line, and a second electrode connected to an even-numbered data line DLB[2P]. The even-numbered output control transistor EMTR may apply a data voltage to the even-numbered data line DLB[2P] in response to the first output control signal CLB.

[0124] The odd-numbered output control transistor OMTR may include a control electrode that receives a second output control signal CLC, a first electrode connected to an output line, and a second electrode connected to an odd-numbered data line DLB[2P-1]. The odd-numbered output control transistor OMTR may apply a data voltage VDATA to the odd-numbered data line DLB[2P-1] in response to the second output control signal CLC.

[0125] In the illustrated embodiment, during the effective period, a data voltage VDATA can be applied to the pixel circuit of pixel PX. In this embodiment, for example, the effective period may include a first scan period SP1D, a second scan period SP2D, a third scan period SP3D, and a fourth scan period SP4D. Each of the first scan period SP1D, the second scan period SP2D, the third scan period SP3D, and the fourth scan period SP4D may include a first period TP1C and a second period TP2C.

[0126] In the first cycle TP1C, the data voltage VDATA can have an even-numbered data voltage EVDATA. In the first cycle TP1C, output amplifiers OAMP1 and OAMP2 can output even-numbered data voltages EVDATA, the first output control signal CLB can be at an active level, and the second output control signal CLC can be at an inactive level.

[0127] In the first cycle TP1C, the first output control signal CLB can be active, and the even-numbered output control transistor EMTR can be turned on. The even-numbered output control transistor EMTR being on allows the even-numbered data voltage EVDATA to be applied to the even-numbered data line DLB[2P]. In the first cycle TP1C, the second output control signal CLC can be inactive, allowing the odd-numbered output control transistor OMTR to be turned off.

[0128] In the second cycle TP2C, the data voltage VDATA can have an odd-numbered data voltage OVDATA. In the second cycle TP2C, output amplifiers OAMP1 and OAMP2 can output an odd-numbered data voltage OVDATA, the first output control signal CLB can be at a deactivated level, and the second output control signal CLC can be at an activated level.

[0129] In the second cycle TP2C, the second output control signal CLC can be active, and the odd-numbered output control transistor OMTR can be turned on. The conduction of the odd-numbered output control transistor OMTR allows the odd-numbered data voltage OVDATA to be applied to the odd-numbered data line DLB[2P-1]. In the second cycle TP2C, the first output control signal CLB can be inactive, allowing the even-numbered output control transistor EMTR to be turned off.

[0130] In the illustrated embodiment, the data driver 500B may be spaced apart from the display panel 100B in a first positioning direction D1. Furthermore, the multiplexer block 600B may be spaced apart from the display panel 100B in a second positioning direction D2. In this embodiment, for example, the data driver 500B may be located in the bottom region of the display panel 100B. In this embodiment, for example, the multiplexer block 600B may be located in the upper region of the display panel 100B. The fact that the data driver 500B is spaced apart from the display panel 100B in the first positioning direction D1, and the multiplexer block 600B is spaced apart from the display panel 100B in the second positioning direction D2, allows for a reduction in the bezel size of the display device 1. In this embodiment, for example, the bottom region of the display device 1 may be reduced.

[0131] Figure 21 It is shown Figure 1 A circuit diagram of an embodiment showing the positions of the display panel 100A, the data driver 500A, and the multiplexer block 600A.

[0132] Reference Figures 1 to 21 The display device 1 may include a display panel 100A, a data driver 500A, and a multiplexer block 600A. The display panel 100A may include data lines DLC[1], DLC[2], DLC[3], DLC[4], ... etc.

[0133] In the illustrated embodiment, the multiplexer block 600A may be spaced apart from the display panel 100A in the first positioning direction D1. The data driver 500A may also be spaced apart from the display panel 100A in the first positioning direction D1.

[0134] Aside from the different location of the 600A multiplexer block, Figure 21 The circuit diagram and Figure 4 The circuit diagrams are essentially the same, so the same reference numerals will be used and any repeated descriptions of the above components will be omitted.

[0135] In the illustrated embodiment, the data voltage VDATA applied to the first data line DLA[1] and the second data line DLA[2] can be selected by the first output control transistor. In the embodiment, for example, the data voltage applied to both data lines can be controlled by a single transistor. Therefore, the number of output control transistors included in the multiplexer block 600A can be reduced. The reduction in the number of output control transistors included in the multiplexer block 600A improves the integration density of the multiplexer block 600A. Therefore, the integration density of the display device 1 can be improved. Furthermore, the reduction in the number of output control transistors included in the multiplexer block 600A reduces the power consumption of the display device 1.

[0136] Furthermore, when the output control transistor MTR is turned on in response to the output control signal CLA, the third color data voltage GVDATA can be applied to the third color pixel G, thereby stopping the output of the first color data voltage RVDATA and the second color data voltage BVDATA. Therefore, the power consumption of the display device 1 can be further reduced.

[0137] Figure 22 This is a block diagram illustrating an embodiment of an electronic device 1000 according to the present invention.

[0138] Reference Figures 1 to 22 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be… Figure 1 The display device 1. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc.

[0139] In this embodiment, the electronic device 1000 may be implemented as a smartphone. However, the electronic device 1000 is not limited to this. In this embodiment, for example, the electronic device 1000 may be implemented as a cellular phone, video phone, smartpad, smartwatch, tablet PC (“PC”), car navigation system, computer monitor, laptop computer, or head-mounted display (“HMD”) device, etc.

[0140] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, a central processing unit (“CPU”), or an application processor (“AP”), etc. Processor 1010 can be coupled to other components via address buses, control buses, data buses, etc. In addition, processor 1010 can be coupled to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0141] Processor 1010 can... Figure 1 The drive controller 200 outputs input image data (IMG), input control signal (CONT), and multiplexer block control signal (MCS). The processor 1010 can perform data mapping based on the connection structure of multiplexer blocks 600A and 600B and the display panel 100. The processor 1010 can generate signals for controlling the gate driver 300, data driver 500, and multiplexer blocks 600A and 600B.

[0142] The memory device 1020 can store data for the operation of the electronic device 1000. In embodiments, for example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, or a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a mobile DRAM device, etc.

[0143] Storage device 1030 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, or an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1040 may include input devices such as a keyboard, keypad, mouse device, touchpad, or touchscreen, and output devices such as a printer or speaker. In some embodiments, display device 1060 may be included in I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be coupled to other components via a bus or other communication link.

[0144] The electronic device 1000 of this invention is shown as a smartphone, but the invention is not limited thereto. The electronic device 1000 can be a television, monitor, laptop computer, or tablet computer. Furthermore, the electronic device 1000 can be a car.

[0145] The display device in the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart boards, portable media players (“PMP”), personal digital assistants (“PDA”), or Cinema Experts Group Audio Layer III (“MP3”) players, etc.

[0146] The foregoing is illustrative of the inventive concept and is not to be construed as limiting it. Although several embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that some modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device (or means) plus function clause is intended to cover structures described herein that perform the listed functions, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limiting it to the disclosed illustrative embodiments, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and equivalents of the claims are included therein.

Claims

1. A display device, wherein, The display device includes: The display panel includes multiple pixels; A gate driver configured to output a gate signal to the display panel; A data driver, configured to generate a data voltage applied to the display panel; and A multiplexer block configured to output the data voltage to the display panel, the multiplexer block comprising: The output control transistor includes: The control electrode is configured to receive the output control signal; The first electrode is connected to the first data line; and The second electrode is connected to the second data line.

2. The display device according to claim 1, wherein, The data voltage includes a first data voltage and a second data voltage. Wherein, the first data line is connected to the first output amplifier that outputs the data voltage, and The second data line is connected to the first data line via the multiplexer block.

3. The display device according to claim 2, wherein, When the output control signal is at an active level, the data driver outputs the second data voltage, and Specifically, when the output control signal is at an inactive level, the data driver outputs the first data voltage.

4. The display device according to claim 2, wherein, When the output control signal is at an inactive level, the first data voltage is applied to the first data line.

5. The display device according to claim 2, wherein, The length of the active period of the output control signal with an active level is longer than the length of the inactive period of the output control signal with an inactive level.

6. The display device according to claim 1, wherein, The data driver includes a first output amplifier and a second output amplifier configured to output the data voltage. The display panel further includes a first data line, a second data line, a third data line, and a fourth data line arranged sequentially. The multiplexer block further includes a first output control transistor connected to the first data line and the second data line, and a second output control transistor connected to the third data line and the fourth data line. Wherein, the first output amplifier is connected to the first data line, and The second output amplifier is connected to the third data line.

7. The display device according to claim 1, wherein, The data driver includes a first output amplifier and a second output amplifier configured to output the data voltage. The display panel further includes a first data line, a second data line, a third data line, and a fourth data line arranged sequentially. The multiplexer block further includes a first output control transistor connected to the first data line and the second data line, and a second output control transistor connected to the third data line and the fourth data line. The first output amplifier is connected to the second data line, and The second output amplifier is connected to the fourth data line.

8. The display device according to claim 1, wherein, The data voltage includes a first data voltage and a second data voltage. Specifically, when the output control signal has an active level, the data driver outputs the first data voltage, and Specifically, when the output control signal is at an inactive level, the data driver outputs the second data voltage.

9. An electronic device, wherein, The electronic device includes: The display panel includes multiple pixels; A gate driver configured to output a gate signal to the display panel; A data driver configured to generate a data voltage applied to the display panel; A multiplexer block configured to output the data voltage to the display panel, the multiplexer block comprising: The first output control transistor includes: The control electrode is configured to receive a second output control signal; The first electrode is connected to the first output line; and The second electrode is connected to the first data line; and The second output control transistor includes: A control electrode is configured to receive a first output control signal; The first electrode is connected to the first output line; and The second electrode is connected to the second data line; and The processor is configured to control the gate driver, the data driver, and the multiplexer block. Wherein, the data driver is spaced apart from the display panel in the first positioning direction, and The multiplexer block is spaced apart from the display panel in a second positioning direction, which is different from the first positioning direction.

10. The electronic device according to claim 9, wherein, The data voltage includes a first data voltage and a second data voltage. The period for applying the data voltage includes a first period and a second period. In the first cycle, the data voltage has the second data voltage, the first output control signal has an active level, the second output control signal has an inactive level, and the second data voltage is applied to the second data line. In the second cycle, the data voltage has the first data voltage, the first output control signal has an inactive level, the second output control signal has an active level, and the first data voltage is applied to the first data line.

Images