High-speed image acquisition and transmission system and method based on FPGA

Abstract

The invention discloses a high-speed image acquisition and transmission system and method based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: configuring a working mode and the number of data output channels of an image sensor by the FPGA through an SPI (Serial Peripheral Interface) after power-on reset; after configuration is completed, the sensor starts to collect image data, the image data is written into the DDR to be cached after being cached by the FIFO, and finally the data in the DDR is read out and transmitted to the upper computer through the Ethernet; according to the invention, the requirement of a machine vision system on real-time acquisition of clear images during image processing can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of image processing, and in particular relates to a high-speed image acquisition and transmission system and method based on FPGA. Background Art

[0002] With the rapid development of electronic technology, machine vision technology plays an increasingly important role in target detection, dimension measurement, PCB defect detection and other fields. The image acquisition system provides an image source for the machine vision system, and is developing towards high speed and high real-time performance. In order to meet the demand for real-time acquisition of clear images when the machine vision system performs image processing, based on the advantages of CMOS image sensors with low power consumption, high speed and low noise and the characteristics of FPGA with high speed, multiple logic resources, flexible programming and high parallelism, the present invention designs a high-performance image transmission acquisition transmission system. Summary of the invention

[0003] In view of this, the present invention provides a high-speed image acquisition and transmission system and method based on FPGA, which can acquire and transmit clear images in real time.

[0004] The technical solution for implementing the present invention is as follows:

[0005] A high-speed image acquisition and transmission system based on FPGA, including a main control module, an image acquisition module, a DDR control module, and a network transmission module;

[0006] The image acquisition module uses PYTHON1300 as the image acquisition front end;

[0007] The main control module configures the sensor's internal registers through the SPI interface, sets the sensor's internal clock frequency to 72MHz, and outputs image synchronization signals, synchronization clock signals, and 10-bit image data;

[0008] The DDR control module is responsible for receiving the image synchronization signal and image data, adding Ethernet packet information to the image data after receiving. The image synchronization signal controls the DDR to cache the image data, and controls the DDR to output the image data to the network transmission module, and retransmits the image data according to the retransmission address sent by the main control module;

[0009] The main control module receives the configuration command from the network transmission module and controls the image sensor accordingly. It also receives the retransmission command sent by the network transmission module and outputs the image address to be retransmitted obtained after decoding the command to the DDR control module.

[0010] The network transmission module transmits the packaged image data to the host computer via Gigabit Ethernet for display, and at the same time receives the gain, resolution, and exposure configuration commands sent by the host computer and transmits them to the main control module.

[0011] Furthermore, if an error occurs when the host computer receives data, the network transmission module will receive a retransmission command sent by the host computer and output it to the main control module.

[0012] Furthermore, FPGA is used as the main control module, PYTHON1300 image sensor is used as the image acquisition module, DDR3 is used to cache image data, image data is transmitted to the host computer through Gigabit Ethernet, and configuration commands sent by the host computer are received to configure the sensor.

[0013] Furthermore, when the system is working normally, it collects and transmits images with a resolution of 1280×1024 at a rate of 90 frames / s.

[0014] A high-speed image acquisition and transmission method based on FPGA. After power-on reset, FPGA configures the working mode and number of data output channels of the image sensor through the SPI interface.

[0015] After the configuration is completed, the sensor starts to collect image data, writes it into DDR for caching after FIFO buffering, and finally reads the data in DDR and transmits it to the host computer via Ethernet.

[0016] Beneficial effects:

[0017] 1. In the scheme of the present invention, a high-speed, small-volume, low-power PYTHON1300 image sensor is used to collect images. The system uses FPGA as the main controller, uses PYTHON1300 image sensor to collect image data, uses DDR3 to cache image data, transmits image data to the host computer through Gigabit Ethernet, and receives configuration commands issued by the host computer to configure the sensor. The system is controlled by FPGA with high speed and abundant resources, and Gigabit Ethernet with fast transmission speed and good stability is used to transmit data and commands.

[0018] 2. The system of the present invention has low power consumption, accurate data and is not easy to lose, small size, good portability and small space occupation, and fast image acquisition and transmission speed.

[0019] 3. The system of the present invention can meet the requirements of the machine vision system for real-time image acquisition and has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The figure is a flow chart of a high-speed image acquisition and transmission system based on FPGA of the present invention.

[0021] Figure 2 A schematic diagram of the image caching principle provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0023] The present invention provides a high-speed image acquisition and transmission system based on FPGA, such as Figure 1 As shown in the figure, it includes a main control module, an image acquisition module, a DDR control module, and a network transmission module. The system uses FPGA as the main controller, uses a PYTHON1300 image sensor to collect image data, uses DDR3 to cache image data, transmits image data to the host computer through Gigabit Ethernet, and receives configuration commands from the host computer to configure the sensor. When the system is working normally, it collects and transmits images with a resolution of 1280×1024 at a rate of 90 frames / s, which meets the requirements of the machine vision system for real-time image acquisition and has high reliability.

[0024] The image acquisition module uses PYTHON1300 as the image acquisition front end. The main control module configures the internal registers of the sensor through the SPI interface, sets the internal clock frequency of the sensor to 72MHz, and outputs image synchronization signals, synchronization clock signals, and 10-bit image data; the DDR control module is responsible for receiving the image synchronization signal and image data, adding Ethernet packet information to the image data after receiving, controlling the DDR to cache the image data according to the image synchronization signal, and controlling the DDR to output the image data to the network transmission module, and retransmitting the image data according to the retransmission address issued by the main control module; the main control module receives the configuration command of the network transmission module and controls the image sensor with it, and receives the retransmission command sent by the network transmission module, and outputs the image address to be retransmitted after decoding the command to the DDR control module; the network transmission module transmits the packaged image data to the host computer through Gigabit Ethernet for display, and receives the gain, resolution, exposure and other configuration commands transmitted by the host computer and transmits them to the main control module.

[0025] If an error occurs when the host computer receives data, the network transmission module will receive the retransmission command sent by the host computer and output it to the main control module.

[0026] The present invention proposes a high-speed image acquisition and transmission method based on FPGA, comprising:

[0027] The system working process is that after power-on reset, FPGA configures the working mode of the image sensor, the number of data output channels, etc. through the SPI interface;

[0028] After the configuration is completed, the sensor starts to collect image data, writes it into DDR for caching after FIFO buffering, and finally reads the data in DDR and transmits it to the host computer via Ethernet.

[0029] Embodiment 1

[0030] The high-speed image acquisition and transmission method based on FPGA provided by the embodiment of the present invention includes: image acquisition method design and image cache method design;

[0031] The FPGA-based high-speed image acquisition and transmission method described in the embodiment of the present invention adopts the trigger shutter mode of the sensor to control the timing of image acquisition, and controls the acquisition and output of image data by the sensor by controlling TRIGGER0. When the rising edge of TRIGGER0 is detected, the sensor starts to acquire images, convert them into data, and output them through the LVDS data channel.

[0032] Before the sensor outputs image data, it first outputs the IMG signal through the sync channel. At this time, the FPGA starts to read the image data and cache it in the FIFO. The order of the sensor output pixels is from the upper left to the lower right. The output image is based on the core. A core consists of 8 pixels from left to right in the horizontal direction. Each data channel outputs two adjacent pixels belonging to the core. When outputting an image, if it is an odd-numbered core, the pixels from the right to the left of the core are output, and if it is an even-numbered core, the pixels from the left to the right are output. Therefore, it is necessary to call the FPGA's on-chip RAM to sort the received pixels and then store them in DDR3. First, the collected image data is saved in RAM. After saving 8 pixels, the pixels are output in sequence according to the order of the image data.

[0033] Since the write clock frequency and data bit width of DDR3 are different from the send data clock and data output interface bit width of the image sensor, the data is first buffered in the internal FIFO of the FPGA and then written into DDR3.

[0034] When FIFO is not empty, the image data in FIFO is stored in DDR3 by transmitting a write command to DDR, and counting is performed while writing data; when there is no data in FIFO, the write operation is stopped, and the completion of the write operation is determined based on the counting result. When FPGA sends a read signal, a read command is written to DDR according to the address of the image in DDR to read the image data. Since the input interface bit width and working clock frequency of DDR and network transmission module are different, the image data read is first cached using FIFO, and then output to the network transmission module. The principle diagram of image cache is shown in the figure. Figure 2 shown.

[0035] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed image acquisition and transmission system based on FPGA, characterized in that: Including main control module, image acquisition module, DDR control module, network transmission module; The image acquisition module uses PYTHON1300 as the image acquisition front end; The main control module configures the sensor's internal registers through the SPI interface, sets the sensor's internal clock frequency to 72MHz, and outputs image synchronization signals, synchronization clock signals, and 10-bit image data; The DDR control module is responsible for receiving the image synchronization signal and image data, adding Ethernet packet information to the image data after receiving. The image synchronization signal controls the DDR to cache the image data, and controls the DDR to output the image data to the network transmission module, and retransmits the image data according to the retransmission address sent by the main control module; The main control module receives the configuration command from the network transmission module and controls the image sensor accordingly. It also receives the retransmission command sent by the network transmission module and outputs the image address to be retransmitted obtained after decoding the command to the DDR control module. The network transmission module transmits the packaged image data to the host computer via Gigabit Ethernet for display, and at the same time receives the gain, resolution, and exposure configuration commands sent by the host computer and transmits them to the main control module.

2. The image acquisition and transmission system according to claim 1, characterized in that: If an error occurs when the host computer receives data, the network transmission module will receive the retransmission command sent by the host computer and output it to the main control module.

3. The image acquisition and transmission system according to claim 1, characterized in that: FPGA is used as the main control module, PYTHON1300 image sensor is used as the image acquisition module, DDR3 is used to cache image data, image data is transmitted to the host computer through Gigabit Ethernet, and configuration commands sent by the host computer are received to configure the sensor.

4. The image acquisition and transmission system according to claim 3, characterized in that: When the system is working normally, it collects and transmits images with a resolution of 1280×1024 at a rate of 90 frames / s.

5. The high-speed image acquisition and transmission method applied to any system of claims 1 to 4, characterized in that: After power-on reset, the FPGA configures the image sensor's operating mode and the number of data output channels through the SPI interface; After the configuration is completed, the sensor starts to collect image data, writes it into DDR for caching after FIFO buffering, and finally reads the data in DDR and transmits it to the host computer via Ethernet.

Images