Display panel

Abstract

The invention provides a display panel which comprises a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of pixel structures and a shading pattern layer. The substrate is provided with a display area. The plurality of scanning lines and the plurality of data lines are arranged on the substrate and intersect with each other. The plurality of pixel structures are arranged in the display area, and each pixel structure comprises a display transistor and a pixel electrode. The display transistor comprises a first semiconductor pattern, a first grid electrode, a first source electrode and a first drain electrode. The first grid electrode is arranged between the substrate and the first semiconductor pattern and is electrically connected with one of the scanning lines. The first source electrode is electrically connected with one of the plurality of data lines. The pixel electrode is electrically connected with the first drain electrode of the display transistor. The shading pattern layer is arranged between the first grid electrode and the substrate and is provided with a first opening overlapped with the first grid electrode.

Description

Technical Field

[0001] The present invention relates to a display technology, and in particular to a display panel. Background Art

[0002] Most current mainstream display panels use thin film transistors to actively control display pixels. However, thin film transistors are often prone to leakage due to the irradiation of light sources (whether backlight or ambient light), resulting in poor electrical properties of the pixel structure and affecting display quality. Summary of the invention

[0003] The present invention is directed to a display panel having better operating electrical properties.

[0004] According to an embodiment of the present invention, a display panel includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel structures and a shading pattern layer. The substrate is provided with a display area. A plurality of scan lines and a plurality of data lines are arranged on the substrate and intersect with each other. A plurality of pixel structures are arranged in the display area, and each includes a display transistor and a pixel electrode. The display transistor includes a first semiconductor pattern, a first gate, a first source and a first drain. The first gate is arranged between the substrate and the first semiconductor pattern and is electrically connected to one of the plurality of scan lines. The first source is electrically connected to one of the plurality of data lines. The pixel electrode is electrically connected to the first drain of the display transistor. The shading pattern layer is arranged between the first gate and the substrate and has a first opening overlapping the first gate.

[0005] In the display panel according to the embodiment of the present invention, the orthographic projection of the first opening of the light shielding pattern layer on the substrate is located within the orthographic projection of the first gate on the substrate.

[0006] In the display panel according to the embodiment of the present invention, the orthographic projection of the light shielding pattern layer on the substrate surrounds the orthographic projection of the first gate on the substrate.

[0007] In the display panel according to an embodiment of the present invention, each of the plurality of pixel structures further comprises a common electrode, which is arranged between the pixel electrode and the substrate and overlaps the pixel electrode. The common electrode and the first gate have a first gap in their orthographic projection on the substrate, and the first gap is located within the orthographic projection of the light-shielding pattern layer on the substrate.

[0008] In the display panel according to the embodiment of the present invention, an orthographic projection of the common electrode and an adjacent one of the plurality of data lines on the substrate has a second gap, and the second gap is located within the orthographic projection of the light shielding pattern layer on the substrate.

[0009] In the display panel according to the embodiment of the present invention, an orthographic projection of the common electrode and an adjacent one of the plurality of scan lines on the substrate has a third gap, and the third gap is located within the orthographic projection of the light shielding pattern layer on the substrate.

[0010] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further comprises a reflective layer and a capacitor electrode. The reflective layer covers the pixel electrode and is electrically connected to the pixel electrode. The reflective layer defines a reflective region of the pixel structure, and a portion of the pixel electrode not covered by the reflective layer defines a penetration region of the pixel structure. The capacitor electrode is disposed in the reflective region and overlaps the common electrode. The pixel electrode is electrically connected to the first drain of the display transistor via the capacitor electrode.

[0011] In the display panel according to the embodiment of the present invention, the orthographic projection of the light shielding pattern layer on the substrate surrounds the orthographic projection of the common electrode on the substrate.

[0012] In the display panel according to the embodiment of the present invention, the light shielding pattern layer has a floating potential.

[0013] In a display panel according to an embodiment of the present invention, the display panel further includes a gate drive circuit, which is arranged in a peripheral area outside the display area and includes a plurality of shift register circuits. The plurality of shift register circuits are electrically connected to the plurality of scan lines, respectively, and each includes a plurality of transistors. The plurality of transistors each include a second semiconductor pattern, a second gate, a second source and a second drain. The second gate is arranged between the substrate and the second semiconductor pattern. The second source and the second drain contact two different areas of the second semiconductor pattern, respectively. The light shielding pattern layer also has a second opening overlapping the second gate.

[0014] In the display panel according to the embodiment of the present invention, the orthographic projection of the second opening of the light shielding pattern layer on the substrate is located within the orthographic projection of the second gate on the substrate.

[0015] In the display panel according to the embodiment of the present invention, the orthographic projection of the light shielding pattern layer on the substrate surrounds the orthographic projection of the second gate on the substrate.

[0016] In a display panel according to an embodiment of the present invention, the display panel further includes a frame glue pattern and a plurality of signal lines. The frame glue pattern is arranged in the peripheral area. The plurality of signal lines are arranged in the peripheral area and electrically connected to the plurality of shift temporary storage circuits. The light transmittance of the plurality of signal lines, the plurality of shift temporary storage circuits and the portion of the light shielding pattern layer covered by the frame glue pattern is greater than 38%.

[0017] In the display panel according to the embodiment of the present invention, the sealant pattern has an outer edge away from the display area, and the distance between one of the plurality of signal lines closest to the outer edge of the sealant pattern and the outer edge is in a range of 200 micrometers to 250 micrometers.

[0018] In a display panel according to an embodiment of the present invention, each of the plurality of shift register circuits includes an output stage circuit. The output stage circuit is provided with an output transistor of a plurality of transistors. The second gate of the output transistor is electrically connected to the pull-down circuit and the pull-up circuit. The second drain of the output transistor is electrically connected to one of the plurality of scan lines. The second source of the output transistor is electrically connected to the clock signal line. The pull-down circuit and the pull-up circuit are each provided with a portion of the plurality of transistors.

[0019] In the display panel according to the embodiment of the present invention, the light shielding pattern layer includes a plurality of light shielding patterns separated from each other, and each of the plurality of light shielding patterns has a plurality of first openings overlapping with a plurality of first gates of a plurality of display transistors.

[0020] In the display panel according to the embodiment of the present invention, each of the plurality of pixel structures comprises a common electrode disposed on the substrate and overlapping the pixel electrode, wherein the common electrode has an opening overlapping the first semiconductor pattern.

[0021] In the display panel according to the embodiment of the present invention, the pixel electrode is located between the common electrode and the substrate. The common electrode is provided with a plurality of micro gaps, and the plurality of micro gaps overlap the pixel electrode.

[0022] In the display panel according to the embodiment of the present invention, the common electrode also overlaps one of the plurality of data lines and one of the plurality of scan lines.

[0023] In the display panel according to the embodiment of the present invention, the light shielding pattern layer is a metal layer or a black resin material layer.

[0024] Based on the above, in a display panel of an embodiment of the present invention, since a light shielding pattern layer is provided between the first gate of the display transistor of the pixel structure and the substrate, it is possible to prevent light from entering through the periphery of the first gate or irradiating the first semiconductor pattern after multiple reflections through the first gate, the first source and the first drain, thereby preventing leakage of the display transistor, thereby ensuring the operating electrical properties of the display panel under irradiation from light sources in different directions. In addition, by providing an opening in the light shielding pattern layer that overlaps the first gate, the flatness of the film layer around the display transistor can be further improved, which helps to improve the yield of the subsequent film forming process. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a front view schematic diagram of a display panel according to a first embodiment of the present invention;

[0026] Figure 2A yes Figure 1 An enlarged front view of a local area of ​​a display panel;

[0027] Figure 2B yes Figure 1 An enlarged rear view of a local area of ​​a display panel;

[0028] Figure 3 yes Figure 2A A schematic cross-sectional view of a display panel;

[0029] Figure 4 is a front view schematic diagram of a display panel according to a second embodiment of the present invention;

[0030] Figure 5A yes Figure 4 An enlarged front view of a local area of ​​a display panel;

[0031] Figure 5B yes Figure 4 An enlarged rear view of a local area of ​​a display panel;

[0032] FIG. 6A to FIG. 6C yes Figure 5A An enlarged front view of a portion of a film layer of a display panel;

[0033] Figure 7 yes Figure 5A A schematic cross-sectional view of a display panel;

[0034] Fig. 8A is a front view schematic diagram of a display panel according to a third embodiment of the present invention;

[0035] Figure 8B yes Fig. 8A A rear view schematic diagram of a display panel;

[0036] Fig. 9 yes Fig. 8A A schematic cross-sectional view of a display panel.

[0037] Description of Reference Numerals

[0038] 10, 10A, 10B: display panel;

[0039] 110, 130: insulation layer;

[0040] 120: gate insulating layer;

[0041] 140: coating layer;

[0042] 140op, OP1, OP2, OP1-B: Open;

[0043] ABL: ambient light;

[0044] C: capacitor;

[0045] CE, CE-B: common electrode;

[0046] CEop: opening;

[0047] CKL: clock signal line;

[0048] CPE: Capacitive electrode;

[0049] d1: distance;

[0050] DA: display area;

[0051] DCC, DCa, DCb: pull-down circuit;

[0052] DE1, DE2: drain;

[0053] DL: data line;

[0054] DT, DT-B: display transistor;

[0055] G1, G2, G3: gap;

[0056] GDC: gate drive circuit;

[0057] GE1, GE2: gate;

[0058] GL: scan line;

[0059] GP: frame glue pattern;

[0060] GPe: outer edge;

[0061] LCL: Liquid crystal layer;

[0062] OLA: Overlapping Area;

[0063] PA: peripheral area;

[0064] PCC: pull-up circuit;

[0065] PE, PE-B: pixel electrodes;

[0066] PUC: output stage circuit;

[0067] PU-T1: output transistor;

[0068] PWL1, PWL2: power lines;

[0069] PX, PX-B: pixel structure;

[0070] PXA: pixel area;

[0071] RA: reflex area;

[0072] RFL: reflective layer;

[0073] SE1, SE2: source;

[0074] SC1, SC2: semiconductor patterns;

[0075] SLT: Micro-slit;

[0076] SPL, SPL-A, SPL-B: light-shielding pattern layer;

[0077] SP: shading pattern;

[0078] SRC: shift register circuit;

[0079] SUB1, SUB2: substrate;

[0080] T, T2~T13: transistors;

[0081] TA: penetration area;

[0082] TH: contact hole;

[0083] X, Y, Z: direction;

[0084] A-A', B-B', C-C': section lines. DETAILED DESCRIPTION

[0085] The term "coupled (or connected)" used throughout the specification of this application may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned throughout the specification of this application are used to name components (element) or to distinguish different embodiments or ranges, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components.

[0086] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0087] Figure 1 is a front view schematic diagram of a display panel according to a first embodiment of the present invention. Figure 2A yes Figure 1 An enlarged front view of a local area of ​​a display panel. Figure 2B yes Figure 1 An enlarged rear view of a local area of ​​a display panel. Figure 3 yes Figure 2A A schematic cross-sectional view of a display panel. Figure 3 Corresponds to Figure 2A At the section line A-A'.

[0088] Please refer to Figure 1 and Figure 2AThe display panel 10 includes a substrate SUB1, a plurality of scan lines GL, a plurality of data lines DL, and a plurality of pixel structures PX. The substrate SUB1 is provided with a display area DA and a peripheral area PA outside the display area DA. The plurality of scan lines GL and the plurality of data lines DL are disposed on the substrate SUB1, intersect with each other and define a plurality of pixel areas PXA. For example, in the present embodiment, the plurality of data lines DL may be arranged along direction X and extend in direction Y, and the plurality of scan lines GL may be arranged along direction Y and extend in direction X.

[0089] A plurality of pixel structures PX are disposed in the display area DA and are respectively located in a plurality of pixel areas PXA. Each of the pixel structures PX includes a display transistor DT and a pixel electrode PE electrically connected to each other. The display transistor DT includes a first semiconductor pattern SC1, a first gate GE1, a first source SE1 and a first drain DE1. The first gate GE1 is disposed between the substrate SUB1 and the first semiconductor pattern SC1 and is electrically connected to one of the plurality of scan lines GL. The first source SE1 is electrically connected to one of the plurality of data lines DL. The first drain DE1 is electrically connected to the pixel electrode PE.

[0090] Please refer to Figure 2A and Figure 3 , the steps of forming the display transistor DT include, for example: sequentially forming a first gate GE1, a gate insulating layer 120, a first semiconductor pattern SC1, a first source SE1 and a first drain DE1 on the substrate SUB1. The first semiconductor pattern SC1 overlaps the first gate GE1 along the direction Z. The first source SE1 and the first drain DE1 are electrically connected to two different regions (e.g., a source region and a drain region) of the first semiconductor pattern SC1, respectively. In the present embodiment, the first gate GE1 of the display transistor DT may be a portion extending from the scan line GL, and the first source SE1 may be a portion extending from the data line DL, but not limited thereto. It should be noted that, if not specifically mentioned below, the overlapping of one component on another component refers to the overlapping relationship of the two components along the direction Z, and no further description will be given.

[0091] In some embodiments, an ohmic contact layer (not shown) is further provided between the first source electrode SE1 and the first semiconductor pattern SC1 and between the first drain electrode DE1 and the first semiconductor pattern SC1, and the material of the ohmic contact layer may be, for example, a doped amorphous silicon layer, but is not limited thereto. In the present embodiment, the first gate electrode GE1 may be optionally disposed below the first semiconductor pattern SC1 to form a bottom-gate type display transistor DT. The gate insulating layer 120 sandwiched between the first gate electrode GE1 and the first semiconductor pattern SC1 may be made of silicon oxide, silicon nitride or other suitable dielectric materials. However, the present invention is not limited thereto. In other embodiments, the first gate electrode GE1 may also be disposed above the first semiconductor pattern SC1 to form a top-gate type display transistor.

[0092] In this embodiment, the display transistor DT is, for example, an amorphous silicon thin film transistor (a-Si TFT), but is not limited thereto. In other embodiments, the display transistor DT may also be a polycrystalline silicon thin film transistor (poly-Si TFT) or a metal oxide semiconductor thin film transistor (metal oxide semiconductor TFT).

[0093] In the present embodiment, the pixel structure PX may further include a common electrode CE and a capacitor electrode CPE. The common electrode CE is disposed between the capacitor electrode CPE and the substrate SUB1 and overlaps the pixel electrode PE. The capacitor electrode CPE is disposed between the pixel electrode PE and the common electrode CE and overlaps the common electrode CE. In the present embodiment, the common electrode CE and the first gate electrode GE1 may belong to the same film layer. The capacitor electrode CPE, the first source electrode SE1 and the first drain electrode DE1 may belong to the same film layer. That is, a gate insulating layer 120 is disposed between the common electrode CE and the capacitor electrode CPE and they are electrically insulated from each other. From another point of view, the common electrode CE and the capacitor electrode CPE that overlap each other may constitute a storage capacitor of the pixel structure PX.

[0094] On the other hand, the display transistor DT may be covered with an insulating layer 130 and a cover layer 140 in sequence. The pixel electrode PE is disposed on the cover layer 140, and is electrically connected to the capacitor electrode CPE via the opening 140op of the cover layer 140 and the contact hole TH of the insulating layer 130. In this embodiment, the capacitor electrode CPE may extend from the first drain electrode DE1 of the display transistor DT. In other words, the pixel electrode PE may be electrically connected to the first drain electrode DE1 of the display transistor DT via the capacitor electrode CPE.

[0095] The insulating layer 130 is, for example, a passivation layer, and its material includes, for example, silicon nitride, silicon oxide, silicon carbide, or aluminum oxide, but is not limited thereto. The material of the covering layer 140 may include an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), an organic material (for example, polyester, polyolefin, polyacryl, polycarbonate, polyalkylene oxide, polyphenylene, polyether, polyketone, polyol, polyaldehyde, or other suitable materials, or a combination thereof), or other suitable materials, or a combination thereof.

[0096] Furthermore, in the present embodiment, the display panel 10 further includes a light shielding pattern layer SPL, which is disposed between the first gate GE1 and the substrate SUB1 and has a first opening OP1 overlapping the first gate GE1. The light shielding pattern layer SPL and the first gate GE1 are electrically insulated from each other by the provision of an insulating layer 110. The insulating layer 110 is, for example, a passivation layer, and its material includes, for example, silicon nitride, silicon oxide, silicon carbide or aluminum oxide, but is not limited thereto.

[0097] It is particularly noted that the orthographic projections of the common electrode CE and the first gate GE1 on the substrate SUB1 have a first gap G1, and the first gap G1 is located within the orthographic projection of the light shielding pattern layer SPL on the substrate SUB1. That is, the light shielding pattern layer SPL can completely shield the first gap G1 between the common electrode CE and the first gate GE1. In this embodiment, the orthographic projection of the first opening OP1 of the light shielding pattern layer SPL on the substrate SUB1 is located within the orthographic projection of the first gate GE1 on the substrate SUB1.

[0098] For example, the light shielding pattern layer SPL may further overlap a portion of the first gate GE1 and a portion of the common electrode CE. That is, in this embodiment, the orthographic projection area of ​​the first opening OP1 on the substrate SUB1 may be smaller than the orthographic projection area of ​​the first gate GE1 on the substrate SUB1, but is not limited thereto. In other embodiments, the orthographic projection contour of the first opening OP1 on the substrate SUB1 may be aligned with the orthographic projection contour of the first gate GE1 on the substrate SUB1.

[0099] In this embodiment, the orthographic projection of the light shielding pattern layer SPL on the substrate SUB1 may surround the orthographic projection of the first gate GE1 on the substrate SUB2 (eg, Figure 2BAs shown). Accordingly, it is possible to effectively prevent light (such as ambient light ABL) incident from one side of the substrate SUB1 from irradiating the first semiconductor pattern SC1 via the edge of the first gate GE1, via multiple reflections between the first gate GE1 and the first source SE1, or via multiple reflections between the first gate GE1 and the first drain DE1, thereby ensuring that the operating electrical properties of the display panel 10 will not be affected by the light irradiation.

[0100] On the other hand, the orthographic projection of the common electrode CE and the adjacent data line DL on the substrate SUB1 has a second gap G2, and the second gap G2 is located within the orthographic projection of the light-shielding pattern layer SPL on the substrate SUB1. Similarly, the orthographic projection of the common electrode CE and the adjacent scan line GL on the substrate SUB1 has a third gap G3, and the third gap G3 is located within the orthographic projection of the light-shielding pattern layer SPL on the substrate SUB1. That is, the light-shielding pattern layer SPL can completely shield the second gap G2 between the common electrode CE and the adjacent data line DL and the third gap G3 between the common electrode CE and the adjacent scan line GL.

[0101] From another perspective, the orthographic projection of the light shielding pattern layer SPL on the substrate SUB1 may surround the orthographic projection of the common electrode CE on the substrate SUB1 (eg Figure 2B As shown). Accordingly, the height difference of the metal stack structure in the pixel area PXA can be reduced. In other words, the flatness of the film stack structure in the pixel area PXA can be improved, thereby improving the yield and film quality of the subsequent film forming process. For example, in this embodiment, the pixel structure PX may further include a reflective layer RFL covering the pixel electrode PE. By setting the light shielding pattern layer SPL, the reflective layer RFL formed in the subsequent process may have a better surface flatness.

[0102] In the present embodiment, the reflective layer RFL may be electrically connected to the pixel electrode PE. That is, the reflective layer RFL of the present embodiment may be a reflective electrode. The pixel electrode PE may be a light-transmitting electrode. The material of the reflective electrode may include, for example, a metal (e.g., silver, aluminum, platinum), an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or other suitable materials, or a stacked layer of a metal material and other conductive materials. The material of the light-transmitting electrode may include, for example, a metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable materials, or a stacked layer of at least two of the above.

[0103] In this embodiment, the reflective layer RFL can define the reflective area RA of the pixel structure PX, and the portion of the pixel electrode PE not covered by the reflective layer RFL can define the transmissive area TA of the pixel structure PX. It is particularly noted that the pixel electrode PE not only overlaps the reflective layer RFL, but also further overlaps the transmissive area TA.

[0104] On the other hand, the display panel 10 may further include a liquid crystal layer LCL and another substrate SUB2. The liquid crystal layer LCL is disposed between the substrate SUB1 and the substrate SUB2. More specifically, the display panel 10 of this embodiment may be a micro-transmissive liquid crystal display panel.

[0105] Further, in this embodiment, the light shielding pattern layer SPL is, for example, a metal layer, and its material includes, for example, molybdenum, aluminum, copper, nickel, chromium, their alloys, or their stacked structures. For example, in this embodiment, the light shielding pattern layer SPL may have a floating potential, but is not limited thereto.

[0106] Other embodiments will be listed below to explain the present disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the aforementioned embodiments and will not be repeated below.

[0107] Figure 4 is a front view schematic diagram of a display panel according to a second embodiment of the present invention. Figure 5A yes Figure 4 An enlarged front view of a local area of ​​a display panel. Figure 5B yes Figure 4 An enlarged rear view of a local area of ​​a display panel. FIG. 6A to FIG. 6C yes Figure 5A An enlarged front view of a portion of the film layer of a display panel. Figure 7 yes Figure 5A A schematic cross-sectional view of a display panel. Figure 7 Corresponds to Figure 5A At the section line B-B'.

[0108] Please refer to Figure 4 and Figure 5A , different from Figure 1 The display panel 10 of the present embodiment is provided with a light shielding pattern layer SPL only in the display area DA, while the display panel 10A of the present embodiment is provided with a light shielding pattern layer SPL-A in both the display area DA and the peripheral area PA. Figure 2A For the detailed description of the light shielding pattern layer SPL of the display panel 10, please refer to the relevant paragraphs of the aforementioned embodiment, which will not be repeated here.

[0109] For example, in the present embodiment, a gate driving circuit GDC may be provided in the peripheral area PA, and the gate driving circuit GDC may include a plurality of shift register circuits SRC and a plurality of signal lines coupled in series. The shift register circuits SRC are electrically connected to a plurality of scan lines GL, respectively, and each includes a plurality of transistors T. The plurality of signal lines may include, for example, a plurality of clock signal lines CKL and a plurality of power lines (e.g., a power line PWL1 and a power line PWL2), but are not limited thereto.

[0110] The transistor T includes a second semiconductor pattern SC2, a second gate GE2, a second source SE2 and a second drain DE2. The second gate GE2 is disposed between the substrate SUB1 and the second semiconductor pattern SC2. The second source SE2 and the second drain DE2 contact two different regions (eg, source region and drain region) of the second semiconductor pattern SC2 respectively.

[0111] In this embodiment, the shift register circuit SRC includes an output stage circuit PUC, a pull-up circuit PCC and a pull-down circuit DCC. The output stage circuit PUC is provided with an output transistor PU-T1 among the aforementioned plurality of transistors T and a capacitor C, and the pull-down circuit DCC and the pull-up circuit PCC are each provided with a portion of the aforementioned plurality of transistors T. The output stage circuit PUC is electrically connected to a clock signal line CKL. The pull-down circuit DCC is electrically connected to a power line PWL1 and a power line PWL2.

[0112] For example, the pull-up circuit PCC is adapted to pull up the first drive signal according to a scan direction signal (e.g., a first scan direction signal or a second scan direction signal). The pull-down circuit DCC is adapted to pull down the first drive signal and output the second drive signal according to a first control signal from the power line PWL1 and a second control signal from the power line PWL2. The output stage circuit PUC is adapted to generate a gate drive signal according to the corresponding clock signal, the first drive signal, and the second drive signal.

[0113] In this embodiment, the number of pull-down circuits DCC of the shift register circuit SRC is illustrated by taking two (respectively, a pull-down circuit DCa and a pull-down circuit DCb) as an example, which does not mean that the present invention is limited thereto. In other embodiments, the number of pull-down circuits of the shift register circuit may also be one. On the other hand, the present invention does not limit the number of transistors T of each shift register circuit SRC, and the number of these components can be adjusted according to the actual circuit design of the product.

[0114] Please refer to Figure 5A , Fig. 6A and Figure 6BIn detail, the pull-up circuit PCC includes a transistor T2 and a transistor T3. The second gate GE2 of the transistor T2 receives a gate drive signal output from the previous stage shift register circuit SRC, the second source SE2 of the transistor T2 receives a first scanning direction signal, and the second drain DE2 of the transistor T2 is connected to the second gate GE2 of the output transistor PU-T1, the output stage circuit PUC and the pull-down circuit DCC. The second gate GE2 of the transistor T3 receives a gate drive signal output from the next stage shift register circuit SRC, and the second source SE2 of the transistor T3 receives a second scanning direction signal. In this embodiment, the first scanning direction signal is used to indicate that the scanning direction of the gate drive circuit GDC is a first direction (for example, from Figure 4 The second scanning direction signal is used to indicate that the scanning direction of the gate driving circuit GDC is a second direction (for example, from the top to the bottom). Figure 4 Scan from bottom to top).

[0115] The output stage circuit PUC includes an output transistor PU-T1 and a capacitor C. The second gate GE2 and the second drain DE2 of the output transistor PU-T1 are electrically connected to the first end and the second end of the capacitor C, respectively. The second source SE2 of the output transistor PU-T1 receives a clock signal from the clock signal line CKL, and the second drain DE2 of the output transistor PU-T1 is connected to the second end of the capacitor and outputs a gate drive signal.

[0116] Please refer to Figure 4 , Figure 5A , Fig. 6A and Figure 6B , the pull-down circuit DCa includes a transistor T4, a transistor T6, a transistor T8, a transistor T10, and a transistor T12. The second source SE2 of the transistor T4 is electrically connected to the second drain DE2 of the output transistor PU-T1. The second gate GE2 of the transistor T6 and the second source SE2 of the transistor T8 are electrically connected to the second gate GE2 of the output transistor PU-T1. The second source SE2 of the transistor T6, the second gate GE2 of the transistor T4, the second gate GE2 of the transistor T8, the second source SE2 of the transistor T12, and the second source SE2 of the transistor T10 are electrically connected to each other. The second drain DE2 of the transistor T4, the transistor T6, the transistor T8, and the transistor T12 are respectively coupled to a reference potential (e.g., VSS). The second gate GE2 and the second drain DE2 of the transistor T10 are electrically connected to each other and receive a second control signal from the power line PWL2. The second gate GE2 of the transistor T12 receives a first control signal from the power line PWL1.

[0117] Similarly, the pull-down circuit DCb includes a transistor T5, a transistor T7, a transistor T9, a transistor T11, and a transistor T13. The second source SE2 of the transistor T5 is electrically connected to the second drain DE2 of the output transistor PU-T1. The second gate GE2 of the transistor T7 and the second source SE2 of the transistor T9 are electrically connected to the second gate GE2 of the output transistor PU-T1. The second source SE2 of the transistor T7, the second gate GE2 of the transistor T5, the second gate GE2 of the transistor T9, the second source SE2 of the transistor T13, and the second source SE2 of the transistor T11 are electrically connected to each other. The second drain DE2 of each of the transistor T5, the transistor T7, the transistor T9, and the transistor T13 is coupled to a reference potential (e.g., VSS). The second gate GE2 and the second drain DE2 of the transistor T11 are electrically connected to each other and receive a first control signal from the power line PWL1. The second gate GE2 of the transistor T13 receives a second control signal from the power line PWL2.

[0118] When the gate driving circuit GDC receives a scanning start signal, a plurality of shift register circuits SRC coupled in series sequentially output gate driving signals to a plurality of scanning lines GL in the display area DA to control a plurality of pixel structures PX respectively and transmit the signals to the display medium layer (e.g. Figure 3 After the last-stage shift register circuit SRC outputs a gate drive signal, the gate drive circuit GDC receives a scan termination signal, and the image update of one frame cycle is completed at this time.

[0119] Please refer to Figure 5A , Figure 5B and Figure 6C , further, the light shielding pattern layer SPL-A of the display panel 10A may be arranged around the plurality of second gates GE2 of the aforementioned plurality of transistors T. More specifically, the light shielding pattern layer SPL-A has a plurality of second openings OP2 overlapping the plurality of second gates GE2 of the transistors T. In the present embodiment, the orthographic projection of the second openings OP2 of the light shielding pattern layer SPL-A on the substrate SUB1 is located within the orthographic projection of the second gate GE2 on the substrate SUB1.

[0120] For example, the light shielding pattern layer SPL-A may further overlap a portion of the second gate GE2. That is, in this embodiment, the orthographic projection area of ​​the second opening OP2 on the substrate SUB1 may be smaller than the orthographic projection area of ​​the second gate GE2 on the substrate SUB1, but is not limited thereto. In other embodiments, the orthographic projection contour of the second opening OP2 on the substrate SUB1 may be aligned with the orthographic projection contour of the second gate GE2 on the substrate SUB1. In addition, there is a gap (such as 0.04mm) between the portions of the second gates GE2 of the plurality of transistors T of the shift register circuit SRC. Figure 6BAs shown), most of the gap can be blocked by the light shielding pattern layer SPL-A.

[0121] Please also refer to Figure 7 By means of the aforementioned configuration of the light-shielding pattern layer SPL-A, it is possible to effectively prevent light (such as ambient light ABL) incident from one side of the substrate SUB1 from irradiating the second semiconductor pattern SC2 via the edge of the second gate GE2, via multiple reflections between the second gate GE2 and the second source SE2, or via multiple reflections between the second gate GE2 and the second drain DE2, thereby ensuring that the operating electrical properties of the display panel 10A will not be affected by light exposure.

[0122] The light-shielding pattern layer SPL-A and the second gate GE2 are electrically insulated from each other due to the presence of an insulating layer 110. In the present embodiment, the light-shielding pattern layer SPL-A is, for example, a metal layer, and its material includes, for example, molybdenum, aluminum, copper, nickel, chromium, the alloys thereof, or the stacked structure thereof. For example, in the present embodiment, the light-shielding pattern layer SPL may have a floating potential, but is not limited thereto. However, the present invention is not limited thereto. In other embodiments, the light-shielding pattern layer may also be a black resin material layer. That is, the light-shielding pattern layer may not be conductive.

[0123] Please refer to Figure 5A In the present embodiment, in order to join the substrate SUB1 and the substrate SUB2 to form a cavity filled with the liquid crystal layer LCL, the display panel 10A further includes a frame glue pattern GP. The frame glue pattern GP is disposed in the peripheral area PA. Although not shown in the figure, the frame glue pattern GP is substantially disposed around the display area DA. It is particularly noted that the extension path of the frame glue pattern GP will overlap with a portion of the gate drive circuit GDC. More specifically, the frame glue pattern GP will cover a plurality of signal lines, a portion of the shift register circuit SRC and a portion of the shading pattern layer SPL-A (such as FIG. 6A to FIG. 6C In this embodiment, the frame glue pattern GP has an outer edge GPe away from the display area, and a distance d1 between one of the plurality of signal lines closest to the outer edge GPe of the frame glue pattern GP (such as the power line PWL2) and the outer edge GPe is in a range of 200 microns to 250 microns.

[0124] For example, in the present embodiment, the material of the frame glue pattern GP is, for example, a photocurable glue material or a photosensitive glue material. Since the substrate SUB2 of the display panel 10A is provided with a light shielding layer (not shown) in the peripheral area PA, during the curing process of the frame glue pattern GP, ​​light (e.g., ultraviolet light) enters the display panel 10A from the substrate SUB1. In order to ensure that the frame glue pattern GP can achieve a higher light curing rate during the manufacturing process, the light transmittance of the portion of the light shielding pattern layer SPL-A and the shift register circuit SRC covered by the frame glue pattern GP is greater than 38%. That is, in the overlapping area OLA of the frame glue pattern GP, ​​the light shielding pattern layer SPL-A and the shift register circuit SRC, the percentage value of the orthographic projection area of ​​the light shielding pattern layer SPLA-A and the shift register circuit SRC located in the overlapping area OLA on the substrate SUB1 to the overlapping area area is less than 62%.

[0125] Fig. 8A is a front view schematic diagram of a display panel according to a third embodiment of the present invention. Figure 8B yes Fig. 8A Schematic diagram of a rear view of a display panel. Fig. 9 yes Fig. 8A A schematic cross-sectional view of a display panel. Fig. 9 Corresponds to Fig. 8A At the section line C-C'.

[0126] Please refer to Fig. 8A , Figure 8B and Fig. 9 The display panel 10B of this embodiment is Figure 2A The main differences of the display panel 10 are: the different configurations of the shading pattern layer and the different pixel structures. For example, in the present embodiment, the common electrode CE-B of the pixel structure PX-B is optionally arranged above the pixel electrode PE-B, that is, the pixel electrode PE-B is located between the common electrode CE-B and the substrate SUB1. More specifically, the pixel electrode PE-B is arranged on the gate insulating layer 120 and is electrically connected to the first drain DE1 of the display transistor DT-B. However, the present invention is not limited to this. In other embodiments, the common electrode may also be arranged on the gate insulating layer 120 and is located between the pixel electrode and the substrate SUB1. The pixel electrode passes through the insulating layer 130 to electrically connect the first drain DE1 of the display transistor DT-B.

[0127] It is particularly noted that, in the present embodiment, the common electrode CE-B may have a plurality of micro-slits SLT overlapping the pixel electrode PE-B and an opening CEop overlapping the first semiconductor pattern SC1 of the display transistor DT-B. More specifically, the pixel structure PX-B of the display panel 10B of the present embodiment drives the liquid crystal layer LCL in a fringe-field switching (FFS) mode, but is not limited thereto. In other embodiments, the pixel structure of the display panel may also drive the liquid crystal layer LCL in an in-plane switching (IPS) mode. On the other hand, in the present embodiment, a plurality of common electrodes CE-B of a plurality of pixel structures PX-B are connected to each other. More specifically, the common electrode CE-B may also overlap one of the plurality of scan lines GL and one of the plurality of data lines DL.

[0128] In the present embodiment, the light shielding pattern layer SPL-B may include a plurality of light shielding patterns SP separated from each other. These light shielding patterns SP respectively have a plurality of first openings OP1-B overlapping a plurality of first gates GE1 of a plurality of display transistors DT-B. For example, the light shielding pattern layer SPL-B may further overlap a portion of the first gate GE1. That is, in the present embodiment, the orthographic projection area of ​​the first opening OP1-B on the substrate SUB1 may be smaller than the orthographic projection area of ​​the first gate GE1 on the substrate SUB1, but is not limited thereto. In other embodiments, the orthographic projection contour of the first opening OP1 on the substrate SUB1 may be aligned with the orthographic projection contour of the first gate GE1 on the substrate SUB1.

[0129] From another perspective, the orthographic projection of the light shielding pattern layer SPL-B on the substrate SUB1 may surround the orthographic projection of the first gate electrode GE1 on the substrate SUB2 (eg, Figure 8B As shown in FIG. 1 ). Accordingly, it is possible to effectively prevent light incident from one side of the substrate SUB1 (e.g., ambient light ABL) from irradiating the first semiconductor pattern SC1 via the edge of the first gate GE1, via multiple reflections between the first gate GE1 and the first source SE1, or via multiple reflections between the first gate GE1 and the first drain DE1. That is, the light shielding pattern SP can shield light incident from the substrate SUB1 (e.g., ambient light ABL). Fig. 9 As shown), it is ensured that the operating electrical properties of the display panel 10B will not be affected by light exposure.

[0130] In summary, in a display panel of an embodiment of the present invention, since a light shielding pattern layer is provided between the first gate of the display transistor of the pixel structure and the substrate, it is possible to prevent light from entering through the periphery of the first gate or irradiating the first semiconductor pattern after multiple reflections through the first gate, the first source and the first drain, thereby preventing leakage of the display transistor, thereby ensuring the operating electrical properties of the display panel under irradiation from light sources in different directions. In addition, by providing an opening in the light shielding pattern layer that overlaps the first gate, the flatness of the film layer around the display transistor can be further improved, which helps to improve the yield of the subsequent film forming process.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A substrate having a display area; A plurality of scan lines and a plurality of data lines are arranged on the substrate, and the plurality of scan lines intersect the plurality of data lines; A plurality of pixel structures are arranged in the display area, and each of the pixel structures comprises: a display transistor, comprising a first semiconductor pattern, a first gate, a first source and a first drain, wherein the first gate is disposed between the substrate and the first semiconductor pattern and is electrically connected to one of the plurality of scan lines, and the first source is electrically connected to one of the plurality of data lines; and a pixel electrode electrically connected to the first drain of the display transistor; and The light shielding pattern layer is disposed between the first grid and the substrate and has a first opening overlapping the first grid.

2. The display panel according to claim 1, characterized in that: An orthographic projection of the first opening of the light-shielding pattern layer on the substrate is located within an orthographic projection of the first gate on the substrate.

3. The display panel according to claim 1, characterized in that: The orthographic projection of the light-shielding pattern layer on the substrate surrounds the orthographic projection of the first gate on the substrate.

4. The display panel according to claim 1, characterized in that: Each of the plurality of pixel structures further comprises: A common electrode is arranged between the pixel electrode and the substrate and overlaps the pixel electrode, wherein the common electrode and the first gate have a first gap in their orthographic projection on the substrate, and the first gap is located within the orthographic projection of the shading pattern layer on the substrate.

5. The display panel according to claim 4, characterized in that: An orthographic projection of the common electrode and an adjacent one of the plurality of data lines on the substrate has a second gap, and the second gap is located within the orthographic projection of the light shielding pattern layer on the substrate.

6. The display panel according to claim 4, characterized in that: An orthographic projection of the common electrode and an adjacent one of the plurality of scanning lines on the substrate has a third gap, and the third gap is located within the orthographic projection of the light shielding pattern layer on the substrate.

7. The display panel according to claim 4, characterized in that: Each of the plurality of pixel structures further comprises: a reflective layer covering the pixel electrode and electrically connected to the pixel electrode, wherein the reflective layer defines a reflective area of ​​the pixel structure, and a portion of the pixel electrode not covered by the reflective layer defines a transmissive area of ​​the pixel structure; and The capacitor electrode is disposed in the reflective region and overlaps the common electrode, wherein the pixel electrode is electrically connected to the first drain of the display transistor via the capacitor electrode.

8. The display panel according to claim 4, characterized in that: The orthographic projection of the light-shielding pattern layer on the substrate surrounds the orthographic projection of the common electrode on the substrate.

9. The display panel according to claim 1, characterized in that: The light shielding pattern layer has a floating potential.

10. The display panel according to claim 1, characterized in that: Also includes: The gate driving circuit is arranged in a peripheral area outside the display area and includes a plurality of shift register circuits, the plurality of shift register circuits are electrically connected to the plurality of scanning lines respectively, and each includes a plurality of transistors, the plurality of transistors each include a second semiconductor pattern, a second gate, a second source and a second drain, the second gate is arranged between the substrate and the second semiconductor pattern, the second source and the second drain respectively contact two different areas of the second semiconductor pattern, wherein the shading pattern layer also has a second opening overlapping the second gate.

11. The display panel according to claim 10, characterized in that: An orthographic projection of the second opening of the light-shielding pattern layer on the substrate is located within an orthographic projection of the second gate on the substrate.

12. The display panel according to claim 10, characterized in that: The orthographic projection of the light-shielding pattern layer on the substrate surrounds the orthographic projection of the second gate on the substrate.

13. The display panel according to claim 10, characterized in that: Also includes: A sealant pattern is arranged in the peripheral area; as well as A plurality of signal lines are arranged in the peripheral area and electrically connected to the plurality of shift register circuits, wherein the light transmittance of the plurality of signal lines, the plurality of shift register circuits and the portion of the light shielding pattern layer covered by the frame glue pattern is greater than 38%.

14. The display panel according to claim 13, characterized in that: The sealant pattern has an outer edge away from the display area, and a distance between one of the plurality of signal lines closest to the outer edge of the sealant pattern and the outer edge is in a range of 200 micrometers to 250 micrometers.

15. The display panel according to claim 10, characterized in that: The multiple shift register circuits each include an output stage circuit, the output stage circuit is provided with an output transistor of the multiple transistors, the second gate of the output transistor is electrically connected to a pull-down circuit and a pull-up circuit, the second drain of the output transistor is electrically connected to one of the multiple scan lines, and the second source of the output transistor is electrically connected to a clock signal line, wherein the pull-down circuit and the pull-up circuit are each provided with a portion of the multiple transistors.

16. The display panel according to claim 1, characterized in that: The light shielding pattern layer includes a plurality of light shielding patterns separated from each other, and each of the plurality of light shielding patterns has a plurality of first openings overlapping with a plurality of first gates of a plurality of display transistors.

17. The display panel according to claim 1, characterized in that: Each of the plurality of pixel structures comprises: The common electrode is disposed on the substrate and overlaps the pixel electrode. The common electrode has an opening overlapping the first semiconductor pattern.

18. The display panel according to claim 17, characterized in that: The pixel electrode is located between the common electrode and the substrate. The common electrode is provided with a plurality of micro gaps, and the plurality of micro gaps overlap the pixel electrode.

19. The display panel according to claim 18, characterized in that: The common electrode also overlaps one of the plurality of data lines and one of the plurality of scan lines.

20. The display panel according to claim 1, characterized in that: The light-shielding pattern layer is a metal layer or a black resin material layer.

Images