Slope-controllable current driving circuit

Abstract

The invention discloses a current driving circuit with a controllable slope. The current driving circuit with the controllable slope comprises a current-voltage conversion circuit, a voltage-current conversion circuit and a current subtraction circuit, the output end of the current-voltage conversion circuit is connected with the input end of the voltage-current conversion circuit, and the output end of the voltage-current conversion circuit is connected with the input end of the current subtraction circuit. The method comprises the following steps: firstly, converting an input current into a voltage square wave signal of which the slope is in direct proportion to the input current, then converting the voltage square wave signal into a current square wave signal, subtracting the current square wave signal from a direct current, and outputting a current driving signal of which the current minimum value is zero and the slope is in direct proportion to the input current; the slope of the current driving signal can be controlled by controlling the input current. The invention can be used for the CAN bus transceiver, provides driving current for the CAN bus transceiver, and controls the slope of the bus so as to reduce electromagnetic radiation during signal transmission.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a current driving circuit with controllable slope, which can be used in a CAN bus transceiver to provide driving current for the CAN bus transceiver. Background Art

[0002] Controller Area Network (CAN) is a low-cost serial communication network used in automotive, industrial automation and other fields. In system applications, when the CAN bus transmits high-level signals, the rapid change of the signal will generate large electromagnetic radiation, which will affect the electromagnetic compatibility of the system. Reducing the slope of the CAN bus can reduce electromagnetic interference in signal transmission. The traditional CAN bus driver provides a fixed current to the bus through switching actions. The rising and falling slopes of the driving current are large and fixed and cannot be controlled, so it is impossible to reduce the slope during transmission to reduce interference. Summary of the invention

[0003] The present invention aims to overcome the problem in the prior art that the bus driving current slope is large and uncontrollable, and to provide a current driving solution with controllable slope to solve the electromagnetic interference generated by the CAN bus during signal transmission.

[0004] In order to achieve the above object, the present invention adopts the following technical solution:

[0005] An embodiment of the present invention provides a current driving circuit with controllable slope, comprising a current-voltage conversion circuit, a voltage-current conversion circuit, and a current subtraction circuit;

[0006] The output end of the current-to-voltage conversion circuit is connected to the input end of the voltage-to-current conversion circuit, and the output end of the voltage-to-current conversion circuit is connected to the input end of the current subtraction circuit;

[0007] The current-to-voltage conversion circuit is used to convert the input current into a voltage square wave signal;

[0008] The voltage-to-current conversion circuit is used to convert the voltage square wave signal output by the current-to-voltage conversion circuit into a current square wave signal;

[0009] The current subtraction circuit is used to obtain an output current by taking the difference between the current square wave signal and a reference current, and the slope of the output current is proportional to the input current.

[0010] Optionally, the current-to-voltage conversion circuit includes a first capacitor, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a first amplitude limiting circuit, a second amplitude limiting circuit, a first PMOS tube and a first NMOS tube;

[0011] The first current mirror generates a charging current of the first capacitor, the second current mirror generates a discharging current of the first capacitor, the third current mirror generates a bias current of the first limiting circuit, the fourth current mirror generates a bias current of the second limiting circuit, the first limiting circuit is used to limit the maximum voltage of the first capacitor, the second limiting circuit is used to limit the minimum voltage of the first capacitor, the first PMOS tube is used to control the first current mirror to charge the first capacitor, and the first NMOS tube is used to control the second current mirror to discharge the first capacitor;

[0012] The input end of the first current mirror is connected to the first input current, the source of the first PMOS tube is connected to the power supply end, the drain of the first PMOS tube is connected to the first current mirror, the input end of the third current mirror is connected to the second input current, the first limiter circuit is respectively connected to the first current mirror, the third current mirror, the second limiter circuit, the first end of the first capacitor and the input end of the voltage-current conversion circuit, the second limiter circuit is respectively connected to the second current mirror and the fourth current mirror, the third current mirror is connected to the fourth current mirror, the drain of the first NMOS tube is connected to the second current mirror, the source of the first NMOS tube and the second end of the first capacitor are both connected to the ground, the input end of the first limiter circuit is connected to the first reference voltage, the input end of the second limiter circuit is connected to the second reference voltage, the gate of the first PMOS tube is connected to the first control signal, the source of the first NMOS tube is connected to the ground, and the gate of the first PMOS tube is connected to the second control signal.

[0013] Optionally, the first control signal and the second control signal have opposite phases.

[0014] Optionally, the first reference voltage is greater than the second reference voltage.

[0015] Optionally, in the current-to-voltage conversion circuit, when the gate of the first PMOS tube is at a low level, the first current mirror charges the first capacitor, and the voltage of the first capacitor rises until it reaches the second reference voltage. The charging current controls the rising slope of the capacitor voltage. When the gate of the first PMOS tube is at a high level, the first current mirror stops charging the first capacitor.

[0016] Optionally, in the current-to-voltage conversion circuit, when the gate of the first NMOS tube is at a high level, the second current mirror discharges the first capacitor, and the voltage of the first capacitor drops until it reaches the second reference voltage. The discharge current controls the slope of the capacitor voltage drop. When the gate of the first NMOS tube is at a low level, the second current mirror stops discharging the first capacitor.

[0017] Optionally, the first current mirror includes a second PMOS tube, a third PMOS tube, and a fourth PMOS tube, the drain of the second PMOS tube is respectively connected to the gate of the second PMOS tube, the gate of the third PMOS tube, and the gate of the fourth PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to the power supply terminal, the source of the third PMOS tube is connected to the drain of the first PMOS tube, and the source of the fourth PMOS tube is connected to the drain of the first PMOS tube;

[0018] The second current mirror includes a second NMOS tube and a third NMOS tube, the drain of the second NMOS tube is respectively connected to the gate of the second NMOS tube, the gate of the third NMOS tube, and the drain of the third PMOS tube, the source of the second NMOS tube is connected to the ground, the source of the third NMOS tube is connected to the drain of the first NMOS tube, and the source of the third NMOS tube is connected to the drain of the first NMOS tube;

[0019] The third current mirror includes a fifth PMOS tube, a sixth PMOS tube, and a seventh PMOS tube, the drain of the fifth PMOS tube is connected to the gate of the fifth PMOS tube, the gate of the sixth PMOS tube, and the gate of the seventh PMOS tube respectively, the source of the fifth PMOS tube, the source of the sixth PMOS tube, and the source of the seventh PMOS tube are all connected to the power supply terminal, and the drain of the fifth PMOS tube is connected to the second input current;

[0020] The fourth current mirror includes a fourth NMOS tube and a fifth NMOS tube, the drain of the fourth NMOS tube is respectively connected to the gate of the fourth NMOS tube, the gate of the fifth NMOS tube, and the drain of the sixth PMOS tube, and the source of the fourth NMOS tube and the source of the fifth NMOS tube are both connected to the ground;

[0021] The first limiter circuit includes a sixth NMOS tube and a seventh NMOS tube, the drain of the sixth NMOS tube is respectively connected to the gate of the sixth NMOS tube, the gate of the seventh NMOS tube, and the drain of the seventh PMOS tube, the source of the sixth NMOS tube is connected to the first reference voltage, and the drain of the seventh NMOS tube is connected to the drain of the fourth PMOS tube;

[0022] The second limiting circuit includes an eighth PMOS tube and a ninth PMOS tube, the drain of the eighth PMOS tube is connected to the gate of the eighth PMOS tube, the gate of the ninth PMOS tube, and the drain of the fifth NMOS tube, the source of the eighth PMOS tube is connected to a second reference voltage, the drain of the ninth PMOS tube is connected to the drain of the third NMOS tube, and the source of the seventh NMOS tube and the source of the ninth PMOS tube are both connected to the first end of the first capacitor.

[0023] Optionally, the voltage-current conversion circuit includes a first operational amplifier, a first resistor, an eighth NMOS tube, a tenth PMOS tube and an eleventh PMOS tube, the non-inverting input terminal of the first operational amplifier is connected to the output terminal of the current-voltage conversion circuit, the inverting input terminal of the first operational amplifier is respectively connected to the first end of the first resistor and the source of the eighth NMOS tube, the output terminal of the first operational amplifier is connected to the gate of the eighth NMOS tube, the second end of the first resistor is connected to the ground, the drain of the eighth NMOS tube is connected to the drain of the tenth PMOS tube, the gate of the tenth PMOS tube and the gate of the eleventh PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are connected to the power supply terminal, and the drain of the eleventh PMOS tube is connected to the current subtraction circuit.

[0024] Optionally, the current subtraction circuit includes a second operational amplifier, a second resistor, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube, the non-inverting input terminal of the second operational amplifier is connected to the second reference voltage, the inverting input terminal of the second operational amplifier is respectively connected to the first end of the second resistor and the source of the ninth NMOS tube, the second end of the second resistor is connected to the ground, the output terminal of the second operational amplifier is connected to the gate of the ninth NMOS tube, the drain of the ninth NMOS tube is respectively connected to the drain of the twelfth PMOS tube, the gate of the twelfth PMOS tube and the gate of the thirteenth PMOS tube, and the The source of the twelfth PMOS tube and the source of the thirteenth PMOS tube are both connected to the power supply end, the drain of the thirteenth PMOS tube is respectively connected to the gate of the tenth NMOS tube, the drain of the tenth NMOS tube, and the gate of the eleventh NMOS tube, the drain of the eleventh NMOS tube is respectively connected to the output end of the voltage-current conversion circuit, the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube, and the gate of the thirteenth NMOS tube, the source of the eleventh NMOS tube, the source of the twelfth NMOS tube, the source of the twelfth NMOS tube, and the source of the thirteenth NMOS tube are all connected to the ground, and the drain of the thirteenth NMOS tube is the current square wave output end of the current driving circuit with controllable slope.

[0025] Optionally, the rising slope and the falling slope of the current square wave are proportional to the input current, and the rising slope and the falling slope of the current square wave can be changed by changing the input current.

[0026] The beneficial effects of the present invention are:

[0027] A current driving circuit with controllable slope of the present invention can change the magnitude of the rising slope and the falling slope of the current square wave of the output current by changing the magnitude of the input current, and provide it to the CAN bus as the driving current, thereby realizing the slope control of the CAN bus and reducing the electromagnetic radiation of the CAN bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the traditional CAN bus and current drive schematic diagram;

[0029] Figure 2 A principle block diagram of a current driving circuit with controllable slope according to the present invention;

[0030] Figure 3 This is a schematic diagram of an embodiment of a current driving circuit with controllable slope according to the present invention;

[0031] Figure 4 is a voltage waveform diagram of the first capacitor in an embodiment of the present invention;

[0032] Figure 5 is a waveform diagram of the output current Io in an embodiment of the present invention;

[0033] Figure 6 is a waveform diagram of the output current Io corresponding to different input current magnitudes in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention and its beneficial effects will be further described in detail below in conjunction with specific implementations and the accompanying drawings, but the specific implementations of the present invention are not limited thereto.

[0035] refer to Figure 2 The principle block diagram of the current driving circuit with controllable slope of the present invention. The embodiment of the present invention provides a current driving circuit with controllable slope, including a current-voltage conversion circuit 100, a voltage-current conversion circuit 200 and a current subtraction circuit 300;

[0036] The output end of the current-to-voltage conversion circuit 100 is connected to the input end of the voltage-to-current conversion circuit 200 , and the output end of the voltage-to-current conversion circuit 200 is connected to the input end of the current subtraction circuit 300 ;

[0037] The current-to-voltage conversion circuit 100 is used to convert the input current into a voltage square wave signal; wherein the voltage square wave signal has a corresponding slope and a limit, and the slope is proportional to the input current;

[0038] The voltage-to-current conversion circuit 200 is used to convert the voltage square wave signal output by the current-to-voltage conversion circuit 100 into a current square wave signal, and the current square wave signal has a corresponding slope;

[0039] The current subtraction circuit 300 is used to obtain an output current by taking the difference between the current square wave signal and the reference current, wherein the slope of the output current is proportional to the input current and the minimum value of the output current is zero.

[0040] refer to Figure 3 In one embodiment, a schematic diagram of an embodiment of a current driving circuit with controllable slope of the present invention further illustrates the technical solution of an embodiment of the present invention.

[0041] In this embodiment, the current-to-voltage conversion circuit 100 includes a first capacitor C1, a first current mirror 101, a second current mirror 102, a third current mirror 103, a fourth current mirror 104, a first limiter circuit 105, a second limiter circuit 106, a first PMOS transistor P1, a first NMOS transistor N1, a first input current I1, a second input current I2, a first reference voltage VREF1, and a second reference voltage VREF2. The first capacitor C1 is used to store charge to generate a voltage, the first current mirror 101 generates a charging current for the first capacitor C1, and the second current mirror 102 generates a charging current for the first capacitor C1. The third current mirror 103 generates a discharge current of the first capacitor C1, the third current mirror 103 generates a bias current of the first limiting circuit 105, the fourth current mirror 104 generates a bias current of the second limiting circuit 106, the first limiting circuit 105 is used to limit the maximum voltage of the capacitor C1, the second limiting circuit 106 is used to limit the minimum voltage of the capacitor C1, the first PMOS tube P1 is used as a switch tube to control the first current mirror 101 to charge or not charge the first capacitor C1, and the first NMOS tube N1 is used as a switch tube to control the second current mirror 102 to discharge or not discharge the first capacitor C1.

[0042] The input end of the first current mirror 101 is connected to the first input current I1, the source of the first PMOS tube P1 is connected to the power supply end, the drain of the first PMOS tube P1 is connected to the first current mirror 101, the input end of the third current mirror 103 is connected to the second input current I2, the first limiter circuit 105 is respectively connected to the first current mirror 101, the third current mirror 103, the second limiter circuit 106, the first end of the first capacitor C1 and the input end of the voltage-current conversion circuit 200, the second limiter circuit 106 is respectively connected to the second current mirror 102 and the fourth current mirror 104, the The third current mirror 103 is connected to the fourth current mirror 104, the drain of the first NMOS tube N1 is connected to the second current mirror 102, the source of the first NMOS tube N1 and the second end of the first capacitor C1 are both connected to the ground, the input end of the first limiter circuit 105 is connected to the first reference voltage VREF1, the input end of the second limiter circuit 106 is connected to the second reference voltage VREF2, the gate of the first PMOS tube P1 is connected to the first control signal Ct1, the source of the first NMOS tube N1 is connected to the ground, and the gate of the first PMOS tube P1 is connected to the second control signal Ct2.

[0043] In one embodiment, the source of the first PMOS transistor P1 is connected to the power supply terminal, the gate of the first PMOS transistor P1 is connected to the first control signal, the source of the first NMOS transistor N1 is connected to the ground, the gate of the first NMOS transistor N1 is connected to the second control signal Ct2, and the first control signal Ct1 and the second control signal Ct2 have opposite phases.

[0044] In one embodiment, the first reference voltage VREF1 is greater than the second reference voltage VREF2.

[0045] In this embodiment, in the current-voltage conversion circuit 100, when the gate of the first PMOS tube P1 is at a low level, the first current mirror 101 charges the first capacitor C1, and the voltage of the first capacitor C1 rises until it reaches the first reference voltage VREF1. The charging current controls the rising slope of the capacitor voltage. When the gate of the first PMOS tube P1 is at a high level, the first current mirror 101 stops charging the first capacitor C1. The rising slope of the voltage of the capacitor C1 is expressed as:

[0046]

[0047] In the above formula, K r is the rising slope of the capacitor voltage C1, V cap (t) is the voltage of capacitor C1, C is the capacitance of capacitor C1, I p is the charging current of capacitor C1.

[0048] In this embodiment, in the current-voltage conversion circuit 100, when the gate of the first NMOS transistor N1 is at a high level, the second current mirror 102 discharges the first capacitor C1, and the voltage of the first capacitor C1 decreases until it reaches the second reference voltage VREF2. The discharge current controls the capacitor voltage drop slope. When the gate of the first NMOS transistor N1 is at a low level, the second current mirror 102 stops discharging the first capacitor C1. The voltage drop slope of the capacitor C1 is expressed as:

[0049]

[0050] In the above formula, K f is the voltage drop slope of capacitor C1, V cap (t) is the voltage of capacitor C1, C is the capacitance of capacitor C1, I n is the discharge current of capacitor C1.

[0051] In one embodiment, the first current mirror 101 includes a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4, the drain of the second PMOS transistor P2 is connected to the gate of the second PMOS transistor P2, the gate of the third PMOS transistor P3, the gate of the fourth PMOS transistor P4, and the input current I1, the source of the second PMOS transistor P2 and the source of the third PMOS transistor P3 are connected to the power supply, and the source of the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1. The second current mirror 102 includes a second NMOS transistor N2 and a third NMOS transistor N3, the drain of the second NMOS transistor N2 is connected to the gate of the second NMOS transistor N2, the gate of the third NMOS transistor N3, and the drain of the third PMOS transistor P3, the source of the second NMOS transistor N2 is connected to the ground, and the source of the third NMOS transistor N3 is connected to the drain of the first NMOS transistor N1. The third current mirror 103 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, and a seventh PMOS transistor P7, the drain of the fifth PMOS transistor P5 is connected to the gate of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6, and the gate of the seventh PMOS transistor P7, the source of the fifth PMOS transistor P5, the source of the sixth PMOS transistor P6, and the source of the seventh PMOS transistor P7 are connected to the power supply, and the drain of the seventh PMOS transistor P7 is connected to the input current I2. The fourth current mirror 104 includes a fourth NMOS transistor N4 and a fifth NMOS transistor N5, the drain of the fourth NMOS transistor N4 is connected to the gate of the fourth NMOS transistor N4, the gate of the fifth NMOS transistor N5, and the drain of the sixth PMOS transistor P6, and the source of the fourth NMOS transistor N4 and the source of the fifth source NMOS transistor N5 are connected to the ground. The first amplitude limiting circuit 105 includes a sixth NMOS transistor N6 and a seventh NMOS transistor N7, the drain of the sixth NMOS transistor N6 is connected to the gate of the sixth NMOS transistor N6, the gate of the seventh NMOS transistor N7, and the drain of the seventh PMOS transistor P7, and the source of the sixth NMOS transistor N6 is connected to the first reference voltage VREF1. The second amplitude limiting circuit 106 includes an eighth PMOS transistor P8 and a ninth PMOS transistor P9, the drain of the eighth PMOS transistor P8 is connected to the gate of the eighth PMOS transistor P8, the gate of the ninth PMOS transistor P9, and the drain of the fifth NMOS transistor N5, the source of the eighth PMOS transistor P8 is connected to the second reference voltage, and the drain of the ninth PMOS transistor P9 is connected to the drain of the third NMOS transistor N3.

[0052] In one embodiment, the voltage-current conversion circuit 200 includes a first operational amplifier A1, a first resistor R1, an eighth NMOS transistor N8, a tenth PMOS transistor P10, and an eleventh PMOS transistor P11. The positive input terminal of the first operational amplifier A1 is connected to the first end of the first capacitor C1, the source of the seventh NMOS transistor N7, and the source of the ninth PMOS transistor P9. The negative input terminal of the first operational amplifier A1 is connected to the first end of the first resistor R1 and the source of the eighth NMOS transistor N8. The output terminal of the first operational amplifier A1 is connected to the gate of the eighth NMOS transistor N8. The second end of the first resistor R1 is connected to the ground. The drain of the eighth NMOS transistor N8 is connected to the drain of the tenth PMOS transistor P10, the gate of the tenth PMOS transistor P10, and the gate of the eleventh PMOS transistor P11. The source of the tenth PMOS transistor P10 and the source of the eleventh PMOS transistor P11 are connected to the power supply terminal.

[0053] In one embodiment, the current subtraction circuit 300 includes a second operational amplifier A2, a second resistor R2, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a twelfth PMOS transistor P12, and a thirteenth PMOS transistor P13. The positive input terminal of the second operational amplifier A2 is connected to the second reference voltage VREF2, the negative input terminal of the second operational amplifier A2 is connected to the first end of the second resistor R2 and the source of the ninth NMOS transistor N9, the second end of the second resistor R2 is connected to the ground, the output terminal of the second operational amplifier A2 is connected to the gate of the ninth NMOS transistor N9, the drain of the ninth NMOS transistor N9 is connected to the drain of the twelfth PMOS transistor P12, the gate of the twelfth PMOS transistor P12, The gate of the thirteenth PMOS tube P13 is connected, the source of the twelfth PMOS tube P12 and the source of the thirteenth PMOS tube P13 are connected to the power supply terminal, the drain of the thirteenth PMOS tube P13 is connected to the gate of the tenth NMOS tube N10, the drain of the tenth NMOS tube N10, and the gate of the eleventh NMOS tube N11, the drain of the eleventh NMOS tube N11 is connected to the drain of the eleventh PMOS tube N11, the drain of the twelfth NMOS tube N12, the gate of the twelfth NMOS tube N12, and the gate of the thirteenth NMOS tube N13, the source of the eleventh NMOS tube N11, the source of the twelfth NMOS tube N12, and the source of the thirteenth NMOS tube N13 are connected to the ground, and the drain of the thirteenth NMOS tube N13 is the current square wave output terminal, and the output current Io is expressed as:

[0054] I o (t) = V cap (t) / R1-V REF2 (t) / R2;

[0055] In the above formula, I O (t) is the output current, V REF2 is the second reference voltage, R1 is the first resistor, R2 is the second resistor, R1=R2=R, V cap (t) Maximum value is V REF1 , the minimum value is V REF2 , so I O (t) minimum is 0A, maximum is (V REF1 -V REF2 ) / RA.

[0056] Current I O (t) The rising slope is expressed as:

[0057]

[0058] Current I O (t) The decreasing slope is expressed as:

[0059]

[0060] From the formula, the rising slope and falling slope of the current square wave are proportional to the input current. The rising slope and falling slope of the current square wave can be changed by changing the input current.

[0061] In this embodiment, the hot-swap protection circuit of this embodiment is designed and simulated using a DB HiTek 0.18um 60V process, and the devices used are 5V devices. Figure 4 is the voltage waveform of the first capacitor C1 in this embodiment. The capacitance C of the first capacitor C1 is equal to 6pF, the input current I1 is equal to 18uA, the input current I2 is equal to 1uA, the capacitor charge and discharge current is equal to 17.9uA, and the first resistor R1 and the second resistor R2 are equal to 59.63KΩ. Figure 4 In the example, the rising slope of the voltage of the first capacitor C1 is 3.00MV / S, and the falling slope is 3.01MV / S. Figure 5 The output current Io waveform is shown in Figure 1. The rising slope of the current Io is 53.15A / S, the falling slope is 52.5A / S, and the minimum current is 593nA. The input current I1 is changed to 7.36uA, 11.27uA, and 24.96uA respectively. The output current Io is as follows: Figure 6 The rising slopes are 21.34A / S, 34.02A / S, and 75.50A / S, and the falling slopes are 21.04A / S, 32.99A / S, and 74.76A / S, respectively. The output current square wave Io slope is controlled by changing the input current I1.

[0062] The above are only preferred embodiments of the present invention. It should be pointed out that the above preferred embodiments should not be regarded as limitations of the present invention. For ordinary technicians in this technical field, several equivalent substitutions, improvements and modifications can be made without departing from the spirit and scope of the present invention. These equivalent substitutions, improvements and modifications should also be regarded as the protection scope of the present invention. The embodiments will not be repeated here. The protection scope of the present invention should be based on the scope defined by the claims.

Claims

1. A current driving circuit with controllable slope, characterized in that: The current driving circuit includes a current-voltage conversion circuit, a voltage-current conversion circuit and a current subtraction circuit; The output end of the current-to-voltage conversion circuit is connected to the input end of the voltage-to-current conversion circuit, and the output end of the voltage-to-current conversion circuit is connected to the input end of the current subtraction circuit; The current-to-voltage conversion circuit is used to convert the input current into a voltage square wave signal; The voltage-to-current conversion circuit is used to convert the voltage square wave signal output by the current-to-voltage conversion circuit into a current square wave signal; The current subtraction circuit is used to obtain an output current by taking the difference between the current square wave signal and a reference current, and the slope of the output current is proportional to the input current.

2. The current driving circuit with controllable slope according to claim 1, characterized in that: The current-to-voltage conversion circuit includes a first capacitor, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a first amplitude limiting circuit, a second amplitude limiting circuit, a first PMOS tube and a first NMOS tube; The first current mirror generates a charging current of the first capacitor, the second current mirror generates a discharging current of the first capacitor, the third current mirror generates a bias current of the first limiting circuit, the fourth current mirror generates a bias current of the second limiting circuit, the first limiting circuit is used to limit the maximum voltage of the first capacitor, the second limiting circuit is used to limit the minimum voltage of the first capacitor, the first PMOS tube is used to control the first current mirror to charge the first capacitor, and the first NMOS tube is used to control the second current mirror to discharge the first capacitor; The input end of the first current mirror is connected to the first input current, the source of the first PMOS tube is connected to the power supply end, the drain of the first PMOS tube is connected to the first current mirror, the input end of the third current mirror is connected to the second input current, the first limiter circuit is respectively connected to the first current mirror, the third current mirror, the second limiter circuit, the first end of the first capacitor and the input end of the voltage-current conversion circuit, the second limiter circuit is respectively connected to the second current mirror and the fourth current mirror, the third current mirror is connected to the fourth current mirror, the drain of the first NMOS tube is connected to the second current mirror, the source of the first NMOS tube and the second end of the first capacitor are both connected to the ground, the input end of the first limiter circuit is connected to the first reference voltage, the input end of the second limiter circuit is connected to the second reference voltage, the gate of the first PMOS tube is connected to the first control signal, the source of the first NMOS tube is connected to the ground, and the gate of the first PMOS tube is connected to the second control signal.

3. The current driving circuit with controllable slope according to claim 2, characterized in that: The first control signal and the second control signal are in opposite phases.

4. The current driving circuit with controllable slope according to claim 2, characterized in that: The first reference voltage is greater than the second reference voltage.

5. The current driving circuit with controllable slope according to claim 2, characterized in that: In the current-to-voltage conversion circuit, when the gate of the first PMOS tube is at a low level, the first current mirror charges the first capacitor, and the voltage of the first capacitor rises until it reaches the second reference voltage. The charging current controls the rising slope of the capacitor voltage. When the gate of the first PMOS tube is at a high level, the first current mirror stops charging the first capacitor.

6. The current driving circuit with controllable slope according to claim 2, characterized in that: In the current-to-voltage conversion circuit, when the gate of the first NMOS tube is at a high level, the second current mirror discharges the first capacitor, and the voltage of the first capacitor decreases until it reaches the second reference voltage. The discharge current controls the slope of the capacitor voltage decrease. When the gate of the first NMOS tube is at a low level, the second current mirror stops discharging the first capacitor.

7. The current driving circuit with controllable slope according to claim 2, characterized in that: The first current mirror includes a second PMOS tube, a third PMOS tube, and a fourth PMOS tube, the drain of the second PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube, and the gate of the fourth PMOS tube respectively, the source of the second PMOS tube and the source of the third PMOS tube are connected to the power supply terminal, the source of the third PMOS tube is connected to the drain of the first PMOS tube, and the source of the fourth PMOS tube is connected to the drain of the first PMOS tube; The second current mirror includes a second NMOS tube and a third NMOS tube, the drain of the second NMOS tube is respectively connected to the gate of the second NMOS tube, the gate of the third NMOS tube, and the drain of the third PMOS tube, the source of the second NMOS tube is connected to the ground, the source of the third NMOS tube is connected to the drain of the first NMOS tube, and the source of the third NMOS tube is connected to the drain of the first NMOS tube; The third current mirror includes a fifth PMOS tube, a sixth PMOS tube, and a seventh PMOS tube, the drain of the fifth PMOS tube is connected to the gate of the fifth PMOS tube, the gate of the sixth PMOS tube, and the gate of the seventh PMOS tube respectively, the source of the fifth PMOS tube, the source of the sixth PMOS tube, and the source of the seventh PMOS tube are all connected to the power supply terminal, and the drain of the fifth PMOS tube is connected to the second input current; The fourth current mirror includes a fourth NMOS tube and a fifth NMOS tube, the drain of the fourth NMOS tube is respectively connected to the gate of the fourth NMOS tube, the gate of the fifth NMOS tube, and the drain of the sixth PMOS tube, and the source of the fourth NMOS tube and the source of the fifth NMOS tube are both connected to the ground; The first limiting circuit includes a sixth NMOS tube and a seventh NMOS tube, the drain of the sixth NMOS tube is respectively connected to the gate of the sixth NMOS tube, the gate of the seventh NMOS tube, and the drain of the seventh PMOS tube, the source of the sixth NMOS tube is connected to the first reference voltage, and the drain of the seventh NMOS tube is connected to the drain of the fourth PMOS tube; The second limiting circuit includes an eighth PMOS tube and a ninth PMOS tube, the drain of the eighth PMOS tube is connected to the gate of the eighth PMOS tube, the gate of the ninth PMOS tube, and the drain of the fifth NMOS tube, the source of the eighth PMOS tube is connected to a second reference voltage, the drain of the ninth PMOS tube is connected to the drain of the third NMOS tube, and the source of the seventh NMOS tube and the source of the ninth PMOS tube are both connected to the first end of the first capacitor.

8. The current driving circuit with controllable slope according to claim 1, characterized in that: The voltage-current conversion circuit includes a first operational amplifier, a first resistor, an eighth NMOS tube, a tenth PMOS tube and an eleventh PMOS tube. The non-inverting input terminal of the first operational amplifier is connected to the output terminal of the current-voltage conversion circuit, the inverting input terminal of the first operational amplifier is respectively connected to the first end of the first resistor and the source of the eighth NMOS tube, the output terminal of the first operational amplifier is connected to the gate of the eighth NMOS tube, the second end of the first resistor is connected to the ground, the drain of the eighth NMOS tube is connected to the drain of the tenth PMOS tube, the gate of the tenth PMOS tube and the gate of the eleventh PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are both connected to the power supply terminal, and the drain of the eleventh PMOS tube is connected to the current subtraction circuit.

9. The current driving circuit with controllable slope according to claim 1, characterized in that: The current subtraction circuit includes a second operational amplifier, a second resistor, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube. The non-inverting input terminal of the second operational amplifier is connected to the second reference voltage, the inverting input terminal of the second operational amplifier is respectively connected to the first end of the second resistor and the source of the ninth NMOS tube, the second end of the second resistor is connected to the ground, the output terminal of the second operational amplifier is connected to the gate of the ninth NMOS tube, the drain of the ninth NMOS tube is respectively connected to the drain of the twelfth PMOS tube, the gate of the twelfth PMOS tube and the gate of the thirteenth PMOS tube, and the The source of the twelfth PMOS tube and the source of the thirteenth PMOS tube are both connected to the power supply end, the drain of the thirteenth PMOS tube is respectively connected to the gate of the tenth NMOS tube, the drain of the tenth NMOS tube, and the gate of the eleventh NMOS tube, the drain of the eleventh NMOS tube is respectively connected to the output end of the voltage-current conversion circuit, the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube, and the gate of the thirteenth NMOS tube, the source of the eleventh NMOS tube, the source of the twelfth NMOS tube, the source of the twelfth NMOS tube, and the source of the thirteenth NMOS tube are all connected to the ground, and the drain of the thirteenth NMOS tube is the current square wave output end of the current driving circuit with controllable slope.

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