Multi-chip fairness scheduling method based on ZNS SSD

Abstract

The invention relates to a multi-chip fairness scheduling method based on a ZNS SSD, and the method comprises the steps: calculating the delay loss ratio of each current data stream in each chip queue for all current data streams of the ZNS SSD; calculating the fairness of each current chip queue according to the delay loss ratio of each current data stream in each chip queue; aiming at each chip queue, taking the latest transaction allocated to each chip queue as a to-be-scheduled transaction, and forwards scheduling the to-be-scheduled transaction in the chip queue by taking the maximum fairness of the chip queue as an optimization target according to the delay loss ratio of the current data stream related to each chip queue in the chip queue; and according to the position maximum values of all the transactions requested by the to-be-scheduled transaction in the corresponding chip queues, scheduling all the transactions requested by the to-be-scheduled transaction to the position maximum values in the corresponding chip queues so as to improve the response time of the request. According to the invention, the performance of the ZNS SSD is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of computer storage, and in particular relates to a multi-chip fairness scheduling method based on ZNS SSD. Background Art

[0002] With the rapid development of information technology, storage systems have become an indispensable and important part of computer architecture. Although traditional SATA solid-state drives (HDDs) and NVMe solid-state drives (SSDs) have made remarkable achievements in improving storage performance and speed, these traditional solutions are still unable to cope with the severe challenges of big data processing and cloud computing applications. The mismatch between traditional block interfaces and flash media has led to a series of problems such as write amplification, performance fluctuations, and high latency.

[0003] In order to solve these problems, ZNS SSD (Zone Namespaced SSD) came into being as an innovative storage solution. ZNS SSD divides the SSD into multiple independent zones and stipulates that only sequential write operations can be performed in each zone, thereby significantly reducing the size of the address mapping table, effectively reducing the write amplification phenomenon, and thus improving the overall performance of the storage system. This design not only retains a standardized ecosystem, but also gives the host side more flexible control over data placement, thereby optimizing storage management and improving storage efficiency.

[0004] However, ZNS SSD divides the logical address space into multiple partitions and maps them to multiple flash chips, which introduces the concept of multi-chip queues. In practical applications, a request issued by the host is often split into transactions in multiple chip-level queues for parallel execution. However, current research mainly focuses on fair scheduling on a single queue, while ignoring the scheduling strategy of the overall request, resulting in limited overall performance improvement. Summary of the invention

[0005] In order to solve the problems existing in the background technology, the present invention provides a multi-chip fairness scheduling method based on ZNS SSD, comprising:

[0006] S1: For all current data flows of the ZNS SSD, calculate the delay loss ratio of each current data flow in each chip queue;

[0007] S2: Calculate the fairness of each chip queue according to the delay loss ratio of each data flow in each chip queue;

[0008] S3: for each chip queue, the transaction most recently assigned to each chip queue is used as the transaction to be scheduled, and the transaction to be scheduled is scheduled forward in the chip queue based on the delay loss ratio of the data flow currently related to each chip queue in the chip queue, with the fairness of the chip queue being maximized as the optimization goal; the data flow related to each chip queue includes: when a certain transaction requested in the data flow is assigned to the chip queue, the data flow is related to the chip queue, otherwise it is not related;

[0009] S4: According to the maximum position of all transactions of the request to which the transaction to be scheduled belongs in the corresponding chip queue, all transactions of the request to which the transaction to be scheduled belongs are scheduled to the maximum position in the corresponding chip queue to optimize the response time of the request.

[0010] The present invention has at least the following beneficial effects

[0011] The present invention can significantly improve the overall performance of ZNS SSD by comprehensively considering the performance differences of different data streams on different chip queues and optimizing the scheduling strategy of transactions accordingly. By identifying chip queues with performance bottlenecks or uneven resource allocation and optimizing them in a targeted manner, the present invention can optimize resource utilization and improve the resource efficiency of the storage system. The scheduling method of the present invention can flexibly respond to the challenges brought by large-scale data processing and cloud computing applications, and provide a useful reference for the innovative development in the field of storage systems. In summary, the multi-chip fairness scheduling method based on ZNS SSD proposed in the present invention optimizes storage system performance and resource utilization by comprehensively considering factors such as data stream performance differences, chip queue fairness, and request response time, and provides strong support for large-scale data processing and cloud computing applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a method flow chart of an embodiment of the present invention;

[0013] Figure 2 The I / O access workflow and partition mapping diagram of the ZNS SSD according to an embodiment of the present invention;

[0014] Figure 3 It is an overall architecture diagram and implementation principle diagram of an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of transaction scheduling according to an embodiment of the present invention;

[0016] Figure 5 Schematic diagram of multi-chip collaborative scheduling according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0018] See also Figure 1 The present invention provides a multi-chip fairness scheduling method based on ZNS SSD, comprising:

[0019] S1: For all current data flows of the ZNS SSD, calculate the delay loss ratio of each current data flow in each chip queue;

[0020] S2: Calculate the fairness of each chip queue according to the delay loss ratio of each data flow in each chip queue;

[0021] S3: for each chip queue, the transaction most recently assigned to each chip queue is used as the transaction to be scheduled, and the transaction to be scheduled is scheduled forward in the chip queue based on the delay loss ratio of the data flow currently related to each chip queue in the chip queue, with the fairness of the chip queue being maximized as the optimization goal; the data flow related to each chip queue includes: when a certain transaction requested in the data flow is assigned to the chip queue, the data flow is related to the chip queue, otherwise it is not related;

[0022] S4: According to the maximum position of all transactions of the request to which the transaction to be scheduled belongs in the corresponding chip queue, all transactions of the request to which the transaction to be scheduled belongs are scheduled to the maximum position in the corresponding chip queue to optimize the response time of the request.

[0023] See also Figure 2 and Figure 3 , in this embodiment, Figure 2 The I / O access workflow and partition map of the ZNS SSD. Figure 2It can be seen from the figure that an I / O access workflow includes four steps. In the first step, the I / O streams from different applications are submitted to the host-side DRAM to form multiple submission queues. In the second step, the host interface logic loop on the device side obtains requests from multiple submission queues and parses the requests into a series of transactions with a 4KB page size. In the third step, the partition flash translation layer provides address translation and transaction scheduling functions to insert transactions into multiple chip queues respectively. Each transaction corresponds to a chip, and each chip corresponds to a chip queue. In the fourth step, the flash channel controller schedules transactions to the backend and executes each transaction in a scheduling order. From the partition mapping diagram, we can see that a zone is usually mapped to multiple chips, so a request will be executed in parallel on multiple chips. When all transactions are completed, the request is considered completed. Therefore, when performing fairness scheduling, it should be considered that a request is located in multiple chips for coordinated scheduling. It takes a certain amount of time for the chip to respond to the transaction. Transactions that are not responded in time will be temporarily stored in the chip queue of the corresponding chip and then wait to be responded. For transactions waiting for response in the chip queue, the transaction scheduling module can schedule certain transactions forward or backward according to pre-agreed rules.

[0024] The multi-chip fairness scheduling method based on ZNS SSD provided by the present invention optimizes the storage system performance and resource utilization by comprehensively considering factors such as data flow performance differences, chip queue fairness and request response time. This method not only improves the overall performance of ZNS SSD, but also optimizes resource utilization, meeting the needs of large-scale data processing and cloud computing applications.

[0025] Preferably, calculating the delay loss ratio of each current data flow in each chip queue includes:

[0026] S11: Calculate the start time of each data flow transaction when it runs alone on each chip and the start time of each data flow transaction when it runs together with other data flow transactions on each chip according to the current processing time of each data flow transaction on each chip;

[0027] In this embodiment, based on the current processing time of each data flow transaction on each chip, the start time of each data flow transaction is calculated if it runs alone on the chip. This helps us understand the potential execution time of each data flow transaction without interference from other data flows. Then, by calculating the start time of each current data flow transaction when it runs together with the transactions of other data flows on each chip, this reflects the actual execution time of each data flow transaction in an actual multi-data flow environment.

[0028] Preferably, the step of calculating the start time of each current transaction of each data flow when it runs separately on each chip comprises:

[0029] Assume that the qth transaction of the current fth data stream is running alone on the cth chip, using PT c,f,q represents the processing time of the qth transaction of the current fth data stream on the cth chip, then the start time of the ith transaction of the current fth data stream on the cth chip is:

[0030]

[0031] in, Indicates the start time of the i-th transaction of the current f-th data flow when it runs alone on the c-th chip, NAT c Indicates the next idle time of the cth chip;

[0032] Preferably, the step of calculating the start time of each current transaction of each data flow and transactions of other data flows when running together on each chip comprises:

[0033] Assume that the qth transaction of the current fth data stream and the transactions of other data streams are running together on the cth chip, use PT′ c,f,q represents the processing time of the qth transaction of the current fth data stream on the cth chip, then the start time of the i′th transaction of the current fth data stream on the cth chip is:

[0034]

[0035] in, Indicates the start time of the i′th transaction of the current fth data flow and the transactions of other data flows running together on the cth chip, NAT′ c Indicates the next idle time of the cth chip;

[0036] In this embodiment, by comparing the start time of the individual operation and the start time of the common operation, the mutual influence degree between the data streams can be preliminarily determined, which provides a basis for the subsequent calculation of the delay loss ratio.

[0037] S12: Calculate the average response time of each data flow when it is running alone on each chip according to the start time of each data flow transaction when it is running alone on each chip and the time when each data flow transaction enters the chip queue;

[0038] Preferably, the response time of each current data stream when running separately on each chip includes:

[0039]

[0040] in, It represents the average response time of the current f-th data stream when it runs alone on the c-th chip; Indicates the start time of the i-th transaction of the current f-th data stream when it runs alone on the c-th chip, PT c,f,i AT represents the processing time of the i-th transaction of the current f-th data stream on the c-th chip, c,f,i Indicates the time when the i-th transaction of the current f-th data flow enters the c-th chip queue, N c,f Indicates the number of transactions in the fth data stream in the current cth chip queue.

[0041] S13: Calculate the average response time of each data flow when the other data flows are running together on each chip according to the start time of each data flow transaction when the other data flows are running together on each chip and the time when each data flow transaction enters the chip queue;

[0042] Preferably, the step of calculating the average response time of each current data stream when other data streams run together on each chip comprises:

[0043]

[0044] in, It represents the average response time of the current f-th data stream when other data streams run together on the c-th chip; PT′ represents the start time of the i′th transaction of the current fth data stream when it runs together with the transactions of other data streams on the cth chip. c,f,i AT represents the processing time of the i-th transaction of the current f-th data stream on the c-th chip, c,f,i ′ represents the time when the i′th transaction of the current fth data stream enters the cth chip-level queue, N c,f Indicates the number of transactions in the fth data stream in the current cth chip queue.

[0045] S14: Calculate the delay loss ratio of each data flow in each chip queue according to the average response time of each data flow when it runs alone on each chip and the average response time of the transactions of each data flow and other data flows when they run together on each chip.

[0046] Preferably, the delay loss ratio of each data flow in each chip queue includes:

[0047]

[0048] Among them, SD c,f It represents the delay loss ratio of the fth data flow in the cth chip queue. represents the average response time of the current f-th data stream when other data streams run together on the c-th chip, It represents the average response time of the current f-th data stream when it runs alone on the c-th chip;

[0049] Preferably, the fairness of each chip queue includes:

[0050]

[0051] Among them, SD c,f It represents the delay loss ratio of the current f-th data flow in the c-th chip queue; min() represents the minimum function; max() represents the maximum function, f∈{1,2,…,f,…,F}, where F represents the number of current data flows.

[0052] In this embodiment, by calculating the start time and average response time of each data stream when it runs alone on each chip and when it runs together with other data streams, the mutual influence between data streams can be accurately evaluated. This helps to understand the delay loss caused by resource contention for each data stream in a multi-data stream environment. By calculating the delay loss ratio of each data stream in each chip queue, the degree of delay loss suffered by data streams in different chip queues due to shared resources can be quantified. Using the delay loss ratio of each chip queue, the fairness index of the queue can be calculated. This index reflects whether the system can treat each data stream fairly when multiple data streams share the same chip resources to ensure that they get relatively balanced processing opportunities. Fairness assessment is crucial to improving the overall system performance and user experience.

[0053] See also Figure 4 Preferably, step S3 comprises:

[0054] S31: according to the fairness of each chip queue and the delay loss ratio of each data flow in each chip queue, divide the data flow related to the chip queue into fair data flow and unfair data flow;

[0055] S32: for each chip queue, define the latest to-be-scheduled transaction assigned to the chip-level queue as N, first determine whether there is an empty space on the chip queue, and if so, schedule transaction N to the empty space closest to the head of the chip queue;

[0056] S33: Determine whether the data flow to which transaction N belongs is an unfair data flow, if so, execute step S34, otherwise execute step S37;

[0057] S34: Determine the transaction W at the previous position of the transaction N in the chip queue. If the transaction R and the transaction N do not belong to the same data flow, execute step S35; otherwise, execute step S37.

[0058] S35: after scheduling transaction N to the previous position of transaction W, determine whether the delay loss ratio of the data flow to which transaction W belongs is less than the delay loss ratio of the data flow to which transaction N belongs. If so, schedule transaction N to the previous position of transaction W. Otherwise, execute step S37.

[0059] S36: Repeat steps S34 to S35;

[0060] S37: End the scheduling of transaction N.

[0061] In this embodiment, by considering the fairness of each chip queue and the delay loss ratio of each data flow in the chip queue, this step realizes the intelligent scheduling of the scheduling affairs. This scheduling strategy not only focuses on the performance of a single data flow, but also strives to improve the fairness and efficiency of the entire system. Step S31 divides the relevant data flows into fair data flows and unfair data flows, which helps to identify those data flows that suffer large delay losses due to uneven resource allocation. Through the priority scheduling of subsequent steps, the performance of these unfair data flows can be gradually improved. Step S32 first checks whether there is a vacancy in the chip queue. If there is, the transaction N is directly scheduled to the vacancy closest to the head of the queue. This strategy reduces unnecessary scheduling delays and improves the response speed of the system. For transaction N identified as an unfair data flow, steps S33 to S35 try to schedule transaction N to a position that can further reduce the delay loss ratio of the data flow to which it belongs through a series of judgments and adjustments. This intelligent adjustment helps to balance the performance differences between different data flows and improve the overall fairness of the system. By comprehensively considering the fairness of the chip queue and the delay loss ratio of the data flow, intelligent scheduling of scheduling affairs is realized. This scheduling strategy not only improves the efficiency and fairness of the system, but also helps to optimize resource allocation and improve overall performance.

[0062] Preferably, the step S31 includes:

[0063] S311: When the fairness of the chip-level queue is less than the set threshold, the data flow related to the chip queue is divided into fair data flow; otherwise, step S312 is executed:

[0064] S312: setting two clustering centers of the k-means algorithm to be the minimum delay loss ratio and the maximum delay loss ratio of the data flow related to the chip queue;

[0065] S313: For each data flow related to the chip queue, calculate the distance between its delay loss ratio and the two cluster centers respectively, and assign the data flow to the cluster to which the cluster center point closest to it belongs;

[0066] S314: For each cluster, calculate the average value of the delay loss ratios of all data flows in the cluster, and use the average value as a new cluster center point;

[0067] S315: Repeat steps S313 and S314 until the cluster center point no longer changes or the maximum number of iterations is reached, and the data flow in the cluster with the smaller cluster center point is regarded as a fair data flow, and the data flow in the other cluster is regarded as an unfair data flow.

[0068] In this embodiment, the data streams related to the chip queue are dynamically divided into fair data streams and unfair data streams through the k-means clustering algorithm, which provides a basis for subsequent optimization scheduling. This division method not only improves the accuracy of clustering, but also helps to improve the fairness and overall performance of the system. By dividing the data streams with relatively small delay losses into fair data streams and dividing the data streams with relatively large delay losses into unfair data streams, step S31 provides a basis for subsequent optimization scheduling. During the scheduling process, transactions in unfair data streams can be given priority to reduce their delay loss ratios, thereby improving the fairness of the entire system.

[0069] See also Figure 5 Preferably, step S4 comprises:

[0070] S41: define all transactions of the request to which the transaction N most recently assigned to the chip-level queue belongs as a set P = {P1, P2, ..., P i ,…,P n}, N∈P, n represents the number of transactions to which transaction N belongs;

[0071] S42: Each transaction P in the set P i The position of its corresponding chip queue is defined as L i ;

[0072] S43: Calculation Schedule all transactions in set P to L at the position of their corresponding chip queues.

[0073] In this embodiment, by scheduling all transactions of the request to which the transaction N that is most recently assigned to the chip-level queue belongs to the same position L at the position of its corresponding chip queue, centralized processing of transactions is achieved, scheduling order is optimized, transaction dispersion is reduced, transaction processing fairness is improved, scheduling strategy is simplified, and it has strong adaptability. These effects jointly improve the overall performance and stability of the system. By scheduling all transactions (set P) of the request to which the transaction N that is most recently assigned to the chip-level queue belongs to the same position L at the position of its corresponding chip queue, it is ensured that these transactions can be processed in a more orderly manner. This helps to reduce waiting time and processing delay between transactions and improve the overall processing efficiency of the system.

[0074] See also Figure 4 ,according to Figure 4 As shown in the figure, it can be seen that the newly arrived request is divided into four transactions located on chip 0, chip 1, chip 2, and chip 3 and executed separately. After the above fairness detection part, the transaction is classified as an unfair flow, so it will be scheduled forward. According to the principle of forward scheduling of unfair flows, transaction N located on chip 0 and chip 1 will be scheduled after transaction T_3 respectively, while transaction N located on chip 2 and chip 3 will remain at the current position.

[0075] See also Figure 5 , Figure 5 (a) shows how the newly arrived transaction will be scheduled if it belongs to an unfair flow. The four transactions N on chip 0, chip 1, chip 2, and chip 3 all come from the same request, which belongs to flow 3. For new transactions on chip 0 and chip 1, transaction N on chip 2 and chip 3 will be aligned, so as to improve the fairness of flow 3 while reducing the impact on ZNS SSD performance.

[0076] Figure 5 (b) Figure 5 (c) shows how fair flows should be scheduled. Figure 5 According to the scheduling method of unfair flow transactions in (a), transaction N should be scheduled and Figure 5 (a) The same position, such as Figure 5 (b), but since it is a fair flow, forward scheduling cannot be performed, so the following Figure 5 The backward scheduling method shown in (c), that is, aligning the new transactions on chip 2 and chip 3 with the new transactions on chip 0 and chip 1, will leave space R for scheduling subsequent new transactions, thereby reducing the response time of subsequent new transactions.

[0077] In summary, the present invention can significantly improve the overall performance of ZNS SSD by comprehensively considering the performance differences of different data streams on different chip queues and optimizing the scheduling strategy of transactions accordingly. By identifying chip queues with performance bottlenecks or uneven resource allocation and optimizing them in a targeted manner, the present invention can optimize resource utilization and improve the resource efficiency of the storage system. The scheduling method of the present invention can flexibly respond to the challenges brought by large-scale data processing and cloud computing applications, and provide a useful reference for the innovative development in the field of storage systems. In summary, the multi-chip fairness scheduling method based on ZNS SSD proposed in the present invention optimizes storage system performance and resource utilization by comprehensively considering factors such as data stream performance differences, chip queue fairness, and request response time, and provides strong support for large-scale data processing and cloud computing applications.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A multi-chip fairness scheduling method based on ZNS SSD, characterized in that: include: S1: For all current data flows of the ZNS SSD, calculate the delay loss ratio of each current data flow in each chip queue; S2: Calculate the fairness of each chip queue according to the delay loss ratio of each data flow in each chip queue; S3: for each chip queue, the transaction most recently assigned to each chip queue is used as the transaction to be scheduled, and the transaction to be scheduled is scheduled forward in the chip queue based on the delay loss ratio of the data flow currently related to each chip queue in the chip queue, with the fairness of the chip queue being maximized as the optimization goal; the data flow related to each chip queue includes: when a certain transaction requested in the data flow is assigned to the chip queue, the data flow is related to the chip queue, otherwise it is not related; S4: According to the maximum position of all transactions of the request to which the transaction to be scheduled belongs in the corresponding chip queue, all transactions of the request to which the transaction to be scheduled belongs are scheduled to the maximum position in the corresponding chip queue to optimize the response time of the request.

2. According to a multi-chip fairness scheduling method based on ZNS SSD according to claim 1, it is characterized in that: The calculation of the delay loss ratio of each data flow in each chip queue comprises: S11: Calculate the start time of each data flow transaction when it runs alone on each chip and the start time of each data flow transaction when it runs together with other data flow transactions on each chip according to the current processing time of each data flow transaction on each chip; S12: Calculate the average response time of each data flow when it is running alone on each chip according to the start time of each data flow transaction when it is running alone on each chip and the time when each data flow transaction enters the chip queue; S13: Calculate the average response time of each data flow when the other data flows are running together on each chip according to the start time of each data flow transaction when the other data flows are running together on each chip and the time when each data flow transaction enters the chip queue; S14: Calculate the delay loss ratio of each data flow in each chip queue according to the response time of each data flow when it runs on each chip alone and the response time of the transaction of each data flow and the transaction of other data flows when they run together on each chip.

3. According to a multi-chip fairness scheduling method based on ZNS SSD in claim 1, it is characterized in that: The fairness of each chip queue includes: Among them, SD c,f It represents the delay loss ratio of the current f-th data flow in the c-th chip queue; min() represents the minimum function; max() represents the maximum function, f∈{1,2,…,f,…,F}, where F represents the number of current data flows.

4. According to a multi-chip fairness scheduling method based on ZNS SSD according to claim 1, it is characterized in that: The step S3 comprises: S31: according to the fairness of each chip queue and the delay loss ratio of each data flow in each chip queue, divide the data flow related to the chip queue into fair data flow and unfair data flow; S32: for each chip queue, define the latest to-be-scheduled transaction assigned to the chip-level queue as N, first determine whether there is an empty space on the chip queue, and if so, schedule transaction N to the empty space closest to the head of the chip queue; S33: Determine whether the data flow to which transaction N belongs is an unfair data flow, if so, execute step S34, otherwise execute step S37; S34: Determine the transaction W in the previous position of the transaction N in the chip queue. If the transaction R and the transaction N do not belong to the same data flow, execute step S35; otherwise, execute step S37; S35: after scheduling transaction N to the previous position of transaction W, determine whether the delay loss ratio of the data flow to which transaction W belongs is less than the delay loss ratio of the data flow to which transaction N belongs. If so, schedule transaction N to the previous position of transaction W. Otherwise, execute step S37. S36: Repeat steps S34 to S35; S37: End the scheduling of transaction N.

5. According to the multi-chip fairness scheduling method based on ZNS SSD in claim 4, it is characterized in that: The step S31 comprises: S311: When the fairness of the chip-level queue is less than the set threshold, the data flow related to the chip queue is divided into fair data flow; otherwise, step S312 is executed: S312: setting two clustering centers of the k-means algorithm to be the minimum delay loss ratio and the maximum delay loss ratio of the data flow related to the chip queue; S313: For each data flow related to the chip queue, calculate the distance between its delay loss ratio and the two cluster centers respectively, and assign the data flow to the cluster to which the cluster center point closest to it belongs; S314: For each cluster, calculate the average value of the delay loss ratios of all data flows in the cluster, and use the average value as a new cluster center point; S315: Repeat steps S313 and S314 until the cluster center point no longer changes or the maximum number of iterations is reached, and the data flow in the cluster with the smaller cluster center point is regarded as a fair data flow, and the data flow in the other cluster is regarded as an unfair data flow.

6. According to a multi-chip fairness scheduling method based on ZNS SSD in claim 1, it is characterized in that: The step S4 comprises: S41: define all transactions of the request to which the transaction N most recently assigned to the chip-level queue belongs as a set P = {P1, P2, ..., P i ,…,P n }, N∈P, n represents the number of transactions to which transaction N belongs; S42: Each transaction P in the set P i The position of its corresponding chip queue is defined as L i ; S43: Calculation Schedule all transactions in set P to L at the position of their corresponding chip queues.

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