LED array driver system

Abstract

The embodiment of the invention relates to an LED array driver system. An embodiment LED driver system includes a power transistor configured to be selectively activated for generating a drive current for an LED array, the power transistor having a first conductive terminal coupled to the LED array and a second conductive terminal coupled to a reference resistor; an operational amplifier having a non-inverting input for receiving a reference voltage, an inverting input coupled to the second conductive terminal of the power transistor, and an output terminal coupled to the first conductive terminal of a pass gate, the transfer gate has a second conductive terminal coupled to the control terminal of the power transistor and a control terminal for receiving an enable signal. And a slew rate control unit configured to control the slew rate of the drive current.

Description

[0001] This application is a divisional application of the invention patent application with the application date of June 7, 2021 (the earliest priority date is June 8, 2020), the Chinese national application number 202110630920.1, and the name “LED Array Driver System”. Technical Field

[0002] The present invention relates generally to the field of electronic devices, and more particularly, to an LED driver system. Background Art

[0003] To drive light emitting diodes (LEDs), LED driver systems are known which are configured to control the current flowing through the LEDs.

[0004] Different kinds of LED driver system architectures are known in the art.

[0005] For example, Figure 1 An LED driver system 100 having a V2I (“voltage to current”) architecture is illustrated, the LED driver system being configured to drive an LED array 102 .

[0006] The LED driver system 100 includes an operational amplifier 104 having a non-inverting input terminal configured to receive a voltage Vbuff, an output terminal connected to a control terminal (e.g., a gate) of a transistor 108 (e.g., an n-type metal oxide semiconductor (MOS) transistor), and an inverting input terminal connected to a conductive terminal (e.g., a source) of the transistor 108. The inverting input terminal of the operational amplifier 104 is also connected to a first terminal of an external resistor Rext, a second terminal of which is connected to a reference terminal (GND terminal) providing a ground voltage.

[0007] Another conductive terminal (e.g., drain) of transistor 108 is connected to an input terminal of a current mirror 120. Current mirror 120 has an output terminal connected to an input terminal of a resistor ladder digital-to-analog converter (DAC) 125 for providing a high-precision reference current Iref that is a mirrored version of an external current Iext flowing through an external resistor Rext, which in turn is a function of the external resistor Rext and a voltage Vbuff.

[0008] The DAC 125 has an output terminal for providing a reference voltage Vref based on a reference current Iref to a non-inverting input terminal of an operational amplifier 130. The operational amplifier 130 has an output terminal connected to a first conductive terminal of a transmission gate TG1 for providing a voltage Vi. The transmission gate TG1 has a second conductive terminal connected to a control terminal (e.g., a gate) of a power transistor N1 (e.g., an n-type power MOS transistor) for providing a voltage Vo.

[0009] The power transistor N1 has a conductive terminal (e.g., a source) connected to the non-inverting terminal of the operational amplifier 130 and a first conductive terminal of the reference resistor Rset, thereby defining a circuit node 135. The reference resistor Rset has a second conductive terminal connected to the ground terminal GND. The power transistor N1 has another conductive terminal (e.g., a drain) connected to the LED array 102.

[0010] The transmission gate TG1 has a control terminal for receiving a pulse width modulation (PWM) control signal CTRL pulsating between a high value and a low value.

[0011] When the control signal CTRL is at a high value, the first conductive terminal and the second conductive terminal of the transmission gate TG1 are electrically connected to each other so that the voltage Vo reaches the voltage Vi, the feedback voltage FDB at the circuit node 135 reaches the reference voltage Vref, and the LED array 102 is crossed by the drive current Iset, which has a value Iset(h) corresponding to the reference voltage Vref divided by the resistance of the reference resistor Rset.

[0012] When the control signal CTRL is at a low value, the first conduction terminal of the transmission gate TG1 is electrically insulated from the second conduction terminal of the transmission gate TG1 and the drive current Iset is at a value Iset(1) equal to zero.

[0013] In this way, it is possible to deliver the drive current Iset in the form of current pulses whose duty cycle is based on the duty cycle of the control signal CTRL. By varying the duty cycle of the control signal CTRL (e.g. at a frequency higher than 100 Hz), the intensity of the light emitted by the LED can thus be adjusted. This LED control technique is called digital dimming.

[0014] In order to avoid or at least reduce control errors when driving the LED array 102 at a low duty cycle, the driving current Iset should have fast rising / falling edges (ie, low slew rate).

[0015] According to a solution known in the art, fast rising / falling edges are obtained by keeping the voltage Vi output by the operational amplifier 130 close to the target voltage Vo at the gate of the power transistor N1 by providing a scaled copy of the power transistor N1 and a reference resistor Rset, connected in such a way that a copy of the feedback loop is formed between the operational amplifier 130 and the power transistor N1, and connected to a transmission gate controlled by a negated version of the control signal CTRL (i.e., a version thereof having a phase difference of 180°). Summary of the invention

[0016] The Applicant has found that the above-mentioned known solutions for controlling LEDs with a current having a reduced slew rate suffer from several disadvantages.

[0017] Firstly, according to the known solutions, although the slew rate is reduced, the actual speed / duration of the rising / falling edge cannot be controlled, which is always fixed for a given current value and therefore cannot be scaled to meet the requirements of a specific application, regardless of the actual value of the current.

[0018] Furthermore, the fast current rising / falling edges obtained using known solutions may result in undesirable electromagnetic interference (EMI).

[0019] In view of the above, the applicant has devised a solution for resolving or at least reducing the above-mentioned disadvantages.

[0020] Aspects of the present invention relate to an LED driver system adapted to be coupled to an LED array for driving the LED array, the LED driver system comprising:

[0021] - a power transistor configured to be selectively enabled for generating a drive current for the LED array, the power transistor having a first conductive terminal coupled to the LED array and a second conductive terminal coupled to the reference resistor;

[0022] an operational amplifier having a non-inverting input terminal for receiving a reference voltage, an inverting input terminal coupled to a second conductive terminal of the power transistor, and an output terminal coupled to a first conductive terminal of a transmission gate, the transmission gate having a second conductive terminal coupled to a control terminal of the power transistor and a control terminal for receiving an enable signal, the first conductive terminal and the second conductive terminal of the transmission gate being electrically connected to each other when the enable signal is at an enable value to cause activation of the power transistor, and being electrically insulated from each other when the enable signal is at a disable value to cause deactivation of the power transistor; and

[0023] a slew rate control unit configured to control the slew rate of the drive current, the slew rate control unit being configured to selectively charge the equivalent capacitance at the control terminal of the power transistor by a charging current and to selectively discharge the equivalent capacitance by a discharging current, the charging current and the discharging current being at least partially dependent on a target value of the drive current.

[0024] According to an embodiment of the present invention, the slew rate control unit is configured in this way to perform the following operations:

[0025] - during a first operating phase of the slew rate control unit, setting the charging current to a first charging value different from zero and independent of the target value,

[0026] - during a second operating phase following the first operating phase of the slew rate control unit, setting the charging current to a second charging value different from zero and depending on the target value;

[0027] - during a third operation phase following the second operation phase of the slew rate control unit, setting the charging current to zero;

[0028] - during a fourth operation phase following the third operation phase of the slew rate control unit, setting the discharge current to a discharge value different from zero and depending on the target value; and

[0029] - During a fifth operation phase following the fourth operation phase of the slew rate control unit, the discharge current is set to zero.

[0030] According to an embodiment of the present invention, the second charging value corresponds to multiplying the target value by a first proportionality coefficient.

[0031] According to an embodiment of the present invention, the slew rate control unit is further configured to set the duration of the rising edge of the drive current during the second operation phase to a value corresponding to the second proportionality factor multiplied by the ratio between the target value and the second charge value.

[0032] According to an embodiment of the present invention, the discharge value is multiplied by the target value by a third proportional coefficient.

[0033] According to an embodiment of the present invention, the slew rate control unit is further configured to set the duration of the falling edge of the drive current during the fourth operation phase to a value corresponding to a fourth proportionality factor multiplied by a ratio between the target value and the discharge value.

[0034] According to an embodiment of the present invention, the slew rate control unit is configured to set the enable signal to a disable value during the first operation phase, the second operation phase, the fourth operation phase and the fifth operation phase.

[0035] According to an embodiment of the present invention, the slew rate control unit is configured to set the enable signal to the enable value during the third operation phase.

[0036] According to an embodiment of the present invention, the LED driver system further includes a first current mirror configured to output a reference current and a control current according to the external current.

[0037] According to an embodiment of the present invention, the reference voltage depends on the reference current.

[0038] According to an embodiment of the present invention, the charging current and the discharging current depend on the control current.

[0039] According to an embodiment of the present invention, the slew rate control unit includes a second current mirror configured to generate the discharge current during the fourth operation phase according to the control current.

[0040] According to an embodiment of the present invention, the slew rate control unit comprises a third current mirror configured to generate the charging current during the second operation phase according to the control current.

[0041] According to an embodiment of the present invention, the first proportionality coefficient and the third proportionality coefficient depend on mirror ratios of the first current mirror, the second current mirror and the third current mirror.

[0042] According to an embodiment of the present invention, the second proportionality coefficient and the fourth proportionality coefficient depend on a reference resistor.

[0043] According to an embodiment of the present invention, during the first operation phase and the fifth operation phase, the power transistor is turned off.

[0044] According to an embodiment of the present invention, the slew rate control unit is configured to perform the following operations:

[0045] - switching from the first operating phase to the second operating phase when the voltage at the control terminal of the power transistor increases to such an extent that the power transistor is switched on, and

[0046] - Switching from the fourth operating phase to the fifth operating phase occurs when the voltage at the control terminal of the power transistor decreases to such an extent that the power transistor is switched off.

[0047] According to an embodiment of the invention, the slew rate control unit is configured such that the charging current increases the voltage at the control terminal of the power transistor from a first voltage value to a second voltage value corresponding to a threshold voltage of the power transistor during the first operation phase.

[0048] According to an embodiment of the invention, the slew rate control unit is configured such that the charging current increases the voltage at the control terminal of the power transistor from the second voltage value to a third voltage value during the second operation phase.

[0049] According to an embodiment of the invention, the slew rate control unit is configured such that during the third operation phase, the voltage at the control terminal of the power transistor is maintained at a third voltage value.

[0050] According to an embodiment of the invention, the slew rate control unit is configured such that the discharge current reduces the voltage at the control terminal of the power transistor from the third voltage value to the second voltage value during the fourth operation phase.

[0051] According to an embodiment of the invention, the slew rate control unit is configured such that during the fifth operation phase, the voltage at the control terminal of the power transistor is maintained at the first voltage value.

[0052] According to an embodiment of the present invention, the third voltage is such as to cause the power transistor to generate a drive current having a target value.

[0053] Another aspect of the invention relates to an electronic system that includes one or more LED driver systems and a corresponding LED array coupled to the one or more LED driver systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] These and other features and advantages of the solution according to the invention will be better understood by reading the following detailed description of its embodiments, which is provided below by way of non-limiting example only and is to be read in conjunction with the accompanying drawings. In this regard, it is expressly intended that the drawings be used simply to conceptually illustrate the structures and processes described. Specifically:

[0055] Figure 1 illustrates an LED driver system according to a solution known in the art;

[0056] Figure 2 An LED driver system according to an embodiment of the present invention is illustrated;

[0057] Figure 3A FIG. 1 shows a flow chart of a first set of operation phases according to an embodiment of the present invention. Figure 2 A simplified depiction of a slew rate control unit of the LED driver system shown in FIG.

[0058] Figure 3B illustrates a time diagram of voltage and current in an LED driver system during a first set of operating phases according to an embodiment of the present invention;

[0059] Figure 4A FIG. 1 shows a flow chart of ... during a second set of operation phases according to an embodiment of the present invention. Figure 2 A simplified depiction of a slew rate control unit of the LED driver system shown in FIG.

[0060] Figure 4Billustrates a time diagram of voltage and current in an LED driver system during a second set of operating phases according to an embodiment of the present invention;

[0061] Figure 5 An exemplary implementation of a slew rate control unit according to an embodiment of the present invention is illustrated in detail;

[0062] FIG. 6A to FIG. 6E The present invention is shown in FIG. Figure 5 The slew rate control unit is Figure 3A and Figure 3B How to operate during the operating phases illustrated in FIG.

[0063] Fig. 7A illustrates exemplary simulation results of how a drive current generated by an LED driver system according to an embodiment of the present invention rises to two different target values;

[0064] Figure 7B illustrates exemplary simulation results of how a drive current generated by an LED driver system according to an embodiment of the present invention drops from two different target values;

[0065] Fig. 8A and Figure 8B illustrates exemplary simulation results of how the duration of a rising edge of a driving current and the duration of a falling edge of a driving current may be set according to an embodiment of the present invention; and

[0066] Fig. 9 An electronic system including an LED driver system for driving an LED array according to an embodiment of the present invention is illustrated in simplified block form. DETAILED DESCRIPTION

[0067] Figure 2 1 is a diagram illustrating an LED driver system 200 configured to drive an LED array 102 according to an embodiment of the present invention. Figure 1 Elements of the LED driver system 100 that are common to the LED driver system 200 are identified by the same reference numerals, and descriptions thereof are omitted for the sake of brevity.

[0068] and Figure 1 Compared with the known LED driver system 100 , the LED driver system 200 according to the embodiment of the present invention comprises a slew rate control unit 210 adapted to control the slew rate of the driving current Iset generated by the LED driver system 200 for driving the LED array 102 .

[0069] According to an embodiment of the present invention, the slew rate control unit 210 has: an input terminal for receiving a control signal CTRL; an input terminal coupled to the non-inverting terminal of the operational amplifier 130 for receiving a reference voltage Vref; and an input terminal coupled to the inverting terminal of the operational amplifier 130 for receiving a feedback voltage FDB.

[0070] According to an embodiment of the present invention, the slew rate control unit 210 is configured to set the duration of the rising edge and the falling edge of the drive current Iset independently of the value of the drive current Iset by appropriately charging / discharging the equivalent (e.g., parasitic) capacitance C at the gate terminal of the power transistor N1 through an appropriate charging current Ich and an appropriate discharging current Idsch. Therefore, according to an embodiment of the present invention, the slew rate control unit 210 has an output terminal, which is coupled to the gate terminal of the power transistor N1 and is configured to selectively provide the charging current Ich and the discharging current Idsch. According to an embodiment of the present invention, and as will be described in detail below, the slew rate control unit 210 is configured to generate the charging current Ich and the discharging current Idsch according to the control current Ic provided by the current mirror 120 and depending on the target value of the drive current Iset.

[0071] According to an embodiment of the present invention, the slew rate control unit 210 is configured to generate an enable signal ENA to be used instead of the control signal CTRL for driving the opening and closing of the transmission gate TG1 .

[0072] According to an embodiment of the present invention, by referring to Figure 3A A simplified depiction of the slew rate control unit 210 shown in FIG. Figure 3B , the slew rate control unit 210 is configured to set the duration Tr of the rising edge of the drive current Iset by charging the equivalent capacitance C at the gate terminal of the power transistor N1 by the charging current Ich generated in the following manner:

[0073] - In the first stage ( Figure 3B During the period (indicated by reference symbol ph1 in FIG), the charging current Ich is set by the slew rate control unit 210 to a value Ichc that is independent of the value of the target drive current Iset; and

[0074] - In the second stage ( Figure 3B During the period (indicated by reference symbol ph2 in FIG. 1 ), the charging current Ich is set by the slew rate control unit 210 to a value Ichv that depends on the target value Iset(h) of the driving current Iset.

[0075] According to an embodiment of the present invention, during the first phase ph1, the voltage Vo at the gate terminal of the power transistor N1 rises from the ground voltage to a value where the voltage difference Vgs across the gate terminal and the source terminal of the power transistor N1 reaches the threshold voltage Vth of the power transistor N1 (i.e., rises until the power transistor N1 is turned on).

[0076] According to an embodiment of the invention, during the second phase ph2 , the voltage Vo rises until it reaches a value such that the drive current Iset reaches the value Iset(h).

[0077] According to an embodiment of the present invention, the slew rate control unit 210 sets the value Ichv taken by the charging current Ich in the second phase ph2 to a value that depends on the (target) value Iset(h).

[0078] As will be described in more detail in the following of this specification, according to an embodiment of the present invention, the slew rate control unit 210 is configured to set the value Ichv taken by the charging current Ich in the second phase ph2 to a value proportional to the (target) value Iset(h), namely:

[0079] Ichv=A×Iset(h) (1)

[0080] Where A is the proportionality factor.

[0081] According to an embodiment of the present invention, the higher the value Iset(h) of the drive current Iset, the higher the value Ichv of the charging current Ich in the second phase ph2, and thus the faster the equivalent capacitance C is charged.

[0082] As will be described in more detail below in this specification, according to an embodiment of the present invention, the slew rate control 210 is configured to set the duration Tr of the rising edge of the drive current Iset (from the value Iset(l) to the value Iset(h)) to a value that is proportional to the (target) value Iset(h) and inversely proportional to the value Ichv taken by the charging current Ich in the second phase ph2, i.e.:

[0083]

[0084] Where B is the proportionality factor.

[0085] Therefore, according to an embodiment of the present invention, the resulting duration Tr of the rising edge of the drive current Iset from the value Iset(l) to the value Iset(h) can be advantageously set independently of the value Iset(h) of the drive current Iset, i.e., by combining equations (1) and (2):

[0086] Tr=B / A (3)

[0087] In other words, the slew rate control unit 210 according to the embodiment of the present invention allows obtaining the same duration Tr of the rising edge of the drive current Iset for different values ​​Iset(h). It must be understood that the duration Tr of the rising edge of the drive current Iset according to the embodiment of the present invention is equal to the duration of the second phase ph2.

[0088] exist Figure 3B In the exemplary time diagram illustrated in FIG. 1 , two exemplary cases are shown, namely a first case where the drive current Iset rises from a value Iset(l) to a value Iset(h)(1), and a second case where the drive current Iset rises from the same value Iset(l) to a value Iset(h)(2) higher than Iset(h)(1). During the first phase ph1, in both cases, the charging current Ich is set by the slew rate control unit 210 to the same value Ichc.

[0089] In the first case, during the second phase ph2, the charging current Ich is set by the slew rate control unit 210 to a value Ichv(1) that depends on the value Iset(h)(1) so that the voltage Vo reaches the value Vo(1) within a time period equal to Tr, thereby causing the drive current Iset to rise until Iset(h)(1).

[0090] In the second case, during the second phase ph2, the charging current Ich is set by the slew rate control unit 210 to a value Ichv(2) that depends on the value Iset(h)(2) so that the voltage Vo reaches the value Vo(2) (higher than Vo(1)) within the same time period equal to Tr, thereby causing the drive current Iset to rise until Iset(h)(2) (higher than Iset(h)(2)).

[0091] According to an embodiment of the present invention, the slew rate control unit 210 keeps the enable signal ENA at a low value during both the first phase ph1 and the second phase ph2, thereby keeping the transmission gate TG1 open. At the beginning of the third phase ph3 after the second phase ph2, i.e., once the voltage Vo at the gate terminal of the power transistor N1 reaches a value that makes the drive current Iset reach the (target) value Iset(h), the slew rate control unit 210 switches the enable signal ENA to a high value, thereby closing the transmission gate TG1.

[0092] In this way, with a voltage Vo that is very close to the voltage Vi, the transition between the open-loop condition (transmission gate TG1 open) and the closed-loop condition (transmission gate TG1 closed) is performed smoothly.

[0093] According to an embodiment of the present invention, by referring to Figure 4AA simplified depiction of the slew rate control unit 210 shown in FIG. Figure 4B , the slew rate control unit 210 is configured to set the duration Tf of the falling edge of the drive current Iset by discharging the equivalent capacitance C at the gate terminal of the power transistor N1 with the discharge current Idsch in the following manner:

[0094] - In the fourth stage ( Figure 4B During the period (indicated by reference symbol ph4 in FIG. 1 ), the discharge current Idsch is set by the slew rate control unit 210 to a value Idschv that depends on the (target) value Iset(h) of the drive current Iset.

[0095] According to an embodiment of the present invention, during the fourth stage ph4, the voltage Vo drops from a value causing the drive current Iset to have a value Iset(h) to a value causing the voltage difference Vgs across the gate terminal and the source terminal of the power transistor N1 to reach a threshold voltage Vth of the power transistor N1, thereby turning off the power transistor N1.

[0096] According to an embodiment of the present invention, the slew rate control unit 210 sets the value Idschv to a value that depends on the (target) value Iset(h).

[0097] As will be described in more detail in the following content of this specification, according to an embodiment of the present invention, the slew rate control unit 210 is configured to set the value Idschv taken by the discharge current Idsch in the fourth phase ph4 to a value proportional to the (target) value Iset(h), namely:

[0098] Idschv=A′×Iset(h) (4)

[0099] Where A' is a proportionality coefficient, for example, equal to coefficient A in equation (1).

[0100] According to an embodiment of the present invention, the higher the value Iset(h) of the drive current Iset is, the higher the value Idschv of the discharge current Idsch in the fourth phase ph4 is, and therefore, the faster the discharge speed of the equivalent capacitance C is.

[0101] As will be described in more detail in the following content of this specification, according to an embodiment of the present invention, the slew rate control 210 is configured to set the duration Tf of the rising edge of the drive current Iset (from the value Iset(h) to the value Iset(l)) to a value that is proportional to the value Iset(h) and inversely proportional to the value Ichv taken by the discharge current Idsch in the fourth phase ph4, that is:

[0102]

[0103] Wherein B' is a proportionality coefficient, for example, equal to the coefficient B of equation (2).

[0104] Therefore, according to an embodiment of the present invention, the resulting duration Tf of the falling edge of the drive current Iset from the value Iset(h) to the value Iset(l) can be advantageously set independently of the value Iset(h) of the drive current Iset, i.e. by combining equations (4) and (5):

[0105] Tr=B′ / A′ (6)

[0106] In other words, the slew rate control unit 210 according to an embodiment of the present invention allows obtaining the same duration Tf of the falling edge of the drive current Iset for different values ​​Iset(h). It must be understood that the duration Tf of the falling edge of the drive current Iset according to an embodiment of the present invention is equal to the duration of the fourth phase ph4. According to an embodiment of the present invention, the duration Tf of the falling edge is equal to the duration Tr of the rising edge.

[0107] exist Figure 4B In the exemplary time diagram illustrated in , two exemplary situations are shown, namely, a first situation in which the driving current Iset drops from a value Iset(h)(1) to a value Iset(l) and a second situation in which the driving current Iset drops from a value Iset(h)(2) (higher than Iset(h)(1)) to a value Iset(l).

[0108] In the first case, during the fourth phase ph4, the discharge current Idsch is set by the slew rate control unit 210 to a value Idschv(1) that depends on the value Iset(h)(1) so that the voltage Vo drops from the value Vo(1) to the threshold voltage value Vth within a time period equal to Tf.

[0109] In the second case, during the fourth phase ph4, the discharge current Idsch is set by the slew rate control unit 210 to a value Idschv(2) that depends on the value Iset(h)(2) so that the voltage Vo drops from the value Vo(2) (higher than Vo(1)) to the threshold voltage value Vth within the same time period equal to Tf.

[0110] According to an embodiment of the present invention, the slew rate control unit 210 switches the enable signal ENA to a low value at the beginning of the fourth phase ph4 , thereby turning on the transmission gate TG1 .

[0111] In this way, with a voltage Vo that is very close to the voltage Vi, the transition between the closed-loop condition (transmission gate TG1 closed) and the open-loop condition (transmission gate TG1 open) is performed smoothly.

[0112] According to an embodiment of the present invention, as soon as the power transistor N1 is turned off, the voltage Vo is pulled down by the pull-down circuit (at Figure 4A The voltage at the input of the transistor PH5 is not visible in the figure) and reaches the ground voltage and is maintained at the ground voltage during the subsequent fifth phase ph5.

[0113] At this point, after phase ph5 expires, the process is repeated and the first phase ph1 begins again.

[0114] Re-assuming the slew rate control unit 210 with respect to the embodiment of the present invention, the resulting drive current Iset oscillates between:

[0115] - low values ​​of Iset(l) at phases ph1 and ph5, and

[0116] a high value Iset(h) at phase ph3 (in the illustrated example, Iset(h)(1) or Iset(h(2)),

[0117] Therein, the rising edge has a duration Tr which corresponds to the duration of phase ph2 and the falling edge has a duration Tf which corresponds to the duration of phase ph4 .

[0118] Figure 5 An exemplary implementation of the slew rate control unit 210 according to an embodiment of the present invention is illustrated in detail.

[0119] According to an embodiment of the present invention, the slew rate control unit 210 includes a first current generator unit, which includes a current mirror CM1, which has: an input terminal, which is connected to the bias current generator Ibias; and an output terminal, which provides a corresponding first operating charging current Ichc, which has a value corresponding to the value Ichc (which is independent of the driving current Iset) according to the current generated by the bias current generator Ibias.

[0120] According to an embodiment of the present invention, the slew rate control unit 210 further includes a second generator unit including a current mirror CM2 and a current mirror CM3. According to an embodiment of the present invention, the current mirror CM2 includes: an input terminal coupled to the current mirror 120 for receiving a control current Ic; a first output terminal for providing a discharge current Idsch according to the received control current Ic; and a second output terminal for providing a current Ix to an input terminal of the current mirror CM3 according to the received control current Ic. According to an embodiment of the present invention, the current mirror CM3 has an output terminal for providing a second operating charging current Ichv having a value corresponding to the value Ichv according to the current Ix (depending on the target value Iset(h) of the drive current Iset).

[0121] According to an embodiment of the present invention, current mirrors 120 , CM1 , CM2 , CM3 are configured in the following manner.

[0122] - Current mirror 120:

[0123]

[0124] - Current mirror CM1:

[0125] Ichc=p×Ibias

[0126] - Current mirror CM2:

[0127] Idschv=m×Ic,Ix=Ic

[0128] - Current mirror CM3:

[0129] Ichv=m×Ix where h, k, m, n, and p are mirror parameters that form the mirror ratio of the current mirror.

[0130] According to an embodiment of the present invention, the slew rate control unit 210 includes a current switch arrangement including four current switching elements M1 to M4 and a transmission gate TG2 .

[0131] According to an embodiment of the present invention, the current switching element M1 includes a transistor, such as a p-type MOS transistor, having: a first conductive terminal (e.g., a source) coupled to the output terminal of the current mirror CM1 for receiving the first operating charging current Ichc; a second conductive terminal (e.g., a drain) connected to the first conductive terminal of the transmission gate TG2 (defining the circuit node 505); and a control terminal (e.g., a gate) connected to the first charging current control unit 510.

[0132] According to an embodiment of the present invention, the current switching element M2 includes a transistor, such as a p-type MOS transistor, having: a first conductive terminal (e.g., a source), coupled to the output terminal of the current mirror CM3, for receiving the second operating charging current Ichv; a second conductive terminal (e.g., a drain), connected to the circuit node 505; and a control terminal (e.g., a gate), connected to the second charging current control unit 520.

[0133] According to an embodiment of the present invention, the current switching element M3 includes a transistor, such as an n-type MOS transistor, having: a first conductive terminal (e.g., a drain), connected to the circuit node 505; a second conductive terminal (e.g., a source), connected to the output terminal of the current mirror CM2 for receiving the discharge current Idsch; and a control terminal (e.g., a gate), connected to the discharge current control unit 530.

[0134] According to an embodiment of the present invention, the current switching element M4 includes a transistor, such as an n-type MOS transistor, which has: a first conductive terminal (e.g., a drain), connected to the circuit node 505; a second conductive terminal (e.g., a source), connected to the ground terminal GND; and a control terminal (e.g., a gate), connected to the discharge current control unit 530.

[0135] According to an embodiment of the present invention, the slew rate control unit 210 also includes a reference power transistor N2, such as an n-type power MOS transistor, which has the same or similar size as the power transistor N1 and includes: a first conductive terminal (e.g., a source), connected to the ground terminal GND; a control terminal (e.g., a gate), coupled to the gate terminal of the power transistor N1 for receiving the voltage Vo; and a second conductive terminal (e.g., a drain), coupled to the bias current generator Ibias'.

[0136] According to an embodiment of the present invention, the first charging current control unit 510 , the second charging current control unit 520 , and the discharging current control unit 530 have corresponding input terminals for receiving the voltage V2 at the drain terminal of the reference power transistor N2 .

[0137] According to an embodiment of the present invention, the first charging current control unit 510 , the second charging current control unit 520 , and the discharging current control unit 530 have further corresponding input terminals for receiving the control signal CTRL.

[0138] According to an embodiment of the invention, the transmission gate TG2 has a second conduction terminal connected to the gate terminal of the power transistor N1 (and thus to the second conduction terminal of the transmission gate TG1 ) and a control terminal for receiving a negated version of the enable signal ENA.

[0139] According to an embodiment of the present invention, the slew rate control unit 210 also includes a comparator 540 having: a non-inverting input terminal connected to the inverting input terminal of the operational amplifier 130; an inverting input terminal connected to the non-inverting input terminal of the operational amplifier 130; and an output terminal connected to the input terminal of the second charging current control unit 520.

[0140] According to an embodiment of the present invention, the slew rate control unit 210 also includes an enable signal generator 550, which is adapted to generate an enable signal ENA based on the output signal Va generated by the first charging current control unit 510, the output signal Vb generated by the second charging current control unit 520, and based on the output signal Vc generated by the discharge current control unit 530.

[0141] FIG. 6A to FIG. 6E The present invention is shown in FIG. Figure 5 The slew rate control unit 210 is Figure 3A and Figure 3B How to operate during the stages ph1 to ph5 shown in the figure;

[0142] According to an embodiment of the present invention, the start condition provides that the control signal CTRL is at a low value, the enable signal ENA is at a low value, the power transistors N1 and N2 are turned off, the transmission gate TG1 is open, the transmission gate TG2 is closed, the voltage V2 at the drain terminal of the reference power transistor N2 is high, and the feedback voltage FDB is lower than the reference voltage Vref, so that the output of the comparator 540 is at a low value. In addition, the starting condition stipulates that the transistors M1, M2, M3 and M4 are turned off, and the drive current Iset is at a value Iset(l) (zero).

[0143] According to an embodiment of the present invention, phase ph1 (see Fig. 6A ) is triggered by the control signal CTRL having switched to a high value, to signal that the transmission gate TG1 is to be closed. However, according to an embodiment of the invention, instead of directly closing the transmission gate TG1 as soon as the control signal CTRL switches to a high value, a precharging of the equivalent capacitance C at the gate terminal of the power transistor N1 is performed, the first part of which corresponds to the phase ph1.

[0144] Specifically, according to an embodiment of the present invention, when the control signal CTRL is switched to a high value and the voltage V2 is at a high value, the first charging current control circuit 510 turns on the transistor M1, thereby causing the charging current Ich corresponding to the first operating charging current Ichc, i.e., having a value corresponding to the value Ichc, which is independent of the drive current Iset, to flow from the current mirror CM1 to the equivalent capacitor C through the transistor M1 and the transmission gate TG2. As a result, the equivalent capacitor C is charged, and the voltage Vo is increased at a rate corresponding to the value of the first operating charging current Ichc.

[0145] According to an embodiment of the present invention, when the voltage Vo reaches a value that enables the activation of the power transistor N1 and the reference power transistor N2, the phase ph2 (see Figure 6B) is triggered. According to an embodiment of the present invention, as soon as the reference power transistor N2 is turned on and the voltage V2 drops to a low value, the first charging current control circuit 510 turns off the transistor M1, while the second charging current control circuit 520 turns on the transistor M2. In this way, a charging current Ich corresponding to the second operating charging current Ichv - that is, having a value corresponding to the value Ichv, which depends on the target value Iset(h) of the drive current Iset (see equation (1)) - is caused to flow from the current mirror CM3 through the transistor M2 and the transmission gate TG2 to the equivalent capacitor C. As a result, the equivalent capacitor C is also charged and the voltage Vo is also increased, this time at a rate corresponding to the value of the second operating charging current Ichv, which in turn depends on the target value Iset(h) of the drive current Iset. During the second phase ph2, the drive current Iset begins to rise at a rate that depends on the second operating charging current Ichv.

[0146] According to an embodiment of the present invention, when the feedback voltage FDB becomes higher than the reference voltage Vref, the phase ph3 (see Figure 6C ) is triggered so that the output of the comparator 540 becomes a high value. In this case, the second charging current control circuit 520 turns off the transistor M2, thereby ending the pre-charging of the equivalent capacitor C, and the enable signal generator 550 is driven for switching the enable signal ENA to a high value, so that the transmission gate TG2 is opened and the transmission gate TG1 is closed, thereby establishing a feedback loop involving the operational amplifier 130 and the power transistor N1 and causing the drive current Iset to take the target value Iset(h).

[0147] According to an embodiment of the present invention, stage ph4 (see Fig.6D ) is triggered by the control signal CTRL having been switched to a low value. In this case, the enable signal generator 550 is driven by the control signal CTRL for switching the enable signal ENA to a low value - so that the transmission gate TG1 is opened and the transmission gate TG2 is closed - and the discharge current control unit 530 switches on the transistor M3. It is therefore the discharge current Idsch - i.e. having a value corresponding to the value Idschv, which depends on the (target) value Iset(h) of the drive current Iset (see equation (4)) - that flows from the equivalent capacitor C to the current mirror CM2 via the transmission gate TG2 and the transistor M3.

[0148] Therefore, the equivalent capacitance C is discharged and the voltage Vo is reduced at a rate corresponding to the value of the discharge current Idsch which in turn depends on the target value Iset(h) of the drive current Iset.During phase ph4, the drive current Iset starts to decrease at a rate depending on the discharge current Idsch.

[0149] According to an embodiment of the present invention, when the voltage Vo decreases to a level that turns off the power transistor N1 and the reference power transistor N2, the phase ph5 (see Fig. 6E ) is triggered. In this case, the voltage V2 is at a low value, and the discharge current control unit 530 turns off the transistor M3 and turns on the transistor M4, thereby pulling the voltage Vo down to the ground voltage. Therefore, the drive current Iset is at the value Iset(1) (zero).

[0150] According to an embodiment of the present invention, the target value Iset(h) of the drive current Iset corresponds to the value Vref of the reference voltage Vref divided by the resistance Rset of the reference resistor Rset:

[0151]

[0152] The value Vref of the reference voltage Vref corresponds to the value Iref of the reference current Iref multiplied by the resistance Rd of DAC125:

[0153] Vref=Iref×Rd (8)

[0154] The value Iref of the reference current Iref in turn corresponds to the mirror ratio h / n of the current mirror 120 multiplied by the value Vbuff of the voltage Vbuff divided by the resistance Rext of the external resistor Rext:

[0155]

[0156] The value Ic of the control current Ic provided by the current mirror 120 corresponds to the mirror ratio k / n of the current mirror 120 multiplied by the value Vbuff of the voltage Vbuff divided by the resistance Rext of the external resistor Rext:

[0157]

[0158] During the second phase ph2, the value Ichv of the second operating charging current Ichv provided by the slew rate control unit 210 corresponds to the mirror ratio m of the current mirror CM3 multiplied by the value Ic of the control current Ic.

[0159] Ichv=m×Ic (11)

[0160] By combining equations (10) and (11), the value Ichv of the second operating charging current Ichv provided by the slew rate control unit 210 during the second phase ph2 according to an embodiment of the present invention can be expressed as a function of the reference current Iref:

[0161]

[0162] By combining equations (8), (10) and (11), the target value Iset(h) of the drive current Iset can be expressed as a function of the value Ic of the control current Ic, or as a function of the value Ichv of the second operating charging current Ichv provided by the slew rate control unit 210 during the second phase ph2:

[0163]

[0164] Therefore, by combining equations (1) and (13), we can obtain:

[0165]

[0166] That is, the proportionality coefficient A of equation (1) is equal to

[0167] To illustrate in more detail how the slew rate control unit 210 according to an embodiment of the present invention sets the duration Tr of the rising edge of the driving current Iset (from the value Iset(l) to the value Iset(h)), the following is considered.

[0168] During the first phase ph1, the voltage Vo at the gate terminal of the power transistor N1 rises until it reaches a value corresponding to the threshold voltage Vth of the power transistor N1:

[0169] Vo=Vgs=Vth (15)

[0170] In the second phase ph2, the voltage Vo rises until it reaches a value that causes the drive current Iset to reach the target value Iset(h):

[0171] Vo=Vgs+ΔV=Vgs+(Rset×Iset(h)) (16)

[0172] Therefore, during the second phase ph2, the equivalent capacitance C is charged during the time period corresponding to the duration Tr of the rising edge to experience a voltage change ΔV=Rset×Iset(h), where:

[0173]

[0174] Therefore, by combining equations (2) and (17), we can obtain:

[0175]

[0176] That is, the proportionality coefficient B of equation (2) is equal to (C×Rset).

[0177] As can be seen in equation (18), the duration Tr of the rising edge increases as the value Ichv decreases, and vice versa.

[0178] Furthermore, by combining equations (14) and (18), we can derive:

[0179]

[0180] As shown in equation (19) (and equation (3)), the slew rate control unit 210 according to an embodiment of the present invention allows the duration Tr of the rising edge of the drive current Iset to be advantageously set for different target values ​​Iset(h) of the drive current Iset, because equation (19) (and equation (3)) does not provide dependence on the target value Iset(h).

[0181] Furthermore, according to the embodiment of the present invention, the duration Tr of the rising edge of the driving current Iset can be easily set by appropriately varying the mirror parameters h, k, and m.

[0182] Similarly, during the fourth phase ph4, the value Idschv of the discharge current Idsch provided by the slew rate control unit 210 corresponds to the mirror ratio m of the current mirror CM2 multiplied by the value Ic of the control current Ic.

[0183] Idschv=m×Ic (20)

[0184] By combining equations (10) and (20), the value Idschv of the discharge current Idschv provided by the slew rate control unit 210 during the fourth phase ph4 according to an embodiment of the present invention can be expressed as a function of the reference current Iref:

[0185]

[0186] By combining equations (8), (20) and (21), the target value Iset(h) of the drive current Iset can be expressed as a function of the value Ic of the control current Ic or as a function of the value Idschv of the discharge current Idschv provided by the slew rate control unit 210 during the fourth phase ph4:

[0187]

[0188] Therefore, by combining equations (4) and (22), we can obtain:

[0189]

[0190] That is, the proportionality coefficient A' of equation (4) is equal to

[0191] To illustrate in more detail how the slew rate control unit 210 according to an embodiment of the present invention sets the duration Tf of the falling edge of the driving current Iset (from the value Iset(h) to the value Iset(l)), the following is considered.

[0192] During the third phase ph3, the voltage Vo at the gate terminal of the power transistor N1 is at a value such that the drive current Iset has a value corresponding to the target value Iset(h):

[0193] Vo=Vgs+ΔV=Vgs+(Rset×Iset(h)) (24)

[0194] During the fourth phase ph4, the equivalent capacitance C is discharged during the time period corresponding to the duration Tf of the falling edge to undergo a voltage change ΔV=Rset×Iset(h) so that the voltage Vo reaches a value corresponding to the threshold voltage Vth of the power transistor. Therefore, the following equation is obtained:

[0195]

[0196] By combining equations (5) and (25), we can obtain:

[0197]

[0198] That is, the proportionality coefficient B' of equation (4) is equal to (C x Rset).

[0199] As can be seen in equation (26), the duration Tf of the falling edge increases as the value Idschv decreases, and vice versa.

[0200] Furthermore, by combining equations (23) and (26), we can derive:

[0201]

[0202] As shown in equation (27) (and equation (6)), the slew rate control unit 210 according to an embodiment of the present invention allows the duration Tf of the falling edge of the drive current Iset to be advantageously set for different target values ​​Iset(h) of the drive current Iset, because equation (27) (and equation (6)) does not provide a dependency on the target value Iset(h).

[0203] Furthermore, according to the embodiment of the present invention, the duration Tf of the falling edge of the driving current Iset can be easily set by appropriately varying the mirror parameters h, k, and m.

[0204] As can be seen by comparing equations (19) and (27), slew rate control unit 210 is advantageously configured to allow symmetrical rising and falling edges, ie, with Tr equal to Tf.

[0205] Fig. 7A FIG. 2 shows exemplary simulation results of how the driving current Iset rises from a value Iset(l)=0A to a value Iset(h)(1)=100mA or a value Iset(h)(2)=200mA using the slew rate control unit 210 according to an embodiment of the present invention, and Figure 7B The diagram illustrates how the drive current Iset decreases from a value Iset(h)(1)=100 mA or a value Iset(h)(2)=200 mA to a value Iset(l)=0 A using a slew rate control unit 210 according to an embodiment of the present invention. The portion corresponding to the rising edge of phase ph1 (during which the equivalent capacitance C is charged with a charging current Ich having a value independent of the drive current Iset) is shown in FIG. Fig. 7A The portion corresponding to the rising edge of phase ph2 (during which the equivalent capacitance C is charged with a charging current Ich having a value depending on the value Iset(h) of the drive current Iset) is marked with reference numeral 710 in FIG. Fig. 7A 720 in the figure, and corresponds to the falling edge of phase ph4 at Figure 7B Identified by reference numeral 730 in FIG.

[0206] As can be seen in the figure, even though the value Iset(h)(2) is twice the value Iset(h)(1), the duration Tr of the rising edge of the drive current Iset and the duration Tf of the falling edge of the drive current Iset are the same.

[0207] In other words, due to the proposed solution, the same duration Tr and / or Tf of the rising and / or falling edges of the drive current Iset can be set for different values ​​Iset(h), i.e. the duration Tr and / or Tf of the rising and / or falling edges of the drive current Iset can be set independently of the actual value of the drive current Iset.

[0208] Furthermore, compared to known solutions, too fast current rising / falling edges are avoided which could potentially lead to undesired electromagnetic interference (EMI).

[0209] Fig. 8A and Figure 8B Exemplary simulation results are illustrated showing how the duration Tr of the rising edge of the drive current Iset and the duration Tf of the falling edge of the drive current Iset vary with changes in the mirror parameters h, k, and m.

[0210] Fig. 9An electronic system 900 (or a portion thereof) including at least one LED driver system 200 for driving an LED array 102 according to the embodiments of the present invention described above is illustrated in simplified block form.

[0211] According to an embodiment of the present invention, the electronic system 900 is adapted to be used in electronic devices such as, for example, personal digital assistants, computers, tablet computers, and smart phones.

[0212] According to an embodiment of the present invention, in addition to the LED driver system 200 , the electronic system 900 may further include a controller 905 , such as, for example, one or more microprocessors and / or one or more microcontrollers.

[0213] According to an embodiment of the present invention, in addition to the LED driver system 200, the electronic system 900 may also include an input / output device 910 (such as, for example, a keyboard and / or a touch screen and / or a visual display) for generating / receiving messages / commands / data, and / or for receiving / sending digital and / or analog signals.

[0214] According to an embodiment of the present invention, in addition to the LED driver system 200, the electronic system 900 may further include a wireless interface 915 for exchanging messages with a wireless communication network (not shown), for example, via radio frequency signals. Examples of the wireless interface 915 may include an antenna and a wireless transceiver.

[0215] According to an embodiment of the present invention, in addition to the LED driver system 200 , the electronic system 900 may further include a storage device 920 , such as, for example, a volatile and / or non-volatile memory device.

[0216] According to an embodiment of the present invention, the electronic system 900 may further include a supply device, such as a battery 925 , for supplying power to the electronic system 900 in addition to the LED driver system 200 .

[0217] According to an embodiment of the present invention, the electronic system 900 may include one or more communication channels (buses) to allow data exchange between the LED driver system 200 and the controller 905 and / or the input / output device 910 and / or the wireless interface 915 and / or the storage device 920 and / or the battery 925 (when they are present).

[0218] Naturally, in order to meet local and specific requirements, a person skilled in the art may apply many logical and / or physical modifications and changes to the solutions described above. More specifically, although the present invention has been described with a certain degree of specificity with reference to the preferred embodiments of the present invention, it should be understood that various omissions, substitutions and changes in form and details and other embodiments are possible. Specifically, different embodiments of the present invention may be practiced even without the specific details set forth in the foregoing description in order to provide a more comprehensive understanding of the present invention; on the contrary, well-known features may have been omitted or simplified so as not to burden the description with unnecessary details. In addition, specific elements and / or method steps that are explicitly intended to be described in conjunction with any disclosed embodiment of the present invention may be incorporated into other embodiments.

Claims

1. A slew rate control unit, comprising: a first input comprising a non-inverting input of the comparator, wherein the first input is configured to receive a reference voltage; a second input comprising an inverting input of the comparator, wherein the second input is configured to receive a feedback signal from a conduction terminal of a power transistor; a first output configured to provide an enable signal to a control terminal of a first transmission gate coupled between a control terminal of the power transistor and an operational amplifier; a second output configured to provide a charge / discharge current to a control terminal of the power transistor; The slew rate control unit is configured as follows: controlling a slew rate of a drive current through the power transistor; selectively charging an equivalent capacitance at the control terminal of the power transistor with a charging current; as well as The equivalent capacitance is selectively discharged with a discharge current, the charge current and the discharge current being at least partially dependent on a target value of the drive current.

2. The slew rate control unit according to claim 1, wherein: The first input is configured to be connected to an inverting input terminal of the operational amplifier, and the second input is configured to be connected to a non-inverting input terminal of the operational amplifier.

3. The slew rate control unit according to claim 1, further comprising: a bias current generator configured to generate a bias current; a second current mirror configured to generate a discharge current according to a control current received from the first current mirror during a fourth operation phase; a third current mirror configured to generate a second operating charging current according to the control current during a second operating phase; as well as a fourth current mirror configured to generate a first operating charging current during a first operating phase according to the bias current and independently of the target value of the drive current; Wherein the reference voltage depends on a reference current received from the first current mirror and the charging current, and wherein the discharging current depends on the control current.

4. The slew rate control unit according to claim 3, further comprising: Current switching devices; as well as A second transmission gate has a first conduction terminal coupled to the current switching device and a second conduction terminal serving as the second output of the slew rate control unit.

5. The slew rate control unit according to claim 4, wherein the current switching device comprises: a first p-type MOS transistor having a source coupled to the output terminal of the fourth current mirror for receiving the first operation charging current, a drain connected to the first conductive terminal of the second transmission gate, and a gate connected to the first charging current control unit; a second p-type MOS transistor having a source coupled to the output terminal of the third current mirror for receiving a second operating charging current, a drain connected to the first conductive terminal of the second transmission gate, and a gate connected to a second charging current control unit, wherein the second charging current control unit has an input connected to the output terminal of the comparator; a first n-type MOS transistor having a drain connected to the first conductive terminal of the second transmission gate, a source connected to the output terminal of the second current mirror for receiving the discharge current, and a gate connected to a discharge current control unit; as well as The second n-type MOS transistor has a drain connected to the first conductive terminal of the second transmission gate, a source connected to a ground terminal, and a gate connected to the discharge current control unit.

6. The slew rate control unit according to claim 5, further comprising a reference power transistor having the same or similar size as the power transistor, and comprising: A first conductive terminal connected to the ground terminal, a control terminal configured to be coupled to the control terminal of the power transistor, and a second conductive terminal coupled to a reference bias current generator.

7. The slew rate control unit of claim 6, wherein the first charging current control unit, the second charging current control unit and the discharging current control unit each have an input terminal connected to the second conductive terminal of the reference power transistor. 8 . The slew rate control unit according to claim 7 , wherein the first charging current control unit, the second charging current control unit and the discharging current control unit each have another input terminal for receiving a control signal.

9. The slew rate control unit of claim 8, wherein the second transmission gate has a second conduction terminal configured to be connected to a control terminal of the power transistor and to a second conduction terminal of the first transmission gate, and a control terminal for receiving a negated version of the enable signal.

10. The slew rate control unit according to claim 9, further comprising an enable signal generator, wherein the enable signal generator is configured to generate the enable signal based on the control signal, a first output signal generated by the first charging current control unit, a second output signal generated by the second charging current control unit, and a third output signal generated by the discharging current control unit.

11. A method of operating a light emitting diode (LED) driver system, the LED driver system comprising: a power transistor having a drain coupled to the LED array and a source coupled to the reference resistor; an operational amplifier having a non-inverting input coupled to a reference voltage; an inverting input coupled to the source of the power transistor; and an output terminal coupled to a first conductive terminal of a transmission gate having a second conductive terminal coupled to a gate of the power transistor and a control terminal coupled to an enable signal generator; and a slew rate control unit having a first input coupled to the non-inverting input terminal of the operational amplifier; and a second input coupled to the inverting input terminal of the operational amplifier, the method comprising: Selectively activating the power transistor to generate a drive current for the LED array, the selective activation comprising: enabling the transmission gate to activate an enable signal of the power transistor by turning on the enable signal generator; and deactivating the power transistor by causing the enable signal to disable the transmission gate by turning off the enable signal generator; Controlling the slew rate of the driving current; selectively charging an equivalent capacitance at a gate of the power transistor by a charging current; and The equivalent capacitance is selectively discharged by a discharge current, wherein the charge current and the discharge current depend at least in part on a target value of the drive current.

12. The method according to claim 11, further comprising: During a first operating phase of the slew rate control unit, setting the charging current to a first charging value different from zero and independent of the target value; during a second operating phase of the slew rate control unit following the first operating phase, setting the charging current to a second charging value different from zero and dependent on the target value; setting the charging current to zero during a third operating phase following the second operating phase of the slew rate control unit; during a fourth operation phase following the third operation phase of the slew rate control unit, setting the discharge current to a discharge value different from zero and depending on the target value; as well as During a fifth operation phase following the fourth operation phase of the slew rate control unit, the discharge current is set to zero.

13. The method according to claim 12, further comprising: setting the enable signal to a disable value to deactivate the power transistor during the first operating phase, the second operating phase, the fourth operating phase, and the fifth operating phase; as well as The enable signal is set to an enable value to cause activation of the power transistor during the third operating phase.

14. The method of claim 12, wherein: The second charging value corresponds to the target value multiplied by a first proportionality coefficient; as well as The method includes setting, during the second operation phase, a duration of a rising edge of the drive current to a value corresponding to a second proportionality factor multiplied by a ratio between the target value and the second charge value.

15. The method according to claim 14, wherein: The discharge value corresponds to the target value multiplied by a third proportionality coefficient; as well as The method includes setting, during the fourth operation phase, a duration of a falling edge of the drive current to a value corresponding to a fourth proportionality factor multiplied by a ratio between the target value and the discharge value.

16. The method according to claim 15, further comprising: The first current mirror outputs a reference current and a control current according to an external current, the reference voltage depends on the reference current and the charging current, and the discharging current depends on the control current; generating the discharge current by a second current mirror according to the control current during the fourth operation phase; as well as The charging current is generated by a third current mirror during the second operation phase according to the control current.

17. The method according to claim 16, wherein: The first proportionality coefficient and the third proportionality coefficient depend on mirror ratios of the first current mirror, the second current mirror, and the third current mirror.

18. The method of claim 14, wherein: The discharge value corresponds to the target value multiplied by a third proportionality coefficient; The method includes: during the fourth operation phase, setting the duration of the falling edge of the drive current to a value corresponding to a fourth proportionality factor multiplied by a ratio between the target value and the discharge value; and The second and fourth proportionality factors are dependent on the reference resistor coupled to the source of the power transistor.

19. The method according to claim 12, further comprising: turning off the power transistor during the first operating phase and the fifth operating phase; switching from the first operating stage to the second operating stage in response to the voltage at the gate of the power transistor rising to a level that turns on the power transistor; as well as Switching from the fourth operation stage to the fifth operation stage is performed in response to the voltage at the gate of the power transistor dropping to a level that turns off the power transistor.

20. The method according to claim 19, further comprising: During the first operation phase, increasing the voltage at the gate of the power transistor from the first voltage value to a second voltage value corresponding to a threshold voltage of the power transistor by the charging current; During the second operation phase, increasing the voltage at the gate of the power transistor from the second voltage value to a third voltage value by the charging current; During the third operating phase, maintaining the voltage at the gate of the power transistor at the third voltage value, the third voltage value causing the power transistor to generate the drive current at the target value; during the fourth operation phase, reducing the voltage at the gate of the power transistor from the third voltage value to the second voltage value by the discharge current; as well as During the fifth operating phase, the voltage at the gate of the power transistor is maintained at the first voltage value.

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