Display panel and display terminal

Abstract

The invention relates to a display panel and a display terminal. The display panel comprises a plurality of thin film transistors, and each thin film transistor comprises a first electrode, a first insulating part, an active part and a second electrode. An opening is formed in the first insulating part; the active part is at least arranged in the open hole and is in contact with the first electrode; the second electrode is in contact with the active part; the display panel further comprises scanning lines extending in the first direction and data lines extending in the second direction, the thin film transistors are connected with the scanning lines and the data lines, and the size of the thin film transistors in the second direction is smaller than or equal to the size of the thin film transistors in the first direction. The active layer is arranged in the open hole, the electrical property of the thin film transistor can be ensured under the condition that the occupied area of the active layer is not increased, the size of the thin film transistor in the second direction is set to be smaller than or equal to the size of the thin film transistor in the first direction, the thin film transistor can be prevented from occupying the area of the second direction too much, and the reliability of the thin film transistor is improved. And the aperture opening ratio of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] The display panel has multiple sub-pixels, each of which includes a displayable area and a non-display area. The non-display area is provided with driving components such as thin film transistors, which are used to drive the sub-pixels for display. The ratio of the displayable area of ​​a sub-pixel to the total area of ​​the sub-pixel is the aperture ratio.

[0003] In the related art, the thin film transistor occupies a large area, which makes it difficult to increase the aperture ratio of the display panel.

[0004] Therefore, it is urgent to solve the above technical problems. Summary of the invention

[0005] The embodiments of the present application provide a display panel to improve the technical problem that the aperture ratio of the display panel is difficult to increase due to the large area occupied by the thin film transistor.

[0006] In order to achieve the above object, according to a first aspect of the present application, a display panel is provided, the display panel comprising a substrate and a plurality of thin film transistors arranged on the substrate, the thin film transistors comprising:

[0007] a first electrode;

[0008] A first insulating portion, disposed on a side of the first electrode facing away from the substrate, the first insulating portion being provided with an opening corresponding to a portion of the first electrode;

[0009] An active portion, at least disposed in the opening and in contact with the first electrode;

[0010] A second electrode is disposed on a side of the first insulating portion away from the substrate, and the second electrode is disposed in contact with an end of the active portion away from the substrate;

[0011] The display panel further includes a scan line extending along a first direction and a data line extending along a second direction, the thin film transistor is connected to the scan line and the data line, and the size of the thin film transistor in the second direction is smaller than or equal to the size of the thin film transistor in the first direction.

[0012] Optionally, a size of the thin film transistor in the second direction is less than or equal to twice a width of the scan line.

[0013] Optionally, the thin film transistor comprises a gate and a gate insulating layer, the gate insulating layer is located on a side of the second electrode and the active portion away from the substrate, the gate is arranged on a side of the gate insulating layer away from the substrate, and the gate at least covers a sidewall of the opening;

[0014] The gate and the scan line are in the same layer and are connected to each other, and the size of the gate in the second direction is smaller than the size of the gate in the first direction.

[0015] Optionally, the display panel includes a plurality of sub-pixels, at least two scanning lines are arranged between two adjacent rows of sub-pixels, and at least two columns of sub-pixels are arranged between two adjacent data lines;

[0016] Wherein, one of the scan lines is connected to one of the sub-pixels via one of the thin film transistors, one of the data lines is connected to the thin film transistor via a connecting segment extending along the first direction, and one of the connecting segments is correspondingly connected to one of the thin film transistors.

[0017] Optionally, the display panel comprises a pixel electrode and a common electrode, the pixel electrode is arranged on a surface of a side of the first electrode close to the substrate and in contact with the first electrode, and the common electrode is arranged on a side of the gate electrode away from the substrate.

[0018] Optionally, the connecting segment is arranged in the same layer as the second electrode and is connected to the second electrode.

[0019] Optionally, the display panel includes a pixel electrode and a common electrode, the pixel electrode is arranged on a side of the gate away from the substrate, and the pixel electrode is electrically connected to the second electrode through a via hole, and the common electrode is arranged in the same layer as the gate.

[0020] Optionally, the connecting segment is arranged in the same layer as and connected to the first electrode.

[0021] Optionally, a size of the thin film transistor in the second direction is less than or equal to 9 micrometers.

[0022] According to a second aspect of the present application, a display terminal is provided, comprising the above-mentioned display panel.

[0023] In the display panel of the embodiment of the present application, by setting the active layer in the opening and in contact with the first electrode, the electrical properties of the thin film transistor can be guaranteed without increasing the footprint of the active layer. By setting the size of the thin film transistor in the second direction to be less than or equal to the size of the thin film transistor in the first direction, it is possible to avoid the thin film transistor occupying too much area in the second direction, thereby reducing the footprint of the thin film transistor and improving the aperture ratio of the display panel.

[0024] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0026] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0027] Figure 1 is a bottom-view structural schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0028] Figure 2A yes Figure 1 A schematic diagram of an enlarged structure of a sub-pixel in FIG.

[0029] Figure 2B yes Figure 1 A schematic diagram of an enlarged structure of another sub-pixel;

[0030] Figure 3 yes Figure 2B A schematic diagram of a local enlarged structure in FIG.

[0031] Figure 4 yes Figure 3 A schematic diagram of a cross-sectional structure at CC in the middle;

[0032] Figure 5 yes Figure 3 Another cross-sectional structural diagram at CC in the middle;

[0033] Figure 6 This is a diagram illustrating the principle of the GRB-GBR's driving method;

[0034] Fig. 7A yes Figure 2A The corresponding flip drive principle diagram;

[0035] Figure 7B yes Figure 2B The corresponding flip drive principle diagram;

[0036] FIG. 8A to FIG. 8G A process flow chart of a thin film transistor provided in an embodiment of the present application;

[0037] Fig. 9It is a schematic structural diagram of a display terminal provided in an exemplary embodiment of the present disclosure.

[0038] Description of reference numerals:

[0039] Display panel 1, display area AA, non-display area NA;

[0040] substrate 10;

[0041] Thin film transistor 20, first electrode 21, first insulating portion 22, opening 22a, active portion 23, second electrode 24, gate 25, gate insulating layer 26;

[0042] Sub-pixel 31, scan line 32, data line 33, connection segment 331, signal line 34;

[0043] A pixel electrode 41, a common electrode 42, and a second insulating portion 43;

[0044] Photoresist pattern 50, active material layer 230, second electrode layer 240;

[0045] A first direction D1 and a second direction D2;

[0046] Display terminal 2, terminal body 3. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] According to the first aspect of the present application, Figures 1 to 5As shown, a display panel 1 is provided, the display panel 1 includes a substrate 10 and a plurality of thin film transistors 20 arranged on the substrate 10, the thin film transistor 20 includes a first electrode 21, a first insulating portion 22, an active portion 23, and a second electrode 24; the first insulating portion 22 is arranged on a side of the first electrode 21 away from the substrate 10, and an opening 22a corresponding to a portion of the first electrode 21 is arranged on the first insulating portion 22; the active portion 23 is at least arranged in the opening 22a and is arranged in contact with the first electrode 21; the second electrode 24 is arranged on a side of the first insulating portion 22 away from the substrate 10, and the second electrode 24 is arranged in contact with an end of the active portion 23 away from the substrate 10; wherein the display panel 1 also includes a scan line 32 extending along a first direction D1 and a data line 33 extending along a second direction D2, the thin film transistor 20 is connected to the scan line 32 and the data line 33, and a size s2 of the thin film transistor 20 in the second direction D2 is less than or equal to a size s1 of the thin film transistor 20 in the first direction D1.

[0049] The display panel 1 may be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0050] The substrate 10 may be a flexible substrate or a rigid substrate. The material of the flexible substrate may be polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyarylate or glass fiber reinforced plastic, etc. The material of the rigid substrate may be glass, etc.

[0051] like Figure 4 and Figure 5 As shown, the thin film transistor 20 is disposed on one side surface of the substrate 10, and other film layers (not shown in the figure) may be disposed between the thin film transistor 20 and the substrate 10. For example, a buffer layer may be disposed between the thin film transistor 20 and the substrate 10, and the material of the buffer layer may be a stack of one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0052] The materials of the first electrode 21 and the second electrode 24 are both conductive materials. For example, the materials of the first electrode 21 and the second electrode 24 can be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof.

[0053] The material of the active portion 23 is a semiconductor, such as single crystal silicon, polycrystalline silicon, metal oxide, etc., but not limited thereto.

[0054] The first insulating portion 22 is a material having insulating capability. The first insulating portion 22 may be an inorganic insulating material or an organic insulating material. Inorganic insulating materials include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride. Organic insulating materials include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and the like.

[0055] like Figure 4 and Figure 5 As shown, the first insulating portion 22 covers the first electrode 21, and the first insulating portion 22 is provided with an opening 22a, the opening 22a penetrates the first insulating portion 22 along the thickness direction of the display panel 1, and the opening 22a exposes the first electrode 21. The active portion 23 is arranged in the opening 22a and contacts the first electrode 21. The active portion 23 can cover the bottom wall and the side wall of the opening 22a. The second electrode 24 is arranged on the upper surface of the first insulating portion 22, and the second electrode 24 contacts the end of the active portion 23 away from the substrate 10. One of the first electrode 21 and the second electrode 24 is a source electrode, and the other is a drain electrode.

[0056] like Figure 2A , Figure 2B and Figure 3 As shown, the scan line 32 extends along a first direction D1, which is the row direction of the display panel 1. The data line 33 extends along a second direction D2, which is the column direction of the display panel 1. The first direction D1 may be perpendicular to the second direction D2, but is not limited thereto.

[0057] The scan line 32 and the data line 33 are both routing lines for realizing signal transmission. The scan line 32 can be used to transmit a scan signal, and the data line 33 is used to transmit a data signal. The scan line 32 and the data line 33 are both connected to the thin film transistor 20, and the thin film transistor 20 realizes display control of the display panel 1 under the drive of the scan signal and the data signal.

[0058] like Figure 2B and Figure 3As shown, the size s2 of the thin film transistor 20 in the second direction D2 refers to the maximum size of the thin film transistor 20 in the second direction D2, and the size s1 of the thin film transistor 20 in the first direction D1 refers to the maximum size of the thin film transistor 20 in the first direction D1. By setting the size s2 of the thin film transistor 20 in the second direction D2 to be less than or equal to the size s1 of the thin film transistor 20 in the first direction D1, the size s2 of the thin film transistor 20 in the second direction D2 can be reduced, and the footprint of the thin film transistor 20 in the second direction D2 can be reduced. The size s1 of the thin film transistor 20 in the first direction D1 is the size in the extension direction of the scan line 32, and the size s1 of the thin film transistor 20 in the first direction D1 does not increase the additional footprint. By reducing the size s2 of the thin film transistor 20 in the second direction D2, the size of the non-display area in the second direction D2 can be reduced, thereby improving the aperture ratio of the display panel 1.

[0059] The non-display area refers to an area in the sub-pixel 31 that cannot emit light and is disposed between two adjacent rows of sub-pixels 31. The non-display area is used to dispose components such as the scan line 32 and the thin film transistor 20.

[0060] Alternatively, if Figure 2B and Figure 3 As shown, the size s2 of the thin film transistor 20 in the second direction D2 is less than or equal to twice the width w of the scan line 32 .

[0061] The width w of the scan line 32 refers to the dimension of the scan line 32 in a direction perpendicular to the extension direction of the scan line 32. The dimension s2 of the thin film transistor 20 in the second direction D2 is less than or equal to twice the width w of the scan line 32, thereby reducing the dimension s2 of the thin film transistor 20 in the second direction D2.

[0062] Alternatively, if Figures 3 to 5 As shown, the thin film transistor 20 includes a gate 25 and a gate insulating layer 26, the gate insulating layer 26 is located on the side of the second electrode 24 and the active portion 23 away from the substrate 10, the gate 25 is arranged on the side of the gate insulating layer 26 away from the substrate 10, and the gate 25 at least covers the side wall of the opening 22a; wherein the gate 25 is in the same layer as the scanning line 32 and is connected, and the size of the gate 25 in the second direction D2 is smaller than the size of the gate 25 in the first direction D1.

[0063] The gate insulating layer 26 is a material having an insulating capability. The gate insulating layer 26 may be an inorganic insulating material. The inorganic insulating material may refer to the arrangement of the inorganic insulating material in the first insulating portion 22 .

[0064] The gate 25 is made of a conductive material and can be made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0065] like Figures 3 to 5 As shown, the gate insulating layer 26 covers the upper surface of the active portion 23 and the second electrode 24, and the gate 25 covers the upper surface of the gate insulating layer 26. The gate 25 covers at least the side wall of the opening 22a. The portion of the active portion 23 located on the side wall of the opening 22a constitutes the channel of the thin film transistor 20.

[0066] like Figures 3 to 5 As shown, the gate 25 can be arranged corresponding to the opening 22a. For example, the gate 25 can cover the sidewalls and the bottom wall of the opening 22a. In order to enhance the control ability of the gate 25 over the active portion 23, the gate 25 can also cover the opening edge of the opening 22a. In order to reduce the footprint of the thin film transistor 20, the shape of the gate 25 can match the shape of the opening 22a, that is, the outline of the gate 25 can be the same as the outline of the opening 22a in any direction.

[0067] like Figure 2B and Figure 3 As shown, the gate 25 and the scan line 32 are arranged in the same layer and connected. The gate 25 and the scan line 32 can be made of the same material, so that the gate 25 and the scan line 32 can be formed by the same patterning process. The patterning process includes coating photoresist, exposure and development, etching, removing photoresist, etc. The patterning process is a conventional process in the art and will not be described in detail here.

[0068] like Figure 3 As shown, the size of the gate 25 in the second direction D2 will affect the footprint of the thin film transistor 20, so by setting the size of the gate 25 in the second direction D2 to be smaller than the size of the gate 25 in the first direction D1, the size of the gate 25 in the second direction D2 can be reduced. The size of the gate 25 in the first direction D1 is the size of the scan line 32 in the extension direction, and the size of the gate 25 in the first direction D1 can be set by adjusting the length of the scan line 32. Therefore, the size of the gate 25 in the first direction D1 has little effect on the aperture ratio.

[0069] Alternatively, if Figure 1 and Figure 2BAs shown, the display panel 1 includes a plurality of sub-pixels 31, at least two scan lines 32 are arranged between two adjacent rows of sub-pixels, and at least two columns of sub-pixels are arranged between two adjacent data lines 33; wherein, a scan line 32 is connected to a sub-pixel 31 through a thin film transistor 20, a data line 33 is connected to the thin film transistor 20 through a connecting segment 331 extending along a first direction D1, and a connecting segment 331 is correspondingly connected to a thin film transistor 20.

[0070] like Figure 1 As shown, the display panel 1 includes a display area AA and a non-display area NA arranged outside the display area AA. The display area AA is provided with a plurality of sub-pixels 31, and the display area AA is used to display images. The sub-pixels 31 can be red sub-pixels, green sub-pixels, and blue sub-pixels, so as to achieve color display. The non-display area NA can be provided with a driving circuit, and the driving circuit is used to drive the sub-pixels 31 to display. The driving circuit includes a gate driving circuit, etc. The gate driving circuit is connected to the scanning line 32, and is used to provide a scanning signal to the scanning line 32.

[0071] The non-display area NA may also be provided with a binding component (not shown in the figure), which may include a driving chip, a flip chip film, a flexible circuit board, etc. The binding component may be connected to the data line 33 through a fan-out trace to provide a data signal for the data line 33 .

[0072] For ease of description, the first direction D1 is defined as the row direction of the display panel 1, and the plurality of sub-pixels 31 arranged along the first direction D1 is a row of sub-pixels. The second direction D2 is defined as the column direction of the display panel 1, and the plurality of sub-pixels 31 arranged along the second direction D2 is a column of sub-pixels.

[0073] In some embodiments, the display panel 1 is an LCD panel. At least two scan lines 32 are arranged between two adjacent rows of sub-pixels. At least two columns of sub-pixels are arranged between two adjacent data lines 33.

[0074] For example, Figure 2A As shown, two scan lines 32 are arranged between two adjacent rows of sub-pixels, and two columns of sub-pixels are arranged between two adjacent data lines 33. Figure 2B As shown, three scan lines 32 are arranged between two adjacent rows of sub-pixels, and three columns of sub-pixels are arranged between two adjacent data lines 33. Through the above arrangement, the number of data lines 33 can be reduced, thereby reducing the cost of the binding components. The increased number of scan lines 32 can be adjusted accordingly through the gate drive circuit, without increasing the cost of the display panel 1.

[0075] like Figure 6As shown, according to the arrangement order of the scan lines 32, the scan lines 32 are respectively referred to as the nth scan line, the n+1th scan line, ... the n+11th scan line. The four adjacent data lines 33 are respectively referred to as the mth data line, the m+1th data line, the m+2th data line, and the m+3th data line. The four adjacent rows of sub-pixels are respectively referred to as the i-th row of sub-pixels, the i+1th row of sub-pixels, the i+2th row of sub-pixels, and the i+3th row of sub-pixels. Among them, m, n, and i are all positive integers. The connection relationship between the sub-pixels 31 and the scan lines 32 and the data lines 33 is described below.

[0076] For ease of explanation, R refers to a red sub-pixel, G refers to a green sub-pixel, and B refers to a blue sub-pixel.

[0077] In some embodiments, the sub-pixels 31 in the same row are arranged in the order of RGB, and the sub-pixels 31 in the same row have the same color. For example, the first sub-pixel 31 in the i-th row is R, the second sub-pixel 31 in the i-th row is G, and the third sub-pixel 31 in the i-th row is B.

[0078] In some embodiments, the display panel 1 may adopt a GRB-GBR driving mode, so that the number of lightly loaded sub-pixels 31 and the number of heavily loaded sub-pixels 31 in the RGB three-color sub-pixels corresponding to the same data line 33 are consistent, thereby improving the color shift problem under the mixed color picture, and a flip driving mode may be implemented, which may improve the image quality of the display panel 1. A mixed color picture refers to a picture in which two colors of sub-pixels 31 in RGB are lit at the same time, and the sub-pixels 31 of another color are not lit.

[0079] It should be noted that a heavily loaded sub-pixel refers to a sub-pixel that requires a longer time to increase the pixel voltage of the sub-pixel 31 to a preset value, and a lightly loaded sub-pixel refers to a sub-pixel that requires a shorter time to increase the pixel voltage of the sub-pixel 31 to a preset value than a heavily loaded sub-pixel. For example, it takes a longer time for the pixel voltage to increase from 0 volts to 5 volts than for the pixel voltage to increase from 3 volts to 5 volts. The sub-pixel that requires a longer time is a heavily loaded sub-pixel, and the sub-pixel that requires a shorter time is a lightly loaded sub-pixel.

[0080] Combine the following Figure 6 The driving method of GRB-GBR is described. Figure 6 The mixed color screen displayed in the figure may be a screen in which R is not lit and GB is lit. Figure 6 (a) shows a waveform diagram of pixel voltages of a plurality of sub-pixels 31 corresponding to the same data line 33; Figure 6 (b) shows the connection relationship between multiple sub-pixels 31 and the data lines 33 and the scanning lines 32.

[0081] like Figure 6As shown in (b), a scan line 32 is connected to a sub-pixel 31 through a thin film transistor 20. Optionally, the nth scan line is connected to the G of the i-th row through the thin film transistor 20, the n+1th scan line is connected to the R of the i-th row through the thin film transistor 20, and the n+2th scan line is connected to the B of the i-th row through the thin film transistor 20. The n+3th scan line is connected to the G of the i+1th row through the thin film transistor 20, the n+4th scan line is connected to the B of the i+1th row through the thin film transistor 20, and the n+5th scan line is connected to the R of the i+1th row through the thin film transistor 20, that is, the six adjacent scan lines are connected to GRB-GBR in sequence. The connection method of the subsequent scan lines 32 is repeated. Wherein, n and i are both positive integers.

[0082] like Figure 6 As shown in (a), the m+1th data line 33 corresponds to GRBGBR in sequence. Among them, the first G and the first B are heavy-loaded sub-pixels, and the second G and the second B are light-loaded sub-pixels. That is, the same data line 33 corresponds to 2 heavy-loaded sub-pixels and 2 light-loaded sub-pixels. The difference between the pixel voltage of the previous sub-pixel 31 of the heavy-loaded sub-pixel and the preset voltage of the heavy-loaded sub-pixel is large, and the heavy-loaded sub-pixel is more difficult to reach the preset voltage; the difference between the pixel voltage of the previous sub-pixel 31 of the light-loaded sub-pixel and the preset voltage of the light-loaded sub-pixel is small, and it is easier to reach the preset voltage. The ordinate of the curve shows the magnitude relationship of the pixel voltage. This is because in the mixed color picture, R is not lit, as shown by the thick black curve in (a), and the ordinate of R is 0; GB is lit, and the ordinate of GB is the preset voltage. The pixel voltage of B following the first R needs to be increased from 0 volts to the preset voltage, and the pixel voltage of the first B is difficult to reach the preset value. The pixel voltages of the second G and the second B only need to be increased from the pixel voltage of the first B to the preset voltages of the second G and the second B. The voltage increase is small and can basically reach the preset value.

[0083] Combine the following Figure 6 and Figure 7B The flip driving method is described by taking the (m+1)th data line as an example, and the settings of other data lines 33 are the same.

[0084] like Figure 6 As shown, a data line 33 is connected to the thin film transistor 20 through a connecting segment 331 extending along the first direction D1, and a connecting segment 331 is correspondingly connected to a thin film transistor 20. It should be noted that, as Figure 2B As shown, when the extension directions of two adjacent connection segments 331 are the same and the two connection segments 331 are connected to the same data line 33, the two adjacent connection segments 331 can be connected to each other, thereby reducing the occupied area of ​​the connection segments 331 in the second direction D2.

[0085] Optionally, the m+1th data line can be connected to the G adjacent to the left side of the i-th row, the R adjacent to the right side of the i-th row, the B adjacent to the right side of the i-th row, the G adjacent to the right side of the i+1-th row, the B adjacent to the left side of the i+1-th row, and the R adjacent to the left side of the i+1-th row through the thin film transistor 20 in order from top to bottom. The connection method of the subsequent data lines 33 is repeated here. By connecting the data lines 33 to the sub-pixels 31 adjacent to the left side and the right side, respectively, the image quality of the display panel 1 can be improved.

[0086] like Figure 7B As shown, Figure 7B Shows Figure 2B The corresponding flip driving mode schematic diagram, that is, the same data line 33 is connected to the sub-pixels 31 on both sides of the data line 33 respectively. Through the above setting, the image quality of the display panel 1 can be improved.

[0087] In some other embodiments, Fig. 7A Shows Figure 2A The corresponding flip driving mode schematic diagram, that is, the same data line 33 is connected to the sub-pixels 31 on both sides of the data line 33 respectively. Through the above setting, the image quality of the display panel 1 can be improved. Fig. 7A and Figure 7B The difference is that Fig. 7A Two scanning lines 32 are arranged between two adjacent rows of sub-pixels 31, and Figure 7B Three scanning lines 32 are arranged between two adjacent rows of sub-pixels.

[0088] In some other embodiments, the sub-pixels 31 connected to the same data line may be different from those in the above-mentioned embodiments. The sub-pixels 31 connected to the same scan line 32 may be different from those in the above-mentioned embodiments. That is to say, the order of the sub-pixels 31 connected to the nth scan line, the n+1th scan line, and the n+2th scan line may be exchanged.

[0089] In some embodiments, three scan lines 32 disposed between two adjacent rows of sub-pixels are referred to as a group of scan lines, and the order of the sub-pixels 31 connected to the two adjacent groups of scan lines may be different. That is, the order of the sub-pixels 31 connected to the n-1th scan line, the nth scan line, and the n+1th scan line may be different from the order of the sub-pixels 31 connected to the n+2th scan line, the n+3th scan line, and the n+4th scan line.

[0090] In some embodiments, Figure 2B As shown, the connection segment 331 can be disposed in the same layer and connected to the data line 33. The material of the connection segment 331 can be the same as that of the data line 33, so that the same patterning process can be used to form the connection segment 331, thereby simplifying the manufacturing process of the display panel 1.

[0091] like Figure 2B As shown, the data line 33 and the scan line 32 are arranged in different layers. The orthographic projection of the connecting segment 331 on the substrate 10 can be arranged between two adjacent scan lines, thereby reducing the coupling capacitance between the connecting segment 331 and the scan line 32.

[0092] like Figure 2B As shown, when three scan lines are arranged adjacent to each other, a certain distance needs to be set between adjacent lines to prevent two adjacent lines from short-circuiting. Therefore, the solution in which three scan lines are arranged between two adjacent rows of sub-pixels occupies a larger area of ​​the non-display area, which is not conducive to improving the aperture ratio of the display panel 1. In this scenario, by reducing the size s2 of the thin film transistor 20 in the second direction D2, the size of the non-display area in the second direction D2 can be significantly reduced.

[0093] Alternatively, if Figure 2B As shown, the spacings between the patterns of the orthographic projections of any two adjacent traces on the substrate 10 are equal and are the minimum values ​​that can be achieved within the process range, thereby further reducing the size of the non-display area in the second direction D2.

[0094] Alternatively, if Figure 4 As shown, in a display panel 1 of an embodiment of the present application, the display panel 1 includes a pixel electrode 41 and a common electrode 42, the pixel electrode 41 is arranged on a side surface of the first electrode 21 close to the substrate 10 and contacts the first electrode 21, and the common electrode 42 is arranged on a side of the gate 25 away from the substrate 10.

[0095] The LCD panel includes a substrate 10, an opposing substrate (not shown) and a liquid crystal layer disposed between the substrate 10 and the opposing substrate. Liquid crystal molecules in the liquid crystal layer are deflected under the drive of the electric field formed by the pixel electrode 41 and the common electrode 42 to control the light transmittance.

[0096] In some embodiments, Figure 4 As shown, the pixel electrode 41 and the common electrode 42 are both disposed on the substrate 10. The pixel electrode 41 is disposed on a surface of the first electrode 21 close to the substrate 10, and the common electrode 42 is disposed on a surface of the gate 25 away from the substrate 10. The pixel electrode 41 is electrically connected to the first electrode 21.

[0097] like Figure 4 As shown, a second insulating portion 43 may be provided between the gate 25 and the common electrode 42. The second insulating portion 43 is made of a material having an insulating capability. The material of the second insulating portion 43 may be set with reference to the material of the first insulating portion 22. The second insulating portion 43 and the first insulating portion 22 may be made of the same or different materials.

[0098] The common electrode 42 can be electrically connected to the signal line 34 through a via hole, and the via hole passes through the second insulating portion 43. The signal line 34 is used to transmit a signal to the common electrode 42. The signal line 34 can be arranged in the same layer as the gate 25. The signal line 34 can be made of the same material as the gate 25, and the signal line 34 can be formed by the same patterning process as the gate 25, thereby simplifying the manufacturing process of the display panel 1.

[0099] Optionally, the connection segment 331 is disposed in the same layer and connected to the second electrode 24. That is, the connection segment 331 can be made of the same material as the second electrode 24, and can be formed by the same patterning process as the second electrode 24, thereby simplifying the manufacturing process of the display panel 1.

[0100] like Figure 2B and Figure 4 As shown, the data line 33 transmits the data signal to the second electrode 24 through the connection segment 331, and the second electrode 24 is used as the source of the thin film transistor 20. The first electrode 21 transmits the data signal to the pixel electrode 41, and the first electrode 21 is used as the drain of the thin film transistor 20.

[0101] It should be noted that Figure 2A , Figure 2B and Figure 3 The viewing direction is a bottom view of the display panel, that is, a view from the substrate 10 of the display panel to the direction of the thin film transistor 20. In this way, the shapes and size relationships of the first electrode 21, the second electrode 24, the gate 25, etc. can be shown. For the film layer sequence of the first electrode 21, the second electrode 24, and the gate 25, please refer to Figure 4 and Figure 5 .

[0102] In some other embodiments, the pixel electrode 41 and the common electrode 42 may be disposed on the substrate 10 and the opposite substrate, respectively. In this case, the liquid crystal layer is located between the pixel electrode 41 and the common electrode 42 .

[0103] The pixel electrode 41 and the common electrode 42 are transparent conductive materials, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), InO (indium oxide), etc.

[0104] Alternatively, if Figure 5 As shown, a display panel 1 provided by another embodiment is shown. Figure 5 and Figure 4The difference lies in the positions and connection methods of the pixel electrode 41 and the common electrode 42. The pixel electrode 41 is arranged on the side of the gate 25 away from the substrate 10, and the pixel electrode 41 is electrically connected to the second electrode 24 through a via hole. The common electrode 42 is arranged on the same layer as the gate 25.

[0105] In some embodiments, Figure 5 As shown, a second insulating portion 43 may be disposed between the pixel electrode 41 and the gate electrode 25, and a via hole penetrates the second insulating portion 43 and the gate insulating layer 26. The pixel electrode 41 is electrically connected to the second electrode 24 through the via hole.

[0106] Alternatively, if Figure 2B As shown, the connection segment 331 is disposed in the same layer and connected to the first electrode 21. That is to say, the connection segment 331 can be made of the same material as the first electrode 21, and can be formed by the same patterning process as the first electrode 21, thereby simplifying the manufacturing process of the display panel 1.

[0107] The data line 33 transmits the data signal to the first electrode 21 through the connection segment 331 , and the first electrode 21 is used as the source of the thin film transistor 20 . The second electrode 24 transmits the data signal to the pixel electrode 41 , and the second electrode 24 is used as the drain of the thin film transistor 20 .

[0108] The common electrode 42, the gate 25, and the signal line 34 can be connected in the same layer. The common electrode 42 is connected to the signal line 34, and the signal line 34 is used to transmit signals to the common electrode 42. The signal line 34 can be made of the same material as the gate 25, so that it can be formed by the same patterning process, thereby simplifying the manufacturing process of the display panel 1.

[0109] Optionally, a dimension s2 of the thin film transistor 20 in the second direction D2 is less than or equal to 9 micrometers.

[0110] In some embodiments, Figure 2B As shown, the footprint of the thin film transistor 20 depends on the footprint of the gate 25. This is because the gate 25 is arranged in the same layer as the scan line 32, and other film layers of the thin film transistor 20 do not affect the spacing between two adjacent scan lines 32. When the size of the gate 25 in the second direction D2 is reduced, the spacing between two adjacent scan lines 32 can be reduced accordingly, thereby reducing the size of the non-display area in the second direction D2 and improving the aperture ratio of the display panel 1. At the same time, reducing the size of the non-display area in the second direction D2 can also reduce the risk of horizontal stripes.

[0111] For example, the size of the gate 25 in the second direction D2 is less than or equal to 9 micrometers, thereby reducing the distance between the gate 25 and the adjacent scan line 32. In particular, when a plurality of scan lines 32 are arranged between two adjacent rows of sub-pixels 31, by reducing the size of the gate 25 in the second direction D2, the area occupied by each group of scan lines 32 in the second direction D2 can be reduced, thereby improving the aperture ratio of the display panel 1.

[0112] The present application provides a comparative example, in which the size of the thin film transistor in the second direction D2 is 23 microns, the size of each group of scanning lines 32 in the second direction D2 is 67 microns, and the light transmittance of the display panel 1 is 5.2%. In the embodiment of the present application, the size s2 of the thin film transistor 20 in the second direction D2 is 9 microns, the size of each group of scanning lines 32 in the second direction D2 is 47.5 microns, and the light transmittance of the display panel 1 is 6.12%. Compared with the comparative example, the light transmittance of the display panel 1 of the present application is increased by 18%.

[0113] It should be noted that the higher the aperture ratio, the higher the light transmittance. The aperture ratio and light transmittance are positively correlated. That is, the aperture ratio of the present application is also improved.

[0114] like FIG. 8A to FIG. 8G As shown, a process flow chart of an embodiment of the present application is shown.

[0115] like Fig. 8A As shown, a first electrode 21 is formed on a substrate 10, a first insulating portion 22 is formed on the first electrode 21, an opening 22a is formed on the first insulating portion 22 by a patterning process, an active material layer 230 is formed on the first insulating portion 22, and the active material layer 230 is provided corresponding to the opening 22a and covers the opening edge of the opening 22a. A second electrode layer 240 is formed on the active material layer 230, and a photoresist pattern 50 is formed on the second electrode layer 240 in an area corresponding to the opening 22a.

[0116] like Figure 8B As shown, the second electrode layer 240 is etched to remove the portion of the second electrode layer 240 that is not covered by the photoresist pattern 50 .

[0117] like Figure 8C As shown, the active material layer 230 is patterned and etched to remove the portion of the active material layer 230 that is not covered by the photoresist pattern 50 .

[0118] like Fig.8D As shown, the photoresist pattern 50 is subjected to an ashing process to remove the portion of the photoresist pattern 50 corresponding to the opening 22 a.

[0119] like Fig. 8EAs shown, the second electrode layer 240 is continuously etched to remove the portion of the second electrode layer 240 not covered by the photoresist pattern 50 .

[0120] like Figure 8F As shown, the active material layer 230 is continuously etched, and the portion of the active material layer 230 not covered by the photoresist pattern 50 is thinned to form the active portion 23 .

[0121] like Figure 8G As shown, the photoresist pattern 50 is removed.

[0122] It should be noted that the above process flow chart does not show the process of forming the gate insulating layer 26 and the gate electrode 25 .

[0123] According to the second aspect of the present application, Fig. 9 As shown, a display terminal 2 is provided, and the display terminal 2 includes the above-mentioned display panel 1.

[0124] In this embodiment, if Fig. 9 As shown, the display terminal 2 includes a display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one body.

[0125] In some embodiments, the display terminal 2 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0126] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0127] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0128] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0129] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a substrate and a plurality of thin film transistors arranged on the substrate, wherein the thin film transistors comprise: a first electrode; A first insulating portion, disposed on a side of the first electrode facing away from the substrate, the first insulating portion being provided with an opening corresponding to a portion of the first electrode; An active portion, at least disposed in the opening and in contact with the first electrode; A second electrode is disposed on a side of the first insulating portion away from the substrate, and the second electrode is disposed in contact with an end of the active portion away from the substrate; The display panel further includes a scan line extending along a first direction and a data line extending along a second direction, the thin film transistor is connected to the scan line and the data line, and the size of the thin film transistor in the second direction is smaller than or equal to the size of the thin film transistor in the first direction.

2. The display panel according to claim 1, characterized in that: The size of the thin film transistor in the second direction is less than or equal to twice the width of the scan line.

3. The display panel according to claim 1, characterized in that: The thin film transistor comprises a gate and a gate insulating layer, wherein the gate insulating layer is located on a side of the second electrode and the active portion away from the substrate, the gate is arranged on a side of the gate insulating layer away from the substrate, and the gate at least covers a side wall of the opening; The gate and the scan line are in the same layer and are connected to each other, and the size of the gate in the second direction is smaller than the size of the gate in the first direction.

4. The display panel according to claim 3, characterized in that: The display panel comprises a plurality of sub-pixels, at least two scanning lines are arranged between two adjacent rows of sub-pixels, and at least two columns of sub-pixels are arranged between two adjacent data lines; Wherein, one of the scan lines is connected to one of the sub-pixels via one of the thin film transistors, one of the data lines is connected to the thin film transistor via a connecting segment extending along the first direction, and one of the connecting segments is correspondingly connected to one of the thin film transistors.

5. The display panel according to claim 4, characterized in that: The display panel includes a pixel electrode and a common electrode. The pixel electrode is arranged on a surface of the first electrode close to the substrate and in contact with the first electrode. The common electrode is arranged on a side of the gate electrode away from the substrate.

6. The display panel according to claim 5, characterized in that: The connecting segment is arranged in the same layer as the second electrode and is connected to the second electrode.

7. The display panel according to claim 4, characterized in that: The display panel includes a pixel electrode and a common electrode. The pixel electrode is arranged on a side of the gate away from the substrate and is electrically connected to the second electrode through a via hole. The common electrode is arranged in the same layer as the gate.

8. The display panel according to claim 7, characterized in that: The connecting section is arranged in the same layer as the first electrode and is connected to the first electrode.

9. The display panel according to claim 1, characterized in that: A size of the thin film transistor in the second direction is less than or equal to 9 micrometers.

10. A display terminal, characterized in that: A display panel comprising any one of claims 1 to 9.

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