Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, and the array substrate is provided with a display area, and comprises a substrate, a first active structure, a first grid electrode, a first source electrode, a passivation layer and a first drain electrode. Wherein the first active structure comprises a semiconductor layer and a conductor layer, the conductor layer is arranged on one side, close to the substrate, of the semiconductor layer, the conductor layer is provided with an opening, and at least one part of the semiconductor layer is arranged in the opening. By controlling the width of the opening, the ultra-short channel effect of the thin film transistor can be achieved, the defect that the size of an existing array substrate thin film transistor device is limited by the yellow light process is overcome, the current passing capacity is improved while the size of the device is reduced, and the requirement for high pixel density is met.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Various electronic devices that require small display devices, such as virtual reality (VR) devices and augmented reality (AR) devices, are emerging, and portable mobile display devices are being widely used. Since these mobile display devices require high resolution and miniaturization, it is important to improve the integration of thin film transistors (TFT) that constitute sub-pixels while reducing power consumption.

[0003] However, as the size of thin film transistors decreases, the size of thin film transistors is determined and limited by the accuracy of the exposure machine, and the smaller the channel, the more difficult it is to stabilize the switching characteristics, and the leakage current increases accordingly. The existing short channel device is limited by the process accuracy of the existing high-precision exposure machine, and the length is about 2 to 3 microns. The exposure amount corresponding to this length is very large, and further reduction in size will be limited, making it difficult to meet the device size requirements under high pixel density. Summary of the invention

[0004] The present application provides an array substrate and a display panel, which can realize the ultra-short channel effect of thin-film transistors in the display area, thereby reducing the size of the device while improving the current passing capacity to meet the requirements of high pixel density; in addition, the array substrate and the display panel provided by the present application can also avoid current conduction between the source and the drain.

[0005] The present application provides an array substrate, the array substrate comprising a display area, the array substrate comprising:

[0006] substrate;

[0007] A first active structure is disposed on the substrate and located in the display area. The first active structure includes a semiconductor layer and a conductor layer. The conductor layer is disposed on a side of the semiconductor layer close to the substrate. The conductor layer has an opening. At least a portion of the semiconductor layer is disposed in the opening.

[0008] A first gate is disposed on the substrate and located in the display area;

[0009] A first source electrode is disposed on the first active structure and located in the display area, and is connected to the first active structure;

[0010] A passivation layer is disposed on a side of the first source electrode away from the substrate;

[0011] The first drain electrode is arranged on the passivation layer, located in the display area, and connected to the first active structure.

[0012] Optionally, in some embodiments of the present application, the material of the first drain electrode is a transparent conductive material.

[0013] Optionally, in some embodiments of the present application, a first via hole and a second via hole are provided on the semiconductor layer, the first source electrode is connected to the conductor layer through the first via hole, and the first drain electrode is connected to the conductor layer through the second via hole.

[0014] Optionally, in some embodiments of the present application, the conductor layer includes a first conductor portion and a second conductor portion that are connected, the first conductor portion is arranged on a side of the second conductor portion close to an opening, the semiconductor layer fills the opening and covers a side of the first conductor portion away from the substrate, and the first source and the first drain are respectively connected to the second conductor portion.

[0015] Optionally, in some embodiments of the present application, the semiconductor layer includes a channel region and a doping region, the doping region is located on both sides of the channel region, the channel region covers the opening, the doping region is located on a side of the semiconductor layer away from the substrate, and the first source and the first drain are respectively connected to the doping region.

[0016] Optionally, in some embodiments of the present application, a first gate insulating layer is arranged on a side of the substrate close to the first active structure; a light shielding layer is arranged on a side of the first gate insulating layer away from the substrate, and the orthographic projection of the opening on the substrate is located within the orthographic projection of the light shielding layer on the substrate; a second gate insulating layer is arranged on a side of the substrate light shielding layer away from the substrate, the conductor layer is arranged on a side of the second gate insulating layer away from the substrate, and the semiconductor layer is arranged on a side of the conductor layer away from the second gate insulating layer; a third gate insulating layer, the third gate insulating layer is arranged on a side of the first active structure away from the substrate, and the first gate is located on a side of the third gate insulating layer away from the substrate; an interlayer dielectric layer, the interlayer dielectric layer is arranged on a side of the first gate away from the substrate, a third via penetrates the interlayer dielectric layer and the third gate insulating layer, the first source is arranged on the interlayer dielectric layer and is connected to the first active structure through the third via; a fourth via penetrates the passivation layer, the interlayer dielectric layer and the third gate insulating layer, and the first drain is connected to the first drain through the fourth via.

[0017] Optionally, in some embodiments of the present application, the light shielding layer is multiplexed as a second gate.

[0018] Optionally, in some embodiments of the present application, the array substrate also includes a non-display area, which is located on at least one side of the display area, and the array substrate also includes: a second active structure, which is arranged on the substrate and is located in the non-display area; a third gate, which is located in the non-display area and is in the same layer and material as the light-shielding layer; a second source and a second drain, which are located in the non-display area, the second source and the second drain are respectively connected to the second active structure, and the second source and the second drain are in the same layer and material as the first gate.

[0019] Optionally, in some embodiments of the present application, the semiconductor layer is a metal oxide semiconductor material, and the second active structure is a polycrystalline silicon semiconductor material.

[0020] The present application also provides a display panel, comprising the array substrate described in any of the above embodiments.

[0021] The beneficial effects of the present application are as follows: the first active structure of the display area of ​​the present application includes a semiconductor layer and a conductor layer, at least a portion of the semiconductor layer is arranged in an opening of the conductor layer to form a channel, and the length of the channel is defined by the width of the opening to obtain a thin film transistor with an ultra-short channel, thereby reducing the size of the device to meet the requirements of high display density, and at the same time, the current passing capacity of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a first film layer structure of an array substrate provided in the first embodiment of the present application.

[0023] Figure 2 A schematic diagram of a second film layer structure of an array substrate provided in the second embodiment of the present application.

[0024] Figure 3 A schematic diagram of a third film layer structure of an array substrate provided in the third embodiment of the present application.

[0025] Figure 4 A schematic diagram of a fourth film layer structure of an array substrate provided in the fourth embodiment of the present application.

[0026] Figure 5 A schematic diagram of a fifth film layer structure of an array substrate provided in the fifth embodiment of the present application.

[0027] Figure 6 A schematic diagram of a sixth film layer structure of an array substrate provided in the sixth embodiment of the present application.

[0028] Figure 7 A flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application.

[0029] Figure 8-Figure 19A schematic diagram of a method for manufacturing an array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0031] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally includes steps or modules that are not listed, or optionally includes other steps or modules inherent to these processes, methods, products or devices.

[0032] Mentioning "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. In addition, it should be noted that the drawings only provide structures that are closely related to the present application, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the inventive point clear at a glance, rather than to indicate that the actual device is the same as the attached drawings. Figure 1 The same is not a limitation of the actual device.

[0033] The embodiment of the present application provides an array substrate, which includes a display area, the array substrate includes a substrate, a first active structure, a first gate, a first source, a passivation layer, and a first drain. The passivation layer is arranged on the side of the first source away from the substrate, and the first drain is arranged on the passivation layer. The source and the drain are arranged in layers to avoid current conduction. The first active structure is arranged on the substrate and located in the display area. The first active structure includes a semiconductor layer and a conductor layer. The conductor layer is arranged on the side of the semiconductor layer close to the substrate, and the conductor layer has an opening. A part of the semiconductor layer is arranged in the opening. The length of the channel is defined by the width of the opening, so as to obtain a thin film transistor with an ultra-short channel, reduce the size of the device to meet the requirements of high pixel density, and also improve the current passing capacity of the device.

[0034] The array substrate provided in the present application is described in detail below through specific embodiments.

[0035] See also Figure 1 , Figure 1 A schematic diagram of the first film layer structure of the array substrate provided in the embodiment of the present application. The array substrate provided in the first embodiment of the present application has a display area 110 and a non-display area 120, including a substrate 100, a buffer layer 35, a second active structure 26, a first gate insulating layer 18, a third gate 27, a light shielding layer 25, a second gate insulating layer 17, a first active structure 11, a third gate insulating layer 16, a second source 28, a second drain 29, a first gate 15, an interlayer dielectric layer 19, a third via 23, a first source 13, a fourth via 24, a first drain 14, a flat layer 36, and a pixel electrode 30. It can be understood that the display area 110 is an area for displaying pictures, and the non-display area 120 can be a gate driver circuit area (Gate Driver OnArray, GOA area) or a demultiplexer area (Demultiplexer, Demux area), which is not used for displaying pictures.

[0036] Among them, the buffer layer 35 is arranged on the substrate 100, the second active structure 26 is arranged on the buffer layer 35 and is located in the non-display area 120. Furthermore, the second active structure adopts low-temperature polysilicon. Since low-temperature polysilicon has advantages such as high mobility, the thin film transistor in the non-display area 120 in the embodiment of the present application has a good driving effect. The first gate insulating layer 18 is arranged on the second active structure 26 and covers the second active structure 26 and the buffer layer 35. The third gate 27 and the light shielding layer 25 are both arranged on the first gate insulating layer 18, and the third gate 27 and the light shielding layer 25 are made of the same material. The third gate 27 is located in the non-display area 120, and the light shielding layer 25 is located in the display area 110. The third gate 27 can be formed by the same patterning process as the light shielding layer 25, which can save the mask and reduce the thickness of the array substrate.

[0037] Optionally, the material of the buffer layer 35 may be SiN x or SiO x The material of the first gate insulating layer 18 includes SiO x or SiN x or SiN x / SiO x or SiNO x Etc., the materials of the third gate 27 and the light shielding layer 25 include Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO.

[0038] The second gate insulating layer 17 is arranged on the third gate 27 and the light shielding layer 25 and covers the third gate 27, the light shielding layer 25 and the first gate insulating layer 18. The first active structure 11 is arranged on the second gate insulating layer 17 and is located in the display area 110. The first active structure 11 includes a semiconductor layer 11a and a conductor layer 11b. The semiconductor layer 11a is arranged on the conductor layer 11b. The conductor layer 11b has an opening 12. A part of the semiconductor layer 11a is arranged in the opening 12 to form a channel 31. The first embodiment of the present application uses the width d of the opening 12 to limit the length of the channel 31, and controls the width d of the opening 12 to be in the range of 0.1 to 1.3 microns, that is, the length of the channel 31 can reach the range of 0.1 to 1.3 microns. Compared with the channel length of the existing short channel thin film transistor of about 2 to 3 microns, the channel length provided by the first embodiment of the present application is greatly reduced, which can achieve the effect of ultra-short channel, further reduce the size of the thin film transistor device, and at the same time improve the current passing capacity of the thin film transistor, so as to meet the smaller device size and requirements of the thin film transistor under high pixel density. Furthermore, the semiconductor layer 11a of the first embodiment of the present application is made of metal oxides, including indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin (IZTO), indium gallium zinc tin oxide (IGZTO), etc., which have good uniformity, low leakage current and high transmittance. In addition, the orthographic projection of the opening 12 on the substrate 100 is located within the orthographic projection of the light shielding layer 25 on the substrate 100, that is, the light shielding layer 25 can play a role in shielding the channel 31, so the array substrate provided by the first embodiment of the present application can also prevent the channel 31 from being affected by light, thereby improving the stability and reliability of the device.

[0039] Optionally, the material of the second gate insulating layer 17 includes SiO x or SiN x or SiN x / SiO x or SiNO x The conductor layer 11b may be made of materials including Al, Mo, Ti, Si, Cu, amorphous metal oxides, amorphous metal elements and amorphous metal alloys.

[0040] The third gate insulating layer 16 is disposed on the semiconductor layer 11a, and the first gate 15, the second source 28, and the second drain 29 are disposed on the same film layer using the same material, and are all disposed on the side of the third gate insulating layer away from the substrate. Furthermore, the second source 28 and the second drain 29 are located in the non-display area 120, and the first gate 15 is located in the display area 110. It can be understood that in this embodiment, the first gate 15 is located on the semiconductor layer 11a, which can make the light-transmitting area of ​​the display area larger, thereby improving the aperture ratio, and the second source 28, the second drain 29 and the first gate 15 of the first embodiment of the present application are formed by the same patterning process, which can save the mask and reduce the thickness of the array substrate. Optionally, the third gate insulating layer material includes SiO x or SiN x or SiN x / SiO x or SiNO x The film materials of the second source 28, the second drain 29 and the first gate 15 include Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO.

[0041] The interlayer dielectric layer 19 is disposed on the first gate 15 and covers the first gate 15, the second source 28, and the second drain 29. The third via 23 is disposed on the interlayer dielectric layer 19 and the third gate insulating layer 16. The first source 13 is disposed on the interlayer dielectric layer 19, and a portion of the first source 13 is filled in the third via 23 and connected to the first active structure 11. The passivation layer 20 is disposed on the first source 13 and covers the first source 13 and the interlayer dielectric layer 19. The fourth via is disposed on the passivation layer 20, the interlayer dielectric layer 19, and the third gate insulating layer 16. The first drain 14 is disposed on the passivation layer 20, and a portion of the first drain 14 is connected to the first active structure 11 through the fourth via 24. The planar layer 36 is disposed on the first drain 14 and fills the fourth via 24. The pixel electrode 30 is disposed on the planar layer 36 and connected to the pixel electrode 30. It can be understood that in the film structure, the first source electrode 13 and the first drain electrode 14 are not arranged in the same layer in the first embodiment of the present application, which can avoid current conduction between each other. Further, the first drain electrode 14 is made of transparent conductive materials, including indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), a transparent conductive film structure composed of two layers of indium tin oxide film (ITO) and a layer of silver film (Ag) (ITO / Ag / ITO), a transparent conductive film structure composed of two layers of indium zinc oxide (IZO) film and a layer of silver (Ag) film (IZO / Ag / IZO), and other transparent amorphous metal oxides and crystalline metal oxides, etc., which can avoid the reduction of the aperture ratio caused by the drain metal and improve the display effect.

[0042] Optionally, the film material of the interlayer dielectric layer 19 includes SiO x or Al2O3 / SiN x / SiO x or SiO x / SiN x / SiO x The first source electrode 13 film material includes Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO, and the passivation layer 20 film material includes SiO x or SiN x or Al2O3 or SiO x / SiN x or Al2O3 / SiN x / SiO x or SiO x / SiN x / SiO xThe planar layer 36 includes a photoresist or SiO x or SiN x or Al2O3 or SiO x / SiN x or Al2O3 / SiN x / SiO x or SiO x / SiN x / SiO x The material of the pixel electrode 30 may include ITO or IZO or ITO / Ag / ITO or IZO / Ag / IZO, etc.

[0043] like Figure 2 As shown, in the second embodiment of the present application, the difference from the first embodiment of the present application is that in the second embodiment, a first via 21 and a second via 22 are provided on the semiconductor layer 11a, the first source 13 is connected to the conductor layer 11b through the first via 21, and the first drain 14 is connected to the conductor layer 11b through the second via 22. There is no need to conductorize the contact area between the semiconductor layer 11a and the first source 13 and the first drain, which can simplify the process and reduce costs.

[0044] like Figure 3 As shown, in the third embodiment of the present application, the semiconductor layer 11a includes a channel region 31 and a doping region 32, the doping region 32 is located on the side of the semiconductor layer 11a away from the substrate and on both sides of the channel region 31, and the channel region 31 covers the opening 12. The difference between this embodiment and the first and second embodiments is that the first source 13 and the first drain 14 are connected to the doping region 32 on the semiconductor layer 11a, and there is no need to set a via hole on the semiconductor layer 11a, which can avoid plasma pollution generated by opening the semiconductor layer.

[0045] In the fourth embodiment of the present application, Figure 4 As shown, the conductor layer 11b includes a first conductor portion 33 and a second conductor portion 34 connected, the first conductor portion 33 is arranged on a side of the second conductor portion 34 close to the opening 12, the semiconductor layer 11a fills the opening 12 and covers the first conductor portion 33, and the first source 13 and the first drain 14 are connected to the second conductor portion 34. It can be understood that the difference between this embodiment and the first, second and third embodiments mentioned above is that this embodiment does not need to conduct the connection area between the semiconductor layer 11a and the first source 13 and the first drain 14, which can simplify the process and reduce the cost; at the same time, in this embodiment, the first source 13 and the first drain 14 do not need to be connected to the second conductor portion 33 through the via hole arranged on the semiconductor layer 11a, which can avoid plasma contamination generated by the opening of the semiconductor layer 11a, and can also reduce the diffusion of the channel 31 to both sides of the channel 31 due to the excessively high carrier concentration.

[0046] like Figure 5 As shown, in the fifth embodiment of the present application, the shading layer 25 located in the display area 110 is reused as the second gate 36, that is, the difference between this embodiment and the first embodiment is that the thin film transistor in the display area of ​​this embodiment is a dual-gate structure, which has a faster switching speed and a higher current density, and can improve the device performance of the thin film transistor.

[0047] In the sixth embodiment of the present application, Figure 6 As shown, the display area 110 is no longer provided with a light shielding layer, and the first gate 37 is provided with the same layer and the same material as the third gate 27, and is no longer provided with the same layer as the second source 28 and the second drain 29. That is, the difference between this embodiment and the first embodiment is that the thin film transistor in the display area 110 of this embodiment is a bottom gate structure, and the preparation process is more efficient, which helps to reduce production costs.

[0048] like Figures 8 to 19 As shown, the method for manufacturing the array substrate provided in the embodiment of the present application includes the following steps:

[0049] S10, providing a substrate 100, which may be a glass substrate or a polyimide flexible substrate.

[0050] S20 , forming a buffer layer 35 and a second active structure 26 on the substrate.

[0051] S30 , forming a first gate insulating layer 18 , a third gate 27 and a light shielding layer 25 on a side of the buffer layer 35 and the second active structure 26 away from the substrate.

[0052] S40 , forming a second gate insulating layer 17 and a conductive layer 11 b on the first gate insulating layer 18 , the third gate 27 and the light shielding layer 25 on a side away from the substrate, and patterning the conductive layer 11 b to form an opening 12 .

[0053] S50 , forming a semiconductor layer 11 a on a side of the conductor layer 11 b away from the substrate, the portion of the semiconductor layer filling the opening 12 forms a channel 31 , and the semiconductor layer 11 a and the conductor layer 11 b together constitute a first active structure 11 .

[0054] S60, forming a third gate insulating layer 16 on a side of the semiconductor layer 11a away from the substrate, the third gate insulating layer 16 covers the semiconductor layer 11a and the second gate insulating layer 17, and patterning the third gate insulating layer 16, the second gate insulating layer 17, and the third gate insulating layer 18.

[0055] S70 , forming a second source electrode 28 , a second drain electrode 29 and a first gate electrode 15 on a side of the third gate insulating layer 16 away from the substrate.

[0056] S80 , forming an interlayer dielectric layer 19 on the second source 28 , the second drain 29 and the first gate 15 at a side away from the substrate, and patterning the interlayer dielectric layer 19 and the third gate insulating layer 16 to form a third via hole 23 .

[0057] S90 , forming a first source electrode 13 on a side of the interlayer dielectric layer 19 away from the substrate, wherein a portion of the first source electrode 13 is filled in the third via hole 23 and connected to the semiconductor layer 11 a of the first active structure 11 .

[0058] S100 , forming a passivation layer 20 on a side of the first source electrode 13 away from the substrate, the passivation layer 20 covering the first source electrode 13 and the interlayer dielectric layer 19 , and patterning the passivation layer 20 , the interlayer dielectric layer 19 , and the third gate insulating layer to form a fourth via hole 24 .

[0059] S110 , forming a first drain electrode 14 on a side of the passivation layer 20 away from the substrate, and a portion of the first drain electrode 14 is connected to the semiconductor layer 11 a in the first active structure 11 through a fourth via hole 24 .

[0060] S120 , forming a planar layer 36 on a side of the first drain electrode 14 away from the substrate, wherein the planar layer 36 covers the first drain electrode 14 and the passivation layer 20 and fills the fourth via hole 24 .

[0061] S130 , forming a display electrode 30 on a side of the planar layer 36 away from the substrate, and contacting the first drain electrode 14 .

[0062] To summarize, the embodiment of the present application sets an opening 12 in the conductor layer 11b and sets a portion of the semiconductor layer 11a in the opening 12 to form a channel 31. Then, by controlling the width d of the opening 12, a shorter channel 31 can be obtained, thereby obtaining a thin film transistor with an ultra-short channel, reducing the size of the TFT device, meeting the needs of high-density pixels, and effectively improving the current passing capacity of the thin film transistor.

[0063] In addition, an embodiment of the present application further provides a display panel, wherein the display panel comprises any array substrate in the above embodiments. The display panel in the embodiment of the present application may be a liquid crystal display panel or an organic light emitting display panel.

[0064] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] The array substrate and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises a display area, and the array substrate comprises: substrate; A first active structure is disposed on the substrate and located in the display area, the first active structure comprises a semiconductor layer and a conductor layer, the conductor layer is disposed on a side of the semiconductor layer close to the substrate, the conductor layer has an opening, and at least a portion of the semiconductor layer is disposed in the opening; A first gate is disposed on the substrate and located in the display area; a first source electrode, disposed on the first active structure and located in the display area, and connected to the first active structure; A passivation layer is arranged on a side of the first source electrode away from the substrate; The first drain electrode is disposed on the passivation layer, located in the display area, and connected to the first active structure.

2. The array substrate according to claim 1, characterized in that: The material of the first drain electrode is a transparent conductive material.

3. The array substrate according to claim 1, characterized in that: The semiconductor layer is provided with a first via hole and a second via hole. The first source electrode is connected to the conductor layer through the first via hole, and the first drain electrode is connected to the conductor layer through the second via hole.

4. The array substrate according to claim 1, characterized in that: The conductor layer includes a first conductor part and a second conductor part connected, the first conductor part is arranged on a side of the second conductor part close to an opening, the semiconductor layer fills the opening and covers a side of the first conductor part away from the substrate, and the first source and the first drain are respectively connected to the second conductor part.

5. The array substrate according to claim 1, characterized in that: The semiconductor layer includes a channel region and a doping region, wherein the doping region is located at both sides of the channel region and covers the opening. The doping region is located at a side of the semiconductor layer away from the substrate, and the first source and the first drain are respectively connected to the doping region.

6. The array substrate according to claim 1, characterized in that: The array substrate further includes: A first gate insulating layer is disposed on a side of the substrate close to the first active structure; A light shielding layer is arranged on a side of the first gate insulating layer away from the substrate, and the orthographic projection of the opening on the substrate is located within the orthographic projection of the light shielding layer on the substrate; A second gate insulating layer is arranged on a side of the substrate light shielding layer away from the substrate, the conductor layer is arranged on a side of the second gate insulating layer away from the substrate, and the semiconductor layer is arranged on a side of the conductor layer away from the second gate insulating layer; a third gate insulating layer, wherein the third gate insulating layer is disposed on a side of the first active structure away from the substrate, and the first gate is located on a side of the third gate insulating layer away from the substrate; an interlayer dielectric layer, the interlayer dielectric layer being arranged on a side of the first gate away from the substrate, a third via hole penetrating the interlayer dielectric layer and the third gate insulating layer, the first source being arranged on the interlayer dielectric layer and connected to the first active structure through the third via hole; A fourth via hole, wherein the fourth via hole penetrates the passivation layer, the interlayer dielectric layer and the third gate insulating layer, and the first drain electrode is connected to the first drain electrode through the fourth via hole.

7. The array substrate according to claim 6, characterized in that: The light shielding layer is multiplexed as a second gate.

8. The array substrate according to claim 6, characterized in that: The array substrate further includes a non-display area, and the non-display area is located on at least one side of the display area. The array substrate further includes: a second active structure, wherein the second active structure is disposed on the substrate and located in the non-display area; A third gate electrode is located in the non-display area and is in the same layer and made of the same material as the light shielding layer; The second source electrode and the second drain electrode are located in the non-display area, the second source electrode and the second drain electrode are respectively connected to the second active structure, and the second source electrode and the second drain electrode are in the same layer and material as the first gate electrode.

9. The array substrate according to claim 8, characterized in that: The semiconductor layer is made of metal oxide semiconductor material, and the second active structure is made of polysilicon semiconductor material.

10. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 9.

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