A highly robust trigger-type thyristor electrostatic protection device and its manufacturing method

Abstract

This invention discloses a highly robust trigger-type thyristor (SCR) ESD protection device. First, the invention utilizes the traditional unidirectional SCR ESD protection device structure and adds an N-well to the cathode side of the SCR device, forming a triple-well structure. A Schottky diode with a P-type guard ring is embedded within the structure. The Schottky diode optimizes the device's triggering process and provides an additional current discharge path. As a result, the device exhibits low trigger voltage and high robustness, effectively protecting the core circuitry of the chip. The device can be used for ESD protection of I / O ports operating at 0 to 5.5V.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection, and in particular to a highly robust trigger-type thyristor electrostatic protection device and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the problem of chip and electronic product failure caused by ESD (electrostatic discharge) has become increasingly serious and has become a major challenge facing engineers. When designing ESD protection devices, it is necessary to pay attention to the trigger voltage V t1 , maintaining voltage V h , Failure current I t2 The trigger voltage must be 10% to 20% lower than the chip's withstand voltage, the holding voltage must be 1.1 to 1.2 times higher than the operating voltage, and the failure current I t2 Determines the robustness of the device and ensures that the I t2 When the clamping voltage is lower than the chip withstand voltage. on ) is closely related to these parameters.

[0003] ESD failure modes include hard, soft, and latent failures, primarily caused by thermal and electrical failures. Thermal failure occurs when transient high currents generate high heat, leading to metal melting or hot spots. Electrical failure occurs when the electric field strength exceeds the dielectric strength, triggering breakdown. As the threat of ESD grows, research into its physical mechanisms is gaining increasing attention.

[0004] Compared with other ESD devices, traditional SCR electrostatic protection devices have a dual-conductance modulation mechanism, high discharge efficiency per unit area, small unit parasitic capacitance, and the best robustness.

[0005] The cross-section of the traditional unidirectional SCR electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 When an ESD pulse is applied to the anode of a traditional unidirectional SCR, the N-well and P-well form a reverse-biased PN junction. When the pulse voltage exceeds the avalanche breakdown voltage of the reverse-biased PN junction, a large avalanche current is generated within the device, flowing through the P-well and then to the cathode through the P-well parasitic resistance R2. The voltage drop across the parasitic resistance of the P-type shallow well is equivalent to the base voltage drop of transistor NPN1. When this voltage exceeds the forward conduction voltage of the lateral NPN1 transistor, the transistor turns on. After this transistor turns on, it provides base current to the PNP transistor. After the PNP transistor also turns on, a positive feedback mechanism is formed, which fully opens the SCR path. Therefore, even if there is no avalanche current, the open SCR path can still discharge a large current. Traditional SCR ESD protection devices can provide ESD protection for circuits with positive operating signal voltages. However, due to their high trigger voltage and low holding voltage, latch-up can easily occur, which requires special consideration during design. Summary of the Invention

[0006] In order to solve the above technical problems, the present invention provides a highly robust trigger-type thyristor electrostatic protection device and a manufacturing method thereof, and is applied to the design of an ESD protection network with an operating voltage of 0 to 5.5V.

[0007] The technical solution of the present invention to solve the above problems is:

[0008] In the first aspect, an embodiment of the present invention provides a highly robust trigger-type thyristor electrostatic protection device, comprising: a P-type substrate, a first N-well, a first P-well, and a second N-well are provided above the P-type substrate; a first N+ injection and a first P+ injection are provided on the first N-well from left to right; a second P+ injection and a second N+ injection are provided on the first P-well from left to right; a third P+ injection is provided between the first P-well and the second N-well; a first metal and a fourth P+ injection are provided on the second N-well from left to right; the third P+ injection and the fourth P+ injection together form a closed P-type protection ring around the first metal; the first metal in the second N-well forms a Schottky contact with the second N-well to constitute an N-type Schottky diode.

[0009] The first N+ injection, the first P+ injection and the first metal in the second P-well are connected together and serve as the anode of the device; the second P+ injection and the second N+ injection electrodes in the first P-well are connected together and serve as the cathode of the device.

[0010] Preferably, there are four field oxygen isolation regions; the first field oxygen isolation region is between the first N+ injection and the first P+ injection region, the second field oxygen isolation region is between the first P+ injection and the second N+ injection region, the third field oxygen isolation region is between the second P+ injection and the second N+ injection region, and the fourth field oxygen isolation region is between the second N+ injection and the third P+ injection region.

[0011] Preferably, the first field oxygen isolation region is located on the surface of the first N-well; the second field oxygen isolation region is located between the first N-well and the first P-well; the third field oxygen isolation region and the fourth field oxygen isolation region are located on the surface of the first P-well.

[0012] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well, and the first P-well constitute a transistor PNP; the first N-well, the first P-well, and the second N+ injection constitute a transistor NPN1; the second N+ injection, the first P-well, and the second N-well constitute a transistor NPN2; and the first metal and the second N-well constitute a forward N-type Schottky diode D1.

[0013] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the breakdown surface is the reverse-biased PN junction composed of the second N-well and the third P+ injection; after avalanche breakdown occurs, the ESD current flows into the cathode through the first metal, the second N-well, the third P+ injection, the first P-well, and the second P+ injection; and a voltage drop is formed on the equivalent resistance Rpw of the first P-well. When the voltage drop reaches 0.7V, transistors NPN1 and NPN2 are turned on, and base current is provided to the left longitudinal PNP transistor to promote its conduction, forming a positive feedback effect, and the device is successfully triggered.

[0014] Preferably, the device's breakdown region is located near the third P+ implant region (the Schottky diode's P-type guard ring). After avalanche breakdown occurs, the trigger path is formed by the series connection of Schottky diode D1 and transistor NPN2, shortening the trigger current path. Furthermore, the Schottky diode has a higher current density, resulting in a lower trigger voltage for the device.

[0015] Preferably, the added Schottky diode has a P-type guard ring, which can increase the curvature radius of its edge depletion layer, thereby significantly weakening the edge surface electric field, effectively protecting the Schottky junction from damage, and at the same time, improving the noise characteristics of the device and optimizing the forward conduction capability of the Schottky diode path.

[0016] Preferably, after the device's main SCR turns on, the Schottky diode in the trigger path remains on due to its lower on-resistance, sharing and dissipating the ESD current with the main SCR. Due to the addition of an additional current path, the device's failure current is significantly increased.

[0017] Preferably, the size S1 of the third field oxygen isolation region is adjustable. When S1 increases, the on-resistance of the main SCR increases. By adjusting S1, a reasonable distribution of current in the main SCR path and the Schottky diode path can be achieved, thereby optimizing the heat energy distribution, further improving the failure current of the device, and enhancing its robustness.

[0018] In a second aspect, an embodiment of the present invention provides a method for manufacturing a highly robust trigger-type thyristor electrostatic protection device, comprising the following steps:

[0019] Step 1: generating a first N-well, a first P-well, and a second N-well in a P-type substrate;

[0020] Step 2: Generate a first N+ injection and a first P+ injection on the first N-well from left to right; generate a second P+ injection and a second N+ injection on the first P-well from left to right; generate a ring-shaped P-type injection region at a specified position in the second N-well; deposit Schottky metal in the ring-shaped P-type injection region in the second N-well to form a Schottky contact with the second N-well to ensure a clean surface;

[0021] Step 3: forming a first field oxygen isolation region between the first N+ implant and the first P+ implant on the first N well, forming a second field oxygen between the first P+ implant on the first N well and the second P+ implant on the first P well, forming a third field oxygen isolation region between the second P+ implant and the second N+ implant on the first P well, and forming a fourth field oxygen isolation region between the second N+ implant and the third P+ implant;

[0022] Step 4: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;

[0023] Step 5: Connect the first N+ injection, the first P+ injection, and the first metal together and use them as the anode of the device, and connect the second P+ injection and the second N+ injection together and use them as the cathode of the device.

[0024] Preferably, before forming the N-type buried layer in the P-type substrate, the method further includes:

[0025] A silicon dioxide film is grown on a P-type substrate, followed by a silicon nitride layer. A photoresist layer is spin-coated on the wafer, exposed and developed using a mask to form an isolation trench. The silicon dioxide, silicon nitride, and isolation trench are etched to remove the photoresist layer, and a silicon dioxide layer is deposited. Chemical mechanical polishing is then performed until the silicon nitride layer is reached, and the silicon nitride layer is removed.

[0026] The beneficial effects of the present invention are:

[0027] 1. The present invention embeds a Schottky diode in the second N-well, uses the P-type guard ring of the Schottky diode and the second N-well as trigger surfaces, optimizes the trigger current path, and reduces the trigger voltage.

[0028] 2. The activation of the main SCR in the device of this invention requires the activation of the Schottky diode trigger path. This ensures effective conduction between the Schottky diode and the series NPN2 path after the main SCR is activated. Due to its low on-resistance, the Schottky diode can synergistically share high ESD currents with the main SCR, thereby increasing the device's failure current. Furthermore, the Schottky diode is embedded outside the main SCR, without affecting its normal operation.

[0029] 3. The embedded Schottky diode of the present invention has a P-type guard ring, which can increase the curvature radius of its edge depletion layer, thereby significantly weakening the edge surface electric field and effectively protecting the Schottky junction from damage. At the same time, it improves the noise characteristics of the device and optimizes the forward conduction capability of the Schottky diode path.

[0030] 4. The size S1 of the third field oxygen isolation region described in the present invention is adjustable. When S1 increases, the on-resistance of the main SCR increases. By adjusting S1, a reasonable distribution of current in the main SCR path and the Schottky diode path can be achieved, thereby optimizing the heat energy distribution, further increasing the failure current of the device, and enhancing its robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.

[0032] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.

[0033] Figure 3 2 is a cross-sectional view of an embodiment of the present invention.

[0034] Figure 4 2 is an equivalent circuit diagram of an embodiment of the present invention.

[0035] Figure 5 This is a simulation diagram of the current density distribution near the trigger point of a highly robust trigger-type thyristor electrostatic protection device provided by one embodiment of the present invention.

[0036] Figure 6 This is a simulation diagram of the total current density distribution of a highly robust trigger-type thyristor electrostatic protection device provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0037] The ESD protection design of the analog switch chip applied to the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] like Figure 3As shown, a highly robust trigger-type thyristor electrostatic protection device comprises: a P-type substrate 101, on which a first N-well 201, a first P-well 202, and a second N-well 203 are provided; on the first N-well 201, a first N+ injection 301 and a first P+ injection 302 are provided in sequence from left to right; on the first P-well 202, a second P+ injection 303 and a second N+ injection 304 are provided in sequence from left to right; between the first P-well 202 and the second N-well 203, a third P+ injection 305 is provided, which is connected across the two wells; on the second N-well 203, a first metal 501, a fourth metal 502, a fourth metal 503, a fourth metal 504, a fourth metal 505, a fourth metal 506, a fourth metal 507, a fourth metal 508, a fourth metal 509, a fourth metal 508, a fourth metal 509, a fourth metal 509, a fourth metal 501, a fourth metal 501, a fourth metal 508, a fourth metal 509, a fourth metal 509, a fourth metal 501 ...4, a third metal 505, a third metal 506, a fourth metal 508, a fourth metal 509, a third metal 509, a third metal 509, a fourth metal 509, a fourth metal 509, a third metal 501, a fourth metal 509, a fourth metal 509, a third metal 509, a third metal 50 P+ injection 306; the third P+ injection 305 and the fourth P+ injection 306 together form a closed P-type guard ring around the first metal 501; the first metal 501 on the second N well 203 forms a Schottky contact with the second N well 203 to form an N-type Schottky diode; the first N+ injection 301 in the first N well 201, the second P+ injection 302 and the first metal 501 in the second N well 203 are connected together and serve as the anode of the device; the second P+ injection 303 in the first P well 202 and the second N+ injection 304 are connected together and serve as the cathode of the device;

[0039] In one embodiment, the first field oxygen isolation region 401 is between the first N+ implant 301 and the first P+ implant 302, the second field oxygen isolation region 402 is between the first P+ implant 302 and the second P+ implant 303, the third field oxygen 403 is between the second P+ implant 303 and the second N+ implant 304, and the fourth field oxygen isolation region 404 is between the second N+ implant 304 and the third P+ implant 305;

[0040] In one embodiment, if Figure 4 As shown, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection 302, the first N-well 201, and the first P-well 202 form a transistor PNP; the first N-well 201, the first P-well 202, and the second N+ injection 304 form a transistor NPN1; the second N+ injection 304, the first P-well 202, and the second N-well 203 form a transistor NPN2; the first metal 501 and the second N-well 203 form a forward N-type Schottky diode D1;

[0041] When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the breakdown surface is the reverse-biased PN junction formed by the second N-well 203 and the third P+ injection 305; after avalanche breakdown occurs, the ESD current flows into the cathode through the first metal 501, the second N-well 203, the third P+ injection 305, the first P-well 202, and the second P+ injection 304; and a voltage drop is formed on the equivalent resistance Rpw of the first P-well 202. When the voltage drop reaches 0.7V, transistors NPN1 and NPN2 are turned on, and provide base current to the left longitudinal PNP transistor, thereby promoting its conduction, forming a positive feedback effect, and the device is successfully triggered. Figure 5 As shown in Figure 1, the trigger path of the Schottky diode in series with NPN2 is successfully turned on, the trigger current path is shorter, and there is a higher current density near the Schottky diode.

[0042] A Schottky diode is provided in the second N-well 203. After the main SCR of the device is turned on, the Schottky diode in the trigger path remains in the open state due to its lower on-resistance, sharing and discharging the ESD current with the main SCR. Figure 6 As shown in Figure 1, when the device is fully turned on, there is a large current density in both the main SCR and the additional Schottky diode path. Due to the addition of the additional current path, the failure current of the device is significantly increased.

[0043] The size S1 of the third field oxygen isolation region 403 is adjustable. When S1 increases, the on-resistance of the main SCR increases. By adjusting S1, a reasonable distribution of current between the main SCR path and the Schottky diode path can be achieved, thereby optimizing the heat energy distribution, further increasing the failure current of the device, and enhancing its robustness.

[0044] The embodiment of the present invention further provides a method for manufacturing a highly robust trigger-type thyristor electrostatic protection device, comprising the following steps: Step 1: generating a first N-well 201, a first P-well 202, and a second N-well 203 in a P-type substrate 101;

[0045] Step 2: Generate a first N+ implant 301 and a first P+ implant 302 sequentially from left to right on the first N-well 201; generate a second P+ implant 303 and a second N+ implant 304 sequentially from left to right on the first P-well; generate an annular P-type implant region (305, 306) at a designated position in the second N-well; deposit a first metal 501 in the annular P-type implant region in the second N-well to form a Schottky contact with the second N-well 203;

[0046] Step 3: forming a first field oxygen isolation region 401 between the first N+ implant 301 and the first P+ implant 302 on the first N-well 201, forming a second field oxygen isolation region 402 between the first P+ implant 302 on the first N-well 201 and the second P+ implant 303 on the first P-well 202, forming a third field oxygen isolation region 403 between the second P+ implant 303 and the second N+ implant 304 on the first P-well 202, and forming a fourth field oxygen isolation region 404 between the second N+ implant 304 and the third P+ implant 305;

[0047] Step 4: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;

[0048] Step 5: Connect the first N+ injection 301, the first P+ injection 302, and the first metal 501 together and use them as the anode of the device, and connect the second P+ injection 302 and the second N+ injection 304 together and use them as the cathode of the device.

[0049] The fabrication method for the highly robust trigger-type thyristor (SCR) electrostatic protection device of the present invention is simple and easy to operate. To maximize the performance of the unidirectional SCR, the Schottky diode introduced in the present invention optimizes the trigger path of the traditional SCR and provides an additional current discharge path, effectively improving the device's protection performance and failure level. This device can be used in ESD protection designs for 0-5.5V I / O ports. The example device of the present invention utilizes a 0.25μm BCDMOS process.

[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A highly robust trigger-type thyristor electrostatic protection device, characterized in that: include: A P-type substrate, wherein a first N-well, a first P-well, and a second N-well are provided on the P-type substrate from left to right; a first N+ injection and a first P+ injection are provided on the first N-well from left to right; a second P+ injection and a third N+ injection are provided on the first P-well from left to right; There is a third P+ injection between the first P well and the second N well; the first metal and the fourth P+ injection are arranged in sequence from left to right on the second N well; The third P+ injection and the fourth P+ injection together form a closed P-type guard ring around the first metal; The first metal on the second N-well forms a Schottky contact with the second N-well to form an N-type Schottky diode; The first N+ injection, the first P+ injection and the first metal in the second N-well are connected together and serve as the anode of the device; the second P+ injection and the second N+ injection electrodes in the first P-well are connected together and serve as the cathode of the device.

2. The highly robust trigger-type thyristor electrostatic protection device according to claim 1, characterized in that: There are four field oxygen isolation regions; the first field oxygen isolation region is between the first N+ injection and the first P+ injection region, the second field oxygen isolation region is between the first P+ injection and the second P+ injection, the third field oxygen isolation region is between the second P+ injection and the second N+ injection, and the fourth field oxygen isolation region is between the second N+ injection and the third P+ injection region.

3. The highly robust trigger-type thyristor electrostatic protection device according to claim 2, characterized in that: The first field oxygen isolation region is located on the surface of the first N-well; the second field oxygen isolation region is located between the first N-well and the first P-well; the third field oxygen isolation region and the fourth field oxygen isolation region are located on the surface of the first P-well.

4. The highly robust trigger-type thyristor electrostatic protection device according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region, the first N-well, and the first P-well form a transistor PNP; the first N-well, the first P-well, and the second N+ injection form a transistor NPN1; the second N+ injection, the first P-well, and the second N-well form a transistor NPN2; the first metal and the second N-well form a forward N-type Schottky diode D1.

5. The highly robust trigger-type thyristor electrostatic protection device according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the breakdown surface is the reverse-biased PN junction composed of the second N-well and the third P+ injection. After avalanche breakdown occurs, the ESD current flows into the cathode through the first metal, the second N-well, the third P+ injection, the first P-well, and the second P+ injection. A voltage drop is formed on the equivalent resistance Rpw of the first P-well. When the voltage drop reaches 0.7V, transistors NPN1 and NPN2 are turned on, and base current is provided to the left vertical PNP transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the device is successfully triggered.

6. The highly robust trigger-type thyristor electrostatic protection device according to claim 1, characterized in that: The breakdown region of the device is located in the third P+ injection region, which is the P-type guard ring of the Schottky diode. After avalanche breakdown occurs, the trigger path is composed of the Schottky diode D1 and the transistor NPN2 in series, making the trigger current path shorter.

7. The highly robust trigger-type thyristor electrostatic protection device according to claim 1, characterized in that: After the main SCR of the device is turned on, the Schottky diode in the trigger path remains in the on state due to its low on-resistance, sharing and discharging the ESD current with the main SCR.

8. The highly robust trigger-type thyristor electrostatic protection device according to claim 2, characterized in that: The size S1 of the third field oxygen isolation region is adjustable. When S1 increases, the on-resistance of the main SCR increases. By adjusting S1, reasonable distribution of current in the main SCR path and the Schottky diode path is achieved.

9. A method for manufacturing a highly robust trigger-type thyristor electrostatic protection device according to any one of claims 1 to 8, comprising the following steps: Step 1: generating a first N-well, a first P-well, and a second N-well in a P-type substrate; Step 2: Generate a first N+ implant and a first P+ implant on the first N well from left to right; Generating a second P+ implant and a second N+ implant sequentially from left to right on the first P well; Generating a ring-shaped P-type implantation region at a designated position of the second N-well; Depositing a Schottky metal in the annular P-type implantation region in the second N-well to form a Schottky contact with the second N-well; Step 3: forming a first field oxygen isolation region between the first N+ implant and the first P+ implant on the first N well, forming a second field oxygen between the first P+ implant on the first N well and the second P+ implant on the first P well, forming a third field oxygen isolation region between the second P+ implant and the second N+ implant on the first P well, and forming a fourth field oxygen isolation region between the second N+ implant and the third P+ implant; Step 4: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas; Step 5: Connect the first N+ injection, the first P+ injection, and the first metal together and use them as the anode of the device, and connect the second P+ injection and the second N+ injection together and use them as the cathode of the device.

10. The method for manufacturing a highly robust trigger-type thyristor electrostatic protection device according to claim 9, characterized in that: The process includes the following steps before step 1: growing a silicon dioxide film on a P-type substrate, and then depositing a silicon nitride layer; spin-coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and isolation shallow groove to remove the photoresist layer, depositing a silicon dioxide layer, and then chemically polishing until the silicon nitride layer is formed to remove the silicon nitride layer.

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