Solar cell, photovoltaic module and manufacturing method of solar cell

Abstract

The invention discloses a solar cell, a photovoltaic module and a manufacturing method of the solar cell, relates to the technical field of solar cells, and aims to solve the problems that the transmission efficiency of carriers is low and the cell efficiency of the solar cell is affected due to the fact that a functional layer is not matched with a work function between a metal electrode and a doped semiconductor layer in component selection. The solar cell comprises a doped semiconductor layer and a passivation layer which are at least stacked on a first surface of a semiconductor substrate, the passivation layer is provided with an opening part exposing a part of the doped semiconductor layer, and an electrode layer is connected with the doped semiconductor layer exposed by the opening part through the opening part. A miscible layer formed by metal atoms in the electrode layer and silicon atoms in the doped semiconductor layer and an interface layer comprising a silicon oxide layer and / or a metal oxide layer are arranged between the electrode layer and the doped semiconductor layer. The mutual dissolution layer and the interface layer are arranged along a first direction, and the first direction is the extension direction of the first surface of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell, a photovoltaic module and a method for manufacturing a solar cell. Background Art

[0002] Solar cells are devices that utilize solar energy and directly convert light energy into electrical energy through the photoelectric effect. Solar cells generally include a semiconductor substrate, a doped semiconductor layer, and a metal electrode. During the sintering process, as corrosion proceeds simultaneously, the metal electrode easily penetrates the doped semiconductor layer and directly contacts the semiconductor substrate, thereby forming a high-density defect state, resulting in a very large load current and reducing the cell efficiency of the solar cell.

[0003] Currently, an additional functional layer (eg, a metal layer or a semiconductor layer) is generally disposed between the metal electrode and the doped semiconductor layer to prevent the metal electrode paste from corroding downward to the semiconductor substrate.

[0004] However, in the prior art, the composition of the functional layer is not matched with the work function between the metal electrode and the doped semiconductor layer, resulting in low carrier transfer efficiency, which in turn affects the cell efficiency of the solar cell. Summary of the invention

[0005] The object of the present invention is to provide a solar cell, a photovoltaic module and a method for manufacturing a solar cell, which are used to improve the transmission efficiency of carriers and thus improve the cell efficiency of the solar cell.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a solar cell. The solar cell comprises: a semiconductor substrate, a doped semiconductor layer, a passivation layer, an electrode layer, an interface layer and a mutual dissolution layer. The doped semiconductor layer is at least arranged on the first surface of the semiconductor substrate, the passivation layer is arranged on the surface of the doped semiconductor layer away from the semiconductor substrate, the passivation layer has an opening, the opening exposes part of the doped semiconductor layer, and the electrode layer is connected to the doped semiconductor layer exposed by the opening through the opening. The mutual dissolution layer and the interface layer are arranged between the electrode layer and the doped semiconductor layer, the metal atoms in the electrode layer and the silicon atoms in the doped semiconductor layer form a mutual dissolution layer, and the interface layer comprises a silicon oxide layer and / or a metal oxide layer. The mutual dissolution layer and the interface layer are arranged along a first direction, and the first direction is the extension direction of the first surface of the semiconductor substrate.

[0007] In the solar cell provided by the present invention, when the interface layer only includes a silicon oxide layer, the silicon oxide can chemically passivate the opening, improve the passivation performance between the electrode layer and the doped semiconductor layer, thereby improving the interface passivation performance, reducing the interface carrier recombination, and improving the battery efficiency. When the interface layer only includes a metal oxide layer, the metal oxide layer can not only play a role in diffusion barrier, but also hinder the metal in the electrode layer from diffusing into the semiconductor substrate, thereby improving the stability of the solar cell. At the same time, since the metal oxide layer has a higher melting point and thermal stability, the structural stability of the interface layer can be improved. In addition, the metal oxide layer can also achieve field passivation, thereby inhibiting carrier recombination, improving the separation and transmission of carriers, and improving battery efficiency. When the interface layer includes both a silicon oxide layer and a metal oxide layer, the interface layer has the effect described above that the interface layer only includes a silicon oxide layer and only includes a metal oxide layer, which will not be repeated here. In addition, the above-mentioned intersoluble layer is formed by the mutual diffusion of metal atoms in the electrode layer and silicon atoms in the doped semiconductor layer, and the intersoluble layer can be referred to as a metal-silicon intersoluble layer. The work function of the metal-silicon inter-soluble layer is between that of metal and silicon, so the work function between the electrode layer, the metal-silicon inter-soluble layer (i.e., the inter-soluble layer), and the doped semiconductor layer changes in a step-like manner. At this time, it is beneficial to reduce the Schottky barrier at the metal-silicon contact interface, thereby improving the carrier transmission efficiency and improving the cell efficiency of the solar cell.

[0008] In one implementation, the mutual dissolving layer and the interface layer are alternately distributed along the first direction, and the mutual dissolving layer and the interface layer form a continuous film layer.

[0009] When the above technical solution is adopted, since the miscible layer and the interface layer form a continuous film layer, it is possible to avoid the situation where there is neither a miscible layer nor an interface layer between the electrode layer and the doped semiconductor layer exposed by the opening, thereby avoiding the problem of poor passivation performance or low carrier transmission efficiency.

[0010] In one implementation, the electrode layer has an extension portion, the extension portion of the electrode layer extends into the doped semiconductor layer, and the extension portion of the electrode layer includes silicon.

[0011] In the case of adopting the above technical solution, combined with the above description, the electrode layer is connected to the doped semiconductor layer exposed by the opening through the opening, the interface layer is arranged between the electrode layer and the doped semiconductor layer, and the extension of the electrode layer extends into the doped semiconductor layer. It can be seen that the electrode layer does not penetrate the doped semiconductor layer into the semiconductor substrate or abuts against the semiconductor substrate. At this time, it can not only reduce or eliminate the probability of forming a high-density defect state, reduce the load current, and improve the battery efficiency of the solar cell; at the same time, it can also avoid the semiconductor substrate from being damaged to ensure that the function of the semiconductor substrate is not affected, thereby ensuring the performance of the solar cell. In addition, since the extension of the electrode layer extends into the doped semiconductor layer, the extension of the electrode layer can increase the contact area between the electrode layer and the doped semiconductor layer, reduce the contact resistance, and reduce the series resistance, so as to effectively collect current and improve the battery efficiency of the solar cell.

[0012] In one implementation, the cross-sectional area of ​​the extension of the electrode layer gradually decreases along the direction away from the electrode layer and along the direction deep into the doped semiconductor layer. And / or, parallel to the first surface, the cross-sectional area of ​​a first portion of the extension of the electrode layer away from the semiconductor substrate is greater than the cross-sectional area of ​​a second portion of the extension of the electrode layer close to the semiconductor substrate.

[0013] When the above technical solution is adopted, the contact area between the electrode layer and the doped semiconductor layer is increased, the contact resistance is reduced, and at the same time, the damage of the electrode layer to the doped semiconductor layer is reduced to ensure that the function of the doped semiconductor layer meets the actual requirements.

[0014] In an implementation manner, along a direction perpendicular to the first surface, a ratio of a depth of the extension portion of the electrode layer extending into the doped semiconductor layer to a thickness of the doped semiconductor layer is less than or equal to 99%.

[0015] When the above technical solution is adopted, the extension of the electrode layer does not penetrate the doped semiconductor layer into the semiconductor substrate. At this time, it can not only reduce or eliminate the probability of forming a high-density defect state, reduce the load current, and improve the battery efficiency of the solar cell; at the same time, it can also avoid the semiconductor substrate from being damaged to ensure that the function of the semiconductor substrate is not affected, thereby ensuring the performance of the solar cell. Furthermore, it also takes into account the increase of the contact area between the electrode layer and the doped semiconductor layer, the reduction of contact resistance, and the reduction of series resistance, so as to effectively collect current and improve the battery efficiency of the solar cell.

[0016] In one implementation, on a surface of the doped semiconductor layer close to the electrode layer, a ratio of a cross-sectional area of ​​an extension portion of the electrode layer on the surface to a cross-sectional area of ​​the opening portion parallel to the first surface is greater than or equal to 1% and less than or equal to 10%.

[0017] When the above technical solution is adopted, the extension of the electrode layer has less pollution to the doped semiconductor layer, ensuring that the quality of the doped semiconductor layer meets the actual requirements. In addition, the contact area between the electrode layer and the doped semiconductor layer is increased, the contact resistance is reduced, and the series resistance is reduced to effectively collect current and improve the cell efficiency of the solar cell.

[0018] In one implementation, the doped semiconductor layer has an extension portion, the extension portion of the doped semiconductor layer extends into the electrode layer, and the extension portion of the doped semiconductor layer includes aluminum elements.

[0019] When the above technical solution is adopted, the extension of the doped semiconductor layer can increase the contact area between the doped semiconductor layer and the electrode layer, reduce the contact resistance, and reduce the series resistance, so as to effectively collect current and improve the cell efficiency of the solar cell.

[0020] In one implementation, the cross-sectional area of ​​the extension portion of the doped semiconductor layer gradually decreases along the direction away from the doped semiconductor layer and along the direction deep into the electrode layer. And / or, parallel to the first surface, the cross-sectional area of ​​the third portion of the extension portion of the doped semiconductor layer away from the semiconductor substrate is smaller than the cross-sectional area of ​​the fourth portion of the extension portion of the doped semiconductor layer close to the semiconductor substrate.

[0021] When the above technical solution is adopted, the contact area between the electrode layer and the doped semiconductor layer is increased, the contact resistance is reduced, and at the same time, the damage of the doped semiconductor layer to the electrode layer is reduced to ensure that the function of the electrode layer meets the actual requirements.

[0022] In one implementation, the doped semiconductor layer includes at least one protruding structure and at least one recessed structure, the protruding structure protrudes toward one side of the electrode layer, two adjacent interface layers are spaced apart at the top of the protruding structure, and the intersoluble layer is located at the top of the protruding structure.

[0023] When the above technical solution is adopted, the convex structure and the concave structure can not only increase the contact area between the electrode layer and the doped semiconductor layer, reduce the contact resistance, reduce the series resistance, effectively collect current, and improve the cell efficiency of the solar cell, but also increase the surface roughness of the doped semiconductor layer, improve the mechanical properties of the electrode layer, and improve the tensile properties of the electrode layer.

[0024] In one implementation, along a direction perpendicular to the first surface, the height of the protruding structure is greater than or equal to 1 nm and less than or equal to 50 nm, and the depth of the recessed structure is greater than or equal to 1 nm and less than or equal to 50 nm.

[0025] In the case of adopting the above technical solution, the height of the protruding structure and the depth of the recessed structure are both greater than or equal to 1nm, and the size of the protruding structure and the recessed structure can be avoided to be too small, so as to increase the contact area between the electrode layer and the doped semiconductor layer, reduce the contact resistance, reduce the series resistance, effectively collect current, and improve the battery efficiency of the solar cell. In addition, the height of the protruding structure is greater than or equal to 1nm, which is conducive to the formation of the mutual solution layer, so that the work function between the electrode layer, the metal-silicon mutual solution layer (i.e., the mutual solution layer), and the doped semiconductor layer changes in a step-like manner, thereby helping to reduce the Schottky barrier at the metal-silicon contact interface, improve the carrier transmission efficiency, and improve the battery efficiency of the solar cell.

[0026] In addition, the height of the protruding structure and the depth of the recessed structure are both less than or equal to 50 nm, which can ensure the quality of the doped semiconductor layer and the electrode layer and avoid serious damage to the doped semiconductor layer and the electrode layer, thereby ensuring the quality of the solar cell.

[0027] In one implementation, the doped semiconductor layer includes a doped polysilicon layer. Along the extension direction of the first surface, the semiconductor substrate includes an opening area and a non-opening area, and the opening portion corresponds to the opening area. The doped polysilicon layer corresponding to the opening area contains amorphous silicon; along the extension direction of the first surface, the doped polysilicon layer within a preset length from the edge of the opening area to the non-opening area contains amorphous silicon; the preset length is greater than or equal to 1 μm and less than or equal to 5 μm.

[0028] In the case of adopting the above technical solution, since amorphous silicon has the characteristic of acid corrosion resistance, amorphous silicon can protect the film layer (such as doped polysilicon layer) located below it, reducing or eliminating the probability of the film layer located below the amorphous silicon being corroded by acid. In addition, the work function between the above electrode layer, amorphous silicon, and doped polysilicon layer changes in a step-by-step manner, which is conducive to reducing the Schottky barrier at the metal-silicon contact interface, thereby improving the transmission efficiency of carriers to improve the battery efficiency of the solar cell. In addition, the above amorphous silicon can be used as a transition layer to reduce the mismatch between different lattice parameters, reduce lattice stress, and help form a more stable structure.

[0029] In one implementation, the surface of the metal oxide layer included in the interface layer has fixed charges.

[0030] When the above technical solution is adopted, since the surface of the metal oxide has a fixed charge, it can form field passivation at the interface between the metal and doped polysilicon, thereby inhibiting carrier recombination, improving carrier separation and transmission, and improving battery efficiency.

[0031] In one implementation, the semiconductor substrate includes a first surface and a second surface opposite to each other, and the first surface includes a first region, a second region, and a third region between the first region and the second region. The doped semiconductor layer includes: a first sub-doped semiconductor layer disposed in the first region and a second sub-doped semiconductor layer disposed in the second region; the first sub-doped semiconductor layer and the second sub-doped semiconductor layer have opposite conductivity types. The passivation layer is formed on the first sub-doped semiconductor layer, the second sub-doped semiconductor layer, and the third region; the passivation layer formed on the first sub-doped semiconductor layer has a first sub-opening portion, the first sub-opening portion exposes a portion of the first sub-doped semiconductor layer; the passivation layer formed on the second sub-doped semiconductor layer has a second sub-opening portion, the second sub-opening portion exposes a portion of the second sub-doped semiconductor layer. The electrode layer includes a first sub-electrode layer and a second sub-electrode layer; the first sub-electrode layer is connected to the first sub-doped semiconductor layer exposed by the first sub-opening portion through the first sub-opening portion; the second sub-electrode layer is connected to the second sub-doped semiconductor layer exposed by the second sub-opening portion through the second sub-opening portion. The interface layer includes a first sub-interface layer and a second sub-interface layer, and the mutual dissolution layer includes a first sub-mutual dissolution layer and a second sub-mutual dissolution layer. The first sub-interface layer and the first sub-interface layer are both located between the first sub-electrode layer and the first sub-doped semiconductor layer; the first sub-interface layer and the first sub-interface layer are arranged along the first direction. The second sub-interface layer and the second sub-interface layer are both located between the second sub-electrode layer and the second sub-doped semiconductor layer; the second sub-interface layer and the second sub-interface layer are arranged along the first direction.

[0032] At this time, the solar cell is a tunneling oxide passivated back contact solar cell (TOPCon BackContact, abbreviated as TBC). Furthermore, the third region can isolate the first sub-doped semiconductor layer from the second sub-doped semiconductor layer, reducing the carrier recombination rate at the lateral junction of the first sub-doped semiconductor layer and the second sub-doped semiconductor layer, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0033] In a second aspect, the present invention further provides a photovoltaic module. The photovoltaic module includes a battery string, an interconnection member, and an encapsulation layer. The battery string is formed by connecting a plurality of solar cells described in the above technical solution, the interconnection member is used to connect a plurality of solar cells in series to form a battery string, and the encapsulation layer is used to cover the surface of the battery string.

[0034] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0035] In a third aspect, the present invention further provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises:

[0036] First, a semiconductor substrate is provided;

[0037] Next, forming a doped semiconductor layer at least on the first surface of the semiconductor substrate;

[0038] Next, forming a passivation layer on a surface of the doped semiconductor layer away from the semiconductor substrate;

[0039] Next, the passivation layer is processed so that the passivation layer has an opening, wherein the opening exposes a portion of the doped semiconductor layer;

[0040] Next, an electrode layer is formed on the passivation layer, and the electrode layer is connected to the doped semiconductor layer exposed by the opening through the opening;

[0041] Among them, a mutual solution layer and an interface layer are formed between the electrode layer and the doped semiconductor layer; the mutual solution layer is formed by metal atoms in the electrode layer and silicon atoms in the doped semiconductor layer; the interface layer includes a silicon oxide layer and / or a metal oxide layer; the mutual solution layer and the interface layer are arranged along a first direction, and the first direction is the extension direction of the first surface of the semiconductor substrate.

[0042] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0044] Figure 1 A schematic diagram of a partial structure of a solar cell in an embodiment of the present invention Figure 1 ;

[0045] Figure 2 In the embodiment of the present invention Figure 1 A magnified view of the structure in the middle E region;

[0046] Figure 3 A schematic diagram of a partial structure of a solar cell in an embodiment of the present invention Figure 2 ;

[0047] Figure 4 In the embodiment of the present invention Figure 3 A magnified view of the structure of the middle F region;

[0048] Figure 5 A schematic diagram of a partial structure of a solar cell in an embodiment of the present invention Figure 3 ;

[0049] Figure 6 A schematic diagram of a partial structure of a tunnel oxide layer passivated back contact solar cell according to an embodiment of the present invention;

[0050] Figure 7 The structure of the solar cell manufactured in the embodiment of the present invention is shown in FIG. Figure 1 ;

[0051] Figure 8 The structure of the solar cell manufactured in the embodiment of the present invention is shown in FIG. Figure 2 ;

[0052] Fig. 9 In the embodiment of the present invention Figure 8 A magnified view of the structure of the middle G region;

[0053] Fig.10 The structure of the solar cell manufactured in the embodiment of the present invention is shown in FIG. Figure 3 ;

[0054] Fig.11 In the embodiment of the present invention Fig.10 A magnified view of the structure of the middle H region;

[0055] Fig.12 The structure of the solar cell manufactured in the embodiment of the present invention is shown in FIG. Figure 4 ;

[0056] Fig.13 In the embodiment of the present invention Fig.12 A magnified view of the structure in the middle K region.

[0057] Reference numerals:

[0058] 1-semiconductor substrate, 10-first region, 11-second region, 12-third region; 2-doped semiconductor layer, 20-convex structure, 21-recessed structure, 22-first sub-doped semiconductor layer, 23-second sub-doped semiconductor layer; 24-extension of the doped semiconductor layer; 3-passivation layer, 30-first passivation layer, 31-second passivation layer; 4-electrode layer, 40-extension of the electrode layer, 41-first metal layer, 42-second metal layer, 43-first sub-electrode layer, 44-second sub-electrode layer; 5-interface layer, 51-silicon oxide layer; 6-amorphous silicon, 7-interchangeable layer. DETAILED DESCRIPTION

[0059] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0060] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0062] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0063] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] In conjunction with the background technology section, in the process of manufacturing solar cells, electrodes are generally prepared by screen printing metal paste and high-temperature sintering. During the sintering process, the metal electrode forms a low-resistance alloy phase with the silicon in the doped polysilicon layer by burning through the anti-reflection layer or through the opening area on the anti-reflection layer, thereby achieving ohmic contact.

[0065] However, during the sintering process, the degree of downward corrosion of the metal slurry is difficult to control, and the thickness of the doped polysilicon layer is usually between tens and hundreds of nanometers. The metal slurry can easily penetrate the doped polysilicon layer and directly contact the semiconductor substrate, thereby achieving a high-density defect state, causing a very large recombination current, which seriously degrades the passivation quality.

[0066] In order to prevent the metal paste from penetrating the doped polysilicon layer, the prior art generally provides an additional functional layer (eg, a metal layer or a semiconductor layer) between the electrode and the doped polysilicon layer to prevent the metal electrode paste from corroding downward to the semiconductor substrate.

[0067] However, the addition of an additional functional layer increases the process steps and reduces the preparation efficiency. In addition, the composition of the functional layer in the prior art does not match the work function between the metal electrode and the doped semiconductor layer, resulting in low carrier transmission efficiency, which in turn affects the cell efficiency of the solar cell.

[0068] In order to solve at least part of the above technical problems, in the first aspect, the present invention provides a solar cell. The solar cell can be a back contact solar cell, a bifacial solar cell, a hybrid HBC (Hybrid Back Contact) cell, a tunneling oxide layer passivated back contact solar cell (TOPCon Back Contact, abbreviated as TBC), etc. Among them, one pole of the hybrid HBC cell is a heterojunction passivation structure, and the other pole is a tunneling oxide passivation structure.

[0069] See also Figures 1 to 4 , the solar cell comprises: a semiconductor substrate, a doped semiconductor layer 2, a passivation layer 3, an electrode layer 4, an interface layer 5 and a mutual dissolution layer 7. The doped semiconductor layer 2 is at least arranged on the first surface of the semiconductor substrate, the passivation layer 3 is arranged on the side of the doped semiconductor layer 2 away from the semiconductor substrate, the passivation layer 3 has an opening, the opening exposes part of the doped semiconductor layer 2, and the electrode layer 4 is connected to the doped semiconductor layer 2 exposed by the opening through the opening. The mutual dissolution layer 7 and the interface layer 5 are arranged between the electrode layer 4 and the doped semiconductor layer 2, the metal atoms in the electrode layer 4 and the silicon atoms in the doped semiconductor layer form a mutual dissolution layer, and the interface layer 5 comprises a silicon oxide layer and / or a metal oxide layer. The mutual dissolution layer 7 and the interface layer 5 are arranged along a first direction, and the first direction is the extension direction of the first surface of the semiconductor substrate. In the present application, the above-mentioned interface layer has a tunneling effect, and the mutual dissolution layer can be conductive.

[0070] See also Figures 1 to 4In the solar cell provided by the embodiment of the present invention, when the interface layer 5 only includes a silicon oxide layer, the silicon oxide can chemically passivate the opening, improve the passivation performance between the electrode layer 4 and the doped semiconductor layer 2, thereby improving the interface passivation performance, reducing the interface carrier recombination, and improving the battery efficiency. When the interface layer 5 only includes a metal oxide layer, the metal oxide layer can not only play a role in diffusion barrier, but also hinder the metal in the electrode layer 4 from diffusing into the semiconductor substrate, thereby improving the stability of the solar cell. At the same time, since the metal oxide layer has a higher melting point and thermal stability, the structural stability of the interface layer can be improved. In addition, the metal oxide layer can also achieve field passivation, thereby inhibiting carrier recombination, improving the separation and transmission of carriers, and improving the battery efficiency. When the interface layer 5 includes both a silicon oxide layer and a metal oxide layer, the interface layer 5 has the effects described above when the interface layer only includes a silicon oxide layer and only includes a metal oxide layer, which will not be repeated here. In addition, the above-mentioned intersoluble layer 7 is formed by the mutual diffusion of metal atoms in the electrode layer 4 and silicon atoms in the doped semiconductor layer. At this time, the intersoluble layer 7 can be referred to as a metal-silicon intersoluble layer. The work function of the metal-silicon inter-soluble layer is between that of metal and silicon, so the work function between the electrode layer 4, the metal-silicon inter-soluble layer (i.e., the inter-soluble layer 7), and the doped semiconductor layer 2 changes in a step-like manner. At this time, it is beneficial to reduce the Schottky barrier at the contact interface between the metal and silicon, thereby improving the carrier transmission efficiency and improving the cell efficiency of the solar cell.

[0071] The number of the above-mentioned miscible layers and interface layers is not specifically limited. For example, the number of miscible layers and the number of interface layers may be 1, or the number of miscible layers and the number of interface layers may be greater than or equal to 2.

[0072] In some examples, “the miscible layer and the interface layer are arranged along a first direction, and the first direction is an extension direction of the first surface of the semiconductor substrate” is explained below. It should be understood that the following description is only for understanding and is not for specific limitation.

[0073] Example 1: two adjacent intersoluble layers and interface layers are spaced apart and distributed along the first direction;

[0074] Example 2: Two adjacent miscible layers and an interface layer are abutted along a first direction;

[0075] Example 3: For two adjacent intersoluble layers and interface layers, on the first surface of the semiconductor substrate, the projection of the interface layer and the projection of the intersoluble layer have an overlapping area, and the ratio of the area of ​​the overlapping area to the area of ​​the projection of the interface layer is less than or equal to 20%. Exemplarily, the ratio can be 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1%, etc.

[0076] It should be noted that for the same solar cell, the three situations listed above may exist at the same time, or any two of them may exist, or only one of them may exist.

[0077] In some examples, the semiconductor substrate includes a first surface and a second surface opposite to each other, and the doped semiconductor layer is disposed at least on the first surface of the semiconductor substrate. In addition, whether the doped semiconductor layer is disposed on the first surface or on the second surface, the doped semiconductor layer can be disposed on the entire surface or partially. The specific arrangement of the doped semiconductor layer can be selected according to actual needs and is not specifically limited here.

[0078] In some examples, in actual application, the embodiments of the present invention do not specifically limit the material of the semiconductor substrate. For example, the semiconductor substrate can be a substrate of any semiconductor material such as a silicon substrate, a silicon germanium substrate, a germanium substrate or a gallium arsenide substrate.

[0079] In some examples, the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any one of the V-group elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, which may be any one of the III-group elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0080] In some examples, the crystal type of the semiconductor substrate may be single crystal or polycrystalline, etc.

[0081] Regarding the interface layer, there is an in-situ formed interface layer between the electrode layer and the doped semiconductor layer. Specifically, there is an in-situ induced formed interface layer between the electrode layer and the doped semiconductor layer. Since the interface layer is in-situ induced, there is no need to additionally design the material and preparation method of the interface layer. Based on this, while improving the passivation effect, it will not affect the preparation efficiency and cost of the battery.

[0082] In some examples, the thickness of the interface layer is greater than or equal to 1nm and less than or equal to 10nm. Exemplarily, the average thickness of the interface layer can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, etc. Optionally, the thickness of the interface layer is greater than or equal to 1nm and less than or equal to 5nm. In some embodiments, the thickness of the interface layer is greater than or equal to 1nm and less than or equal to 2nm. In other embodiments, the thickness of the interface layer is greater than or equal to 1nm and less than or equal to 1.5nm. The thickness direction of the interface layer is consistent with the direction A perpendicular to the first surface. Combined with the foregoing description, since the above-mentioned interface layer has a tunneling effect and since the thickness of the interface layer satisfies the above-mentioned value range, the interface layer not only does not absorb light, but also can improve the reflection of light and reduce optical losses.

[0083] In some examples, the thickness of the intersoluble layer is greater than or equal to 1 nm and less than or equal to 5 nm. Exemplarily, the thickness of the interface layer can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm. Optionally, the thickness of the intersoluble layer is greater than or equal to 1 nm and less than or equal to 2 nm. In some embodiments, the thickness of the intersoluble layer is greater than or equal to 1 nm and less than or equal to 1.5 nm.

[0084] For some examples, see Figure 1 , the intersoluble layer 7 and the interface layer 5 are alternately distributed along the first direction, the intersoluble layer 7 and the interface layer 5 form a continuous film layer, and the first direction is the extension direction of the first surface of the semiconductor substrate. In the case of adopting the above technical solution, since the intersoluble layer 7 and the interface layer 5 form a continuous film layer, it is possible to avoid the situation where there is neither an intersoluble layer nor an interface layer between the electrode layer 4 and the doped semiconductor layer 2 exposed by the opening, thereby avoiding the problem of poor passivation performance or low carrier transmission efficiency.

[0085] In some examples, the electrode layer 4 has an extension portion, the extension portion 40 of the electrode layer extends into the doped semiconductor layer 2 , and the extension portion 40 of the electrode layer includes silicon.

[0086] Combined with the above description, the electrode layer 4 is connected to the doped semiconductor layer 2 exposed by the opening through the opening, the interface layer 5 is arranged between the electrode layer 4 and the doped semiconductor layer 2, and the extension portion 40 of the electrode layer extends into the doped semiconductor layer 2. It can be seen that the electrode layer 4 does not penetrate the doped semiconductor layer 2 into the semiconductor substrate or abuts against the semiconductor substrate. At this time, it can not only reduce or eliminate the probability of forming a high-density defect state, reduce the load current, and improve the battery efficiency of the solar cell; at the same time, it can also avoid the semiconductor substrate from being damaged to ensure that the function of the semiconductor substrate is not affected, thereby ensuring the performance of the solar cell. In addition, since the extension portion 40 of the electrode layer extends into the doped semiconductor layer 2, the extension portion 40 of the electrode layer can increase the contact area between the electrode layer and the doped semiconductor layer 2, reduce the contact resistance, and reduce the series resistance, so as to effectively collect current and improve the battery efficiency of the solar cell.

[0087] For some examples, see Figure 4 , along the direction away from the electrode layer 4 and along the direction deep into the doped semiconductor layer 2, the cross-sectional area of ​​the extension portion 40 of the electrode layer gradually decreases. And / or, parallel to the first surface, the cross-sectional area of ​​the first part of the extension portion 40 of the electrode layer away from the semiconductor substrate is greater than the cross-sectional area of ​​the second part of the extension portion 40 of the electrode layer close to the semiconductor substrate. When the above technical solution is adopted, while increasing the contact area between the electrode layer 4 and the doped semiconductor layer 2 and reducing the contact resistance, the damage of the electrode layer 4 to the doped semiconductor layer 2 is reduced to ensure that the function of the doped semiconductor layer 2 meets the actual requirements. Exemplarily, the shape of the extension portion 40 of the above-mentioned electrode layer includes a quadrangular pyramid, a triangular prism, and other regular or irregular shapes.

[0088] For some examples, see Figure 4, along the direction perpendicular to the first surface, the ratio of the depth of the extension portion 40 of the electrode layer extending into the doped semiconductor layer 2 to the thickness of the doped semiconductor layer 2 is less than or equal to 99%. Exemplarily, the ratio can be 0.1%, 1%, 5%, 10%, 15%, 20%, 23%, 25%, 30%, 35%, 40%, 44%, 45%, 50%, 55%, 60%, 63%, 65%, 70%, 75%, 78%, 80%, 83%, 85%, 89%, 90%, 95% or 99%, etc. In the case of adopting the above technical solution, the extension portion 40 of the electrode layer does not penetrate the doped semiconductor layer 2 into the semiconductor substrate 1, which can not only reduce or eliminate the probability of forming a high-density defect state, reduce the load current, and improve the battery efficiency of the solar cell; at the same time, it can also avoid the semiconductor substrate 1 from being damaged to ensure that the function of the semiconductor substrate 1 is not affected, thereby ensuring the performance of the solar cell. Furthermore, it also takes into account increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance, and reducing the series resistance to effectively collect current and improve the cell efficiency of the solar cell.

[0089] In some examples, on a surface of the doped semiconductor layer close to the electrode layer, the ratio of the cross-sectional area of ​​the extension of the electrode layer on the surface to the cross-sectional area of ​​the opening parallel to the first surface is greater than or equal to 1% and less than or equal to 10%. Exemplarily, the ratio may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%, etc. When the above technical solution is adopted, the extension of the electrode layer has less pollution to the doped semiconductor layer, ensuring that the quality of the doped semiconductor layer meets the actual requirements. In addition, it takes into account increasing the contact area between the electrode layer and the doped semiconductor layer, reducing the contact resistance, and reducing the series resistance, so as to effectively collect current and improve the battery efficiency of the solar cell.

[0090] For some examples, see Figure 4 The doped semiconductor layer 2 has an extension portion, the extension portion 24 of the doped semiconductor layer extends into the electrode layer 4, and the extension portion 24 of the doped semiconductor layer includes aluminum. When the above technical solution is adopted, the extension portion 24 of the doped semiconductor layer can increase the contact area between the doped semiconductor layer 2 and the electrode layer 4, reduce the contact resistance, reduce the series resistance, effectively collect current, and improve the battery efficiency of the solar cell.

[0091] In some examples, the cross-sectional area of ​​the extension portion 24 of the doped semiconductor layer gradually decreases along the direction away from the doped semiconductor layer 2 and along the direction deep into the electrode layer 4. And / or, parallel to the first surface, the cross-sectional area of ​​the third portion of the extension portion 24 of the doped semiconductor layer away from the semiconductor substrate is smaller than the cross-sectional area of ​​the fourth portion of the extension portion 24 of the doped semiconductor layer close to the semiconductor substrate. When the above technical solution is adopted, while increasing the contact area between the electrode layer 4 and the doped semiconductor layer 2 and reducing the contact resistance, the damage of the doped semiconductor layer 2 to the electrode layer 4 is reduced to ensure that the function of the electrode layer 4 meets the actual requirements.

[0092] For some examples, see Figures 1 to 9 The doped semiconductor layer 2 includes at least one protruding structure 20 and at least one recessed structure 21. The protruding structure 20 protrudes toward one side of the electrode layer 4. Two adjacent interface layers 5 are spaced apart at the top of the protruding structure 20. The intersoluble layer 7 is located at the top of the protruding structure 20.

[0093] The above-mentioned convex structure and concave structure can not only increase the contact area between the electrode and the doped semiconductor layer, reduce the contact resistance, reduce the series resistance, effectively collect current, and improve the cell efficiency of the solar cell, but also increase the surface roughness of the doped semiconductor layer, improve the mechanical properties of the electrode layer, and improve the tensile properties of the electrode layer.

[0094] See also Figures 1 to 13 In an embodiment of the present invention, the opening of the passivation layer is formed by laser processing, and the protruding structure 20 and the recessed structure 21 included in the doped semiconductor layer 2 are also formed under the action of the laser when the laser is opened. When the interface layer 5 includes a silicon oxide layer 51, the silicon oxide layer 51 is formed by contacting the doped polysilicon with oxygen in the air after the laser opening. Since the top tension of the protruding structure 20 is large, the silicon oxide layer 51 is not easy to form a film on the top of the protruding structure 20, so that the silicon oxide layer 51 forms a discontinuous area on the top of the protruding structure 20, and when the silicon oxide layer 51 is subsequently converted into the interface layer 5 in situ, the discontinuous area is still retained. In addition, in the top area of ​​the protruding structure 20, stress and defects are more concentrated, resulting in the metal and silicon in the interface area being easy to diffuse each other, so a metal-silicon inter-soluble layer is formed in the discontinuous area of ​​the top area of ​​the protruding structure 20. When the interface layer 5 includes a metal oxide layer, the metal oxide layer can be formed by reducing silicon oxide by at least one metal in the metal electrode. Due to the reduction effect of the metal on silicon oxide, the thickness of the silicon oxide layer 51 becomes thinner. Thus, firstly, the resistance of the silicon oxide layer 51 itself is reduced, and secondly, the probability of carrier tunneling is increased, the series resistance is reduced, and the cell efficiency of the solar cell is improved.

[0095] Exemplarily, the interface layer includes a silicon oxide layer and an aluminum oxide layer, or the interface layer includes an aluminum oxide layer, or the interface layer includes a silicon oxide layer.

[0096] For example, see Figure 8 and Fig. 9 , the doped semiconductor layer includes a plurality of convex structures 20, a plurality of concave structures 21 and a plurality of horizontal structures. For example, along the first direction, the horizontal structure, the convex structure 20, the concave structure 21 and the convex structure 20 are regarded as a small unit, and the position of the doped semiconductor layer corresponding to the opening portion includes three small units. It should be noted that the horizontal structure refers to a portion of the surface of the doped semiconductor layer facing away from the semiconductor substrate 1 that is parallel to the horizontal plane or parallel to the upper and lower surfaces of the semiconductor substrate 1.

[0097] For some examples, see Figure 2 , along the direction perpendicular to the first surface, the height H of the protruding structure is greater than or equal to 1 nm and less than or equal to 50 nm, and the depth D of the recessed structure is greater than or equal to 1 nm and less than or equal to 50 nm. Exemplarily, the height of the protruding structure and the depth of the recessed structure may be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc. The height of the protruding structure and the depth of the recessed structure may be equal or unequal, and are not specifically limited here.

[0098] In the case of adopting the above technical solution, the height of the protruding structure and the depth of the recessed structure are both greater than or equal to 1nm, so that the size of the protruding structure and the recessed structure can be avoided to be too small, so as to increase the contact area between the electrode layer and the doped semiconductor layer, reduce the contact resistance, reduce the series resistance, effectively collect the current, and improve the battery efficiency of the solar cell. In addition, the height of the protruding structure is greater than or equal to 1nm, which is conducive to the formation of the mutual dissolution layer, so that the work function between the electrode layer, the metal-silicon mutual dissolution layer (i.e., the mutual dissolution layer), and the doped semiconductor layer changes in a step-like manner, thereby helping to reduce the Schottky barrier of the metal-silicon contact interface, improve the transmission efficiency of the carrier, and improve the battery efficiency of the solar cell. In addition, the height of the protruding structure and the depth of the recessed structure are both less than or equal to 50nm, so that the quality of the doped semiconductor layer and the electrode layer can be ensured, and the doped semiconductor layer and the electrode layer can be avoided from being severely damaged, thereby ensuring the quality of the solar cell.

[0099] For some examples, see Figure 5, the doped semiconductor layer 2 includes a doped polysilicon layer. Along the extension direction of the first surface, the semiconductor substrate includes an opening area and a non-opening area, and the opening portion corresponds to the opening area. The doped polysilicon layer corresponding to the opening area has amorphous silicon 6; along the extension direction of the first surface, the doped polysilicon layer within a preset length from the edge of the opening area to the non-opening area has amorphous silicon 6; the preset length L is greater than or equal to 1μm and less than or equal to 5μm. Exemplarily, the preset length L can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm, etc.

[0100] Since the amorphous silicon 6 has the characteristic of acid corrosion resistance, the amorphous silicon 6 can protect the film layer (such as the doped polysilicon layer) located below it, reducing or eliminating the probability of the film layer located below the amorphous silicon 6 being corroded by acid. In addition, the work function between the electrode layer 4, the amorphous silicon 6, and the doped polysilicon layer changes in a step-like manner, which is conducive to reducing the Schottky barrier at the metal-silicon contact interface, thereby improving the carrier transmission efficiency, so as to improve the battery efficiency of the solar cell. In addition, the amorphous silicon 6 can be used as a transition layer to reduce the mismatch between different lattice parameters, reduce lattice stress, and help form a more stable structure.

[0101] In some examples, the ratio of the thickness of the amorphous silicon to the thickness of the doped polysilicon layer is greater than or equal to 1% and less than or equal to 20%, and the thickness direction of the amorphous silicon and the thickness direction of the doped polysilicon layer are both consistent with the direction perpendicular to the first surface. Exemplarily, the above thickness ratio can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19% or 20%, etc.

[0102] For some examples, see Figure 6 , the electrode layer 4 includes: a first metal layer 41 and a second metal layer 42. The first metal layer 41 is connected to the doped semiconductor layer 2 exposed by the opening through the opening, and the second metal layer 42 is formed on a side of the first metal layer 41 away from the semiconductor substrate 1. When the above technical solution is adopted, the first metal layer 41 is in direct contact with the doped semiconductor layer 2, and the second metal layer 42 is formed above the first metal layer 41, which is used for welding and improving the oxidation resistance and corrosion resistance of the electrode layer 4.

[0103] In some examples, the second metal layer has a weldable property, which can improve the connection adhesion between the electrode and the interconnection member (such as a welding strip), improve the connection strength between the electrode and the interconnection member, and thus improve the structural stability of the photovoltaic module including the solar cell.

[0104] In some examples, the material of the first metal layer includes one or more of Al, Zn, Fe, Co, Mg, Cu, Ag, Ti, Cr and alloys thereof. The material of the second metal layer includes one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn, Zn and alloys thereof. When the above technical solution is adopted, the first metal layer needs to be easily corroded so as to open the isolation area between the n-region and the p-region by wet method to avoid short circuit, so the first metal layer is made of the above materials. The second metal layer needs to be corrosion-resistant and weldable to cooperate with the subsequent wet process, so the second metal layer is made of the above materials.

[0105] Exemplarily, the first metal layer and the second metal layer can be prepared by PVD (Physical Vapor Deposition), PVD combined with light injection, PVD combined with annealing, or PVD combined with annealing and light injection. Among them, PVD methods include magnetron sputtering, evaporation, ion plating, etc. The annealing method includes vacuum annealing or dark annealing under inert atmosphere protection. When the annealing method is vacuum annealing, PVD and annealing can be performed in the same vacuum coating equipment. For example, the PVD process can be one of the following optional methods: the first metal layer and the second metal layer are both prepared by magnetron sputtering, or both are prepared by evaporation, or one of the metal layers is prepared by magnetron sputtering and the other metal layer is prepared by evaporation. The preparation of the first metal layer and the second metal layer can be completed in the same process, so that the process flow can be simplified.

[0106] In some examples, the first metal layer may be a single-layer structure or the first metal layer includes at least two first metal sub-layers. When the first metal layer includes at least two first metal sub-layers, the material of any first metal sub-layer includes one or more of Al, Zn, Fe, Co, Mg, Cu, Ag, Ti, Cr and alloys thereof.

[0107] For example, when the material of the first metal layer is Al, the material of the second metal layer is Ni. For another example, when the first metal layer is a multilayer structure, the material of the first metal layer close to the doped semiconductor layer is Al, the material of the first metal layer far from the doped semiconductor layer is Cu, and the material of the second metal layer is Ni. For another example, when the material of the first metal layer is Al, the material of the second metal layer is Ni-Cu alloy.

[0108] When the above technical solution is adopted, optics (back reflection), electricity (conductivity) and cost are taken into consideration. For example, when the first metal layer includes two first metal sub-layers, one first metal sub-layer is made of Ag or Ti or Ni or Cr, and the other first metal sub-layer is made of Al, and Al is used as the main conductive layer. At this time, both battery efficiency and cost are taken into consideration. In addition, for metals that are easily diffused with Si (such as Cu), a sub-layer needs to be added to act as a diffusion barrier layer (such as a first metal sub-layer made of Ag or Ti or Ni or Cr).

[0109] In some examples, the second metal layer may be a single-layer structure or the second metal layer includes at least two second metal sub-layers. When the second metal layer includes at least two second metal sub-layers, the material of any second metal sub-layer includes one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn, ZnTi, Cr and alloys thereof.

[0110] In the case of adopting the above technical solution, when the second metal layer includes two second metal sub-layers, the uppermost second metal sub-layer is used for welding, and the lower second metal sub-layer is used as a diffusion barrier layer to prevent Al of the first metal layer from diffusing into the welding layer and destroying the welding performance. Furthermore, when the second metal sub-layer is made of the above material, it can be ensured that the formed second metal layer has the advantages of corrosion resistance, oxidation resistance, good weldability, etc.

[0111] The first metal layer is used as the main conductive layer and requires a certain thickness to ensure its conductivity. The second metal layer is mainly used for welding. Considering the cost and welding requirements, in some examples, the ratio of the thickness of the second metal layer to the thickness of the first metal layer in the direction perpendicular to the first surface is less than or equal to 10%. Exemplarily, the thickness ratio can be 10%, 9.5%, 9%, 8.5%, 8%, 7.5%, 7%, 6.5%, 6%, 5.5%, 5%, 4.5%, 4%, 3.5%, 3%, 2.5% or 2%, etc.

[0112] Combined with the above description, in some examples, the surface of the metal oxide layer included in the interface layer has a fixed charge. Since the surface of the metal oxide has a fixed charge, it can form a field passivation at the interface between the metal and the doped polysilicon, thereby inhibiting carrier recombination, improving carrier separation and transmission, and improving battery efficiency.

[0113] In the embodiments of the present invention, see Figures 1 to 6The passivation layer 3 includes a first passivation layer 30 and a second passivation layer 31 which are stacked, and the first passivation layer 30 is formed on a side of the doped semiconductor layer 2 away from the semiconductor substrate 1. The first passivation layer 30 includes a stack of one or more layers of aluminum oxide, silicon oxide, silicon nitride, aluminum oxynitride, and silicon oxynitride. The second passivation layer 31 includes a stack of one or more layers of silicon nitride, silicon oxynitride, and silicon oxide. Exemplarily, the first passivation layer 30 includes an aluminum oxide layer, and the second passivation layer 31 includes silicon nitride and silicon oxynitride which are stacked in a direction away from the semiconductor substrate 1.

[0114] A specific type of solar cell is used as an example for description below. It should be understood that the following description is only for understanding and not for specific limitation. Specifically, the solar cell is a tunnel oxide passivated back contact solar cell (TOPCon Back Contact, abbreviated as TBC).

[0115] See also Figure 6 The above-mentioned tunneling oxide layer passivated back contact solar cell includes a semiconductor substrate 1, a first sub-doped semiconductor layer 22, a second sub-doped semiconductor layer 23, a passivation layer 3, a first sub-electrode layer 43, a second sub-electrode layer 44, a first sub-interface layer, a second sub-interface layer, a first sub-interface layer and a second sub-interface layer.

[0116] The semiconductor substrate 1 includes a first surface and a second surface opposite to each other; the first surface includes a first region 10 , a second region 11 , and a third region 12 located between the first region 10 and the second region 11 .

[0117] The doped semiconductor layer 2 includes: a first sub-doped semiconductor layer 22 disposed in the first region 10 and a second sub-doped semiconductor layer 23 disposed in the second region 11; the first sub-doped semiconductor layer 22 and the second sub-doped semiconductor layer 23 have opposite conductivity types. The third region 12 isolates the first sub-doped semiconductor layer 22 and the second sub-doped semiconductor layer 23, thereby reducing the carrier recombination rate at the lateral boundary between the first sub-doped semiconductor layer 22 and the second sub-doped semiconductor layer 23, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0118] The passivation layer 3 is formed on the first sub-doped semiconductor layer 22, the second sub-doped semiconductor layer 23 and the third region 12; the passivation layer 3 formed on the first sub-doped semiconductor layer 22 has a first sub-opening portion, and the first sub-opening portion exposes a portion of the first sub-doped semiconductor layer 22; the passivation layer 3 formed on the second sub-doped semiconductor layer 23 has a second sub-opening portion, and the second sub-opening portion exposes a portion of the second sub-doped semiconductor layer 23.

[0119] The electrode layer 4 includes a first sub-electrode layer 43 and a second sub-electrode layer 44; the first sub-electrode layer 43 is connected to the first sub-doped semiconductor layer 22 exposed by the first sub-opening through the first sub-opening; the second sub-electrode layer 44 is connected to the second sub-doped semiconductor layer 23 exposed by the second sub-opening through the second sub-opening.

[0120] The interface layer includes a first sub-interface layer and a second sub-interface layer, and the mutual dissolving layer includes a first sub-mutual dissolving layer and a second sub-mutual dissolving layer. The first sub-interface layer and the first sub-mutual dissolving layer are both located between the first sub-electrode layer and the first sub-doped semiconductor layer; the first sub-mutual dissolving layer and the first sub-interface layer are arranged along a first direction.

[0121] The number of the first sub-interfacial layers and the first sub-interface layers is not specifically limited. For example, the number of the first sub-interfacial layers and the first sub-interface layers can be 1, or the number of the first sub-interfacial layers and the first sub-interface layers can both be greater than or equal to 2.

[0122] In some examples, the following explanation is given for “the first sub-interfacial layer and the first sub-interface layer are arranged along a first direction, and the first direction is an extension direction of the first surface of the semiconductor substrate”. It should be understood that the following description is only for understanding and is not for specific limitation.

[0123] Example 1: two adjacent first sub-intersoluble layers and first sub-interface layers are spaced apart and distributed along the first direction;

[0124] Example 2: Two adjacent first sub-intersoluble layers and the first sub-interface layer are abutted along the first direction;

[0125] Example 3: For two adjacent first sub-interface layers and first sub-interface layers, on the first surface of the semiconductor substrate, the projection of the first sub-interface layer and the projection of the first sub-interface layer have an overlapping area, and the ratio of the area of ​​the overlapping area to the area of ​​the projection of the first sub-interface layer is less than or equal to 20%. Exemplarily, the ratio can be 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1%, etc.

[0126] It should be noted that for the same solar cell, the three situations listed above may exist at the same time, or any two of them may exist, or only one of them may exist.

[0127] In one example, the second sub-interface layer and the second sub-interface layer are both located between the second sub-electrode layer and the second sub-doped semiconductor layer; and the second sub-interface layer and the second sub-interface layer are arranged along the first direction.

[0128] The number of the second sub-interface layers and the second sub-interface layers is not specifically limited. For example, the number of the second sub-interface layers and the second sub-interface layers can be 1, or the number of the second sub-interface layers and the second sub-interface layers can both be greater than or equal to 2.

[0129] In some examples, “the second sub-interfacial layer and the second sub-interface layer are arranged along a first direction, and the first direction is an extension direction of the first surface of the semiconductor substrate” is explained below. It should be understood that the following description is only for understanding and is not for specific limitation.

[0130] Example 1: two adjacent second sub-intersoluble layers and second sub-interface layers are spaced apart and distributed along the first direction;

[0131] Example 2: Two adjacent second sub-intermixture layers and second sub-interface layers are abutted along the first direction;

[0132] Example 3: For two adjacent second sub-interface layers and second sub-interface layers, on the first surface of the semiconductor substrate, the projection of the second sub-interface layer and the projection of the second sub-interface layer have an overlapping area, and the ratio of the area of ​​the overlapping area to the area of ​​the projection of the second sub-interface layer is less than or equal to 20%. Exemplarily, the ratio can be 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1%, etc.

[0133] It should be noted that for the same solar cell, the three situations listed above may exist at the same time, or any two of them may exist, or only one of them may exist.

[0134] For the first sub-doped semiconductor layer and the second sub-doped semiconductor layer, in terms of doping type, the doping type of the first sub-doped semiconductor layer can be N-type, and the doping type of the second sub-doped semiconductor layer is P-type; or, the doping type of the first sub-doped semiconductor layer can also be P-type, and the doping type of the second sub-doped semiconductor layer is N-type. The embodiment of the present invention does not specifically limit the doping type of the first sub-doped semiconductor layer and the second sub-doped semiconductor layer, as long as the doping types of the two are opposite. When the doping type is P-type, it is generally doped with group III elements. When the doping type is N-type, it is generally doped with group V elements or group VI elements. In terms of materials, the material of the first sub-doped semiconductor layer and / or the second sub-doped semiconductor layer may include any semiconductor material such as silicon, silicon germanium or germanium.

[0135] In terms of scope, the boundary between the first region 10 and the third region 12, and the boundary between the third region 12 and the second region 11 on the first surface of the semiconductor substrate 1 are both virtual boundaries. Figure 6As shown, the first sub-doped semiconductor layer 22 is formed on the first region 10, so the range of the first region 10 on the first surface of the semiconductor substrate 1 can be determined according to the requirements of the formation range of the first sub-doped semiconductor layer 22 in the actual application scenario. When the first region 10 is determined, the second region 11 and the third region 12 can be determined accordingly, and then the range of the second region 11 on the first surface of the semiconductor substrate 1 is determined according to the requirements of the formation range of the second sub-doped semiconductor layer 23 in the actual application scenario.

[0136] See also Figure 6 , the surfaces of the first region 10 and the second region 11 are both polished surfaces. At this time, the surfaces of the first region 10 and the second region 11 are flat. When a film layer is subsequently formed on the first region 10 and the second region 11, the thickness of the film layer formed on the first region 10 and the second region 11 whose surfaces are polished surfaces is greater than that on the first region 10 and the second region 11 whose surfaces are velvet surfaces. In particular, when the film layer is a passivation layer, since the thickness of the passivation layer 3 formed on the first region 10 and the second region 11 whose surfaces are polished surfaces is greater, the passivation effect of the passivation layer 3 on the first region 10 and the second region 11 can be improved, and the carrier recombination rate on the surface of the first region 10 and the second region 11 can be reduced, thereby improving the photoelectric conversion efficiency of the solar cell. Furthermore, the third region 12 has a pyramid-shaped texture structure.

[0137] In some examples, the surface roughness of the first sub-interface layer between the first sub-doped semiconductor layer and the first sub-electrode layer is greater than or equal to 1nm and less than or equal to 50nm, and the surface roughness of the second sub-interface layer between the second sub-doped semiconductor layer and the second sub-electrode layer is greater than or equal to 1nm and less than or equal to 50nm. Exemplarily, the surface roughness of the first sub-interface layer and the second sub-interface layer can be 1nm, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm, etc. Further, the surface roughness of the first sub-interface layer and the second sub-interface layer can be equal or unequal. The surface roughness of the first sub-interface layer and the second sub-interface layer within the above value range can not only improve the mechanical properties of the first sub-electrode layer and the second sub-electrode layer (for the convenience of describing the term "electrode" later), but also improve the tensile properties of the electrode layer. In this way, in the later welding process, the connection adhesion between the electrode layer and the interconnection (such as a welding strip) can be increased, and the connection strength between the electrode layer and the interconnection can be improved, thereby improving the structural stability of the photovoltaic module including the solar cell. At the same time, it can also increase the contact area between the electrode layer and the doped semiconductor layer, reduce the contact resistance, and reduce the series resistance to effectively collect current and improve the cell efficiency of the solar cell.

[0138] In some examples, on a surface of the first sub-doped semiconductor layer close to the first sub-electrode layer, the ratio of the cross-sectional area of ​​the extension portion of the first sub-electrode layer on the surface to the cross-sectional area of ​​the first sub-opening portion parallel to the first surface is greater than or equal to 1% and less than or equal to 10%. Exemplarily, the ratio may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%, etc.

[0139] In some examples, on a surface of the second sub-doped semiconductor layer close to the second sub-electrode layer, the ratio of the cross-sectional area of ​​the extension portion of the second sub-electrode layer on the surface to the cross-sectional area of ​​the second sub-opening portion parallel to the first surface is greater than or equal to 1% and less than or equal to 10%. Exemplarily, the ratio may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%, etc.

[0140] In some examples, along a direction perpendicular to the first surface, a ratio of a depth of an extension of the first sub-electrode layer extending into the first sub-doped semiconductor layer to a total thickness of the first sub-doped semiconductor layer is less than or equal to 99%. Exemplarily, the ratio may be 0.1%, 1%, 5%, 10%, 15%, 20%, 23%, 25%, 30%, 35%, 40%, 44%, 45%, 50%, 55%, 60%, 63%, 65%, 70%, 75%, 78%, 80%, 83%, 85%, 89%, 90%, 95% or 99%, etc.

[0141] In some examples, along a direction perpendicular to the first surface, a ratio of a depth of an extension of the second sub-electrode layer extending into the second sub-doped semiconductor layer to a total thickness of the second sub-doped semiconductor layer is less than or equal to 99%. Exemplarily, the ratio may be 0.1%, 1%, 5%, 10%, 15%, 20%, 23%, 25%, 30%, 35%, 40%, 44%, 45%, 50%, 55%, 60%, 63%, 65%, 70%, 75%, 78%, 80%, 83%, 85%, 89%, 90%, 95% or 99%, etc.

[0142] In some examples, the first sub-doped semiconductor layer includes a doped polysilicon layer. Along the extension direction of the first surface, the semiconductor substrate corresponding to the first sub-doped semiconductor layer includes an opening area and a non-opening area, and the opening portion corresponds to the opening area. The doped polysilicon layer corresponding to the opening area contains amorphous silicon; along the extension direction of the first surface, the doped polysilicon layer within a preset length from the edge of the opening area to the non-opening area contains amorphous silicon; the preset length is greater than or equal to 1μm and less than or equal to 5μm. Exemplarily, the preset length can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm, etc. In some examples, the ratio of the thickness of amorphous silicon to the thickness of the doped polysilicon layer is greater than or equal to 1% and less than or equal to 20%, and the thickness direction of the amorphous silicon and the thickness direction of the doped polysilicon layer are both consistent with the direction perpendicular to the first surface. Exemplarily, the ratio of the above thicknesses can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19% or 20%, etc.

[0143] In some examples, the second sub-doped semiconductor layer includes a doped polysilicon layer. Along the extension direction of the first surface, the semiconductor substrate corresponding to the second sub-doped semiconductor layer includes an opening area and a non-opening area, and the opening portion corresponds to the opening area. The doped polysilicon layer corresponding to the opening area contains amorphous silicon; along the extension direction of the first surface, the doped polysilicon layer within a preset length from the edge of the opening area to the non-opening area contains amorphous silicon; the preset length is greater than or equal to 1μm and less than or equal to 5μm. Exemplarily, the preset length can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm, etc. In some examples, the ratio of the thickness of amorphous silicon to the thickness of the doped polysilicon layer is greater than or equal to 1% and less than or equal to 20%, and the thickness direction of the amorphous silicon and the thickness direction of the doped polysilicon layer are both consistent with the direction perpendicular to the first surface. Exemplarily, the ratio of the above thicknesses can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19% or 20%, etc.

[0144] In a second aspect, an embodiment of the present invention further provides a photovoltaic module. The photovoltaic module includes a battery string, an interconnection member, and an encapsulation layer. The battery string is formed by connecting a plurality of solar cells described in the above technical solution, the interconnection member is used to connect a plurality of solar cells in series to form a battery string, and the encapsulation layer is used to cover the surface of the battery string.

[0145] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0146] In some embodiments, the photovoltaic module includes a cover plate, an encapsulation layer, a battery string, an encapsulation layer and a back plate. Wherein, the battery string is formed by connecting a plurality of solar cells described in the first aspect. For example, the number of solar cells connected in series can be 4-20, and the above-mentioned solar cells form a plurality of battery modules, each battery module has the same number of solar cells, and the solar cells in the battery modules are connected in series. The battery modules can be connected in series or in parallel, and the solar cells in the battery string are connected by bus bars arranged on both sides of the electrical connection layer, and the multiple columns of welding strips (i.e., interconnects) of adjacent solar cells are correspondingly connected or integrated. The spacing between two adjacent battery modules is greater than or equal to 0.5 mm and less than or equal to 10 mm, and the spacing between two adjacent solar cells in each battery module is greater than or equal to 0.5 mm and less than or equal to 10 mm. Exemplarily, the spacing between two adjacent battery modules and the spacing between two adjacent solar cells in each battery module can be 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm, 6.5mm, 7mm, 7.5mm, 8mm, 8.5mm, 9mm, 9.5mm or 10mm, etc.

[0147] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises:

[0148] First, a semiconductor substrate is provided. For the related description of the semiconductor substrate, reference may be made to the first aspect and will not be repeated here.

[0149] Before actual use, the semiconductor substrate is first polished and cleaned. The specific processing process is not described in detail here, and reference may be made to the prior art.

[0150] Next, forming a doped semiconductor layer at least on the first surface of the semiconductor substrate;

[0151] For example, a process such as chemical vapor deposition can be used to form a semiconductor material layer at least on the first surface of the semiconductor substrate. Then, the semiconductor material layer is doped to form a doped semiconductor layer on the surface of the semiconductor substrate, and a doped silicon glass layer is formed on the doped semiconductor layer. The material and thickness of the doped semiconductor layer can refer to the above description.

[0152] For example, the semiconductor material layer may be a polysilicon layer, and a doped polysilicon layer and a phosphosilicate glass layer on the surface thereof are formed by a phosphorus diffusion device. The phosphosilicate glass layer may be selectively removed or retained according to actual needs.

[0153] Next, see Figure 7 A passivation layer 3 is formed on a side of the doped semiconductor layer 2 away from the semiconductor substrate 1. For the relevant description of the passivation layer, reference may be made to the first aspect and will not be repeated here.

[0154] Next, see Figure 8 , processing the passivation layer 3 so that the passivation layer 3 has an opening, and the opening exposes a portion of the doped semiconductor layer 2;

[0155] For example, see Figures 8 to 11 , the passivation layer 3 is laser grooved so that the passivation layer 3 has an opening, and the opening exposes a portion of the doped semiconductor layer 2. In this process, at least one protruding structure 20 and at least one recessed structure 21 are formed on the surface of the doped semiconductor layer 2 under the action of the laser. Under the action of oxygen in the environment, a silicon oxide layer 51 is generated on the surface of the doped semiconductor layer 2 at the opening. Since the top tension of the protruding structure 20 is large, the silicon oxide layer 51 is not easy to form a film on the top of the protruding structure 20, thereby forming a discontinuous area of ​​the silicon oxide layer 51 on the top of the protruding structure 20.

[0156] Next, see Fig.12 and Fig.13 , forming an electrode layer 4 on the passivation layer 3, wherein the electrode layer 4 is connected to the doped semiconductor layer 2 exposed by the opening through the opening;

[0157] Exemplarily, the electrode layer is prepared on the surface and opening of the passivation layer by PVD (Physical Vapor Deposition), PVD combined with light injection, PVD combined with annealing, or PVD combined with annealing and light injection. In this process, part or all of the silicon oxide is reduced by the metal in the electrode, so that the thickness of the silicon oxide layer 51 becomes thinner, and the interface layer 5 is finally obtained. That is, an in-situ induced interface layer 5 is formed between the electrode layer 4 and the doped semiconductor layer 2. It should be noted that, depending on the degree of reduction, the interface layer 5 can be composed of silicon oxide and metal oxide, or the interface layer 5 can be composed only of metal oxide. Of course, in one possible case, the metal does not reduce the silicon oxide layer 51, so that the interface layer 5 only includes silicon oxide. In one example, a mutual solution layer 7 is also formed between the electrode layer 4 and the doped semiconductor layer 2, and the mutual solution layer 7 is formed by metal atoms in the electrode layer 4 and silicon atoms in the doped semiconductor layer. The mutual solution layer and the interface layer are arranged along a first direction, and the first direction is the extension direction of the first surface of the semiconductor substrate. For the relevant description of the miscible layer and the interface layer, please refer to the first aspect and will not be described in detail here.

[0158] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0159] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0160] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: Semiconductor substrate; A doped semiconductor layer is disposed at least on the first surface of the semiconductor substrate; A passivation layer is disposed on a side of the doped semiconductor layer away from the semiconductor substrate; The passivation layer has an opening, and the opening exposes a portion of the doped semiconductor layer; an electrode layer, wherein the electrode layer is connected to the doped semiconductor layer exposed by the opening through the opening; A mutual dissolution layer and an interface layer are provided between the electrode layer and the doped semiconductor layer; the metal atoms in the electrode layer and the silicon atoms in the doped semiconductor layer form the mutual dissolution layer; the interface layer includes a silicon oxide layer and / or a metal oxide layer; The intersoluble layer and the interface layer are arranged along a first direction, and the first direction is an extension direction of the first surface of the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that The mutual dissolving layer and the interface layer are alternately distributed along the first direction, and the mutual dissolving layer and the interface layer form a continuous film layer.

3. The solar cell according to claim 1, characterized in that The electrode layer has an extension portion, and the extension portion of the electrode layer extends into the doped semiconductor layer; the extension portion of the electrode layer includes silicon element.

4. The solar cell according to claim 3, characterized in that: Along the direction away from the electrode layer and along the direction deep into the doped semiconductor layer, the cross-sectional area of ​​the extension portion of the electrode layer gradually decreases; And / or, parallel to the first surface, a cross-sectional area of ​​a first portion of the extension portion of the electrode layer away from the semiconductor substrate is greater than a cross-sectional area of ​​a second portion of the extension portion of the electrode layer close to the semiconductor substrate.

5. The solar cell according to claim 3, characterized in that: Along a direction perpendicular to the first surface, a ratio of a depth of the extension portion of the electrode layer extending into the doped semiconductor layer to a thickness of the doped semiconductor layer is less than or equal to 99%.

6. The solar cell according to claim 3, characterized in that: On a surface of the doped semiconductor layer close to the electrode layer, a ratio of a cross-sectional area of ​​an extension portion of the electrode layer on the surface to a cross-sectional area of ​​the opening portion parallel to the first surface is greater than or equal to 1% and less than or equal to 10%.

7. The solar cell according to claim 1, characterized in that The doped semiconductor layer has an extension portion, and the extension portion of the doped semiconductor layer extends into the electrode layer; the extension portion of the doped semiconductor layer includes aluminum elements.

8. The solar cell according to claim 7, characterized in that: Along the direction away from the doped semiconductor layer and along the direction going deeper into the electrode layer, the cross-sectional area of ​​the extension portion of the doped semiconductor layer gradually decreases; And / or, parallel to the first surface, a cross-sectional area of ​​a third portion of the extension portion of the doped semiconductor layer away from the semiconductor substrate is smaller than a cross-sectional area of ​​a fourth portion of the extension portion of the doped semiconductor layer close to the semiconductor substrate.

9. The solar cell according to claim 1, characterized in that: The doped semiconductor layer includes at least one protruding structure and at least one recessed structure; the protruding structure protrudes toward one side of the electrode layer; two adjacent interface layers are spaced apart at the top of the protruding structure, and the intersoluble layer is located at the top of the protruding structure.

10. The solar cell according to claim 9, characterized in that: Along a direction perpendicular to the first surface, a height of the protruding structure is greater than or equal to 1 nm and less than or equal to 50 nm, and a depth of the recessed structure is greater than or equal to 1 nm and less than or equal to 50 nm.

11. The solar cell according to any one of claims 1 to 10, characterized in that: The doped semiconductor layer includes a doped polysilicon layer; along the extension direction of the first surface, the semiconductor substrate includes an opening area and a non-opening area, and the opening portion corresponds to the opening area; The doped polysilicon layer corresponding to the opening area contains amorphous silicon; Along the extension direction of the first surface, the doped polysilicon layer within a preset length from the edge of the opening area to the non-opening area contains amorphous silicon; the preset length is greater than or equal to 1 μm and less than or equal to 5 μm.

12. The solar cell according to claim 1, characterized in that The interface layer includes a metal oxide layer whose surface has fixed charges.

13. The solar cell according to any one of claims 1 to 12, characterized in that: The semiconductor substrate comprises the first surface and the second surface opposite to each other; the first surface comprises a first region, a second region and a third region located between the first region and the second region; The doped semiconductor layer comprises: a first sub-doped semiconductor layer disposed in the first region and a second sub-doped semiconductor layer disposed in the second region; the first sub-doped semiconductor layer and the second sub-doped semiconductor layer have opposite conductivity types; The passivation layer is formed on the first sub-doped semiconductor layer, the second sub-doped semiconductor layer and the third region; the passivation layer formed on the first sub-doped semiconductor layer has a first sub-opening portion, and the first sub-opening portion exposes a portion of the first sub-doped semiconductor layer; the passivation layer formed on the second sub-doped semiconductor layer has a second sub-opening portion, and the second sub-opening portion exposes a portion of the second sub-doped semiconductor layer; The electrode layer includes a first sub-electrode layer and a second sub-electrode layer; the first sub-electrode layer is connected to the first sub-doped semiconductor layer exposed by the first sub-opening through the first sub-opening; the second sub-electrode layer is connected to the second sub-doped semiconductor layer exposed by the second sub-opening through the second sub-opening; The interface layer includes a first sub-interface layer and a second sub-interface layer, and the mutual dissolving layer includes a first sub-mutual dissolving layer and a second sub-mutual dissolving layer; The first sub-interface layer and the first sub-interface layer are both located between the first sub-electrode layer and the first sub-doped semiconductor layer; the first sub-interface layer and the first sub-interface layer are arranged along the first direction; The second sub-interface layer and the second sub-interface layer are both located between the second sub-electrode layer and the second sub-doped semiconductor layer; the second sub-interface layer and the second sub-interface layer are arranged along the first direction.

14. A photovoltaic module, characterized in that: The photovoltaic module comprises: A battery string, wherein the battery string is formed by connecting a plurality of solar cells according to any one of claims 1 to 13; An interconnector, wherein the interconnector is used to connect a plurality of the solar cells in series to form the cell string; The encapsulation layer is used to cover the surface of the battery string.

15. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate; forming a doped semiconductor layer at least on a first surface of the semiconductor substrate; forming a passivation layer on a surface of the doped semiconductor layer away from the semiconductor substrate; Processing the passivation layer so that the passivation layer has an opening, wherein the opening exposes a portion of the doped semiconductor layer; forming an electrode layer on the passivation layer, wherein the electrode layer is connected to the doped semiconductor layer exposed by the opening through the opening; Among them, a mutual solution layer and an interface layer are formed between the electrode layer and the doped semiconductor layer; the mutual solution layer is formed by metal atoms in the electrode layer and silicon atoms in the doped semiconductor layer; the interface layer includes a silicon oxide layer and / or a metal oxide layer; the mutual solution layer and the interface layer are arranged along a first direction, and the first direction is the extension direction of the first surface of the semiconductor substrate.

Images