Pixel circuit, driving method thereof and display device

Abstract

The invention provides a pixel circuit, a driving method thereof and a display device, the pixel circuit comprises a driving circuit, a first compensation circuit and a second compensation circuit, the first compensation circuit comprises a first storage capacitor, a first pole of the first storage capacitor is electrically connected with a control end of the driving circuit, and a second pole of the second storage capacitor is electrically connected with a control end of the driving circuit; the second electrode of the first storage capacitor is electrically connected with the first end of the driving circuit; the second compensation circuit comprises a second storage capacitor and a first switch transistor, a first electrode of the second storage capacitor is electrically connected with the first end of the driving circuit, a first electrode of the first switch transistor is electrically connected with the second storage capacitor, and a grid electrode of the first switch transistor is configured to receive a second compensation control signal; and the second compensation circuit is configured to compensate the driving circuit in response to a second compensation control signal, and the first switch transistor in the pixel circuit can reduce the voltage of the first end of the driving circuit when being closed, so that the driving current is more stable, and the brightness uniformity of the display panel comprising the pixel circuit is further improved.

Description

Pixel circuit, driving method thereof, and display device Technical Field

[0001] At least one embodiment of the present disclosure relates to a pixel circuit, a driving method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, low-temperature polycrystalline silicon-oxide (LTPO) pixel circuits have been increasingly used in display devices. Combined with the narrow-frame design, the LTPO pixel circuit has a high refresh rate, can achieve low leakage, and is conducive to improving the stability of the gate voltage of the driving transistor.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0005] At least one embodiment of the present disclosure provides a pixel circuit, which includes a driving circuit, a first compensation circuit and a second compensation circuit, wherein the driving circuit includes a control end, a first end and a second end, and is configured to control the magnitude of the driving current flowing through the first end and the second end; the first compensation circuit is configured to apply a reference signal to the control end of the driving circuit in response to a first compensation control signal, wherein the first compensation circuit includes a first storage capacitor, a first electrode of the first storage capacitor is electrically connected to the control end of the driving circuit, and a second electrode of the first storage capacitor is electrically connected to the first end of the driving circuit; the second compensation circuit includes a second storage capacitor and a first switching transistor, wherein the first electrode of the second storage capacitor is electrically connected to the first end of the driving circuit, the first electrode of the first switching transistor is electrically connected to the second storage capacitor, the gate of the first switching transistor is configured to receive a second compensation control signal, and the second compensation circuit is configured to compensate the driving circuit in response to the second compensation control signal.

[0006] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a light-emitting element, which is configured to emit light under the drive of the driving current, wherein the first end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element; the driving circuit includes a driving transistor, the gate of the driving transistor is electrically connected to the first node as the control end of the driving circuit, the first pole of the driving transistor is electrically connected to the second node as the first end of the driving circuit, and the second pole of the driving transistor is electrically connected to the third node as the second end of the driving circuit.

[0007] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the first electrode of the first switch transistor is electrically connected to the first electrode of the second storage capacitor, and the second electrode of the first switch transistor is electrically connected to the second node.

[0008] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the first electrode of the second storage capacitor is electrically connected to the second node, and the second electrode of the second storage capacitor is electrically connected to the first electrode of the first switching transistor.

[0009] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a reset circuit, wherein the control end of the reset circuit is configured to receive a reset control signal, the first end of the reset circuit is electrically connected to the first electrode of the light-emitting element, the second end of the reset circuit is electrically connected to the reset signal end to receive the reset signal, and the reset circuit is configured to apply the reset signal to the first electrode of the light-emitting element and the first end of the driving circuit in response to the reset control signal; the reset circuit includes a reset transistor, the gate of the reset transistor is electrically connected to the reset control end to receive the reset control signal, the first pole of the reset transistor is electrically connected to the first electrode of the light-emitting element, and the second pole of the reset transistor is electrically connected to the reset signal end to receive the reset signal.

[0010] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second electrode of the second storage capacitor is electrically connected to the constant voltage terminal to receive the constant voltage from the constant voltage terminal.

[0011] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first electrode of the first switching transistor is electrically connected to the first electrode of the second storage capacitor, the second electrode of the first switching transistor is electrically connected to the second node, and the second electrode of the second storage capacitor is electrically connected to the constant voltage end.

[0012] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first electrode of the second storage capacitor is electrically connected to the second node, the second electrode of the second storage capacitor is electrically connected to the first electrode of the first switching transistor, and the second electrode of the first switching transistor is electrically connected to the constant voltage end.

[0013] For example, in the pixel circuit provided according to at least one embodiment of the present disclosure, the reset transistor serves as the first switching transistor, the reset control signal serves as the second compensation control signal, and the reset signal terminal electrically connected to the second electrode of the reset transistor serves as the constant voltage terminal; the first electrode of the second storage capacitor is electrically connected to the second node, and the second electrode of the second storage capacitor is electrically connected to the second electrode of the reset transistor to be electrically connected to the reset signal terminal.

[0014] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second electrode of the second storage capacitor is electrically connected to the first electrode of the light-emitting element, and the first electrode of the reset transistor is electrically connected to the first electrode of the light-emitting element.

[0015] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a first light-emitting control circuit, the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the second end of the driving circuit, the second end of the first light-emitting control circuit is electrically connected to the first voltage end to receive a first power supply voltage, and the first light-emitting control circuit is configured to apply the first power supply voltage to the second end of the driving circuit 1 in response to the first light-emitting control signal; the first light-emitting control circuit includes a first light-emitting control transistor, the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control end to receive the first light-emitting control signal, the first electrode of the first light-emitting control transistor is electrically connected to the first voltage end to receive the first power supply voltage, and the second electrode of the first light-emitting control transistor is electrically connected to the third node.

[0016] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a second light-emitting control circuit, the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the second node, the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element, the second light-emitting control circuit is configured to apply the driving current to the light-emitting element and allow the reset signal to be applied to the first end of the driving circuit in response to the second light-emitting control signal, the second light-emitting control signal is different from the first light-emitting control signal; the second light-emitting control circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control end to receive the second light-emitting control signal, the first electrode of the second light-emitting control transistor is electrically connected to the second node, the second electrode of the light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second voltage end to receive a second power supply voltage.

[0017] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the gate of the first switching transistor and the gate of the second light-emitting control transistor are electrically connected, the first switching transistor and the second light-emitting control transistor share a gate, the second light-emitting control signal serves as the second compensation control signal, and the type of the first switching transistor is different from the type of the second light-emitting control transistor; or the gate of the first switching transistor and the gate of the second light-emitting control transistor are independent of each other and not electrically connected.

[0018] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the gate of the first switching transistor is electrically connected to the gate of the reset transistor, the first switching transistor and the reset transistor share a gate, the reset control signal serves as the second compensation control signal, and the type of the first switching transistor is the same as the type of the reset transistor; or, the gate of the first switching transistor and the gate of the reset transistor are independent of each other and not electrically connected.

[0019] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second compensation circuit also includes a second switching transistor, the first electrode of the second switching transistor is electrically connected to the second electrode of the second storage capacitor, and the second electrode of the second switching transistor is electrically connected to the constant voltage end.

[0020] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second compensation circuit also includes a second switching transistor, the second electrode of the second storage capacitor is electrically connected to the first electrode of the second switching transistor, and the second electrode of the second switching transistor is electrically connected to the first electrode of the light-emitting element.

[0021] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, at least two of the gates of the first switching transistor, the second switching transistor, and the reset transistor are electrically connected, and the at least two share a gate and are of the same type.

[0022] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a data write circuit, the control end of the data write circuit is configured to receive a data scan signal, the first end of the data write circuit is electrically connected to the data signal end to receive the data signal, the second end of the data write circuit is electrically connected to the first node, and the data write circuit is configured to write the data signal to the control end of the driving circuit in response to the data scan signal; wherein, the data write circuit includes a data transistor, the gate of the data transistor is electrically connected to the data scan signal end to receive the data scan signal, the first electrode of the data transistor is electrically connected to the data signal end to receive the data signal, and the second electrode of the data transistor is electrically connected to the first node.

[0023] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the control end of the first compensation circuit is configured to receive the first compensation control signal, the first end of the first compensation circuit is electrically connected to the reference signal end to receive the reference signal, the first compensation circuit includes a first compensation transistor, the gate of the first compensation transistor is electrically connected to the first compensation control signal end to receive the first compensation control signal, the first electrode of the first compensation transistor is electrically connected to the reference signal end to receive the reference signal, and the second electrode of the first compensation transistor is electrically connected to the first node.

[0024] At least one embodiment of the present disclosure further provides a display device, which includes the pixel circuit described in any of the above embodiments.

[0025] At least one embodiment of the present disclosure further provides a driving method, which is applicable to the pixel circuit according to any of the above embodiments, and the driving method includes: in a data writing stage, the second compensation control signal is an on signal to turn on the first switching transistor; when entering the light-emitting stage from the data writing stage, the second compensation control signal is changed from an on signal to an off signal to turn off the first switching transistor, wherein in the light-emitting stage, the second compensation control signal remains an off signal.

[0026] For example, according to the driving method provided by at least one embodiment of the present disclosure, the pixel circuit also includes a data writing circuit, the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the data signal end to receive the data signal, the second end of the data writing circuit is electrically connected to the first node, and the data writing circuit is configured to write the data signal to the control end of the driving circuit in response to the data scanning signal; the driving method also includes: in the data writing stage, making the data scanning signal a turn-on signal to write the data signal to the control end of the driving circuit; and when entering the light-emitting stage from the data writing stage, making the data scanning signal change from a turn-on signal to a turn-off signal to simultaneously turn off the data writing circuit and the first switching transistor, wherein, in the light-emitting stage, the data scanning signal remains a turn-off signal.

[0027] For example, according to the driving method provided by at least one embodiment of the present disclosure, the driving method also includes: in a compensation stage before the data writing stage, setting the second compensation control signal as a turn-on signal to turn on the first switching transistor, and the second compensation circuit is configured to compensate the driving circuit in response to the second compensation control signal.

[0028] For example, according to the driving method provided by at least one embodiment of the present disclosure, in the compensation stage, the second electrode of the second storage capacitor receives a constant voltage from the constant voltage terminal.

[0029] For example, according to the driving method provided by at least one embodiment of the present disclosure, the pixel circuit further includes a light-emitting element, a second light-emitting control circuit and a reset circuit; the light-emitting element is configured to emit light under the drive current; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the first end of the driving circuit, and the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element; the control end of the reset circuit is configured to receive a reset control signal, the first end of the reset circuit is electrically connected to the first electrode of the light-emitting element, and the second end of the reset circuit is electrically connected to the reset signal end to receive the reset signal; the driving method further includes: in a reset stage before the compensation stage, setting the first compensation control signal to a turn-on signal to turn on the first compensation circuit, the first compensation circuit applies the reference signal to the control end of the driving circuit, setting the second light-emitting control signal to a turn-on signal to turn on the second light-emitting control circuit, and setting the reset control signal to a turn-on signal to turn on the reset circuit, applying the reset signal to the first electrode of the light-emitting element through the reset circuit, and applying the reset signal to the first end of the driving circuit through the second light-emitting control circuit.

[0030] For example, according to the driving method provided by at least one embodiment of the present disclosure, in each of the reset stage, the compensation stage, the data writing stage, and the light-emitting stage, the second compensation control signal and the second light-emitting control signal are opposite switching signals to control the switching states of their corresponding circuits in opposite directions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0032] FIG1 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0033] FIG. 2A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 1 .

[0034] FIG. 2B is a schematic diagram of the pixel circuit shown in FIG. 2A in a reset phase.

[0035] FIG. 2C is a schematic diagram of the pixel circuit shown in FIG. 2A in a compensation stage.

[0036] FIG. 2D is a schematic diagram of the pixel circuit shown in FIG. 2A in a data writing phase.

[0037] FIG. 2E is a schematic diagram of the pixel circuit shown in FIG. 2A in a light emitting stage.

[0038] FIG3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0039] FIG4 is a circuit diagram of another implementation example of the pixel circuit shown in FIG1 .

[0040] FIG5 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0041] FIG6 is a circuit diagram of yet another implementation example of the pixel circuit shown in FIG1 .

[0042] FIG7 is a circuit diagram of yet another implementation example of the pixel circuit shown in FIG1 .

[0043] FIG8 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0044] FIG9 is a circuit diagram of an implementation example of the pixel circuit shown in FIG8 .

[0045] FIG10 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0046] FIG. 11A is a circuit diagram of another implementation example of the pixel circuit shown in FIG. 8 .

[0047] FIG11B is a schematic diagram of the pixel circuit shown in FIG11A in a reset phase.

[0048] FIG. 11C is a schematic diagram of the pixel circuit shown in FIG. 11A in a compensation stage.

[0049] FIG11D is a schematic diagram of the pixel circuit shown in FIG11A in a data writing phase.

[0050] FIG11E is a schematic diagram of the pixel circuit shown in FIG11A in a light emitting stage.

[0051] FIG12 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0052] FIG13 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0053] FIG14 is a circuit diagram of an implementation example of the pixel circuit shown in FIG13 .

[0054] FIG15 is a circuit diagram of another implementation example of the pixel circuit shown in FIG13 .

[0055] FIG16 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0056] FIG17A is a circuit diagram of an implementation example of the pixel circuit shown in FIG16 .

[0057] FIG17B is a schematic diagram of the pixel circuit shown in FIG17A in a reset phase.

[0058] FIG17C is a schematic diagram of the pixel circuit shown in FIG17A in the compensation stage.

[0059] FIG17D is a schematic diagram of the pixel circuit shown in FIG17A in a data writing phase.

[0060] FIG17E is a schematic diagram of the pixel circuit shown in FIG17A in a light emitting stage.

[0061] FIG18 is a circuit diagram of another implementation example of the pixel circuit shown in FIG16 .

[0062] FIG19 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0063] FIG20 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0064] FIG21A is a circuit diagram of an implementation example of the pixel circuit shown in FIG20 .

[0065] FIG21B is a schematic diagram of the pixel circuit shown in FIG21A in a reset phase.

[0066] FIG21C is a schematic diagram of the pixel circuit shown in FIG21A in the compensation stage.

[0067] FIG21D is a schematic diagram of the pixel circuit shown in FIG21A in a data writing phase.

[0068] FIG21E is a schematic diagram of the pixel circuit shown in FIG21A in a light emitting stage.

[0069] FIG22 is a circuit diagram of another implementation example of the pixel circuit shown in FIG20 .

[0070] FIG23 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0072] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0073] The features "perpendicular," "parallel," and "identical" used in the embodiments of the present disclosure include the features "perpendicular," "parallel," and "identical" in the strict sense, as well as "approximately perpendicular," "approximately parallel," and "approximately identical" that include certain errors, taking into account the errors associated with the measurement of specific quantities (i.e., the limitations of the measurement system), and represent within the acceptable deviation range for the specific value determined by ordinary technicians in this field. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center.

[0074] In some cases, a display device may experience short-term afterimages during display. This means that after displaying the same image for a period of time, when the display device switches to the next image, a portion of the original image will remain and appear in the next image. After a period of time, the afterimage disappears. The cause of the short-term afterimage may be the hysteresis effect of the driver transistor in the pixel circuit. The hysteresis effect is mainly caused by the threshold voltage (Vth) shift caused by mobile ions remaining in the holes. When the display device switches images, the Vgs (the voltage difference between the gate and source of the driver transistor) in the initialization phase of the driver transistor may be different, which may cause the threshold voltage of the driver transistor to shift.

[0075] For example, after a display device displays an initial image for a period of time, when the display device switches to a new image, the initial image may still partially remain for several hours, thereby affecting the display. Therefore, eliminating the threshold voltage (Vth) offset of the driving transistor is an urgent problem to be solved.

[0076] At the same time, in the pixel circuit, the first electrode of the data write transistor is usually electrically connected to the gate of the drive transistor so that the data write transistor can write the data signal to the gate of the drive transistor in response to the data scan signal. When the pixel circuit switches to the light-emitting stage, the data write transistor will be in the off state. Since there is a parasitic capacitance between the gate of the data write transistor and the first electrode of the above-mentioned data write transistor, the voltage of the first electrode of the data write transistor may be reduced at the moment the data write transistor is turned off, thereby reducing the gate-source voltage Vgs of the drive transistor in the light-emitting stage. Therefore, when the gate-source voltage Vgs of the drive transistors of different sub-pixels in the display panel are reduced to different degrees in the light-emitting stage, the brightness of different sub-pixels is different, which in turn affects the uniformity of the brightness of the entire display panel. In addition, due to the complex internal structure of the pixel circuit, some external signals may have parasitic capacitance with the drive transistor, which may cause crosstalk, causing the display panel to display abnormally and affecting the display effect.

[0077] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0078] At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a first compensation circuit and a second compensation circuit, the driving circuit including a control end, a first end and a second end, and being configured to control the magnitude of the driving current flowing through the first end and the second end; the first compensation circuit is configured to apply a reference signal to the control end of the driving circuit in response to a first compensation control signal, the first compensation circuit includes a first storage capacitor, the first electrode of the first storage capacitor is electrically connected to the control end of the driving circuit, and the second electrode of the first storage capacitor is electrically connected to the first end of the driving circuit; the second compensation circuit includes a second storage capacitor and a first switching transistor, the first electrode of the second storage capacitor is electrically connected to the first end of the driving circuit, the first electrode of the first switching transistor is electrically connected to the second storage capacitor, the gate of the first switching transistor is configured to receive a second compensation control signal, and the second compensation circuit is configured to compensate the driving circuit in response to the second compensation control signal.

[0079] At least one embodiment of the present disclosure provides a pixel circuit that reduces the impact of the offset of the threshold voltage of the driving transistor by electrically connecting one electrode of the second storage capacitor of the second compensation circuit to the first end of the driving circuit; at the same time, by providing a first switching transistor electrically connected to the second storage capacitor, on the one hand, when the pixel circuit switches to the light-emitting stage, the first switching transistor can reduce the voltage of the first end of the driving circuit when it switches from on to off, thereby reducing the impact of the data writing transistor on reducing the gate voltage of the driving transistor when it is turned off, so that the Vgs fluctuation of the driving transistor in the light-emitting stage is smaller, thereby improving the uniformity of the brightness of the display panel. On the other hand, the first switching transistor can also reduce the parasitic capacitance between other external signals and the driving transistor, thereby reducing crosstalk and improving the display effect. During the operation of the pixel circuit, it is difficult to quickly reduce the voltage drop at the first end of the driving circuit when the pixel circuit switches to the light-emitting stage. It is also an important factor affecting display uniformity. Therefore, the pixel circuit provided by the embodiment of the present application solves this problem and is of great significance to improving display quality.

[0080] The pixel circuit and its driving method, and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0081] FIG1 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0082] As shown in FIG1 , the pixel circuit 10 includes a driving circuit 100 , a data writing circuit 200 , a first compensation circuit 300 , a first light emitting control circuit 400 , a second light emitting control circuit 500 , a light emitting element 600 , a reset circuit 700 and a second compensation circuit 800 .

[0083] As shown in FIG1 , the driving circuit 100 includes a control terminal 100m, a first terminal 100a, and a second terminal 100b. The control terminal 100m of the driving circuit 100 is electrically connected to a first node N1, the first terminal 100a of the driving circuit 100 is electrically connected to a second node N2, and the second terminal 100b of the driving circuit 100 is electrically connected to a third node N3. The driving circuit 100 is configured to control the magnitude of a driving current flowing through the first terminal 100a and the second terminal 100b. For example, the driving current can be used to drive the light-emitting element 600 to emit light. For example, in the light-emitting phase, the driving circuit 100 can provide a driving current to the light-emitting element 600 to drive the light-emitting element 600 to emit light, and the light can be emitted according to a desired "grayscale".

[0084] As shown in FIG1 , the data write circuit 200 includes a control terminal 200m, a first terminal 200a, and a second terminal 200b. The control terminal 200m of the data write circuit 200 is configured to receive a data scan signal G1. The first terminal 200a of the data write circuit 200 is electrically connected to the data signal terminal DATA to receive the data signal DATA. The second terminal 200b of the data write circuit 200 is electrically connected to the first node N1. The data write circuit 200 is configured to write the data signal DATA to the control terminal 100m of the driver circuit 100 in response to the data scan signal G1. For example, during a data write phase, the data write circuit 200 is turned on in response to the data scan signal G1, thereby writing the data signal DATA to the control terminal 100m of the driver circuit 100. For example, the data signal DATA can be stored in the first compensation circuit 300 so that, during a light-emitting phase, a driving current is generated based on the data signal DATA to drive the light-emitting element 600 to emit light.

[0085] As shown in FIG1 , the first compensation circuit 300 includes a control terminal 300m, a first terminal 300a, a second terminal 300b, and a third terminal 300c. The control terminal 300m of the first compensation circuit 300 is configured to receive a first compensation control signal G2. The first terminal 300a of the first compensation circuit 300 is electrically connected to the reference signal terminal REF to receive the reference signal REF. The second terminal 300b of the first compensation circuit 300 is electrically connected to the first node N1. The third terminal 300c of the first compensation circuit 300 is electrically connected to the second node N2. The first compensation circuit 300 is configured to apply the reference signal REF to the control terminal 100m of the driving circuit 100 in response to the first compensation control signal G2. For example, the first compensation circuit 300 may include a first storage capacitor. The first compensation circuit 300 may be turned on in response to the first compensation control signal G2, thereby storing the data signal DATA written by the data write circuit 200 in the first storage capacitor of the first compensation circuit 300. For example, the reference signal REF may be a reference voltage.

[0086] As shown in FIG1 , the first light-emission control circuit 400 includes a control terminal 400m, a first terminal 400a, and a second terminal 400b. The control terminal 400m of the first light-emission control circuit 400 is configured to receive a first light-emission control signal EM1. The first terminal 400a of the first light-emission control circuit 400 is connected to a third node N3 to be electrically connected to the second terminal 100b of the driver circuit 100. The second terminal 400b of the first light-emission control circuit 400 is electrically connected to a first voltage terminal ELVDD to receive a first power supply voltage ELVDD. The first light-emission control circuit 400 is configured to apply the first power supply voltage ELVDD to the second terminal 100b of the driver circuit 100 in response to the first light-emission control signal EM1. For example, during the compensation phase, the first light-emission control circuit 400 can be turned on in response to the first light-emission control signal EM1, thereby applying the first power supply voltage ELVDD to the second terminal 100b of the driver circuit 100. For example, during the light-emitting phase, the first light-emitting control circuit 400 may also be turned on in response to the first light-emitting control signal EM1, thereby applying the first power supply voltage ELVDD to the second terminal 100b of the driver circuit 100. When the driver circuit 100 is turned on, the first power supply voltage ELVDD is written to the first terminal 100a of the driver circuit 100. Consequently, the driver circuit 100 can apply this first power supply voltage ELVDD to the light-emitting element 600 to provide a driving voltage, thereby driving the light-emitting element 600 to emit light. The second terminal of the light-emitting element 600 receives the second power supply voltage VSS, and the light-emitting element 600 emits light under the influence of the first power supply voltage ELVDD and the second power supply voltage VSS. For example, the first power supply voltage ELVDD can be a high voltage, and the second power supply voltage VSS can be a low voltage, but the embodiments of the present disclosure are not limited to this.

[0087] As shown in FIG1 , the second light-emitting control circuit 500 includes a control terminal 500m, a first terminal 500a, and a second terminal 500b. The control terminal 500m of the second light-emitting control circuit 500 is configured to receive a second light-emitting control signal EM2. The first terminal 500a of the second light-emitting control circuit 500 is electrically connected to the second node N2, and the second terminal 500b of the second light-emitting control circuit 500 is electrically connected to the first electrode 600a of the light-emitting element 600. The second light-emitting control circuit 500 is configured to apply a drive current to the light-emitting element 600 in response to the second light-emitting control signal EM2 and to allow the reset signal VINI to be applied to the first terminal 100a of the driver circuit 100. For example, during the light-emitting phase, the second light-emitting control circuit 500 is turned on in response to the second light-emitting control signal EM2, so that the driver circuit 100 can apply a drive current to the light-emitting element 600 through the second light-emitting control circuit 500 to cause the light-emitting element 600 to emit light. For example, during the reset phase, the second light-emitting control circuit 500 can be turned on in response to the second light-emitting control signal EM2, thereby allowing the reset signal VINI to be applied to the first terminal 100a of the driver circuit 100 in conjunction with other circuit components (e.g., the reset circuit 700), thereby achieving a reset operation for the driver circuit 100 and the light-emitting element 600. For example, during the compensation phase and the data writing phase, the second light-emitting control circuit 500 is turned off in response to the second light-emitting control signal EM2, thereby preventing the light-emitting element 600 from emitting light, thereby improving the contrast of the corresponding display device. For example, the reset signal VINI can be a reset voltage.

[0088] For example, as shown in FIG1 , the second light-emitting control signal EM2 is different from the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 can be electrically connected to different signal output terminals. As described above, for example, during the compensation phase, the first light-emitting control signal EM1 can be the only light-on signal. For example, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be both light-on signals during a portion of the time period. For example, during the light-emitting phase, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be both light-on signals to cause the light-emitting element 600 to emit light.

[0089] As shown in FIG1 , the light-emitting element 600 includes a first electrode 600a and a second electrode 600b. The first electrode 600a of the light-emitting element 600 is electrically connected to the second terminal 500b of the second light-emitting control circuit 500, and the second electrode 600b of the light-emitting element 600 is electrically connected to the second voltage terminal VSS to receive the second power supply voltage VSS. For example, the second voltage terminal VSS can be grounded, that is, the second power supply voltage VSS can be 0V. For example, the second power supply voltage VSS can be a negative voltage. The light-emitting element 600 is configured to emit light when driven by a driving current. The first terminal 100a of the driving circuit 100 is electrically connected to the first electrode 600a of the light-emitting element 600, and the driving circuit 100 is configured to control the magnitude of the driving current flowing through the light-emitting element 600. For example, in one example, as shown in FIG1 , the first electrode 600a of the light-emitting element 600 can be electrically connected to the first terminal 100a of the driving circuit 100 via the second light-emitting control circuit 500. Embodiments of the present disclosure include but are not limited to this scenario. For example, the light-emitting element 600 may be an organic light-emitting diode (OLED). In the embodiments described below, the light-emitting element 600 is taken as an OLED, but the embodiments of the present disclosure include but are not limited to this. The light-emitting element 600 may also be other types of electroluminescent devices such as inorganic light-emitting diodes, quantum dot light-emitting elements, etc. The embodiments of the present disclosure do not limit the type of light-emitting element.

[0090] As shown in FIG1 , the reset circuit 700 includes a control terminal 700m, a first terminal 700a, and a second terminal 700b. The control terminal 700m of the reset circuit 700 is configured to receive a reset control signal RST. The first terminal 700a of the reset circuit 700 is electrically connected to the first electrode 600a of the light-emitting element 600. The second terminal 700b of the reset circuit 700 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. The reset circuit 700 is configured to apply the reset signal VINI to the first electrode 600a of the light-emitting element 600 and the first terminal 100a of the driving circuit 100 in response to the reset control signal RST, thereby implementing a reset operation.

[0091] As shown in FIG1 , the second compensation circuit 800 includes a control terminal 800m, a first terminal 800a, and a second terminal 800b. The control terminal 800m of the second compensation circuit 800 is configured to receive a second compensation control signal. The first terminal 800a of the second compensation circuit 800 is electrically connected to the second node N2, and the second terminal 800b of the second compensation circuit 800 is electrically connected to the first electrode 600a of the light-emitting element 600. The second compensation circuit 800 is configured to compensate the driving circuit 100 in response to the second compensation control signal. For example, in the pixel circuit 10 shown in FIG1 , the second compensation circuit 800 and the second light-emitting control circuit 500 share the same control terminal. Thus, the second light-emitting control signal EM2 also serves as the second compensation control signal to control the on and off of the second compensation circuit 800. This simplifies the structure of the pixel circuit and the control method by taking advantage of the specific requirements of the pixel circuit's operation for the second light-emitting control signal and the second compensation control signal. However, the embodiments of the present disclosure are not limited to this situation. For example, in some embodiments of the present disclosure, the control end of the second compensation circuit 800 and the control end of the second light-emitting control circuit 500 can be independent of each other, and the second compensation control signal is different from the second light-emitting control signal EM2. The two are signals that are independently controlled by each other. The second compensation control signal and the second light-emitting control signal EM2 can come from different signal output ends, and the embodiments of the present disclosure are not limited to this.

[0092] FIG2A is a circuit diagram of an implementation example of the pixel circuit shown in FIG1 ; FIG3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0093] For example, the pixel circuit shown in FIG1 can be implemented as the pixel circuit structure shown in FIG2A . As shown in FIG2A , the pixel circuit 101 includes: a driving transistor DT, a data transistor T1, a first emission control transistor T2, a first compensation transistor T3, a second emission control transistor T4, a reset transistor T5, a first switch transistor T6, a first storage capacitor C1, a second storage capacitor C2, and a light-emitting element. For example, the data transistor T1, the first emission control transistor T2, the first compensation transistor T3, the second emission control transistor T4, the reset transistor T5, and the first switch transistor T6 function as switch transistors. For example, the embodiments of the present disclosure are described using an OLED as the light-emitting element, but are not limited to this. For example, the light-emitting element may also be other light-emitting devices, and the embodiments of the present disclosure are not limited to this. For example, when the light-emitting element is an OLED, the light-emitting element may be of various types, such as top-emitting or bottom-emitting, and may emit red, green, blue, or white light, and the embodiments of the present disclosure are not limited to this.

[0094] For example, as shown in Figures 1 and 2A, the driving circuit 100 includes a driving transistor DT, the gate of the driving transistor DT serves as the control terminal 100m of the driving circuit 100, and is electrically connected to the first node N1; the first electrode of the driving transistor DT serves as the first terminal 100a of the driving circuit 100, and is electrically connected to the second node N2; the second electrode of the driving transistor DT serves as the second terminal 100b of the driving circuit 100, and is electrically connected to the third node N3.

[0095] For example, as shown in Figures 1 and 2A, the data write circuit 200 includes a data transistor T1, the gate of the data transistor T1 is electrically connected to the data scan signal terminal G1 to receive the data scan signal G1, the first electrode of the data transistor T1 is electrically connected to the data signal terminal DATA to receive the data signal DATA, and the second electrode of the data transistor T1 is electrically connected to the first node N1 (the gate of the driving transistor DT).

[0096] For example, as shown in Figures 1 and 2A, the first light-emitting control circuit 400 includes a first light-emitting control transistor T2, a gate of the first light-emitting control transistor T2 is electrically connected to the first light-emitting control terminal EM1 to receive the first light-emitting control signal EM1, a first electrode of the first light-emitting control transistor T2 is electrically connected to the first voltage terminal ELVDD to receive the first power supply voltage ELVDD, and a second electrode of the first light-emitting control transistor T2 is electrically connected to the third node N3 (the second electrode of the driving transistor DT).

[0097] For example, as shown in Figures 1 and 2A, the first compensation circuit 300 includes a first compensation transistor T3 and a first storage capacitor C1. The gate of the first compensation transistor T3 is electrically connected to the first compensation control signal terminal G2 to receive the first compensation control signal G2. The first electrode of the first compensation transistor T3 is electrically connected to the reference signal terminal REF to receive the reference signal REF. The second electrode of the first compensation transistor T3 is electrically connected to the first node N1 (the gate of the driving transistor DT). The first electrode of the first storage capacitor C1 is electrically connected to the control terminal 100m (the first node N1) of the driving circuit 100, and the second electrode of the first storage capacitor C1 is electrically connected to the first terminal 100a (the second node N2) of the driving circuit 100.

[0098] For example, as shown in Figures 1 and 2A, the second light-emitting control circuit 500 includes a second light-emitting control transistor T4, the gate of which is electrically connected to the second light-emitting control terminal EM2 to receive the second light-emitting control signal EM2, the first electrode of the second light-emitting control transistor T4 is electrically connected to the second node N2 (the first electrode of the driving transistor DT), and the second electrode of the second light-emitting control transistor T4 is electrically connected to the first electrode 600a of the light-emitting element 600.

[0099] For example, as shown in Figures 1 and 2A, the light-emitting element 600 can be implemented as a light-emitting diode (LED), for example, an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED) or an inorganic light-emitting diode, for example, a micro light-emitting diode (Micro LED) or a micro OLED.

[0100] For example, as shown in Figures 1 and 2A, the reset circuit 700 includes a reset transistor T5, the gate of the reset transistor T5 is electrically connected to the reset control terminal RST to receive the reset control signal RST, the first electrode of the reset transistor T5 is electrically connected to the first electrode 600a of the light-emitting element 600, and the second electrode of the reset transistor T5 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI.

[0101] For example, as shown in Figures 1 and 2A, the second compensation circuit 800 includes a second storage capacitor C2 and a first switch transistor T6, and the second compensation circuit 800 is configured to compensate the driving circuit 100 in response to a second compensation control signal. The gate of the first switch transistor T6 is configured to receive the second compensation control signal. For example, in the pixel circuit 101 shown in Figure 2A, the second light emission control signal EM2 serves as the second compensation control signal, but the embodiments of the present disclosure are not limited thereto. For example, in the embodiment shown in Figure 2A, the first electrode of the first switch transistor T6 is electrically connected to the second storage capacitor C2, and the second electrode of the second switch transistor T6 is electrically connected to the second node N2 (the first electrode of the driving transistor DT). Thus, the first electrode of the second storage capacitor C2 is electrically connected to the first terminal 100a of the driving circuit 100. For example, in the pixel circuit 101 shown in Figure 2A, the second storage capacitor C2 is indirectly electrically connected to the first terminal 100a of the driving circuit 100 through the second switch transistor T6, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the second storage capacitor C2 may also be directly electrically connected to the first end 100a of the driving circuit 100, that is, no transistors, capacitors or other elements are arranged between the second storage capacitor C2 and the first end 100a of the driving circuit 100. The embodiments of the present disclosure do not limit the position of the second storage capacitor C2 in the second compensation circuit 800.

[0102] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2 and the third node N3 do not necessarily represent actual components, but represent the junction points of related circuit connections in the circuit diagram. In the description of the embodiments of the present disclosure, the symbol DATA can represent both a data signal terminal and a data signal; similarly, the symbol G1 can represent both a data scan signal terminal and a data scan signal; the symbol REF can represent both a reference signal terminal and a reference signal; the symbol G2 can represent both a first compensation control signal terminal and a first compensation control signal; the symbol EM1 can represent both a first light-emitting control terminal and a first light-emitting control signal; the symbol ELVDD can represent both a first voltage terminal and a first power supply voltage; the symbol EM2 can represent both a second light-emitting control terminal and a second light-emitting control signal; the symbol RST can represent both a reset control terminal and a reset control signal; the symbol VINI can represent both a reset signal terminal and a reset signal, and can also represent a reset voltage; the symbol VSS can represent both a second voltage terminal and a second power supply voltage signal; the symbol Vx can represent both a constant voltage terminal and a constant voltage. The following embodiments are the same and will not be repeated here.

[0103] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0104] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages). However, the embodiments of the present disclosure do not limit the type of transistor. When the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0105] The working principle of the pixel circuit 101 shown in FIG2A is described below in conjunction with the signal timing diagram shown in FIG3. As shown in FIG3, the display process of each frame of image includes four stages, namely reset stage 1, compensation stage 2, data writing stage 3 and light emitting stage 4.

[0106] It should be noted that Figure 2B is a schematic diagram of the pixel circuit shown in Figure 2A during the reset phase; Figure 2C is a schematic diagram of the pixel circuit shown in Figure 2A during the compensation phase; Figure 2D is a schematic diagram of the pixel circuit shown in Figure 2A during the data writing phase; and Figure 2E is a schematic diagram of the pixel circuit shown in Figure 2A during the light emitting phase. Furthermore, transistors marked with dashed lines in Figures 2B through 2E are all in an off state during the corresponding phase.

[0107] For example, in the pixel circuit 101 shown in Figure 2A, the driving transistor DT, the data transistor T1, the first light-emitting control transistor T2, the first compensation transistor T3, the reset transistor T5 and the first switching transistor T6 are all N-type transistors, that is, the gate of each transistor is turned on when a high-level signal is connected, and is turned off when a low-level signal is connected; the second light-emitting control transistor T4 is a P-type transistor, for example, a low-temperature polycrystalline silicon thin film transistor, which is turned on when the gate of the second light-emitting control transistor T4 is connected to a low-level signal, and is turned off when a high-level signal is connected.

[0108] As shown in Figures 2D, 2E, and 3, an embodiment of the present disclosure provides a driving method, including: during a data writing phase 3, a second compensation control signal EM2 is an on signal to turn on a first switch transistor T6. Furthermore, when entering a light-emitting phase 4 from the data writing phase 3, the second compensation control signal EM2 is switched from an on signal to an off signal to turn off the first switch transistor T6. During the light-emitting phase 4, the second compensation control signal EM2 remains an off signal. When the first switch transistor T6 switches from an on state to an off state, due to the parasitic capacitance between the gate of the first switch transistor T6 and the second electrode of the first switch transistor T6, the voltage at the second electrode of the first switch transistor T6 decreases, thereby decreasing the voltage at the first electrode of the drive transistor DT, for example, rapidly decreasing the voltage at the first electrode of the drive transistor DT. This compensates for the gate-source voltage Vgs of the drive transistor DT. Simultaneously, when the data transistor T1 switches from an on state to an off state, causing the gate voltage of the drive transistor DT to decrease, fluctuations in the gate-source voltage Vgs of the drive transistor DT are reduced, thereby improving the brightness uniformity of the display panel.

[0109] Specifically, for example, as shown in Figures 1 and 3, in reset phase 1, the driving method includes: setting the first compensation control signal G2 to an on-signal to turn on the first compensation circuit 300, so that the first compensation circuit 300 can apply the reference signal REF to the control terminal 100m of the driving circuit 100. At the same time, setting the second emission control signal EM2 to an on-signal to turn on the second emission control circuit 500, and setting the reset control signal RST to an on-signal to turn on the reset circuit 700. At this time, the reset signal VINI can be applied to the first electrode 600a of the light-emitting element 600 via the reset circuit 700, and the reset signal VINI can be applied to the first terminal 100a of the driving circuit 100 via the second emission control circuit 500.

[0110] Correspondingly, as shown in FIG2B and FIG3, the first compensation control signal G2 and the reset control signal RST are set to high-level signals to turn on the first compensation transistor T3 and the reset transistor T5; the second light-emitting control signal EM2 is set to a low-level signal to turn on the second light-emitting control transistor T4. Therefore, the first compensation transistor T3 can apply the reference signal REF to the gate of the driving transistor DT, and the reset signal VINI can be applied to the first electrode of the light-emitting element OLED through the reset transistor T5 and applied to the first electrode of the driving transistor DT through the second light-emitting control transistor T4. In the reset phase 1, for example, the reference signal REF is the reference voltage V REF , the reset signal VINI is the reset voltage V INI Let V REF -V INI >Vth, that is, the gate-source voltage Vgs of the driving transistor DT>Vth, so the driving transistor DT is in the on state, and the reset signal VINI is applied to the second node N2 (that is, applied to the first electrode of the light-emitting element OLED) and the third node N3, thereby resetting the second node N2 and the third node N3.

[0111] For example, as shown in FIG1 and FIG3 , in compensation phase 2, the driving method further includes: setting the first light-emitting control signal EM1 to a start signal to turn on the first light-emitting control circuit 400, and the first light-emitting control circuit 400 applies the first power supply voltage ELVDD to the second terminal 100b of the driving circuit 100 to compensate and charge the driving circuit 100. Setting the second compensation control signal to a start signal to turn on the first switch transistor T6, and the second compensation circuit (for example, implemented as the first switch transistor T6 and the second storage capacitor C2) is configured to compensate the driving circuit 100 (implemented as the driving transistor DT) in response to the second compensation control signal.

[0112] Correspondingly, as shown in Figures 2C and 3, in compensation phase 2, the first emission control signal EM1 and the first compensation control signal G2 are set to high-level signals, turning on the first emission control transistor T2 and the first compensation transistor T3. Simultaneously, the second emission control signal EM2 and the reset control signal RST are set to high-level signals, turning on the first switching transistor T6 and the reset transistor T5. The first emission control transistor T2 applies the first power supply voltage ELVDD to the second electrode of the drive transistor DT, the first compensation transistor T3 applies the reference signal REF to the gate of the drive transistor DT, and the reset signal VINI is applied to the second electrode of the second storage capacitor C2.

[0113] For example, as shown in FIG2C , during compensation phase 2, a reference signal REF is applied to the gate of the driving transistor DT in the form of a reference voltage, such that the gate voltage Vg of the driving transistor DT is equal to the reference voltage Vref. At the start of compensation phase 2, the voltage Vs at the first electrode (i.e., the second node N2) of the driving transistor DT is equal to the reset voltage Vini, and the difference Vgs between the reference voltage Vref and the reset voltage Vini is greater than the threshold voltage Vth of the driving transistor DT, such that Vgs-Vth>0. Therefore, the driving transistor DT is in an on state. Since the first emission control transistor T2 is in an on state, the driving transistor DT can be charged using the first power supply voltage ELVDD until the driving transistor DT is turned off, such that the voltage Vs at the first terminal of the driving transistor DT is equal to Vref-Vth. Consequently, this charging process allows information such as the threshold voltage Vth of the driving transistor DT to be stored in the first storage capacitor C1.

[0114] For example, as shown in Figures 2C and 3, in compensation stage 2, the second electrode of the second storage capacitor C2 receives a constant voltage from the constant voltage terminal. In this embodiment, the second electrode of the second storage capacitor C2 is electrically connected to the first electrode of the light-emitting element OLED, and the first electrode of the reset transistor T5 is electrically connected to the first electrode of the light-emitting element OLED. For example, for the pixel circuit 101, since the reset transistor T5 is turned on in response to the reset control signal RST, the reset signal VINI serves as the above-mentioned constant voltage, thereby reducing the risk of the voltage of the first electrode of the driving transistor DT jumping due to interference from external signals. In addition, the reset transistor T5 is in the on state, which can make the voltage of the first electrode of the light-emitting element more stable, reduce the parasitic capacitance between the first electrode of the light-emitting element and other elements, and thus reduce the risk of the light-emitting element emitting light or the like in compensation stage 2.

[0115] For example, as shown in Figures 1 and 3 , during data writing phase 3, the driving method further includes setting the data scanning signal G1 to an on signal to write the data signal DATA to the control terminal 100m of the driving circuit 100. As shown in Figures 1 , 2D , 2E , and 3 , when entering light-emitting phase 4 from data writing phase 3, the data scanning signal G1 is switched from an on signal to an off signal, and the second compensation control signal EM2 is switched from an on signal to an off signal to simultaneously shut down the data writing circuit 200 and the first switching transistor T6. Furthermore, during light-emitting phase 4, the data scanning signal G1 remains an off signal. Since the first switching transistor T6 and the second light-emitting control transistor T4 share a common gate in this embodiment, the second compensation control signal, i.e., the second light-emitting control signal, is the same signal. Therefore, in this embodiment, both the second compensation control signal and the second light-emitting control signal are represented by the reference numeral EM2.

[0116] Correspondingly, as shown in Figures 2D and 3, in the data writing phase 3, the data scanning signal G1, the reset control signal RST, and the second light-emitting control signal EM2 are set to high-level signals to turn on the data transistor T1, the reset transistor T5, and the first switch transistor T6. As a result, the data transistor T1 writes the data signal DATA to the gate of the driving transistor DT. For example, the data signal DATA can be a data voltage DATA, so that the voltage value of the gate of the driving transistor DT is equal to the data voltage value Vdata. At the same time, the voltage of the second electrode (third node N3) of the driving transistor DT is the first power supply voltage ELVDD, and the voltage value of the first electrode (second node N2) of the driving transistor DT is Vref-Vth+C1 / (C1+C2)×(Vdata-Vref). Here, for clarity, the capacitance of the first storage capacitor is labeled C1, which is the same as the first storage capacitor, and the capacitance of the second storage capacitor is labeled C2, which is the same as the second storage capacitor.

[0117] Correspondingly, as shown in Figures 2E and 3, in light-emitting phase 4, the first light-emitting control signal EM1 is set to a high level signal to turn on the first light-emitting control transistor T2; the second light-emitting control signal EM2 is set to a low level signal to turn on the second light-emitting control transistor T4 and turn off the first switch transistor T6. The first switch transistor T6 and the second light-emitting control transistor T4 are of opposite types, so the second light-emitting control signal EM2 (also known as the second compensation control signal) received by their shared gate turns one on while turning off the other. In this way, a drive current is applied to the light-emitting element via the second light-emitting control transistor T4, causing it to emit light.

[0118] For example, as shown in FIG2E , in light-emitting phase 4, the gate voltage of the driving transistor DT is Vdata, the voltage at the first electrode (second node N2) of the driving transistor DT is Vref-Vth+C1 / (C1+C2)×(Vdata-Vref), and the voltage at the second electrode (third node N3) of the driving transistor DT is the first power supply voltage ELVDD. Vgs of the driving transistor DT is Vdata-(Vref-Vth+C1 / (C1+C2)×(Vdata-Vref)).

[0119] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0120] I=K×(Vgs-Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is: I=K×((Vdata-Vref)×Cst2 / (Cst1+Cst2)) 2

[0121] According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor DT. This can compensate for the pixel circuit, solve the problem of threshold voltage Vth drift of the driving transistor DT due to process technology and long-term operation, and eliminate its influence on the driving current, thereby improving the display effect of the display device using this pixel circuit.

[0122] For example, as shown in Figures 2D and 2E, during data writing phase 3, the data transistor T1 and the first switch transistor T6 are both in the on state. When entering light-emitting phase 4 from data writing phase 3, the data transistor T1 and the first switch transistor T6 are both turned off. The gate-source voltage Vgs of the driving transistor DT is Vg-Vs, where Vg represents the gate voltage of the driving transistor DT and Vs represents the voltage at the first electrode of the driving transistor DT. Therefore, when the data transistor T1 is turned off, due to the parasitic capacitance between the gate of the data transistor T1 and its second electrode (the first node N1), the data transistor T1 may cause the voltage at the first node N1 to decrease when it is turned off, thereby causing the gate voltage Vg of the driving transistor DT to decrease. When the first switch transistor T6 is turned off, due to the parasitic capacitance between the gate of the first switch transistor T6 and its second electrode (the second node N2), the first switch transistor T6 can also reduce the voltage of the second node N2 when it is turned off, that is, the voltage value Vs of the first electrode of the driving transistor DT is reduced. In this way, the difference between the gate voltage of the driving transistor DT and the voltage of the first electrode of the driving transistor DT (that is, the gate-source voltage Vgs of the driving transistor DT) can be made basically unchanged, or have smaller fluctuations, so as to make the driving current flowing through the light-emitting element more stable and make the brightness of the display panel more uniform.

[0123] With such an arrangement, in the pixel circuit provided in the embodiment of the present application, by combining the first light-on transistor T6 with the second storage capacitor C2, the first storage capacitor C1 and other components, not only the technical problem of how to compensate for the threshold voltage of the driving transistor is solved, but also the technical problem of instability of the gate-source voltage Vgs of the driving transistors of multiple pixels caused by the difficulty in quickly reducing the voltage of the first electrode of the driving transistor while the gate voltage of the driving transistor is reduced when switching to the light-emitting stage is solved.

[0124] For example, as shown in Figures 2B-2E , in each of the reset phase 1, the compensation phase 2, the data writing phase 3, and the light-emitting phase 4, the second compensation control signal and the second light-emitting control signal EM2 are opposite switching signals to control the switching states of their corresponding circuits in opposite directions. The second compensation control signal and the second light-emitting control signal EM2 being opposite switching signals means that whether the first switching transistor T6 (or the second compensation circuit) is turned on in response to the second compensation control signal is opposite to whether the second light-emitting control transistor T4 (or the second light-emitting control circuit) is turned on in response to the second light-emitting control signal EM2. For example, when the second compensation control signal serves as a turn-on signal for the first switching transistor T6, the second light-emitting control signal EM2 serves as a turn-off signal for the second light-emitting control transistor T4. Conversely, when the second compensation control signal serves as a turn-off signal for the first switching transistor T6, the second light-emitting control signal EM2 serves as a turn-on signal for the second light-emitting control transistor T4.

[0125] For example, as shown in Figures 2B-2E , during compensation phase 2 and data writing phase 3, the second compensation control signal is an on signal, and the first switch transistor T6 is in an on state; the second light-emitting control signal is an off signal, and the second light-emitting control transistor T4 is in an off state, thereby compensating the driving circuit via the second compensation circuit. For example, during reset phase 1 and light-emitting phase 4, the second compensation control signal is an off signal, and the first switch transistor T6 is in an off state; the second light-emitting control signal is an on signal, and the second light-emitting control transistor T4 is in an on state. Thus, during reset phase 1, the reset signal VINI is applied to the second node N2 via the second light-emitting control transistor T4, and during light-emitting phase 4, the light-emitting element OLED is driven to emit light.

[0126] Thus, as shown in Figures 2B-2E , for example, the first switching transistor T6 and the second emission control transistor T4 can share a gate. By making the first switching transistor T6 and the second emission control transistor T4 of opposite types, both can be controlled by the second emission control signal EM2. For example, the first switching transistor T6 and the second emission control transistor T4 sharing a gate means that the gate of the first switching transistor T6 and the gate of the second emission control transistor T4 are electrically connected to the same gate line, i.e., share a common gate line. For example, when the second emission control signal EM2 is a high voltage signal, the first switching transistor T6 is turned on and the second emission control transistor T4 is turned off; when the second emission control signal EM2 is a low voltage signal, the first switching transistor T6 is turned off and the second emission control transistor T4 is turned on. This makes the structure of the pixel circuit simpler and the control method of the pixel circuit more convenient.

[0127] FIG4 is a circuit diagram of another implementation example of the pixel circuit shown in FIG1 ; FIG5 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0128] For example, the pixel circuit shown in FIG. 1 may also be implemented as the pixel circuit structure shown in FIG. 4 .

[0129] For example, as shown in Figure 4, the pixel circuit 102 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switch transistor T6, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0130] For example, as shown in FIG4 , in pixel circuit 102, a first electrode of a first switching transistor T6 is electrically connected to a first electrode of a second storage capacitor C2, and a second electrode of the first switching transistor T6 is electrically connected to a second node N2. The second electrode of the second storage capacitor C2 is electrically connected to a first electrode of the light-emitting element OLED, and a first electrode of a reset transistor T5 is electrically connected to a first electrode of the light-emitting element OLED. Thus, the second electrode of the second storage capacitor C2 can receive a reset signal VINI via the reset transistor T5, with the reset signal VINI serving as the constant voltage. The gate of the first switching transistor T6 is electrically connected to the gate of the second emission control transistor T4. The first switching transistor T6 and the second emission control transistor T4 share a common gate. The second emission control signal EM2 serves as a second compensation control signal, and the type of the first switching transistor T6 is different from that of the second emission control transistor T4.

[0131] For example, as shown in FIG4 , the difference between the pixel circuit 102 and the pixel circuit 101 shown in FIG2A is that the types of the first switching transistor T6 and the second light-emission control transistor T4 have changed, while the rest of the structure is the same. In the pixel circuit 102, the first switching transistor T6 is a P-type transistor, which is turned on when a low-level signal is applied to the gate of the first switching transistor T6 and turned off when a high-level signal is applied. The second light-emission control transistor T4 is an N-type transistor, which is turned on when a high-level signal is applied to the gate of the second light-emission control transistor T4 and turned off when a low-level signal is applied. For other structures in the pixel circuit 102, please refer to the relevant description of the pixel circuit 101 shown in FIG2A in the above embodiment, and will not be repeated here.

[0132] For example, as shown in Figures 4 and 5, during the driving process of the pixel circuit 102, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in Figure 2A. Compared to the timing diagram shown in Figure 3, the timing states of the data signal DATA, reset control signal RST, data scanning signal G1, first compensation control signal G2, and first light-emitting control signal EM1 in Figure 5 remain unchanged. The difference lies in the control signal of the second light-emitting control signal EM2. For example, in the pixel circuit 102, since the second light-emitting control transistor T4 is an N-type transistor and the first switch transistor T6 is a P-type transistor, during the compensation phase 2 and the data writing phase 3, the second light-emitting control signal EM2 is a low-level signal, so that the first switch transistor T6 is in the on state and the second light-emitting control transistor T4 is in the off state, thereby facilitating compensation of the driving circuit by the second compensation circuit. In the reset phase 1 and the light emitting phase 4, the second light emitting control signal EM2 is a high level signal, so that the second light emitting control transistor T4 is turned on and the first switch transistor T6 is turned off, which is beneficial for charging the pixel circuit 102 and emitting light of the light emitting element.

[0133] For example, for the working process and corresponding technical effects of the pixel circuit 102 shown in Figure 4 when it is in the reset stage 1, compensation stage 2, data writing stage 3 and light-emitting stage 4, please refer to the relevant description of Figures 2B to 2E in the above embodiments, and will not be repeated here.

[0134] Fig. 6 is a circuit diagram of another implementation example of the pixel circuit shown in Fig. 1. For example, the pixel circuit shown in Fig. 1 can also be implemented as the pixel circuit structure shown in Fig. 6.

[0135] For example, as shown in Figure 6, the pixel circuit 103 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switch transistor T6, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0136] For example, as shown in FIG6 , in pixel circuit 103, the gate of the first switching transistor T6 is electrically connected to the gate of the second emission control transistor T4, the first switching transistor T6 and the second emission control transistor T4 share a common gate, the second emission control signal EM2 serves as the second compensation control signal, and the type of the first switching transistor T6 is different from the type of the second emission control transistor T4. The second electrode of the second storage capacitor C2 is electrically connected to the first electrode of the light-emitting element OLED, and the first electrode of the reset transistor T5 is electrically connected to the first electrode of the light-emitting element OLED.

[0137] For example, as shown in FIG6 , the difference between the pixel circuit 103 and the pixel circuit 101 shown in FIG2A is that: in the pixel circuit 103, the first electrode of the second storage capacitor C2 is electrically connected to the second node N2, and the second electrode of the second storage capacitor C2 is electrically connected to the first electrode of the first switch transistor T6. Thus, the second electrode of the second storage capacitor C2 is electrically connected to the first electrode of the light-emitting element OLED through the first switch transistor T6, that is, the second electrode of the second storage capacitor C2 is indirectly connected to the first electrode of the light-emitting element OLED. For example, the first electrode of the second storage capacitor C2 is directly electrically connected to the second node N2, that is, there are no other components such as transistors and capacitors between the first electrode of the second storage capacitor C2 and the second node N2. For other structures in the pixel circuit 103, please refer to the relevant description of the pixel circuit 101 shown in FIG2A in the above embodiment, and will not be repeated here.

[0138] For example, as shown in FIG6 , during the driving process of the pixel circuit 103, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG2A . Therefore, the timing diagram corresponding to the pixel circuit 103 can also be found in FIG3 . For example, the operating process and corresponding technical effects of the pixel circuit 103 shown in FIG6 in the reset phase 1, compensation phase 2, data writing phase 3, and light emitting phase 4 can be found in the relevant description of FIG2B to FIG2E in the above embodiments, and will not be repeated here.

[0139] For example, as shown in Figures 3 and 6, during data writing phase 3, the data transistor T1 and the first switch transistor T6 are both in the on state. When entering light-emitting phase 4 from data writing phase 3, the data transistor T1 and the first switch transistor T6 both transition from the on state to the off state. The gate-source voltage Vgs of the drive transistor DT is Vg-Vs, where Vg represents the gate voltage of the drive transistor DT and Vs represents the voltage at the first electrode of the drive transistor DT. When the data transistor T1 transitions to the off state, due to the parasitic capacitance between the gate of the data transistor T1 and its second electrode (first node N1), the data transistor T1 may reduce the voltage at the first node N1 when it is turned off, thereby reducing the voltage Vg at the gate of the drive transistor DT. When the first switch transistor T6 transitions from the on state to the off state, due to the parasitic capacitance between the gate of the first switch transistor T6 and its first electrode (the second electrode of the second storage capacitor C2), the first switch transistor T6 may also reduce the voltage at the second electrode of the second storage capacitor C2 when it is turned off. Since the voltage across the second storage capacitor C2 does not suddenly change, when the voltage at the second electrode of the second storage capacitor C2 decreases, the voltage at the first electrode of the second storage capacitor C2 also decreases. Consequently, the voltage at the first electrode of the driving transistor DT decreases accordingly. This allows the difference between the gate voltage of the driving transistor DT and the voltage at the first electrode of the driving transistor DT (i.e., the gate-source voltage Vgs of the driving transistor DT) to remain essentially unchanged or have minimal fluctuations, thereby facilitating a more stable driving current flowing through the light-emitting element and achieving more uniform brightness on the display panel.

[0140] Fig. 7 is a circuit diagram of another implementation example of the pixel circuit shown in Fig. 1. For example, the pixel circuit shown in Fig. 1 can also be implemented as the pixel circuit structure shown in Fig. 7.

[0141] For example, as shown in Figure 7, the pixel circuit 104 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switch transistor T6, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0142] For example, as shown in FIG7 , in pixel circuit 104, the gate of first switch transistor T6 is electrically connected to the gate of second emission control transistor T4, first switch transistor T6 and second emission control transistor T4 share a common gate, second emission control signal EM2 serves as a second compensation control signal, and the type of first switch transistor T6 is different from the type of second emission control transistor T4. A second electrode of second storage capacitor C2 is electrically connected to the first electrode of light-emitting element OLED, and a first electrode of reset transistor T5 is electrically connected to the first electrode of light-emitting element OLED. Simultaneously, in pixel circuit 104, a first electrode of second storage capacitor C2 is electrically connected to second node N2, and a second electrode of second storage capacitor C2 is electrically connected to the first electrode of first switch transistor T6. Thus, the second electrode of second storage capacitor C2 is electrically connected to the first electrode of light-emitting element OLED via first switch transistor T6.

[0143] For example, as shown in FIG7 , the difference between the pixel circuit 104 and the pixel circuit 103 shown in FIG6 is that the types of the first switching transistor T6 and the second light-emission control transistor T4 have changed, while the rest of the structure is the same. In the pixel circuit 104, the first switching transistor T6 is a P-type transistor, which turns on when a low-level signal is applied to the gate of the first switching transistor T6 and turns off when a high-level signal is applied. The second light-emission control transistor T4 is an N-type transistor, which turns on when a high-level signal is applied to the gate of the second light-emission control transistor T4 and turns off when a low-level signal is applied. For other structures in the pixel circuit 104, please refer to the relevant description of the pixel circuit 103 shown in FIG6 in the above embodiment, and will not be repeated here.

[0144] For example, as shown in FIG7 , during the driving process of the pixel circuit 104, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 103 shown in FIG6 . Compared to the timing diagram shown in FIG6 , the timing states of the data signal DATA, the reset control signal RST, the data scanning signal G1, the first compensation control signal G2, and the first light-emitting control signal EM1 remain unchanged, except that the control signal of the second light-emitting control signal EM2 is different. Therefore, the timing diagram corresponding to the pixel circuit 104 can also be seen in FIG5 . For example, the operating process and corresponding technical effects of the pixel circuit 104 shown in FIG7 in the reset phase 1, the compensation phase 2, the data writing phase 3, and the light-emitting phase 4 can be referred to the relevant description of FIG2B to FIG2E in the above embodiment, and will not be repeated here.

[0145] For example, as shown in Figures 2A, 4, 6, and 7, when the first switch transistor T6 and the second emission control transistor T4 share a gate, the second emission control signal EM2 serves as the second compensation control signal, and the type of the first switch transistor T6 is different from the type of the second emission control transistor T4, the type of the first switch transistor T6 and the type of the second emission control transistor T4 can be reasonably selected according to design requirements. For example, when the first switch transistor T6 is a P-type transistor, the second emission control transistor T4 can be an N-type transistor. For example, when the first switch transistor T6 is an N-type transistor, the second emission control transistor T4 can be a P-type transistor, thereby making the structure of the pixel circuit more flexible and changeable.

[0146] FIG8 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0147] For example, as shown in FIG8 , the pixel circuit 20 includes a driving circuit 100, a data writing circuit 200, a first compensation circuit 300, a first light-emitting control circuit 400, a second light-emitting control circuit 500, a light-emitting element 600, a reset circuit 700, and a second compensation circuit 800. Compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 20 differs in that the control terminal 500m of the second light-emitting control circuit 500 and the control terminal 800m of the second compensation circuit 800 are independent of each other and are not connected. The control terminal 800 of the second compensation circuit 800 is configured to receive a second compensation control signal G3, and the control terminal 500m of the second light-emitting control circuit 500 is configured to receive a second light-emitting control signal EM2. The second compensation control signal G3 is different from the second light-emitting control signal EM2. For example, the two can be electrically connected to different signal output terminals to serve as independent control signals. For other structures in the pixel circuit 20, please refer to the relevant description of FIG1 in the above embodiment, and will not be repeated here.

[0148] FIG9 is a circuit diagram of an implementation example of the pixel circuit shown in FIG8 ; FIG10 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0149] For example, the pixel circuit shown in FIG. 8 may be implemented as the pixel circuit structure shown in FIG. 9 .

[0150] For example, as shown in Figure 9, the pixel circuit 105 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switch transistor T6, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0151] For example, as shown in FIG9 , in the pixel circuit 105, a first electrode of the first switch transistor T6 is electrically connected to a first electrode of the second storage capacitor C2, a second electrode of the first switch transistor T6 is electrically connected to a second node N2, a second electrode of the second storage capacitor C2 is electrically connected to a first electrode of the light-emitting element OLED, and a first electrode of the reset transistor T5 is electrically connected to a first electrode of the light-emitting element OLED.

[0152] For example, as shown in FIG9 , the pixel circuit 105 differs from the pixel circuit 101 shown in FIG2A in that the gate of the first switching transistor T6 and the gate of the second emission control transistor T4 are independent of each other and are not electrically connected. For example, the gate of the first switching transistor T6 is configured to receive the second compensation control signal G3, and the gate of the second emission control transistor T4 is configured to receive the second emission control signal EM2. Thus, the first switching transistor T6 and the second emission control transistor T4 can be independently controlled, providing a more flexible control method for the pixel circuit 105. Furthermore, the first switching transistor T6 and the second emission control transistor T4 are of the same type and are both N-type transistors. Of course, in other embodiments, the types of the first switching transistor T6 and the second emission control transistor T4 can also be different, as long as the independent second compensation control signal G3 and the second emission control signal EM2 are controlled to control the first switching transistor T6 and the second emission control transistor T4 to the desired on or off state as needed.

[0153] For example, the timing diagram corresponding to pixel circuit 105 can be seen in FIG10 . For example, as shown in FIG9 and FIG10 , during the driving process of pixel circuit 105, the operating state (e.g., on or off) of each transistor is the same as that of pixel circuit 101 shown in FIG2A , except that the type of the first switch transistor T6 and the second emission control transistor T4 are changed. Compared to the timing diagram shown in FIG3 , the timing states of the data signal DATA, reset control signal RST, data scanning signal G1, first compensation control signal G2, and first emission control signal EM1 in the timing diagram of FIG10 remain unchanged. The difference lies in the control signal of the second emission control signal EM2, and the addition of the timing state of the second compensation control signal G3. For example, in pixel circuit 105, since the second emission control transistor T4 and the first switch transistor T6 are both N-type transistors, during compensation phase 2 and data writing phase 3, the second emission control signal EM2 is a low-level signal, turning the second emission control transistor T4 off; and the second compensation control signal G3 is a high-level signal, turning the first switch transistor T6 on. In the reset stage 1 and the light-emitting stage 4, the second light-emitting control signal EM2 is a high-level signal, so that the second light-emitting control transistor T4 is in the on state; the second compensation control signal G3 is a low-level signal, so that the first switch transistor T6 is in the off state, which is beneficial to the charging of the pixel circuit 102 and the light-emitting element to emit light.

[0154] For example, for the working process and corresponding technical effects of the pixel circuit 105 shown in Figure 9 when it is in the reset stage 1, compensation stage 2, data writing stage 3 and light-emitting stage 4, please refer to the relevant description of Figures 2B to 2E in the above embodiments, and will not be repeated here.

[0155] For example, in some embodiments of the present disclosure, referring to the pixel circuit 105 shown in FIG9 , the type of the second light emitting control transistor T4 and the type of the first switch transistor T6 may also be different, and may be specifically set according to design requirements.

[0156] Figure 11A is a circuit diagram of another implementation example of the pixel circuit shown in Figure 8; Figure 12 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure; Figure 11B is a schematic diagram of the pixel circuit shown in Figure 11 in the reset phase; Figure 11C is a schematic diagram of the pixel circuit shown in Figure 11A in the compensation phase; Figure 11D is a schematic diagram of the pixel circuit shown in Figure 11A in the data writing phase; and Figure 11E is a schematic diagram of the pixel circuit shown in Figure 11A in the light emitting phase. In addition, transistors marked with dotted lines in Figures 11B to 11E are all in the off state during the corresponding phase.

[0157] For example, the pixel circuit shown in FIG8 may also be implemented as the pixel circuit structure shown in FIG11A .

[0158] For example, as shown in Figure 11A, the pixel circuit 106 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switching transistor T6, a second switching transistor T7, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0159] For example, as shown in FIG11A , in the pixel circuit 106, a first electrode of the first switch transistor T6 is electrically connected to a first electrode of the second storage capacitor C2, a second electrode of the first switch transistor T6 is electrically connected to a second node N2, a second electrode of the second storage capacitor C2 is electrically connected to a first electrode of the light-emitting element OLED, and a first electrode of the reset transistor T5 is electrically connected to a first electrode of the light-emitting element OLED.

[0160] For example, as shown in FIG11A , the pixel circuit 106 differs from the pixel circuit 105 shown in FIG9 in that the second compensation circuit 800 (see FIG8 ) further includes a second switching transistor T7. The second electrode of the second storage capacitor C2 is electrically connected to the first electrode of the second switching transistor T7, and the second electrode of the second switching transistor T7 is electrically connected to the first electrode of the light-emitting element OLED, thereby indirectly electrically connecting the second electrode of the second storage capacitor C2 to the first electrode of the light-emitting element OLED. For example, the gate of the second switching transistor T7 is independent of and not electrically connected to the gate of the first switching transistor T6 and the gate of the second emission control transistor T4. Of course, in other embodiments, when the second switching transistor T7 is present, the first switching transistor T6 and the second emission control transistor T4 may share a gate. The gate of the second switching transistor T7 is configured to receive a third compensation control signal G4. Thus, the first switching transistor T6, the second switching transistor T7, and the second emission control transistor T4 can all be controlled independently, providing a more flexible control method for the pixel circuit 106. In addition, the type of the first switch transistor T6 , the type of the second switch transistor T7 , and the type of the second light emission control transistor T4 are all the same, and are all N-type transistors, but the embodiments of the present disclosure include but are not limited to this.

[0161] For example, as shown in Figures 11A and 12, the timing diagram corresponding to the pixel circuit 106 can be found in Figure 12. For example, during the driving process of the pixel circuit 106, compared to the timing diagram shown in Figure 10, the timing states of the data signal DATA, the reset control signal RST, the data scanning signal G1, the first compensation control signal G2, the first light-emitting control signal EM1, the second light-emitting control signal EM2, and the second compensation control signal G3 in the timing diagram of Figure 12 are the same, and the difference is that the timing state of the third compensation control signal G4 is newly added.

[0162] For example, as shown in Figures 11B and 11E , in the pixel circuit 106, since the second switch transistor T7 is an N-type transistor, during the reset phase 1 and the light-emitting phase 4, the third compensation control signal G4 is a low-level signal, so that the second switch transistor T7 is in a closed state, thereby facilitating the charging of the pixel circuit 102 and facilitating the emission of the light-emitting element. For example, as shown in Figures 11C and 11D , the third compensation control signal G4 is a high-level signal, so that the second switch transistor T7 is in an open state, thereby facilitating compensation of the driving circuit by the second compensation circuit.

[0163] For example, for the specific working process and corresponding technical effects of the pixel circuit 105 shown in Figures 11B-11E when it is in the reset stage 1, compensation stage 2, data writing stage 3 and light-emitting stage 4, please refer to the relevant description of Figures 2B-2E in the above embodiments, and will not be repeated here.

[0164] For example, as shown in Figures 11B and 11E , during reset phase 1 and light-emitting phase 4, since both the first switch transistor T6 and the second switch transistor T7 are in the off state, the first and second electrodes of the second storage capacitor C2 are disconnected from other components in the pixel circuit 106. This reduces the parasitic capacitance between the second storage capacitor C2 and other components in the pixel circuit 106, thereby reducing the risk of circuit failure. Adding the second switch transistor T7, on the one hand, allows for controlling the supply of a constant voltage to the second electrode of the second storage capacitor C2 at specific times by controlling the on and off state of the second switch transistor T7; on the other hand, by simultaneously turning off the second switch transistor T7 and the first switch transistor T6, it ensures the reliability of disconnecting the first and second electrodes of the second storage capacitor C2 from other components in the pixel circuit 106.

[0165] FIG13 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0166] For example, as shown in FIG13 , the pixel circuit 30 includes a driving circuit 100, a data writing circuit 200, a first compensation circuit 300, a first light-emitting control circuit 400, a second light-emitting control circuit 500, a light-emitting element 600, a reset circuit 700, and a second compensation circuit 800. Compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 30 differs in that the second terminal 800b of the second compensation circuit 800 is configured to receive a constant voltage Vx from the constant voltage terminal Vx. For example, the constant voltage terminal Vx serves as an independent signal input terminal, thereby independently controlling the constant voltage Vx. For other structures in the pixel circuit 30, please refer to the relevant description of FIG1 in the above embodiment, and will not be repeated here.

[0167] FIG14 is a circuit diagram of an implementation example of the pixel circuit shown in FIG13 .

[0168] For example, the pixel circuit shown in FIG13 may be implemented as the pixel circuit structure shown in FIG14 .

[0169] For example, as shown in Figure 14, the pixel circuit 107 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switching transistor T6, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0170] For example, as shown in FIG14 , in pixel circuit 107, the first electrode of first switch transistor T6 is electrically connected to the first electrode of second storage capacitor C2, and the second electrode of first switch transistor T6 is electrically connected to second node N2, thereby indirectly electrically connecting second storage capacitor C2 to second node N2. The first electrode of reset transistor T5 is electrically connected to the first electrode of light-emitting element OLED. For example, as shown in FIG14 , pixel circuit 107 differs from pixel circuit 101 shown in FIG2A in that the second electrode of second storage capacitor C2 is electrically connected to constant voltage terminal Vx to receive constant voltage Vx from constant voltage terminal Vx.

[0171] For example, as shown in FIG14 , the timing diagram corresponding to the pixel circuit 107 can be found in FIG3 . For example, during the driving process of the pixel circuit 107, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG2A . For example, the operating process of the pixel circuit 107 shown in FIG14 during the reset phase 1, the compensation phase 2, the data writing phase 3, and the light emitting phase 4 can be found in the description of FIG2B to FIG2E in the above embodiments, and will not be repeated here.

[0172] For example, as shown in Figure 14, in the reset stage 1 and the light-emitting stage 4, the first switching transistor T6 is in the off state, thereby disconnecting the second storage capacitor C2 from other components in the pixel circuit 107, thereby reducing the parasitic capacitance between the second storage capacitor C2 and other components in the pixel circuit 107, thereby reducing the risk of circuit failure.

[0173] Fig. 15 is a circuit diagram of another implementation example of the pixel circuit shown in Fig. 13. For example, the pixel circuit shown in Fig. 13 can also be implemented as the pixel circuit structure shown in Fig. 15.

[0174] For example, as shown in Figure 15, the pixel circuit 108 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switching transistor T6, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0175] For example, as shown in Figure 15, the difference between the pixel circuit 108 and the pixel circuit 101 shown in Figure 2A is that the first electrode of the second storage capacitor C2 is electrically connected to the second node N2, the second electrode of the second storage capacitor C2 is electrically connected to the first electrode of the first switching transistor T6, and the second electrode of the first switching transistor T6 is electrically connected to the constant voltage terminal Vx.

[0176] For example, as shown in FIG15 , the timing diagram corresponding to the pixel circuit 108 can be found in FIG3 . For example, during the driving process of the pixel circuit 108, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG2A . For example, the operating process of the pixel circuit 108 shown in FIG15 during the reset phase 1, the compensation phase 2, the data writing phase 3, and the light emitting phase 4 can be found in the description of FIG2B to FIG2E in the above embodiments, and will not be repeated here.

[0177] For example, as shown in FIG15 , the first electrode of the second storage capacitor C2 can be directly electrically connected to the second node N2. In the data writing phase 3, the data transistor T1 and the first switch transistor T6 are both in the on state. When entering the light emitting phase 4 from the data writing phase 3, the data transistor T1 and the first switch transistor T6 are both turned off. When the first switch transistor T6 is turned off, due to the parasitic capacitance between the gate of the first switch transistor T6 and its first electrode (the second electrode of the second storage capacitor C2), the first switch transistor T6 can reduce the voltage of the second electrode of the second storage capacitor C2 when it is turned off. Since the voltage across the second storage capacitor C2 does not suddenly change, when the voltage of the second electrode of the second storage capacitor C2 decreases, the voltage of the first electrode of the second storage capacitor C2 also decreases. As a result, the voltage of the first electrode of the driving transistor DT decreases accordingly. In this way, the difference between the gate voltage of the driving transistor DT and the voltage of the first electrode of the driving transistor DT (i.e., Vgs of the driving transistor DT) can be basically unchanged, or fluctuate less, so as to make the driving current flowing through the light-emitting element more stable and the brightness of the display panel more uniform.

[0178] FIG16 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0179] For example, as shown in FIG16 , the pixel circuit 40 includes a driving circuit 100, a data writing circuit 200, a first compensation circuit 300, a first light-emitting control circuit 400, a second light-emitting control circuit 500, a light-emitting element 600, and a second compensation circuit 700. For example, compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 40 differs in that the second compensation circuit 700 is different. For the remaining structures, refer to the relevant description of FIG1 in the above embodiment and are not repeated here.

[0180] For example, as shown in FIG16 , the second compensation circuit 700 includes a control terminal 700m, a first terminal 700a, a second terminal 700b, and a third terminal 700c. The control terminal 700m of the second compensation circuit 700 is configured to receive a reset control signal RST. The first terminal 700a of the second compensation circuit 700 is electrically connected to the second node N2. The second terminal 700b of the second compensation circuit 700 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. The third terminal 700c of the second compensation circuit 700 is electrically connected to the first electrode of the light-emitting element OLED. For example, the second compensation circuit 700 is configured to compensate the driving circuit 100. Furthermore, the second compensation circuit 700 also serves as a reset circuit and is configured to reset the driving circuit 100 and the light-emitting element OLED.

[0181] Fig. 17A is a circuit diagram of an implementation example of the pixel circuit shown in Fig. 16. For example, the pixel circuit shown in Fig. 16 can be implemented as the pixel circuit structure shown in Fig. 17A.

[0182] For example, as shown in FIG17A , the pixel circuit 109 includes a driving transistor DT, a data transistor T1, a first light-emission control transistor T2, a first compensation transistor T3, a second light-emission control transistor T4, a reset transistor T5, a first storage capacitor C1, a second storage capacitor C2, and a light-emitting element. For example, compared to the pixel circuit 101 shown in FIG2A , the pixel circuit 109 differs in that the reset transistor T5 is reused as a first switching transistor and the connection method of the second storage capacitor C2 is different. For the remaining structures, reference can be made to the description of FIG2A in the above embodiment and will not be repeated here.

[0183] For example, as shown in Figures 16 and 17A, in the pixel circuit 109, the reset transistor T5 can be reused as the first switching transistor, so that the second compensation circuit 700 is implemented as the reset transistor T5 and the second storage capacitor C2. In this case, the second compensation circuit 700 is configured to compensate the driving circuit 100 in response to the second compensation control signal. The reset control signal RST serves as the second compensation control signal, and the reset signal terminal VINI electrically connected to the second electrode of the reset transistor T5 serves as a constant voltage terminal to provide the above-mentioned constant voltage. The first electrode of the second storage capacitor C2 is electrically connected to the second node N2, and the second electrode of the second storage capacitor C2 is electrically connected to the second electrode of the reset transistor T5 to be electrically connected to the reset signal terminal VINI.

[0184] For example, as shown in Figures 16 and 17A, in the pixel circuit 109, the second compensation circuit 700 can also serve as a reset circuit to reset the driving circuit 100 and the light-emitting element OLED. The reset circuit can be implemented as a reset transistor T5. The gate of the reset transistor T5 is electrically connected to the reset control terminal RST to receive the reset control signal RST, the first electrode of the reset transistor T5 is electrically connected to the first electrode of the light-emitting element OLED, and the second electrode of the reset transistor T5 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. For example, according to design requirements, some resistor elements or capacitor elements can be further provided between the second electrode of the reset transistor T5 and the reset signal terminal VINI, and the embodiments of the present disclosure are not limited to this.

[0185] Figure 17B is a schematic diagram of the pixel circuit shown in Figure 17A during the reset phase; Figure 17C is a schematic diagram of the pixel circuit shown in Figure 17A during the compensation phase; Figure 17D is a schematic diagram of the pixel circuit shown in Figure 17A during the data writing phase; and Figure 17E is a schematic diagram of the pixel circuit shown in Figure 17A during the light emitting phase. In addition, transistors marked with dashed lines in Figures 17B through 17E are all in the off state during the corresponding phase.

[0186] For example, the timing diagram corresponding to the pixel circuit 109 can be seen in FIG3. For example, as shown in FIG17B to FIG17E and FIG3, in each of the reset phase 1, the compensation phase 2, the data writing phase 3, and the light emitting phase 4, the operating states of the driving transistor DT, the data transistor T1, the first light emission control transistor T2, the first compensation transistor T3, the second light emission control transistor T4, the reset transistor T5, the first storage capacitor C1, the second storage capacitor C2, and the light emitting element in the pixel circuit 109 are the same as the operating states of the corresponding elements in the pixel circuit 101 in FIG2A.

[0187] For example, as shown in FIG17B , in reset phase 1, the reset transistor T5 is turned on, and the reset signal VINI can be applied to the first electrode of the light-emitting element OLED through the reset transistor T5, and applied to the first electrode of the driving transistor DT through the second light-emitting control transistor T4. For example, as shown in FIG17C , in compensation phase 2 and data writing phase 3, the reset transistor T5 is turned on, and the second light-emitting control transistor T4 is turned off. The reset signal VINI can be applied to the first electrode of the light-emitting element OLED through the reset transistor T5, so that the voltage of the first electrode 600a remains stable, thereby reducing the risk of abnormal light emission of the light-emitting element OLED due to a sudden change in the voltage of the first electrode 600a.

[0188] For example, as shown in Figures 17D and 17E , when entering the light-emitting phase 4 from the data writing phase 3, the data transistor T1 and the reset transistor T5 (multiplexed as the first switching transistor) are both turned off. When the data transistor T1 is turned off, due to the parasitic capacitance between the gate of the data transistor T1 and its second electrode (the first node N1), the data transistor T1 may reduce the voltage of the first node N1 when it is turned off. When the reset transistor T5 (multiplexed as the first switching transistor) is turned off, due to the parasitic capacitance between the gate of the reset transistor T5 and its second electrode (the second electrode of the second storage capacitor C2), the reset transistor T5 may reduce the voltage of the second electrode of the second storage capacitor C2 when it is turned off. Since the voltage across the second storage capacitor C2 does not suddenly change, when the voltage of the second electrode of the second storage capacitor C2 decreases, the voltage of the first electrode of the second storage capacitor C2 also decreases. As a result, the voltage value Vs of the first electrode of the driving transistor DT decreases accordingly. In this way, the difference between the gate voltage of the driving transistor DT and the voltage of the first electrode of the driving transistor DT (i.e., the gate-source voltage Vgs of the driving transistor DT) can be made basically unchanged, or have a smaller fluctuation, so as to make the driving current flowing through the light-emitting element OLED more stable and make the brightness of the display panel more uniform.

[0189] For example, as shown in FIG17A , compared to the pixel circuit 101 shown in FIG2A , by multiplexing the reset transistor T5 as the first switch transistor, the number of transistors in the pixel circuit 109 can be reduced, thereby simplifying the structure of the pixel circuit 109 and simplifying the control method of the pixel circuit. Simplifying the structure of the pixel circuit not only helps to reduce the space occupied by each pixel circuit, but also helps to simplify the manufacturing process and reduce the difficulty of manufacturing the display panel including the pixel circuit, thereby improving the yield of the display panel.

[0190] FIG18 is a circuit diagram of another implementation example of the pixel circuit shown in FIG16 ; FIG19 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0191] For example, the pixel circuit shown in FIG16 may also be implemented as the pixel circuit structure shown in FIG18 .

[0192] For example, as shown in FIG18 , the pixel circuit 110 includes a driving transistor DT, a data transistor T1, a first light emission control transistor T2, a first compensation transistor T3, a second light emission control transistor T4, a reset transistor T5, a first storage capacitor C1, a second storage capacitor C2, and a light-emitting element OLED. For example, compared to the pixel circuit 109 shown in FIG17A , the pixel circuit 110 differs in that the type of the first light emission control transistor T2 is different. For the remaining structures, reference can be made to the description of FIG17A in the above embodiment, and no further description is given here.

[0193] For example, as shown in FIG18 , the first light emission control transistor T2 is a P-type transistor, which is turned on when a low-level signal is connected to the gate of the first light emission control transistor T2 , and is turned off when a high-level signal is connected to the gate of the first light emission control transistor T2 .

[0194] For example, as shown in Figures 18 and 19 , during the driving process of pixel circuit 110, the operating state (e.g., on or off) of each transistor is the same as that of pixel circuit 109 shown in Figure 17A . Compared to the timing diagram shown in Figure 3 , the timing states of the data signal DATA, reset control signal RST, data scanning signal G1, first compensation control signal G2, and second emission control signal EM2 remain unchanged. The difference lies in the control signal of first emission control signal EM1. For example, in pixel circuit 110, since first emission control transistor T2 is a P-type transistor, during reset phase 1 and data write phase 3, first emission control signal EM1 is a high-level signal, turning first emission control transistor T2 off. During compensation phase 2 and emission phase 4, first emission control signal EM1 is a low-level signal, turning first emission control transistor T2 on. Therefore, the type of first emission control transistor T2 can be selected according to design requirements, thereby providing pixel circuit 110 with a flexible and diverse structural form.

[0195] FIG20 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0196] For example, as shown in FIG20 , the pixel circuit 50 includes a driving circuit 100, a data writing circuit 200, a first compensation circuit 300, a first light-emitting control circuit 400, a second light-emitting control circuit 500, a light-emitting element 600, a reset circuit 700, and a second compensation circuit 800. For example, compared with the pixel circuit 10 shown in FIG1 , the pixel circuit 40 differs in that the second compensation circuit 800 is different. For the remaining structures, refer to the relevant description of FIG1 in the above embodiment and are not repeated here.

[0197] For example, referring to FIG. 20 , the second compensation circuit 800 includes a control terminal 800m, a first terminal 800a, and a second terminal 800b. The control terminal 800m of the second compensation circuit 800 is configured to receive a second compensation control signal. The first terminal 800a of the second compensation circuit 800 is electrically connected to the second node N2. The second terminal 800b of the second compensation circuit 800 is electrically connected to the constant voltage terminal Vx to receive the constant voltage Vx. The second compensation circuit 800 is configured to compensate the driving circuit 100 in response to the second compensation control signal. For example, in the pixel circuit 50 shown in FIG. 20 , the control terminal 800m of the second compensation circuit 800 is electrically connected to the control terminal 700m of the reset circuit 700. That is, the two serve as a common control terminal. Thus, the reset control signal RST also serves as the second compensation control signal to simultaneously control the on / off of the second compensation circuit 800 and the reset circuit 700. For example, when the reset control signal RST is used as an on signal, the reset circuit 700 and the second compensation circuit 800 are turned on at the same time; when the reset control signal RST is used as a off signal, the reset circuit 700 and the second compensation circuit 800 are turned off at the same time.

[0198] Figure 21A is a circuit diagram of an implementation example of the pixel circuit shown in Figure 20. Figure 21B is a schematic diagram of the pixel circuit shown in Figure 21A during a reset phase; Figure 21C is a schematic diagram of the pixel circuit shown in Figure 21A during a compensation phase; Figure 21D is a schematic diagram of the pixel circuit shown in Figure 21A during a data write phase; and Figure 21E is a schematic diagram of the pixel circuit shown in Figure 21A during a light-emitting phase. Furthermore, transistors marked with dashed lines in Figures 21B through 21E are all in an off state during the corresponding phase.

[0199] For example, as shown in Figure 21A, the pixel circuit 111 includes a driving transistor DT, a data transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first switching transistor T6, a first storage capacitor C1, a second storage capacitor C2 and a light-emitting element.

[0200] For example, as shown in FIG21A , the difference between the pixel circuit 111 and the pixel circuit 102 shown in FIG4 is that the connection method and type of the first switch transistor T6 and the connection method of the second storage capacitor C2 are changed, while the remaining structures are the same. For other structures in the pixel circuit 111, please refer to the description of FIG4 in the above embodiment, and will not be repeated here.

[0201] For example, as shown in FIG21A , in the pixel circuit 111, the gate of the first switch transistor T6 is electrically connected to the gate of the reset transistor T5. The first switch transistor T6 and the reset transistor T5 share a common gate. The reset control signal RST serves as the second compensation control signal. The type of the first switch transistor T6 is the same as that of the reset transistor T5. The first electrode of the first switch transistor T6 is electrically connected to the first electrode of the second storage capacitor C2, the second electrode of the first switch transistor T6 is electrically connected to the second node N2, and the second electrode of the second storage capacitor C2 is electrically connected to the constant voltage terminal Vx to receive the constant voltage Vx from the constant voltage terminal Vx. For example, when the reset control signal RST is an on signal, the first switch transistor T6 and the reset transistor T5 are both on. Conversely, when the reset control signal RST is an off signal, the first switch transistor T6 and the reset transistor T5 are both off.

[0202] For example, as shown in FIG21A , the timing diagram corresponding to the pixel circuit 111 is the same as that of the pixel circuit 102 shown in FIG4 , and both can be referred to in FIG5 . The difference lies in the different operating processes of the first switch transistor T6 and the second storage capacitor C2 . The operating processes of other components in the pixel circuit 111 can be referred to the relevant description of FIG4 in the above embodiment, and will not be repeated here.

[0203] For example, as shown in Figure 21B, in the reset stage 1, the first switching transistor T6 and the reset transistor T5 are turned on in response to the reset control signal RST, the voltage of the first electrode of the first switching transistor T6 (the first electrode of the second storage capacitor C2) is the reset voltage VINI, and the voltage of the second electrode of the second storage capacitor C2 is the constant voltage Vx.

[0204] For example, as shown in FIG21C , in compensation phase 2, the first switch transistor T6 and the reset transistor T5 are turned on in response to the reset control signal RST. The initial voltage at the first electrode of the first switch transistor T6 (the first electrode of the second storage capacitor C2) is the reset voltage VINI. The first light-emitting control transistor T2 is in the on state, thereby charging the driving transistor DT. When the driving transistor DT is turned off, the voltage at the first terminal of the driving transistor DT, i.e., the voltage at the first electrode of the first switch transistor T6 (the first electrode of the second storage capacitor C2), is Vs=Vref-Vth, and the voltage at the second electrode of the second storage capacitor C2 is a constant voltage Vx.

[0205] For example, as shown in Figure 21D, in the data writing phase 3, the first switching transistor T6 and the reset transistor T5 are turned on in response to the reset control signal RST, and the data signal DATA is written to the gate of the driving transistor DT. The voltage of the first end of the driving transistor DT, that is, the voltage of the first electrode of the first switching transistor T6 (the first electrode of the second storage capacitor C2) is Vref-Vth+C1 / (C1+C2)×(Vdata-Vref), and the voltage of the second electrode of the second storage capacitor C2 is a constant voltage Vx.

[0206] For example, as shown in FIG21E , in light-emitting phase 4, the first switch transistor T6 and the reset transistor T5 are turned off in response to the reset control signal RST, and the data transistor T1 is turned off in response to the data scan signal G1. When the data transistor T1 is turned off, the voltage of the first node N1 is reduced, and when the first switch transistor T6 is turned off, the voltage of the second node N2 is reduced. This allows the difference between the gate voltage of the drive transistor DT and the voltage of the first electrode of the drive transistor DT (i.e., the gate-source voltage Vgs of the drive transistor DT) to remain substantially constant or have minimal fluctuations, thereby facilitating a more stable drive current flowing through the light-emitting element and achieving more uniform brightness on the display panel. Simultaneously, since the first switch transistor T6 is in the off state, both the first electrode and the second electrode of the second storage capacitor C2 are disconnected from other components in the pixel circuit 106. This reduces the parasitic capacitance between the second storage capacitor C2 and other components in the pixel circuit 106, thereby reducing the risk of circuit failure.

[0207] For example, referring to FIG21A , in some embodiments of the present disclosure, the gate of the first switch transistor T6 and the gate of the reset transistor T5 may also be independent of each other and not electrically connected. For example, the gate of the first switch transistor T6 is configured to receive the second compensation control signal, and the gate of the reset transistor T5 is configured to receive the reset signal RST, and the second compensation control signal and the reset signal RST are respectively from different signal terminals. In this case, the type of the first switch transistor T6 and the type of the reset transistor T5 may also be different. Thus, the first switch transistor T6 can be controlled separately, so that the pixel circuit has a more flexible control method.

[0208] FIG22 is a circuit diagram of another implementation example of the pixel circuit shown in FIG20 .

[0209] For example, as shown in FIG22 , the pixel circuit 112 includes a drive transistor DT, a data transistor T1, a first light emission control transistor T2, a first compensation transistor T3, a second light emission control transistor T4, a reset transistor T5, a first switch transistor T6, a second switch transistor T7, a first storage capacitor C1, a second storage capacitor C2, and a light-emitting element. For example, the difference between the pixel circuit 112 and the pixel circuit 111 shown in FIG21A is that the pixel circuit 111 further includes a second switch transistor T7, and the rest of the structure is the same. For other structures in the pixel circuit 111, please refer to the description of FIG21A in the above embodiment, and will not be repeated here.

[0210] For example, as shown in FIG22 , in the pixel circuit 112, a first electrode of the first switch transistor T6 is electrically connected to a first electrode of the second storage capacitor C2, a second electrode of the first switch transistor T6 is electrically connected to a second node N2, a first electrode of the second switch transistor T7 is electrically connected to a second electrode of the second storage capacitor C2, and a second electrode of the second switch transistor T7 is electrically connected to a constant voltage terminal Vx to receive a constant voltage Vx from the constant voltage terminal Vx, thereby allowing the second electrode of the second storage capacitor C2 to receive the constant voltage Vx via the second switch transistor T7. The gate of the first switch transistor T6, the gate of the second switch transistor T7, and the gate of the reset transistor T5 are electrically connected, and the first switch transistor T6 and the second switch transistor T7 share a gate with the reset transistor T5. The reset control signal RST serves as a second compensation control signal, and the types of the first switch transistor T6 and the second switch transistor T7 are the same as those of the reset transistor T5. For example, when the reset control signal RST is an on signal, the first switch transistor T6, the second switch transistor T7 and the reset transistor T5 are all turned on; conversely, when the reset control signal RST is an off signal, the first switch transistor T6, the second switch transistor T7 and the reset transistor T5 are all turned off.

[0211] For example, as shown in FIG22, the timing diagram corresponding to the pixel circuit 112 is the same as that of the pixel circuit 111 shown in FIG21A, and both can refer to FIG5. The operation process of the pixel circuit 112 can refer to the relevant description of FIG21A in the above embodiment, and will not be repeated here.

[0212] For example, as shown in Figures 5 and 22, in the light-emitting stage 4, since the first switching transistor T6, the second switching transistor T7 and the reset transistor T5 in the pixel circuit 112 are all in the off state, the first electrode and the second electrode of the second storage capacitor C2 can be disconnected from other components in the pixel circuit 112, and the first electrode and the second electrode of the second storage capacitor C2 are also disconnected from the constant voltage terminal Vx, thereby further reducing the risk of parasitic capacitance generated between the second storage capacitor C2 and other components in the pixel circuit 112, thereby reducing the occurrence of circuit failure.

[0213] For example, referring to FIG22 , for the pixel circuit 112, the gate of the first switch transistor T6, the gate of the second switch transistor T7, and the gate of the reset transistor T5 may not be electrically connected. For example, in some embodiments of the present disclosure, at least two of the gate of the first switch transistor T6, the gate of the second switch transistor T7, and the gate of the reset transistor T5 may be electrically connected, and the at least two of the first switch transistor T6, the second switch transistor T7, and the reset transistor T5 may share a gate and be of the same type.

[0214] For example, referring to FIG. 22 , for the pixel circuit 112 , the gate of the first switching transistor T6 and the gate of the second switching transistor T7 can be electrically connected, and the first switching transistor T6 and the second switching transistor T7 share a gate and are of the same type. The gates of the first switching transistor T6 and the second switching transistor T7 are configured to receive a second compensation control signal, and the gate of the reset transistor T5 is configured to receive a reset control signal RST, with the second compensation control signal and the reset control signal RST coming from different signal terminals.

[0215] For example, referring to FIG. 22 , for the pixel circuit 112 , the gate of one of the first switching transistor T6 and the second switching transistor T7 can be electrically connected to the gate of the reset transistor T5 , and the first switching transistor T6 and the second switching transistor T7 share a gate with the reset transistor T5 and are of the same type. The gate of the other of the first switching transistor T6 and the second switching transistor T7 is configured to receive the second compensation control signal, and the gate of the reset transistor T5 is configured to receive the reset control signal RST, and the second compensation control signal and the reset control signal RST are respectively output from different signal output terminals.

[0216] For example, referring to Figures 5 and 22, the embodiments of the present disclosure do not limit the electrical connection form and type of the first switch transistor T6, the second switch transistor T7, and the reset transistor T5, as long as the first switch transistor T6, the second switch transistor T7, and the reset transistor T5 are all in the on state in the reset stage 1, the compensation stage 2, and the data writing stage 3, and are all in the off state in the light-emitting stage 4.

[0217] Figure 23 is a schematic block diagram of a display device provided in at least one embodiment of the present disclosure. Referring to Figure 23, a display device 1000 provided in at least one embodiment of the present disclosure includes any pixel circuit 1001 provided in the embodiments of the present disclosure. The display device may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other device with display functionality. The embodiments of the present disclosure are not limited thereto.

[0218] The other structures and functions of the display device provided by the embodiment of the present disclosure can be implemented with reference to conventional technologies, and the embodiment of the present disclosure does not limit this. The technical effects of the display device provided by the embodiment of the present disclosure can be referred to the above description of the technical effects of the pixel circuit provided by the embodiment of the present disclosure, and will not be repeated here.

[0219] For example, the display device 1000 provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, and the embodiments of the present disclosure are not limited thereto.

[0220] There are a few points to note:

[0221] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0222] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0223] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure, which is determined by the appended claims.

Claims

1. A pixel circuit, comprising: A driving circuit, comprising a control terminal, a first terminal and a second terminal, and configured to control the magnitude of a driving current flowing through the first terminal and the second terminal; a first compensation circuit configured to apply a reference signal to the control terminal of the driving circuit in response to a first compensation control signal, wherein the first compensation circuit comprises a first storage capacitor, a first electrode of the first storage capacitor is electrically connected to the control terminal of the driving circuit, and a second electrode of the first storage capacitor is electrically connected to the first terminal of the driving circuit; and The second compensation circuit includes a second storage capacitor and a first switching transistor, wherein a first electrode of the second storage capacitor is electrically connected to a first end of the driving circuit, a first electrode of the first switching transistor is electrically connected to the second storage capacitor, a gate of the first switching transistor is configured to receive a second compensation control signal, and the second compensation circuit is configured to compensate the driving circuit in response to the second compensation control signal.

2. The pixel circuit according to claim 1, further comprising: a light emitting element, configured to emit light under the driving of the driving current, wherein the first end of the driving circuit is electrically connected to the first electrode of the light emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light emitting element; The driving circuit includes a driving transistor, a gate of the driving transistor being electrically connected to a first node as a control terminal of the driving circuit, a first electrode of the driving transistor being electrically connected to a second node as a first terminal of the driving circuit, and a second electrode of the driving transistor being electrically connected to a third node as a second terminal of the driving circuit.

3. The pixel circuit according to claim 2, wherein: A first electrode of the first switch transistor is electrically connected to a first electrode of the second storage capacitor, and a second electrode of the first switch transistor is electrically connected to the second node.

4. The pixel circuit according to claim 2, wherein: A first electrode of the second storage capacitor is electrically connected to the second node, and a second electrode of the second storage capacitor is electrically connected to a first electrode of the first switch transistor.

5. The pixel circuit according to any one of claims 2 to 4, further comprising: A reset circuit, wherein the control end of the reset circuit is configured to receive a reset control signal, the first end of the reset circuit is electrically connected to the first electrode of the light emitting element, and the reset circuit The second end is electrically connected to the reset signal end to receive a reset signal, and the reset circuit is configured to apply the reset signal to the first electrode of the light emitting element and the first end of the driving circuit in response to the reset control signal; The reset circuit includes a reset transistor, a gate of the reset transistor is electrically connected to a reset control terminal to receive the reset control signal, a first electrode of the reset transistor is electrically connected to a first electrode of the light-emitting element, and a second electrode of the reset transistor is electrically connected to the reset signal terminal to receive the reset signal.

6. The pixel circuit according to claim 5, wherein: The second electrode of the second storage capacitor is electrically connected to the constant voltage terminal to receive the constant voltage from the constant voltage terminal.

7. The pixel circuit according to claim 6, wherein: The first electrode of the first switch transistor is electrically connected to the first electrode of the second storage capacitor, the second electrode of the first switch transistor is electrically connected to the second node, and the second electrode of the second storage capacitor is electrically connected to the constant voltage terminal.

8. The pixel circuit according to claim 6, wherein: A first electrode of the second storage capacitor is electrically connected to the second node, a second electrode of the second storage capacitor is electrically connected to a first electrode of the first switch transistor, and a second electrode of the first switch transistor is electrically connected to the constant voltage terminal.

9. The pixel circuit according to claim 6, wherein: The reset transistor serves as the first switch transistor, the reset control signal serves as the second compensation control signal, and the reset signal terminal electrically connected to the second electrode of the reset transistor serves as the constant voltage terminal; A first electrode of the second storage capacitor is electrically connected to the second node, and a second electrode of the second storage capacitor is electrically connected to a second electrode of the reset transistor so as to be electrically connected to the reset signal terminal.

10. The pixel circuit according to claim 5, wherein: The second electrode of the second storage capacitor is electrically connected to the first electrode of the light emitting element, and the first electrode of the reset transistor is electrically connected to the first electrode of the light emitting element.

11. The pixel circuit according to any one of claims 2 to 10, wherein: The pixel circuit further includes a first light-emitting control circuit, a control terminal of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first terminal of the first light-emitting control circuit is electrically connected to a second terminal of the driving circuit, a second terminal of the first light-emitting control circuit is electrically connected to a first voltage terminal to receive a first power supply voltage, and the first light-emitting control circuit is configured to apply the first power supply voltage to the second terminal of the driving circuit 1 in response to the first light-emitting control signal; The first light emitting control circuit includes a first light emitting control transistor, the gate of the first light emitting control transistor is electrically connected to the first light emitting control terminal to receive the first light emitting control signal, A first electrode of a light emitting control transistor is electrically connected to the first voltage terminal to receive the first power supply voltage, and a second electrode of the first light emitting control transistor is electrically connected to the third node.

12. The pixel circuit according to any one of claims 5 to 10, wherein: The pixel circuit further includes a second light emitting control circuit, a control terminal of the second light emitting control circuit is configured to receive a second light emitting control signal, a first terminal of the second light emitting control circuit is electrically connected to the second node, a second terminal of the second light emitting control circuit is electrically connected to the first electrode of the light emitting element, the second light emitting control circuit is configured to apply the driving current to the light emitting element and allow the reset signal to be applied to the first terminal of the driving circuit in response to the second light emitting control signal, and the second light emitting control signal is different from the first light emitting control signal; The second light-emitting control circuit includes a second light-emitting control transistor, a gate of the second light-emitting control transistor is electrically connected to a second light-emitting control terminal to receive the second light-emitting control signal, a first electrode of the second light-emitting control transistor is electrically connected to the second node, a second electrode of the light-emitting control transistor is electrically connected to a first electrode of the light-emitting element, and a second electrode of the light-emitting element is electrically connected to a second voltage terminal to receive a second power supply voltage.

13. The pixel circuit according to claim 12, wherein: The gate of the first switch transistor is electrically connected to the gate of the second light emission control transistor, the first switch transistor and the second light emission control transistor share a gate, the second light emission control signal serves as the second compensation control signal, and the type of the first switch transistor is different from the type of the second light emission control transistor; or The gate of the first switch transistor and the gate of the second light emission control transistor are independent of each other and are not electrically connected.

14. The pixel circuit according to claim 6, wherein: The gate of the first switch transistor is electrically connected to the gate of the reset transistor, the first switch transistor and the reset transistor share a gate, the reset control signal serves as the second compensation control signal, and the type of the first switch transistor is the same as the type of the reset transistor; or, The gate of the first switch transistor and the gate of the reset transistor are independent of each other and are not electrically connected.

15. The pixel circuit according to claim 6, wherein: The second compensation circuit further includes a second switching transistor, The first electrode of the second switch transistor is electrically connected to the second electrode of the second storage capacitor, and the second electrode of the second switch transistor is electrically connected to the constant voltage terminal.

16. The pixel circuit according to claim 10, wherein: The second compensation circuit further includes a second switching transistor, The second electrode of the second storage capacitor is electrically connected to the first electrode of the second switch transistor, and the second electrode of the second switch transistor is electrically connected to the first electrode of the light emitting element.

17. The pixel circuit according to claim 15 or 16, wherein: At least two of the gate of the first switch transistor, the gate of the second switch transistor and the gate of the reset transistor are electrically connected, and the at least two share a gate and are of the same type.

18. The pixel circuit according to any one of claims 2 to 17, wherein: The pixel circuit further includes a data writing circuit, wherein a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected to a data signal end to receive a data signal, and a second end of the data writing circuit is electrically connected to the first node. The data writing circuit is configured to write the data signal into the control terminal of the driving circuit in response to the data scanning signal; Among them, the data writing circuit includes a data transistor, the gate of the data transistor is electrically connected to the data scanning signal end to receive the data scanning signal, the first electrode of the data transistor is electrically connected to the data signal end to receive the data signal, and the second electrode of the data transistor is electrically connected to the first node.

19. The pixel circuit according to any one of claims 2 to 18, wherein: The control end of the first compensation circuit is configured to receive the first compensation control signal, and the first end of the first compensation circuit is electrically connected to the reference signal end to receive the reference signal. The first compensation circuit includes a first compensation transistor, a gate of the first compensation transistor is electrically connected to a first compensation control signal terminal to receive the first compensation control signal, a first electrode of the first compensation transistor is electrically connected to the reference signal terminal to receive the reference signal, and a second electrode of the first compensation transistor is electrically connected to the first node.

20. A display device comprising the pixel circuit according to any one of claims 1 to 19.

21. A driving method, applicable to the pixel circuit according to any one of claims 1 to 19, the driving method comprising: In the data writing stage, the second compensation control signal is a turn-on signal to turn on the first switch transistor; When entering the light-emitting stage from the data writing stage, the second compensation control signal is changed from an on signal to an off signal to turn off the first switch transistor, wherein, in the light-emitting stage, the The second compensation control signal remains as an off signal.

22. The driving method according to claim 21, wherein: The pixel circuit further comprises a data writing circuit, wherein a control terminal of the data writing circuit is configured to receive a data scanning signal, a first terminal of the data writing circuit is electrically connected to a data signal terminal to receive a data signal, a second terminal of the data writing circuit is electrically connected to the first node, and the data writing circuit is configured to write the data signal to the control terminal of the driving circuit in response to the data scanning signal; The driving method further includes: In the data writing phase, the data scanning signal is set to be an on signal to write the data signal into the control end of the driving circuit; and When entering the light-emitting stage from the data writing stage, the data scanning signal is changed from an on signal to an off signal to simultaneously turn off the data writing circuit and the first switching transistor, wherein in the light-emitting stage, the data scanning signal remains as an off signal.

23. The driving method according to claim 21 or 22, further comprising: In the compensation phase before the data writing phase, the second compensation control signal is set as a turn-on signal to turn on the first switch transistor, and the second compensation circuit is configured to compensate the driving circuit in response to the second compensation control signal.

24. The driving method according to claim 23, wherein: In the compensation stage, the second electrode of the second storage capacitor receives a constant voltage from a constant voltage terminal.

25. The driving method according to claim 23 or 24, wherein: The pixel circuit further includes a light emitting element, a second light emitting control circuit and a reset circuit; the light emitting element is configured to emit light under the driving of the driving current; The control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the first end of the driving circuit, and the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element; the control end of the reset circuit is configured to receive a reset control signal, the first end of the reset circuit is electrically connected to the first electrode of the light-emitting element, and the second end of the reset circuit is electrically connected to the reset signal end to receive the reset signal; The driving method further comprises: in a reset phase before the compensation phase, The first compensation control signal is set as a start signal to start the first compensation circuit, and the first compensation circuit applies the reference signal to the control terminal of the driving circuit. The second light emitting control signal is set to be an on signal to turn on the second light emitting control circuit, and The reset control signal is set as a start signal to start the reset circuit, the reset signal is applied to the first electrode of the light-emitting element through the reset circuit, and the reset signal is applied to the first end of the driving circuit through the second light-emitting control circuit.

26. The driving method according to claim 25, wherein: In each of the reset phase, the compensation phase, the data writing phase, and the light emitting phase, the second compensation control signal and the second light emitting control signal are opposite switching signals to control the switching states of their corresponding circuits to be opposite.

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